A MOS device and a method of manufacturing the same
By introducing an h-BNC layer and an h-BN/Al2O3 high-k gate dielectric structure into SiC-based MOS devices, the interface trap and interface state problems of SiC-based MOS devices are solved, the density and mobility of conductive carriers are improved, and the on-resistance and operating frequency of the devices are increased.
Patent Information
- Application Number
- CN202210776329.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-30
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2042-06-30
AI Technical Summary
SiC-based MOS devices suffer from interface traps and interface state problems at the interface, resulting in high on-resistance and low operating frequency. Furthermore, existing technologies lack effective interface modulation methods to improve the density and mobility of conductive carriers in the channel layer.
An h-BNC layer is formed on the substrate, combined with an h-BN buffer layer and an Al2O3 anti-leakage layer, to form a high-k gate dielectric heterostructure. The band gap and mobility of the h-BNC layer can be adjusted to improve the density and mobility of conductive carriers.
This technology enables high-density, high-mobility conductive carriers in SiC-based MOS devices, improving the device's on-resistance and operating frequency performance.
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Figure CN115064595B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor technology, in particular to a MOS device and a preparation method thereof. BACKGROUND
[0002] The third generation semiconductor silicon carbide (SiC) has the characteristics of wide band gap (3.26eV, 3 times of silicon (Si)), high breakdown field strength (3.0MV / cm, 10 times of Si), high saturated electron drift velocity (2.0*107cm / s, 2.5 times of Si) and high thermal conductivity (4.9W / (cm*K), 3.3 times of Si), and also has excellent physical and chemical stability and mechanical strength, and is the first choice for developing high-voltage, high-frequency and high-temperature devices.
[0003] On the one hand, the SiC-based MOS device needs to obtain a gate oxide layer by thermal oxidation of the surface, and the temperature of thermal oxidation is usually higher than 1100℃. However, unlike Si oxidation, SiC oxidation involves the oxidation reaction of Si and C elements, and C atom related interface traps are easily formed at the SiO2 / SiC interface. At the same time, when the oxidation is incomplete, Si sub-oxides and interface states are easily formed at the interface. These interface states not only reduce the conductive carriers in the channel of the SiC-based MOS device, but also form scattering centers to further reduce the channel mobility, which seriously affects the interface quality of the gate dielectric and SiC, resulting in high on-resistance and low working frequency of the device.
[0004] On the other hand, in recent years, two-dimensional crystal materials represented by graphene and molybdenum disulfide (MoS2) have attracted widespread attention. They have excellent mechanical, optical and electrical properties, and thus have a very broad application prospect in the fields of energy, materials, microelectronics, biochemistry and the like. However, the research on their properties has just started. Among them, the zero band gap of graphene hinders its application in normally-off devices, and other topological insulating materials such as MoS2 and Bi2Te3 do not have high-temperature characteristics. So far, the research combining SiC and two-dimensional materials still remains in the field of nano-optoelectronics, and there is still a lack of technical innovation and revolution for the currently popular MOS-based devices.
[0005] Therefore, it is urgent to find a new interface regulation method based on the SiC-based MOS device, so that the channel layer can generate high-density and high-mobility conductive carriers. SUMMARY
[0006] In view of the above defects in the prior art, the present disclosure provides a MOS device and a preparation method thereof. By arranging an h-BNC layer on the substrate, the band gap and mobility of the h-BNC layer can be adjusted, so that the lower surface of the substrate can generate high-density and high-mobility conductive carriers.
[0007] The present disclosure provides a MOS device, comprising: a substrate; a carbon transport layer disposed on one side of the upper surface of the substrate, the carbon transport layer containing C elements; an h-BNC layer disposed on the other side of the upper surface of the substrate; a buffer layer disposed above the carbon transport layer and the h-BNC layer; the material of the buffer layer is h-BN; an anti-leakage layer disposed above the buffer layer; the material of the anti-leakage layer is Al2O3; a source electrode disposed on the lower surface of the substrate; a gate electrode disposed above the anti-leakage layer; an isolation layer disposed on one side of the carbon transport layer, the h-BNC layer, the buffer layer and the anti-leakage layer, the upper end of the isolation layer contacting the gate electrode, and the lower end of the isolation layer contacting the substrate.
[0008] Optionally, the materials of the carbon transport layer, the h-BNC layer and the buffer layer all have hexagonal structure and two-dimensional layered structure; the material of the substrate has hexagonal wurtzite structure.
[0009] Optionally, the thickness of the buffer layer is 3-20 nm.
[0010] Optionally, the thickness of the anti-leakage layer is 3-100 nm.
[0011] Optionally, the material of the substrate includes one of {0001} face SiC epitaxial material, {1100} face SiC epitaxial material or {1120} face SiC epitaxial material.
[0012] Optionally, the material of the isolation layer includes at least one of SiO2, SiO x , Si3N4 or Si x N y .
[0013] The present disclosure also provides a preparation method of a MOS device, comprising: step A, preparing a carbon transport layer on one side of the upper surface of a substrate and an h-BN layer on the other side; step B, reacting the h-BN material contained in the h-BN layer with the C elements contained in the carbon transport layer to form an h-BNC layer; step C, preparing a buffer layer on the carbon transport layer and the h-BNC layer; step D, preparing an isolation layer on the upper surface of the substrate on one side of the carbon transport layer, the h-BNC layer, the buffer layer and the anti-leakage layer; step E, preparing an anti-leakage layer on the buffer layer; wherein the upper surface of the anti-leakage layer is flush with the upper surface of the isolation layer; step F, preparing a gate electrode on the anti-leakage layer and the isolation layer; and preparing a source electrode on the lower surface of the substrate.
[0014] Optionally, step A comprises: step A1, growing graphite on the upper surface of the substrate; and step A2, annealing the graphite to form the carbon transport layer; wherein the growth temperature is 900-1800℃, and the annealing temperature is 1200-1700℃.
[0015] Optionally, the reaction temperature in step B is 1150-1600°C.
[0016] Optionally, step E comprises: step E1, before preparing the anti-creeping layer, annealing the object prepared in step D; wherein the annealing temperature is 400-1300°C, and the annealing time is 0.2-3 hours.
[0017] The MOS device and the preparation method thereof in the present disclosure can generate high-density and high-mobility conductive carriers on the lower surface of the substrate by setting the h-BNC layer on the substrate, and the band gap and the mobility of the h-BNC layer are adjustable.
[0018] The MOS device and the preparation method thereof in the present disclosure can isolate the anti-creeping layer and the h-BNC layer by setting the material of the buffer layer as h-BN, and the h-BN is lattice matched with the composition material of the h-BNC layer, and can play a buffering role on the conductive carriers from the h-BNC layer, and the h-BN can also act as a gate medium and prevent creeping.
[0019] The MOS device and the preparation method thereof in the present disclosure can not only prevent static electricity by setting the material of the anti-static layer as Al2O3, but also form a high-k gate medium heterostructure by vertically stacking Al2O3 together. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 The structure schematic diagram of the MOS device according to Embodiment 1 of the present disclosure is schematically shown;
[0021] Figure 2 The flow chart of the preparation method of the MOS device according to Embodiment 1 of the present disclosure is schematically shown;
[0022] Figure 3 The structure schematic diagram of the substrate 10 according to Embodiment 1 of the present disclosure is schematically shown;
[0023] Figure 4 The structure schematic diagram of the object prepared in step A1 according to Embodiment 1 of the present disclosure is schematically shown;
[0024] Figure 5 The structure schematic diagram of the object prepared in step A2 according to Embodiment 1 of the present disclosure is schematically shown;
[0025] Figure 6 The structure schematic diagram of the object prepared in step B according to Embodiment 1 of the present disclosure is schematically shown;
[0026] Figure 7schematically illustrates a structural diagram of an object prepared according to Embodiment 1 of the present disclosure through Step C;
[0027] Figure 8 schematically illustrates a structural diagram of an object prepared according to Embodiment 1 of the present disclosure through Step D;
[0028] Figure 9 schematically illustrates a structural diagram of an object prepared according to Embodiment 1 of the present disclosure through Step E;
[0029] Figure 10 schematically illustrates a structural diagram of a MOS device according to Embodiment 2 of the present disclosure;
[0030] Figure 11 schematically illustrates a flowchart of a method for preparing a MOS device according to Embodiment 2 of the present disclosure;
[0031] Figure 12 schematically illustrates a structural diagram of a substrate 10 according to Embodiment 2 of the present disclosure;
[0032] Figure 13 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step Al;
[0033] Figure 14 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step A2;
[0034] Figure 15 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step B;
[0035] Figure 16 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step C;
[0036] Figure 17 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step D;
[0037] Figure 18 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step E;
[0038] Figure 19 schematically illustrates a structural diagram of an object prepared according to Embodiment 2 of the present disclosure through Step F;
[0039] Figure 20 schematically illustrates a structural diagram of a MOS device according to Embodiment 3 of the present disclosure.
[0040] Reference Signs:
[0041] 10 - substrate; 11 - trench structure; 12 - trench; 20 - carbon transfer layer; 30 - h-BNC layer; 31 - h-BN layer; 40 - buffer layer; 50 - leakage prevention layer; 51 - isolation layer; 60 - gate electrode; 70 - source electrode. DETAILED DESCRIPTION
[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it would be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and
[0043] The terms used herein are merely used to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0044] Embodiment 1
[0045] Figure 1 A structure diagram of a MOS device according to Embodiment 1 of the present disclosure is schematically shown.
[0046] As Figure 1 shown, Embodiment 1 of the present disclosure provides a MOS device, which includes a substrate 10, a carbon transfer layer 20, an h-BNC layer 30, a buffer layer 40, a leakage prevention layer 50, a source electrode 70, a gate electrode 60, and an isolation layer 51.
[0047] The upper surface of the substrate 10 is a planar structure.
[0048] The carbon transfer layer 20 is disposed on one side of the upper surface of the substrate 10, and the carbon transfer layer 20 contains C elements.
[0049] The h-BNC layer 30 is disposed on the other side of the upper surface of the substrate 10.
[0050] The buffer layer 40 is disposed above the carbon transfer layer 20 and the h-BNC layer 30, and the material used for the buffer layer 40 is h-BN.
[0051] The leakage prevention layer 50 is disposed above the buffer layer 40, and the material used for the leakage prevention layer 50 is AI2O3.
[0052] The source electrode 70 is disposed on the lower surface of the substrate 10.
[0053] The gate electrode 60 is disposed above the leakage protection layer 50.
[0054] An isolation layer 51 is disposed on one side of the carbon transport layer 20, the h-BNC layer 30, the buffer layer 40 and the leakage prevention layer 50, with its upper end contacting the gate electrode 60 and its lower end contacting the substrate 10.
[0055] Furthermore, the materials used for the carbon transport layer 20, the h-BNC layer 30, and the buffer layer 40 all have hexagonal and two-dimensional layered structures; the material used for the substrate 10 has a hexagonal wurtzite structure.
[0056] Since the substrate 10 has a hexagonal wurtzite structure, the selection of the hexagonal carbon transport layer 20, h-BNC layer 30 and buffer layer 40 will better match the substrate 10.
[0057] Furthermore, the thickness of the buffer layer 40 is 3–20 nm.
[0058] Furthermore, the thickness of the anti-leakage layer 50 is 3–100 nm.
[0059] Furthermore, the substrate 10 is made of one of the following materials: {0001} SiC epitaxial material, {1100} SiC epitaxial material, or {1120} SiC epitaxial material.
[0060] Meanwhile, the substrate 10 in this disclosure may also include one or more power electronic semiconductor materials such as silicon, gallium nitride, gallium oxide, and diamond.
[0061] Furthermore, the materials used in the isolation layer 51 include SiO2 and SiO2. x Si3N4 or Si x N y At least one of them.
[0062] Figure 2 A flowchart illustrating a method for fabricating a MOS device according to Embodiment 1 of this disclosure is shown schematically.
[0063] like Figure 2 As shown, Embodiment 1 of this disclosure also provides a method for fabricating a MOS device, including steps A to F.
[0064] Before performing step A, the substrate 10 needs to be cleaned.
[0065] Specifically, the substrate 10 is ultrasonically cleaned at least once with acetone and ethanol in sequence, and then rinsed with deionized water.
[0066] The organically ultrasonicated substrate 10 is boiled in a mixture of concentrated sulfuric acid and hydrogen peroxide for at least 10 minutes.
[0067] The substrate 10 boiled in concentrated sulfuric acid is boiled in No. 1 liquid and No. 2 liquid for 15 minutes in turn, washed with deionized water, and dried with nitrogen for standby.
[0068] The washed substrate 10 is soaked in diluted hydrofluoric acid for 1 minute until the surface oxide is removed, and the soaked substrate 10 is washed with deionized water and dried after washing.
[0069] The No. 1 liquid is a mixture of ammonia, hydrogen peroxide and deionized water, with a volume ratio of ammonia: hydrogen peroxide: deionized water = 1:2:5. The No. 2 liquid is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5. The diluted hydrofluoric acid has a volume ratio of hydrogen fluoride: deionized water = 1:3.
[0070] Step A includes steps A01 and A02.
[0071] Figure 3 The structural schematic diagram of the substrate 10 according to Embodiment 1 of the present disclosure is schematically shown.
[0072] Figure 4 The structural schematic diagram of the object prepared through Step A1 according to Embodiment 1 of the present disclosure is schematically shown.
[0073] Step A01: A carbon transfer layer 20 is prepared on one side of the upper surface of the substrate 10.
[0074] Specifically, graphite is grown on one side of the upper surface of the substrate 10 as shown in FIG. 1 to form the carbon transfer layer 20 by chemical vapor deposition (CVD) or epitaxy. Figure 3 The prepared object is as shown in FIG. 2. Figure 4
[0075] The growth temperature is 900-1800°C, and H2 or Ar can be used for annealing treatment during the growth process, and the annealing temperature is 1200-1700°C.
[0076] Figure 5 The structural schematic diagram of the object prepared through Step A2 according to Embodiment 1 of the present disclosure is schematically shown.
[0077] Step A02: An h-BN layer 31 is prepared on the other side of the upper surface of the substrate 10.
[0078] Specifically, h-BN material is grown on the other side of the upper surface of the substrate 10 as shown in FIG. 3 to form the h-BN layer 31 by ion beam sputtering deposition (IBSD). Figure 4 The prepared object is as shown in FIG. 4. Figure 5
[0079] The h-BN layer 31 and the carbon transfer layer 20 coexist on the upper surface of the substrate 10.
[0080] Figure 6 The schematic diagram shows the structure of the object obtained by step B according to Embodiment 1 of this disclosure.
[0081] Step B: React the h-BN material contained in the h-BN layer 31 with the C element contained in the carbon transport layer 20 to form the h-BNC layer 30.
[0082] Specifically, through chemical vapor deposition (CVD) and high-temperature thermal annealing processes, Figure 5 The h-BN material in the h-BN layer 31 reacts with the C element in the carbon transport layer 20 to transform into a ternary hybrid h-BNC material, thereby forming the h-BNC layer 30. The resulting object is as follows: Figure 6 As shown.
[0083] In the high-temperature annealing process, the annealing temperature is 1150-1600℃.
[0084] Figure 7 The diagram illustrates the structure of the object obtained by step C according to Embodiment 1 of this disclosure.
[0085] Step C: Prepare a buffer layer 40 on the carbon transport layer 20 and the h-BNC layer 30.
[0086] Specifically, this involves using chemical vapor deposition (CVD) or physical vapor deposition on... Figure 6 h-BN material is grown on the carbon transport layer 20 and the h-BNC layer 30 to form a buffer layer 40. The resulting object is as follows: Figure 7 As shown.
[0087] Figure 8 The schematic diagram illustrates the structure of the object obtained by step D according to Embodiment 1 of this disclosure.
[0088] Step D: An isolation layer 51 is prepared on the upper surface of the substrate 10 on one side of the carbon transport layer 20, the h-BNC layer 30, the buffer layer 40 and the leakage prevention layer 50.
[0089] Specifically, this involves using methods such as chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition, or thin film sputtering to... Figure 7 On the upper surface of the substrate 10 on one side of the carbon transport layer 20, h-BNC layer 30, buffer layer 40, and leakage prevention layer 50, a passivation dielectric material is deposited, and the deposited product is photolithographically etched to form an isolation layer 51. The resulting object is an h-BN / h-BNC / SiC heterojunction, such as... Figure 8 As shown.
[0090] The passivation medium material can be SiO2 or SiO2. xSi3N4 or Si x N y It can also be SiO2 or SiO x Si3N4 and Si x N y The combination of .
[0091] Figure 9 The diagram illustrates the structure of the object obtained by step E according to Embodiment 1 of this disclosure.
[0092] Step E: Prepare a leakage prevention layer 50 on the buffer layer 40.
[0093] Specifically, for Figure 8 The h-BN / h-BNC / SiC heterojunction in the sample is annealed at a temperature of 400℃ to 1300℃ in an annealing atmosphere of N2, Ar, NO, NH3 or N2O for 0.2 to 3 hours.
[0094] Methods such as chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition, or thin film sputtering are used to... Figure 8 A high-quality Al2O3 thin film is deposited on the buffer layer 40 to form a leakage prevention layer 50. The resulting object is as follows: Figure 9 As shown.
[0095] Step F: A gate electrode 60 is fabricated on the leakage prevention layer 50 and the isolation layer 51; a source electrode 70 is fabricated on the lower surface of the substrate 10.
[0096] Specifically, this involves using methods such as electron beam evaporation or sputtering, in... Figure 9 A metal thin film is deposited on the leakage protection layer 50 and the isolation layer 51. The metal thin film is transformed into a gate electrode 60 by combining photolithography and etching technology.
[0097] The material used for the gate electrode 60 includes at least one of Ti, Al, Ni, W, Mo, Ag, Au and Pt.
[0098] Through methods such as electron beam evaporation or sputtering, in Figure 9 Another metal thin film is deposited on the lower surface of the intermediate substrate 10, and the metal thin film is annealed to form an ohmic contact, thus completing the fabrication of the source electrode 70. The resulting object is as follows: Figure 1 As shown.
[0099] The source electrode 70 is made of at least one of Ni, Ti, W, Ag and Au.
[0100] Example 2
[0101] Figure 10 A schematic diagram of the structure of a MOS device according to Embodiment 2 of this disclosure is shown.
[0102] As Figure 10 Embodiment 2 of the present disclosure provides a MOS device, comprising a substrate 10, a carbon transfer layer 20, an h-BNC layer 30, a buffer layer 40, an anti-leakage layer 50, a source electrode 70, a gate electrode 60 and an isolation layer 51.
[0103] The upper part of the substrate 10 is provided with a groove 12, which is divided into a left groove and a right groove. The right groove is taken as an example for description below.
[0104] The carbon transfer layer 20 is arranged on one side of the groove bottom / groove sidewall surface in the right groove, and the carbon transfer layer 20 contains C elements.
[0105] The h-BNC layer 30 is arranged on the other side of the groove bottom / groove sidewall surface in the right groove.
[0106] The buffer layer 40 is arranged above the carbon transfer layer 20 and the h-BNC layer 30 of the groove bottom / groove sidewall, and the material of the buffer layer 40 is h-BN.
[0107] The anti-leakage layer 50 is arranged above the buffer layer 40 of the groove bottom / groove sidewall, and the material of the anti-leakage layer 50 is Al2O3.
[0108] The source electrode 70 is arranged on the lower surface of the substrate 10.
[0109] The gate electrode 60 is arranged above the anti-leakage layer 50.
[0110] The isolation layer 51 is arranged on one side of the carbon transfer layer 20, the h-BNC layer 30, the buffer layer 40 and the anti-leakage layer 50 of the groove bottom, and the upper end contacts the gate electrode 60 and the lower end contacts the substrate 10.
[0111] Further, the materials of the carbon transfer layer 20, the h-BNC layer 30 and the buffer layer 40 all have hexagonal structure and two-dimensional layered structure; and the material of the substrate 10 has hexagonal wurtzite structure.
[0112] Since the substrate 10 has hexagonal wurtzite structure, the carbon transfer layer 20, the h-BNC layer 30 and the buffer layer 40 with hexagonal structure are selected to better match the substrate 10.
[0113] Further, the thickness of the buffer layer 40 is 3-20 nm.
[0114] Further, the thickness of the anti-leakage layer 50 is 3-100 nm.
[0115] Further, the material of the substrate 10 includes one of {0001} face SiC epitaxial material, {1100} face SiC epitaxial material or {1120} face SiC epitaxial material.
[0116] Meanwhile, the substrate 10 in the present disclosure can also include one or more of silicon, gallium nitride, gallium oxide, diamond, and other power electronic semiconductor materials.
[0117] Further, the material used for the isolation layer 51 includes at least one of SiO2, SiO x , Si3N4, or Si x N y .
[0118] Figure 11 A flow chart of a method for manufacturing a MOS device according to the embodiment 2 of the present disclosure is schematically shown.
[0119] As shown in the embodiment 2 of the present disclosure, a method for manufacturing a MOS device is also provided, which includes steps A-F. Figure 11
[0120] Before performing step A, the substrate 10 needs to be cleaned first.
[0121] Specifically, the substrate 10 is cleaned with acetone and ethanol by ultrasonic cleaning at least once, and then the substrate 10 is washed with deionized water.
[0122] The substrate 10 after organic ultrasonic cleaning is placed in a mixed solution of concentrated sulfuric acid and hydrogen peroxide and boiled for at least 10 min.
[0123] The substrate 10 boiled in concentrated sulfuric acid is boiled in the first liquid and the second liquid for 15 min, respectively, and then washed with deionized water and dried with nitrogen for standby.
[0124] The washed substrate 10 is placed in diluted hydrofluoric acid and soaked for 1 min until the surface oxides are removed, and then the soaked substrate 10 is cleaned with deionized water and dried after cleaning.
[0125] The first liquid is a mixed solution of ammonia, hydrogen peroxide, and deionized water, with a volume ratio of ammonia:hydrogen peroxide:deionized water = 1:2:5. The second liquid is a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water, with a volume ratio of hydrochloric acid:hydrogen peroxide:deionized water = 1:2:5. The diluted hydrofluoric acid has a volume ratio of hydrogen fluoride:deionized water = 1:3.
[0126] Figure 12 A structural schematic diagram of the trench structure 11 according to the embodiment 2 of the present disclosure is schematically shown.
[0127] Before performing step A, the substrate 10 is etched by physical etching or chemical etching to form the trench structure 11.
[0128] The etching method can be reactive ion etching (RIE) or inductively coupled plasma (ICP), and the etching gas includes at least one of SF6 / O2, NF3 / Ar, CF4, HBr, CHF3 / O2 and C4F8 / O2. During the etching process, the inductively coupled plasma (ICP) has a power of 600W-1000W, a bias power of 100W-300W, and a temperature of 17°C-70°C.
[0129] The depth of the trench 12 in the trench structure 11 obtained by etching is 0.5-3μm.
[0130] The step A includes steps A01 and A02.
[0131] Figure 13 The structure schematic diagram of the object obtained by step A1 in Embodiment 2 of the present disclosure is schematically shown.
[0132] The right trench is taken as an example for illustration.
[0133] Step A01: a carbon transfer layer 20 is prepared on one side of the upper surface of the right trench.
[0134] Specifically, graphite is grown on one side of the trench bottom / trench sidewall surface in the right trench as shown in FIG. 2B to form the carbon transfer layer 20 by chemical vapor deposition (CVD) or epitaxy. The obtained object is as shown in FIG. 2C. Figure 13 Figure 13
[0135] The growth temperature is 900-1800°C, and annealing treatment can be performed by using H2 or Ar during the growth process, and the annealing temperature is 1200-1700°C.
[0136] Figure 14 The structure schematic diagram of the object obtained by step A2 in Embodiment 2 of the present disclosure is schematically shown.
[0137] Step A02: an h-BN layer 31 is prepared on the other side of the upper surface of the right trench.
[0138] Specifically, h-BN material is grown on the other side of the trench bottom / trench sidewall surface in the right trench as shown in FIG. 3B to form the h-BN layer 31 by ion beam sputtering deposition (IBSD). The obtained object is as shown in FIG. 3C. Figure 4 Figure 14
[0139] The h-BN layer 31 and the carbon transfer layer 20 coexist on the upper surface of the right trench.
[0140] Figure 15 The structure schematic diagram of the object obtained by step B in Embodiment 2 of the present disclosure is schematically shown.
[0141] Step B: React the h-BN material contained in the h-BN layer 31 with the C element contained in the carbon transport layer 20 to form the h-BNC layer 30.
[0142] Specifically, through chemical vapor deposition (CVD) and high-temperature thermal annealing processes, Figure 15 The h-BN material in the h-BN layer 31 reacts with the C element in the carbon transport layer 20 to transform into a ternary hybrid h-BNC material, thereby forming the h-BNC layer 30. The resulting object is as follows: Figure 15 As shown.
[0143] In the high-temperature annealing process, the annealing temperature is 1150-1600℃.
[0144] Figure 16 The diagram illustrates the structure of the object obtained by step C according to Embodiment 2 of this disclosure.
[0145] Step C: Prepare a buffer layer 40 on the carbon transport layer 20 and the h-BNC layer 30.
[0146] Specifically, this involves using chemical vapor deposition (CVD) or physical vapor deposition on... Figure 16 h-BN material is grown on the carbon transport layer 20 and the h-BNC layer 30 to form a buffer layer 40. The resulting object is as follows: Figure 16 As shown.
[0147] Figure 17 The schematic diagram illustrates the structure of the object obtained by step D according to Embodiment 2 of this disclosure.
[0148] Step D: Prepare an isolation layer 51 on the upper surface of the right trench on one side of the carbon transport layer 20, h-BNC layer 30, buffer layer 40 and leakage prevention layer 50.
[0149] Specifically, this involves using methods such as chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition, or thin film sputtering to... Figure 17 On the upper surface of the right trench on one side of the carbon transport layer 20, h-BNC layer 30, buffer layer 40, and leakage prevention layer 50, a passivation dielectric material is deposited, and the deposited product is photolithographically lithographically formed to form the isolation layer 51. The resulting object is an h-BN / h-BNC / SiC heterojunction, such as... Figure 17 As shown.
[0150] The passivation medium material can be SiO2 or SiO2. x Si3N4 or Si x N y It can also be SiO2 or SiO x Si3N4 and Si x Ny The combination of .
[0151] Figure 18 The diagram illustrates the structure of the object obtained in step E according to embodiment 2 of this disclosure.
[0152] Step E: Prepare a leakage prevention layer 50 on the buffer layer 40.
[0153] Specifically, for Figure 18 The h-BN / h-BNC / SiC heterojunction in the sample is annealed at a temperature of 400℃ to 1300℃ in an annealing atmosphere of N2, Ar, NO, NH3 or N2O for 0.2 to 3 hours.
[0154] Methods such as chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition, or thin film sputtering are used to... Figure 17 A high-quality Al2O3 thin film is deposited on the buffer layer 40 to form a leakage prevention layer 50. The resulting object is as follows: Figure 18 As shown.
[0155] Figure 19 The schematic diagram shows the structure of the object obtained by step F according to embodiment 2 of this disclosure.
[0156] Step F: A gate electrode 60 is fabricated on the leakage protection layer 50 and the isolation layer 51; a source electrode 70 is fabricated on the lower surface of the right trench.
[0157] Specifically, this involves using methods such as electron beam evaporation or sputtering, in... Figure 18 A metal thin film is deposited on the leakage protection layer 50 and the isolation layer 51. The metal thin film is transformed into a gate electrode 60 by combining photolithography and etching technology.
[0158] The material used for the gate electrode 60 includes at least one of Ti, Al, Ni, W, Mo, Ag, Au and Pt.
[0159] Through methods such as electron beam evaporation or sputtering, in Figure 18 Another metal thin film is deposited on the lower surface of the right trench, and the metal thin film is annealed to form an ohmic contact, thus completing the fabrication of the source electrode 70.
[0160] The source electrode 70 is made of at least one of Ni, Ti, W, Ag, and Au. The resulting object is as follows: Figure 19 As shown.
[0161] The same process is applied to the left trench as to the right trench, resulting in the following: Figure 10 The MOS device shown is in which the isolation layer 51 of the left trench contacts the isolation layer 51 of the right trench.
[0162] Example 3
[0163] Figure 20 A structural schematic diagram of a MOS device according to Embodiment 3 of the present disclosure is schematically shown.
[0164] All operations in Embodiment 2 are performed, the intermediate isolation layer 51 is removed, and the left trench and the right trench are combined completely symmetrically to form a MOS device as shown in Figure 20 .
[0165] The specific embodiments described above further illustrate the purposes, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only for specific embodiments of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A MOS device, characterized by, The application relates to a carbon-based field effect transistor, which comprises the following parts: a substrate (10); a carbon transmission layer (20) arranged on one side of the upper surface of the substrate (10), wherein the carbon transmission layer (20) contains C elements; an h-BNC layer (30) arranged on the other side of the upper surface of the substrate (10); a buffer layer (40) arranged above the carbon transmission layer (20) and the h-BNC layer (30), wherein the buffer layer (40) is made of h-BN; an anti-creeping layer (50) arranged above the buffer layer (40), wherein the anti-creeping layer (50) is made of Al2O3; a source electrode (70) arranged on the lower surface of the substrate (10); a gate electrode (60) arranged above the anti-creeping layer (50); an isolation layer (51) arranged on one side of the carbon transmission layer (20), the h-BNC layer (30), the buffer layer (40) and the anti-creeping layer (50), wherein the upper end of the isolation layer (51) is connected with the gate electrode (60), and the lower end of the isolation layer (51) is connected with the substrate (10).
2. The MOS device of claim 1, wherein, The materials used in the carbon transmission layer (20), the h-BNC layer (30) and the buffer layer (40) all have hexagonal structure and two-dimensional layer structure; and the material used in the substrate (10) has hexagonal wurtzite structure.
3. The MOS device of claim 1, wherein, The thickness of the buffer layer (40) is 3-20 nm.
4. The MOS device of claim 1, wherein, The thickness of the anti-creeping layer (50) is 3-100 nm.
5. The MOS device of claim 1, wherein, The substrate (10) is made of materials including {000} } SiC epitaxial material, {1 00} SiC epitaxial material or {11 One type of SiC epitaxial material with a 0} plane.
6. The MOS device of claim 1, wherein, The material used for the isolation layer (51) includes at least one of SiO x 2 x N y 7. A method of manufacturing a MOS device according to any one of claims 1 to 6, characterized by, The application further discloses a preparation method of the carbon-based field effect transistor. The application discloses a preparation method of the carbon-based field effect transistor, which comprises the following steps: step A: a carbon transmission layer (20) is prepared on one side of the upper surface of a substrate (10), and an h-BN layer (31) is prepared on the other side of the upper surface of the substrate (10); step B: chemical vapor deposition and high-temperature heat annealing processes are adopted to make h-BN material contained in the h-BN layer (31) react with C elements contained in the carbon transmission layer (20), so that the h-BN material is converted into ternary hybrid h-BNC material, thereby forming an h-BNC layer (30), wherein the reaction temperature is 1150-1600 DEG C; step C: a buffer layer (40) is prepared on the carbon transmission layer (20) and the h-BNC layer (30); step D: an isolation layer (51) is prepared on the upper surface of the substrate (10) on one side of the carbon transmission layer (20), the h-BNC layer (30) and the buffer layer (40); step E: an anti-creeping layer (50) is prepared on the buffer layer (40); wherein the upper surface of the anti-creeping layer (50) is flush with the upper surface of the isolation layer (51); step F: a gate electrode (60) is prepared on the anti-creeping layer (50) and the isolation layer (51); 8. The method of fabricating a MOS device of claim 7, wherein, and step G: a source electrode (70) is prepared on the lower surface of the substrate (10). The step A comprises the following steps: step A1: graphite is grown on the upper surface of the substrate (10); step A2: the graphite is subjected to annealing treatment, so as to form the carbon transmission layer (20); 9. The method of claim 7, wherein the step of forming the gate oxide layer is performed by thermal oxidation. wherein the growth temperature is 900-1800 DEG C, and the annealing temperature is 1200-1700 DEG C. The step E comprises the following steps: step E1: before the anti-creeping layer (50) is prepared, the object prepared in step D is subjected to annealing treatment; wherein the annealing temperature is 400 DEG C-1300 DEG C, and the annealing time is 0.2-3 hours.
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