Scan chain testing method and system for digital integrated circuit and digital integrated circuit

Abstract

The present invention provides a scan chain test method and system for a digital integrated circuit. The method includes converting a switching vector and an input data vector into a combination vector according to a preset rule, and then generating a combination signal according to the combination vector and inputting it into the digital integrated circuit, and then separating the combination signal in the digital integrated circuit to obtain a switching signal and an input data signal, and then performing a scan chain test. By combining the original two signals into one signal and inputting it into the digital integrated circuit, the demand for a PAD port is reduced. Therefore, only three PAD ports are needed to perform a scan chain test. Specifically, one PAD port is used to input a combination signal, one PAD port is used to input a system clock, and the last PAD port is used to output an output signal of the scan chain. The test coverage and observability of a digital integrated circuit with only three PAD ports are improved, thereby improving the quality of mass production testing.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuit testing, and more specifically, to a scan chain testing method and system for a digital integrated circuit and a digital integrated circuit. Background Art

[0002] Design for Test (DFT) is an important part of digital integrated circuit design. DFT refers to inserting various hardware logics into the original design of digital integrated circuits to improve the testability (including controllability and observability) of digital integrated circuits, thereby making digital integrated circuits easy to test and significantly saving the testing costs of digital integrated circuits.

[0003] Scan chain testing is an important method of DFT technology. This method can set the state of each trigger in the circuit from outside the digital integrated circuit, and through the design of a simple scan chain, scan and observe whether the trigger is working in a normal state, so as to detect the correctness of the circuit.

[0004] Digital integrated circuits are composed of a large number of combinational components and sequential components. The sequential components are specifically embodied as a single D-type flip-flop (DFF). The basic components of digital integrated circuits are as follows: Figure 1 As shown, the system clock (CLOCK) is used to control the input and output of the corresponding data of the data ports (including D and Q) of each DFF.

[0005] Scan chain testing is to replace the sequential element DFF in the digital integrated circuit with the corresponding scannable sequential element scan trigger (SDFF); then connect the output terminal Q of the previous SDFF to the data input terminal of the next SDFF, thereby forming a test serial shift register from input to output, namely the scan chain; through the control of CLOCK, the test of sequential elements and combinational logic is realized. The circuit after the scan chain design is realized is as follows Figure 2 shown.

[0006] After adopting the scan design technology, under the control of the switching signal SEN at the scan chain control end and the system clock CLOCK at the clock end, the required data can be serially shifted to the scan register unit through the input data signal SDI at the scan chain data input end, and each unit can be serially controlled; at the same time, they can also be serially observed through the output signal SDO at the scan chain output end. This increases the controllability and observability of the timing circuit. In the prior art, the specific workflow of the scan chain test after scan design is as follows:

[0007] 1. Set the digital integrated circuit to SCAN mode. At this time, the clock of the internal SDFF is unified into the system clock SLOCK of the clock end, and SDFF is triggered by the rising edge;

[0008] 2. When the switching signal SEN at the scan chain control end is 1, the scan chain is fully connected, and the output of the internal SDFF is the input of the next level SDFF, which is connected in series in sequence;

[0009] 3. Input an input data vector to the internal SDFF of the digital integrated circuit through the input data signal SDI at the data input end of the scan chain until the value of the internal SDFF is equal to the expected value;

[0010] 4. Set SEN = 0 for one cycle. During this cycle, the value of each SDFF will be updated to the input value under normal function.

[0011] 5. Set SEN = 1 and keep it, so that the data of the scan chain is output from the output end of the scan chain, and compare it with the theoretical result;

[0012] 6. After the current test vector is tested, continue to the next test vector test until all input test vectors have completed the test.

[0013] From the above introduction to existing scan chain tests, it can be seen that the existing scan chain test scheme requires digital integrated circuits to have four PAD ports, which serve as the scan chain control terminal, clock terminal, scan chain data input terminal and scan chain output terminal respectively. However, digital integrated circuits in certain fields, such as radio frequency chips, cannot provide four PAD ports for scan chain design, which makes it impossible to implement scan chain design for such chips; for such chips, scan chain testing can only be replaced by functional vector testing at present, but the functional vector needs to be generated manually rather than by tools, which will have two disadvantages: first, it is necessary to increase more design process work; second, the artificially generated functional vector cannot accurately judge the test coverage of digital integrated circuits, and cannot guarantee the quality of mass production testing, which has a high application risk. Summary of the invention

[0014] In view of this, the present invention provides a scan chain testing method and system for a digital integrated circuit and a digital integrated circuit to improve the quality of mass production testing.

[0015] In order to achieve the above objectives, the proposed solution is as follows:

[0016] In a first aspect, a scan chain testing method for a digital integrated circuit is provided, comprising:

[0017] Cross-arrange the data in the switching vector and the input data vector to obtain a combined vector;

[0018] Generate a corresponding combined signal according to the combined vector;

[0019] separating the combined signal into a switching signal and an input data signal in the digital integrated circuit;

[0020] Performing a scan chain test on the digital integrated circuit using the switching signal, the input data signal and the system clock to obtain an actual output signal of the digital integrated circuit;

[0021] The theoretical output data vector is compared with the actual output signal to obtain the scan chain test result.

[0022] Preferably, generating a corresponding combined signal according to the combined vector includes:

[0023] Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width equal to half a period of the system clock, and 1 corresponds to a high level with a width equal to half a period of the system clock;

[0024] Separating the combined signal into a switching signal and an input data signal in the digital integrated circuit comprises:

[0025] The combined signal is used as the input signal of a falling edge triggered trigger in the digital integrated circuit, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger obtained is one of the switching signal and the input data signal, and the combined signal is the other of the switching signal and the input data signal.

[0026] Preferably, generating a corresponding combined signal according to the combined vector includes:

[0027] Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock;

[0028] Separating the combined signal into a switching signal and an input data signal in the digital integrated circuit comprises:

[0029] The scanning logic circuit of the digital integrated circuit is used to separate the parts of the combined signal corresponding to the odd cycles and the even cycles of the system clock to obtain a switching signal and an input data signal.

[0030] In a second aspect, a scan chain test system for a digital integrated circuit is provided, comprising: an MCU and the digital integrated circuit;

[0031] The MCU is used to cross-arrange the data in the switching vector and the input data vector to obtain a combined vector;

[0032] The MCU is further used to generate a corresponding combination signal according to the combination vector;

[0033] The digital integrated circuit is used to separate the combined signal into a switching signal and an input data signal;

[0034] The digital integrated circuit is further used to perform a scan chain test using the switching signal, the input data signal and the system clock to obtain an actual output signal and output it;

[0035] The MCU is also used to compare the theoretical output data vector with the actual output signal of the digital integrated circuit to obtain the scan chain test result.

[0036] Preferably, the MCU is specifically used for:

[0037] Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width equal to half a period of the system clock, and 1 corresponds to a high level with a width equal to half a period of the system clock;

[0038] The digital integrated circuit includes a scan logic circuit, which includes a falling edge triggered trigger, the combination signal is used as the input signal of the falling edge triggered trigger, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger is one of the switching signal and the input data signal, and the combination signal is the other of the switching signal and the input data signal.

[0039] Preferably, the MCU is specifically used for:

[0040] Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock;

[0041] The scanning logic circuit further includes a separation circuit, and the separation circuit is specifically used for:

[0042] The parts of the combined signal corresponding to the odd-numbered cycles and the even-numbered cycles of the system clock are separated to obtain a switching signal and an input data signal.

[0043] Preferably, the separation circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first NOT gate and a second NOT gate, wherein the first trigger, the second trigger, the third trigger, the fourth trigger and the fifth trigger are all D-type triggers triggered by rising edges;

[0044] The data input terminal of the first trigger is used to receive the combination signal, and the data output terminal of the first trigger is connected to the data input terminal of the second trigger and the data input terminal of the third trigger respectively;

[0045] The data output terminal of the second trigger is connected to the data input terminal of the fourth trigger;

[0046] The data input terminal of the fifth flip-flop is connected to the output terminal of the first NOT gate, the input terminal of the first NOT gate is connected to the data output terminal of the fifth flip-flop, the clock terminal of the fifth flip-flop is connected to the output terminal of the second NOT gate, and the input terminal of the second NOT gate is used to receive the system clock;

[0047] One input end of the AND gate is used to receive the system clock, the other input end of the AND gate is connected to the data output end of the fifth flip-flop, and the output end of the AND gate is respectively connected to the clock ends of the third flip-flop and the fourth flip-flop;

[0048] The clock ends of the first trigger and the second trigger are both used to receive the system clock, the output signal of the third trigger is one of the switching signal and the input data signal, and the output signal of the fourth trigger is the other of the switching signal and the input data signal.

[0049] In a third aspect, a digital integrated circuit is provided, comprising:

[0050] a scanning logic circuit, configured to separate a combination signal received from the MCU into a switching signal and an input data signal, wherein the combination signal is a combination signal generated by the MCU according to the combination vector after the MCU cross-arranges the data in the switching vector and the input data vector to obtain the combination vector; and

[0051] It is used to perform a scan chain test using the switching signal, the input data signal and the system clock, obtain an actual output signal and output it to the MCU, so that the MCU compares the theoretical output data vector with the actual output signal to obtain a scan chain test result.

[0052] Preferably, the scanning logic circuit includes a falling edge triggered trigger;

[0053] The combination signal is specifically a combination signal generated by the MCU according to the fact that 0 in the combination vector corresponds to a low level with a width equal to half a cycle of the system clock, and 1 corresponds to a high level with a width equal to half a cycle of the system clock;

[0054] The falling edge triggered flip-flop is used to:

[0055] The combined signal is used as the input signal of the falling edge triggered trigger, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger is one of the switching signal and the input data signal, and the combined signal is the other of the switching signal and the input data signal.

[0056] Preferably, the scanning logic circuit comprises a separation circuit;

[0057] The combination signal is specifically a combination signal generated by the MCU according to the fact that 0 in the combination vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock;

[0058] The separation circuit is used for:

[0059] The parts of the combined signal corresponding to the odd-numbered cycles and the even-numbered cycles of the system clock are separated to obtain a switching signal and an input data signal.

[0060] Preferably, the separation circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first NOT gate and a second NOT gate, wherein the first trigger, the second trigger, the third trigger, the fourth trigger and the fifth trigger are all D-type triggers triggered by rising edges;

[0061] The data input terminal of the first trigger is used to receive the combination signal, and the data output terminal of the first trigger is connected to the data input terminal of the second trigger and the data input terminal of the third trigger respectively;

[0062] The data output terminal of the second trigger is connected to the data input terminal of the fourth trigger;

[0063] The data input terminal of the fifth flip-flop is connected to the output terminal of the first NOT gate, the input terminal of the first NOT gate is connected to the data output terminal of the fifth flip-flop, the clock terminal of the fifth flip-flop is connected to the output terminal of the second NOT gate, and the input terminal of the second NOT gate is used to receive the system clock;

[0064] One input end of the AND gate is used to receive the system clock, the other input end of the AND gate is connected to the data output end of the fifth flip-flop, and the output end of the AND gate is respectively connected to the clock ends of the third flip-flop and the fourth flip-flop;

[0065] The clock ends of the first trigger and the second trigger are both used to receive the system clock, the output signal of the third trigger is one of the switching signal and the input data signal, and the output signal of the fourth trigger is the other of the switching signal and the input data signal.

[0066] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0067] The above technical solution provides a method and system for testing the scan chain of a digital integrated circuit. The method includes converting a switching vector and an input data vector into a combination vector according to a preset rule, and then generating a combination signal according to the combination vector and inputting it into the digital integrated circuit, and then separating the combination signal in the digital integrated circuit to obtain a switching signal and an input data signal, and then performing a scan chain test. By combining the original two signals into one signal and inputting it into the digital integrated circuit, the demand for a PAD port is reduced. Therefore, only three PAD ports are needed to perform a scan chain test. Specifically, one PAD port is used to input a combination signal, one PAD port is used to input a system clock, and the last PAD port is used to output the output signal of the scan chain. The test coverage and observability of digital integrated circuits with only three PAD ports are improved, thereby improving the quality of mass production testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0069] Figure 1 A schematic diagram of the basic components of a digital integrated circuit;

[0070] Figure 2 Circuit diagram after implementing scan chain design for digital integrated circuit;

[0071] Figure 3 A flow chart of a scan chain testing method for a digital integrated circuit provided by an embodiment of the present invention;

[0072] Figure 4 A schematic diagram of a combined signal provided by an embodiment of the present invention;

[0073] Figure 5 A schematic diagram of a falling edge triggered trigger provided by an embodiment of the present invention;

[0074] Figure 6It is a schematic diagram of a test vector during testing in the prior art;

[0075] Figure 7 A schematic diagram of a test vector provided by an embodiment of the present invention during testing;

[0076] Figure 8 A schematic diagram of a separation circuit provided by an embodiment of the present invention;

[0077] Fig. 9 A schematic diagram of another test vector provided by an embodiment of the present invention during testing;

[0078] Fig.10 A schematic diagram of a scan chain testing system for a digital integrated circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0080] See also Figure 3 , a scan chain testing method for a digital integrated circuit provided in this embodiment, the method comprises the following steps:

[0081] S31: Cross-arrange the data in the switching vector and the input data vector to obtain a combined vector.

[0082] After the logic synthesis of the digital circuit to be tested in the digital integrated circuit, the corresponding test vector is automatically generated according to the designed digital circuit through the EDA software for subsequent mass production testing. The test vector includes the system clock vector SCAN_CLK, the switching vector SCAN_SE, the input data vector SCAN_IN and the output data vector SCAN_OUT. The system clock vector SCAN_CLK consists of 0 and 1 and contains time information (i.e., the level width corresponding to 0 and 1). The switching vector SCAN_SE consists of 0 / 1 and contains time information (i.e., the level width corresponding to 0 and 1). The input data vector SCAN_IN consists of 0 and 1, and its length is the number of triggers in the digital integrated circuit to be tested. The output data vector SCAN_OUT consists of 0 and 1; the output data vector SCAN_OUT is the theoretical output data vector, which is used to compare with the actual output signal of the scan chain to obtain the scan chain test result.

[0083] Cross-arranging the data in the switching vector and the input data vector means alternately obtaining data from the switching vector and the input data vector and arranging them in sequence. Specifically, a data may be obtained from the input data vector first, and then a data may be obtained from the switching vector, and the acquisition may be performed alternately until all the data in the input data vector and the switching vector are acquired; it should be noted that the switching vector and the input data vector have the same length. The data in the switching vector and the input data vector are arranged in chronological order. When cross-arranging the data in the switching vector or the input data vector, the data is acquired in sequence in the order in which they are arranged.

[0084] S32: Generate a corresponding combined signal according to the combined vector.

[0085] In the present invention, the combination signal is a timing level signal composed of high and low levels; if the data in the combination vector is 0, a low level of a fixed width is generated, and if the data in the combination vector is 1, a high level of a fixed width is generated, thereby generating a corresponding combination signal. The fixed width can be half a cycle of the system clock. If T represents one cycle of the system clock, the fixed width is T / 2. The system clock is generated according to the system clock vector SCAN_CLK. The fixed width can also be one cycle of the system clock, that is, T.

[0086] For the case of a fixed width of T / 2, a level with a width greater than 0 and less than T / 2 is generated when generating a combinational signal. The level can be a high level or a low level, so that the level with a width of T / 2 generated according to 0 or 1 in the combinational vector crosses the rising edge or falling edge of the system clock, and then the system clock can be used as the input clock of the trigger to collect the information of the switching vector and input data vector in the combinational signal. Figure 4 , is a combined signal, 0 and 1 both correspond to levels with a width of T / 2.

[0087] S33: Separating the combined signal into a switching signal and an input data signal in the digital integrated circuit.

[0088] The digital integrated circuit includes a scan logic circuit; specifically, a separation circuit is set in the scan logic circuit of the digital integrated circuit, and the separation circuit is used to separate the combined signal into a switching signal and an input data signal. The scan logic circuit refers to a dedicated scan logic circuit in the digital integrated circuit under test, due to the existence of a scan chain design. The main function of the scan logic circuit is to define the switching signal, input data signal, system clock and input and output ports corresponding to the output signal of the digital integrated circuit under test in the scan chain test mode, as well as the selection logic in the SCAN mode and non-SCAN mode.

[0089] It should be pointed out that in the prior art, a switching signal is generated according to a switching vector, and an input data signal is generated according to an input data vector, and then the switching signal and the input data signal are respectively input into a digital integrated circuit through a PAD port; in this embodiment, the switching vector and the input data vector are first combined together according to a certain rule to generate a combination vector, and a combination signal is generated according to the combination vector, and the combination signal is input into the digital integrated circuit, and the combination signal is separated into a switching signal and an input data signal in the scan logic circuit of the digital integrated circuit. In this way, the solution provided by the present invention can also perform scan chain testing on digital integrated circuits with only three PAD ports. The input data signal and the switching signal are also timing level signals composed of high and low levels.

[0090] S34: Perform a scan chain test on the digital integrated circuit using the switching signal, the input data signal and the system clock to obtain an actual output signal of the digital integrated circuit.

[0091] The present invention can adopt the process of inputting the switching signal, the input data signal and the system clock into the scan chain of the digital integrated circuit in the prior art to test the scan chain of the digital integrated circuit. The specific test process will not be described in detail in this embodiment. It should be pointed out that the actual output signal of the digital integrated circuit obtained in step S34 is the signal actually output by the scan chain of the digital integrated circuit.

[0092] S35: Compare the theoretical output data vector with the actual output signal of the digital integrated circuit to obtain a scan chain test result.

[0093] The process of comparing the theoretical output data vector and the actual output signal of the digital integrated circuit in the prior art to obtain the scan chain test result can also be adopted by the present invention. The specific comparison process will not be described in detail in this embodiment.

[0094] For the case where the fixed width is T / 2, that is, for the case where the combination signal is generated according to the 0 in the combination vector corresponding to the low level with a width equal to half the period of the system clock, and the 1 corresponding to the high level with a width equal to half the period of the system clock, the separation circuit in the scanning logic circuit of the digital integrated circuit is a falling edge triggered flip-flop. The combination signal is used as the input signal of the falling edge triggered flip-flop, and the system clock is used as the input clock of the falling edge triggered flip-flop. The output signal of the falling edge triggered flip-flop is one of the switching signal and the input data signal, and the combination signal is the other of the switching signal and the input data signal.

[0095] Whether the output signal of the falling edge triggered trigger is specifically a switching signal or an input data signal is related to the combination vector. For example, the data of the input data vector in the combination vector is before the data of the switching vector, that is, when data is obtained alternately from the switching vector and the input data vector and arranged in sequence, data is obtained from the input data vector first; in this case, the output signal of the falling edge triggered trigger is a switching signal, and since the input data signal in the combination signal can still be collected on the rising edge of the system clock, the combination signal is directly input as the input data signal to the trigger in the digital integrated circuit under test. The data of the input data vector in the combination vector is after the data of the switching vector; in this case, the output signal of the falling edge triggered trigger is an input data signal, and since the switching signal in the combination signal can still be collected on the rising edge of the system clock, the combination signal is directly used as a switching signal. The triggers in the digital integrated circuit under test are all rising edge triggered.

[0096] See also Figure 5 , is a falling edge triggered trigger provided in this embodiment, which is composed of a rising edge triggered D type trigger and a NOT gate, the output end of the NOT gate is connected to the clock input end of the D type trigger, the input end of the NOT gate is used to input the system clock, the signal input end of the D type trigger is used to input the combination signal, and the signal output end of the D type trigger outputs one of the switching signal and the input data signal.

[0097] See also Figure 6 , which is a schematic diagram of the test vector in the prior art during testing. The input data signal is generated according to the input data vector, and the switching signal is generated according to the switching vector. Both the input data signal and the switching signal are timing level signals composed of high and low levels. In the prior art, both 0 and 1 in the input data vector correspond to a level with a width of one cycle of the system clock. Specifically, when the data of the input data vector is 1, a high level with a width of T is generated, and when the data is 0, a low level with a width of T is generated to obtain the input data signal. Similarly, the switching signal is obtained. Both the input data signal and the switching signal can be collected at the rising edge of the system clock.

[0098] The initial state of the trigger refers to the initial state of a series of triggers on the scan chain inside the digital integrated circuit under test. The initial state of the trigger is equal to the default value, and in this embodiment, the default is all 0. After the trigger is loaded, it means that during the period when the switching signal continues to be 1 (i.e., high level), the input data signal loaded into the trigger is triggered by the rising edge of the system clock.

[0099] See also Figure 7, is a schematic diagram of the test vector during testing when the fixed width is T / 2 in an embodiment of the present invention. 0 and 1 in the combination vector both correspond to a level with a width of T / 2, and a level with a width greater than 0 and less than T / 2 is generated at the beginning, so that the switching signal is separated at the falling edge of the system clock, and because the input data signal in the combination signal can be collected at the rising edge of the system clock, the combination signal is directly used as the input data signal for testing.

[0100] For the case where the width is fixed to T, that is, according to the combination vector, 0 corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock, a combination signal is generated, and the separation circuit separates the parts of the combination signal corresponding to the odd cycles and even cycles of the system clock to obtain a switching signal and an input data signal. And the number of cycles of the system clock is doubled to separate the combination signal. In some specific embodiments, the separation circuit in the scanning logic circuit of the digital integrated circuit includes: a first trigger D1, a second trigger D2, a third trigger D3, a fourth trigger D4, a fifth trigger D5, a first NOT gate N1, a second NOT gate N2 and an AND gate A, such as Figure 8 The first trigger D1, the second trigger D2, the third trigger D3, the fourth trigger D4 and the fifth trigger D5 are all rising edge triggered D type triggers.

[0101] See also Figure 8 , the data input terminal D of the first trigger D1 is used to receive the combination signal; the data output terminal Q of the first trigger D1 is connected to the data input terminal D of the second trigger D2 and the data input terminal D of the third trigger D3 respectively. The data output terminal Q of the second trigger D2 is connected to the data input terminal of the fourth trigger D4. The data input terminal D of the fifth trigger D5 is connected to the output terminal of the first NOT gate N1, and the input terminal of the first NOT gate N1 is connected to the data output terminal Q of the fifth trigger D5. The clock terminal CLK of the fifth trigger D5 is connected to the output terminal of the second NOT gate N2; the input terminal of the second NOT gate N2 is used to receive the system clock. The fifth trigger D5, the non-first NOT gate N1 and the second NOT gate N2 form a 1-bit counter; the fifth trigger D5 and the second NOT gate N2 form a falling edge triggered trigger, using the falling edge triggered logic to ensure that the generated gated clock has no glitches.

[0102] One input end of the AND gate A is used to receive the system clock, the other input end of the AND gate is connected to the data output end Q of the fifth flip-flop D5, and the output end of the AND gate is respectively connected to the clock end CLK of the third flip-flop D3 and the fourth flip-flop D4.

[0103] The clock terminals CLK of the first trigger D1 and the second trigger D2 are both used to receive the system clock. The output signal of the third trigger D3 is one of the switching signal and the input data signal, and the output signal of the fourth trigger D4 is the other of the switching signal and the input data signal. Which signal the third trigger D3 and the fourth trigger D4 specifically output is related to the combination vector. For example, the data of the input data vector in the combination vector is before the data of the switching vector. In this case, the third trigger D3 outputs the switching signal and the fourth trigger D4 outputs the data input signal; the data of the input data vector in the combination vector is after the data of the switching vector, then the third trigger D3 outputs the data input signal and the fourth trigger D4 outputs the switching signal. In this way, the combination signal is separated once every two system clock cycles, and the width of 0 and 1 in the obtained data input signal and the switching signal is two system clock cycles. Therefore, the number of system clock cycles should be doubled to perform scan chain testing.

[0104] Only when the fifth flip-flop D5 outputs 1, the AND gate A outputs the system clock, thereby separating the parts of the combined signal corresponding to the odd and even cycles of the system clock. Fig. 9 , is a schematic diagram of the test vector during testing when the fixed width is T in an embodiment of the present invention.

[0105] See also Fig.10 , a scan chain test system for a digital integrated circuit is provided for this embodiment, including: an MCU and a digital integrated circuit. The MCU is used to cross-arrange the data in the switching vector and the input data vector to obtain a combination vector; the MCU is also used to generate a corresponding combination signal according to the combination vector.

[0106] The digital integrated circuit is used to separate the combined signal into a switching signal and an input data signal; the digital integrated circuit is also used to perform a scan chain test using the switching signal, the input data signal and the system clock to obtain and output the actual output signal. The MCU is also used to compare the theoretical output data vector with the actual output signal of the digital integrated circuit to obtain the scan chain test result.

[0107] The present embodiment also provides a digital integrated circuit, which includes a scan logic circuit. The scan logic circuit is used to separate the combination signal received from the MCU into a switching signal and an input data signal. The combination signal is a combination signal generated according to the combination vector after the MCU cross-arranges the data in the switching vector and the input data vector to obtain the combination vector; the scan logic circuit is also used to perform a scan chain test using the switching signal, the input data signal and the system clock to obtain an actual output signal and output it to the MCU, so that the MCU compares the theoretical output data vector with the actual output signal of the digital integrated circuit to obtain a scan chain test result.

[0108] As for the system and digital integrated circuit embodiments, since they are basically corresponding to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. Those skilled in the art can understand and implement them without creative work.

[0109] In this article, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0110] Each embodiment in this specification focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other, and the features recorded in each embodiment in this specification can be replaced or combined with each other.

[0111] The above description of the embodiments disclosed in the present invention enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A scan chain testing method for a digital integrated circuit, characterized in that: include: Cross-arrange the data in the switching vector and the input data vector to obtain a combined vector; Generate a corresponding combined signal according to the combined vector; separating the combined signal into a switching signal and an input data signal in the digital integrated circuit; Performing a scan chain test on the digital integrated circuit using the switching signal, the input data signal and the system clock to obtain an actual output signal of the digital integrated circuit; The theoretical output data vector is compared with the actual output signal to obtain the scan chain test result.

2. The scan chain testing method according to claim 1, characterized in that: Generating a corresponding combined signal according to the combined vector includes: Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width equal to half a period of the system clock, and 1 corresponds to a high level with a width equal to half a period of the system clock; Separating the combined signal into a switching signal and an input data signal in the digital integrated circuit comprises: The combined signal is used as the input signal of a falling edge triggered trigger in the digital integrated circuit, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger obtained is one of the switching signal and the input data signal, and the combined signal is the other of the switching signal and the input data signal.

3. The scan chain testing method according to claim 1, characterized in that: Generating a corresponding combined signal according to the combined vector includes: Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock; Separating the combined signal into a switching signal and an input data signal in the digital integrated circuit comprises: The scanning logic circuit of the digital integrated circuit is used to separate the parts of the combined signal corresponding to the odd cycles and the even cycles of the system clock to obtain a switching signal and an input data signal.

4. A scan chain test system for a digital integrated circuit, characterized in that: Comprising: MCU and the digital integrated circuit; The MCU is used to cross-arrange the data in the switching vector and the input data vector to obtain a combined vector; The MCU is further used to generate a corresponding combination signal according to the combination vector; The digital integrated circuit is used to separate the combined signal into a switching signal and an input data signal; The digital integrated circuit is further used to perform a scan chain test using the switching signal, the input data signal and the system clock to obtain an actual output signal and output it; The MCU is also used to compare the theoretical output data vector with the actual output signal of the digital integrated circuit to obtain the scan chain test result.

5. The scan chain test system according to claim 4, characterized in that: The MCU is specifically used for: Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width equal to half a period of the system clock, and 1 corresponds to a high level with a width equal to half a period of the system clock; The digital integrated circuit includes a scan logic circuit, which includes a falling edge triggered trigger, the combination signal is used as the input signal of the falling edge triggered trigger, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger is one of the switching signal and the input data signal, and the combination signal is the other of the switching signal and the input data signal.

6. The scan chain test system according to claim 4, characterized in that: The MCU is specifically used for: Generate the combined signal according to the fact that 0 in the combined vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock; The digital integrated circuit includes a scanning logic circuit, and the scanning logic circuit includes a separation circuit, and the separation circuit is specifically used for: The parts of the combined signal corresponding to the odd-numbered cycles and the even-numbered cycles of the system clock are separated to obtain a switching signal and an input data signal.

7. The scan chain test system according to claim 6, characterized in that: The separation circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first NOT gate and a second NOT gate, wherein the first trigger, the second trigger, the third trigger, the fourth trigger and the fifth trigger are all D-type triggers triggered by a rising edge; The data input terminal of the first trigger is used to receive the combination signal, and the data output terminal of the first trigger is connected to the data input terminal of the second trigger and the data input terminal of the third trigger respectively; The data output terminal of the second trigger is connected to the data input terminal of the fourth trigger; The data input terminal of the fifth flip-flop is connected to the output terminal of the first NOT gate, the input terminal of the first NOT gate is connected to the data output terminal of the fifth flip-flop, the clock terminal of the fifth flip-flop is connected to the output terminal of the second NOT gate, and the input terminal of the second NOT gate is used to receive the system clock; One input end of the AND gate is used to receive the system clock, the other input end of the AND gate is connected to the data output end of the fifth flip-flop, and the output end of the AND gate is respectively connected to the clock ends of the third flip-flop and the fourth flip-flop; The clock ends of the first trigger and the second trigger are both used to receive the system clock, the output signal of the third trigger is one of the switching signal and the input data signal, and the output signal of the fourth trigger is the other of the switching signal and the input data signal.

8. A digital integrated circuit, characterized in that: include: A scanning logic circuit is used to separate a combination signal received from the MCU into a switching signal and an input data signal, wherein the combination signal is a combination signal generated by the MCU according to the combination vector after the MCU cross-arranges the data in the switching vector and the input data vector to obtain the combination vector; as well as It is used to perform a scan chain test using the switching signal, the input data signal and the system clock, obtain an actual output signal and output it to the MCU, so that the MCU compares the theoretical output data vector with the actual output signal to obtain a scan chain test result.

9. The digital integrated circuit according to claim 8, characterized in that: The scanning logic circuit includes a falling edge triggered trigger; The combination signal is specifically a combination signal generated by the MCU according to the fact that 0 in the combination vector corresponds to a low level with a width equal to half a cycle of the system clock, and 1 corresponds to a high level with a width equal to half a cycle of the system clock; The falling edge triggered flip-flop is used to: The combined signal is used as the input signal of the falling edge triggered trigger, and the system clock is used as the input clock of the falling edge triggered trigger, the output signal of the falling edge triggered trigger is one of the switching signal and the input data signal, and the combined signal is the other of the switching signal and the input data signal.

10. The digital integrated circuit according to claim 8, characterized in that: The scanning logic circuit includes a separation circuit; The combination signal is specifically a combination signal generated by the MCU according to the fact that 0 in the combination vector corresponds to a low level with a width of one cycle of the system clock, and 1 corresponds to a high level with a width of one cycle of the system clock; The separation circuit is used for: The parts of the combined signal corresponding to the odd-numbered cycles and the even-numbered cycles of the system clock are separated to obtain a switching signal and an input data signal.

11. The digital integrated circuit according to claim 10, characterized in that: The separation circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first NOT gate and a second NOT gate, wherein the first trigger, the second trigger, the third trigger, the fourth trigger and the fifth trigger are all D-type triggers triggered by a rising edge; The data input terminal of the first trigger is used to receive the combination signal, and the data output terminal of the first trigger is connected to the data input terminal of the second trigger and the data input terminal of the third trigger respectively; The data output terminal of the second trigger is connected to the data input terminal of the fourth trigger; The data input terminal of the fifth flip-flop is connected to the output terminal of the first NOT gate, the input terminal of the first NOT gate is connected to the data output terminal of the fifth flip-flop, the clock terminal of the fifth flip-flop is connected to the output terminal of the second NOT gate, and the input terminal of the second NOT gate is used to receive the system clock; One input end of the AND gate is used to receive the system clock, the other input end of the AND gate is connected to the data output end of the fifth flip-flop, and the output end of the AND gate is respectively connected to the clock ends of the third flip-flop and the fourth flip-flop; The clock ends of the first trigger and the second trigger are both used to receive the system clock, the output signal of the third trigger is one of the switching signal and the input data signal, and the output signal of the fourth trigger is the other of the switching signal and the input data signal.

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