Power redistribution for memory devices

Abstract

In one embodiment, a data storage device includes a plurality of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density including one or more memory dies. The die density of each memory die package is configured to provide uniform heat distribution across the plurality of memory die packages. The respective die densities of two memories of the die package are different from each other.

Description

Background Technology

[0001] This application relates generally to data storage devices, and more specifically to distributing power to thermally flattened components within a memory device to improve the characteristics of the memory device, such as data retention and performance.

[0002] Generally, in data storage devices, specifically in commercial data storage devices such as solid-state drives (“SSDs”), the temperature of the memory die (e.g., NAND die) is a critical parameter that allows the performance of the memory device to be adjusted to ensure that the memory die temperature does not exceed a predetermined threshold. Since a given data storage device contains multiple memory dies, these multiple memory dies are typically evaluated as a single device with respect to temperature. Therefore, the memory die with the highest temperature determines the amount of adjustment (e.g., performance) applied to the data storage device as a whole. Because the hottest memory die controls the performance of the data storage device, this approach can lead to performance degradation of the data storage device. Summary of the Invention

[0003] Adjusting the performance of a data storage device based on the hottest component (such as the memory die) can unnecessarily degrade its performance. Thermal flattening of the components within the data storage device by reallocating power to certain components and / or placing higher-power components in cooler sections of the device can improve its performance.

[0004] One embodiment of this disclosure is a data storage device. The data storage device includes a plurality of memory die packages disposed on at least one substrate within the data storage device. Each of the plurality of memory die packages has a die density comprising one or more memory dies. The die density of each memory die package is configured to provide a uniform thermal distribution across the plurality of memory die packages. The die densities of two memory die packages from the plurality of memory die packages are different from each other.

[0005] Another embodiment of this disclosure is a method comprising performing thermal analysis on a memory device using an electronic processor, the memory device having an initial memory device design with multiple memory die packages. The method further comprises performing a thermal flattening operation on the memory device. The method further comprises updating the thermal analysis based on the thermal flattening operation, and determining whether the updated thermal analysis meets a predetermined threshold. The method further comprises generating a final memory device design in response to determining that the updated thermal analysis meets the predetermined threshold.

[0006] Another embodiment of this disclosure is a non-transitory computer-readable medium that enables an electronic processor to perform thermal analysis on a memory device including a plurality of memory die packages and to perform a thermal flattening operation on the memory device. The non-transitory computer-readable medium also enables the electronic processor to update the thermal analysis based on the thermal flattening operation, determine whether the updated thermal analysis meets a predetermined threshold, and generate an updated memory device design in response to determining that the updated thermal analysis meets the predetermined threshold.

[0007] Various aspects of this disclosure provide improvements to data storage devices. For example, allocating power to thermally flattened components within the data storage device provides improved data performance. This disclosure can be embodied in various forms, including hardware or circuitry controlled by software, firmware, or a combination thereof. The foregoing summary is intended only to give general insight into various aspects of this disclosure and is not intended to limit the scope of this disclosure in any way. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view illustrating an exemplary memory device according to some implementation schemes.

[0009] Figure 2 This illustrates some implementation schemes. Figure 1 A schematic diagram of the heat transfer circuit of a memory device.

[0010] Figure 3 It is a graph showing how the data retention of a memory device changes over time according to some implementation schemes.

[0011] Figure 4 It is a graph showing the relationship between the performance of a memory device and temperature according to some implementation schemes.

[0012] Figure 5 This is a block diagram illustrating a memory device according to some implementation schemes.

[0013] Figure 6 This illustrates some implementation schemes. Figure 5 A side view of the memory device.

[0014] Figure 7 This illustrates some implementation schemes. Figure 5 A block diagram for thermal analysis of memory devices.

[0015] Figure 8 This is a block diagram illustrating a memory device after power redistribution according to some implementation schemes.

[0016] Figure 9 This illustrates, according to some implementation schemes, the situation after power redistribution has taken place. Figure 5A block diagram for thermal analysis of memory devices.

[0017] Figure 10 This is a flowchart illustrating a process for thermally flattening a memory device according to some embodiments. Detailed Implementation

[0018] In the following description, numerous details, such as data storage device configuration and controller operation, are set forth to provide an understanding of one or more aspects of this disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of this application. The following description is intended only to give a general conception of various aspects of this disclosure and is not intended to limit the scope of this disclosure in any way. It should also be understood by those skilled in the art that the drawings are not drawn to scale and some features are exaggerated to highlight such features. Furthermore, it will be apparent to those skilled in the art that although this disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid-state memories, such as NOR, PCM (“phase-change memory”), ReRAM, or other solid-state memories.

[0019] Figure 1 This is a block diagram of an exemplary NAND die package 100, which includes a memory die 102 (such as a NAND memory die) attached to a substrate 104 via a die attachment film 106. The memory die 102 may include one or more stacks of dies (e.g., NAND dies), such as four memory dies, eight memory dies, sixteen memory dies, and / or other numbers of memory dies suitable for a given memory device or application. Figure 1In this example, substrate 104 is attached to printed circuit board (“PCB”) 108 via conductive coupling element 110 (such as solder balls or other solder joints). PCB 108 is then attached to housing 112 using thermal interface material (“TIM”) 114. TIM 114 can be a material configured to provide a low thermal resistance connection between PCB 108 and housing 112, allowing efficient heat transfer from PCB 108 and consequently from memory die 102 to housing 112. Memory die 102 and die attachment film 106 are covered with molding compound 116, such as thermosetting plastics, epoxy resins (e.g., cresol varnish or biphenyl), silica filters, or other molding compounds suitable for the application. Molding compound 116 is also attached to housing 112 using die TIM 118. In one example, die TIM 118 is similar in material and function to the described PCPTIM 114. However, in other examples, the die TIM 118 is a different material from the PCB TIM 114. The housing 112 may include a heatsink 120 along one or more portions of the housing 112 (such as the molding compound side of the NAND die 102). As will be described in more detail below, the heatsink 120 functions to transfer heat from the housing 112 to a surface having an ambient temperature T. A The surrounding air.

[0020] Figure 1 The memory device 100 is only used to illustrate the configuration of a general-purpose memory device and is not limited to the illustrated embodiment. Those skilled in the art will understand that the memory device may also include a control die and passive devices, and the NAND die 102 may include one or more stacks of NAND dies connected to a substrate to provide a predetermined amount of memory capacity, such as 8Gb to 1Tb.

[0021] Figure 2 The heat transfer circuit 200 of the memory device 100 is shown, and specifically the junction temperature T of the aforementioned memory die 102 is shown. J 202. For example Figure 2 As shown, the heat transfer circuit 200 is represented as a parallel resistor circuit. The first branch 204 of the parallel resistor circuit 200 represents heat transfer from the memory die 102 to the surrounding air via the die attachment film 106, substrate 104, conductive coupling element 110, PCB 108, PCB thermal interface material 114, and housing 112. Therefore, the first branch 204 includes the die attachment film thermal resistance 206, substrate thermal resistance 208, conductive coupling element thermal resistance 210, PCB resistance 212, housing thermal resistance 214, and housing-to-ambient thermal resistance 216. Thermal resistances 206, 208, 210, 212, 214, and 216 are coupled to a common point 218 representing the ambient temperature.

[0022] The second branch 220 of the parallel resistor circuit 200 represents the T of the NAND die 102 via molding compound 116, die thermal interface material 118, housing 112 and heat sink 120. J Heat transfer from 202 to the surrounding air. For example... Figure 2 As shown, the second branch 220 includes a molding compound thermal resistance 222, a thermal interface material 224, a housing / heat sink thermal resistance 226, and a heat sink-to-ambient thermal resistance 228. Thermal resistances 206, 208, 210, 212, 214, and 216 are coupled to a common point 218 representing the ambient temperature.

[0023] Since the heat transfer circuit 200 is a parallel circuit, the branch with the lowest thermal resistance will transfer the most heat from T. J 202 is conducted to the surrounding air (common point 218). Therefore, if the second branch 220 has a lower overall thermal resistance, more heat will be conducted through the second branch 220 than through the first branch 204. Similarly, if the first branch 204 has a lower overall thermal resistance than the second branch 220, more heat will be conducted through the first branch 204 than through the second branch 220. Furthermore, due to the parallel configuration represented by the parallel resistor circuit 200, reducing the thermal resistance of any one branch reduces the overall thermal resistance of the heat transfer circuit 200.

[0024] In some implementations, the heat transfer efficiency of memory device 100 can be improved by forcing air, such as through one or more fans, over housing 112 or heat sink 120. However, improving the heat transfer of memory device 100 by utilizing one or more fans may increase the power consumption of memory device 100, and increasing airflow by accelerating fan rotation speed typically requires applying more power to the fans. For large data centers, this additional power requirement can be significant, so simply adding fans or other forced ventilation systems to improve the performance of memory device 100 can result in undesirable power consumption for a given application.

[0025] Now go to Figure 3 The graph 300, according to some embodiments, illustrates the change in data retention of a memory device (such as memory device 100) over time. The data lines represent 20-year baselines 302, 10-year baselines 304, 2-year baselines 306, and 1-year baselines 308 within a temperature range of 25°C to 85°C. (As in...) Figure 3As can be seen, with increasing temperature, the data retention time (shown in years) decreases substantially linearly for each of the 20-year baseline 302, 10-year baseline 304, 2-year baseline 306, and 1-year baseline 308. Furthermore, at temperatures above 55°C, the data retention time begins to decline in less than a year. Therefore, reducing the temperature of memory devices (and specifically, the NAND dies within memory devices) is crucial to ensuring optimal data retention time.

[0026] Figure 4 A graph 400 is provided, which shows the NAND die performance 402 in response to changes in NAND die temperature 404. (As...) Figure 4 As shown, when the NAND die temperature 404 approaches the high temperature value (approximately 72.5°C), the NAND die performance 402 is essentially regulated (in...). Figure 4 In some examples, the NAND die temperature was adjusted to approximately 90%, or about 1540 MB / s, until the temperature dropped back to a lower threshold (approximately 68°C). Therefore, it is evident that by better regulating the NAND die temperature 404, large fluctuations in the NAND die performance 402 can be reduced. In some examples, this is done by regulating the NAND die performance 402 to prevent the NAND die temperature 404 from reaching high temperatures. However, by thermally flattening the NAND die, higher performance levels were achieved without increasing the NAND die temperature 404 beyond its high-temperature limit.

[0027] Now go to Figure 5 The figure shows a block diagram of a memory device 500 according to some embodiments. Figure 5 As shown, the memory device 500 includes a first circuit board 502 and a second circuit board 504. The first circuit board 502 includes NAND die packages 506, 508, 510, 512, 514, 516, 518, and 520 arranged in a 4×2 array. The second circuit board 504 includes NAND die packages 522, 524, 526, 528, 530, 532, 534, and 536, also arranged in a 4×2 array. The first circuit board 502 and the second circuit board 504 may be located inside a housing 538. In some embodiments, the housing 538 may be a metal housing, such as aluminum, steel, or other thermally conductive materials.

[0028] In some implementations, the first circuit board 502 and the second circuit board 504 may be positioned such that the sides (i.e., the rear sides) of the first circuit board 502 and the second circuit board 504, excluding the NAND die package, are positioned adjacent to each other. Simply go to Figure 6 This configuration shows the orientation of the first circuit board 502 and the second circuit board 504. Also... Figure 6As shown, other circuitry 540 is also illustrated. This other circuitry 540 may include various components such as a memory controller, host interface, registers, power supply, power regulation circuitry, read / write circuitry, and other components or circuitry required to operate the memory device 500. Figure 6 In the illustrated embodiment, the second circuit board 504 is positioned such that NAND die packages 522-536 face the housing 538. In contrast, the first circuit board 502 is positioned such that NAND die packages 506-520 face other circuitry 540. Therefore, NAND die packages 522-536 are closer to and / or attached to the housing 538, and will generally have better thermal conductivity characteristics than NAND die packages 506-520. Regarding Figure 5 and Figure 6 The memory device configurations and layouts described herein are for illustrative purposes only, and it is expected that the hot-flattening process and applications described herein can be used with any memory device configuration.

[0029] Return now Figure 5 Equal power is applied to and consumed by each of the NAND die packages 506-536 in the memory device 500. Although Figure 5 The power shown is equal to 0.528W, but it should be understood that various power levels can be applied for a given memory device or application. Since the same power is applied to each NAND die package 506-536, the temperature of the NAND die packages 506-536 is regulated based on their ability to dissipate heat and / or transfer it to the housing 538 and / or ambient air. Additionally, each NAND die package in NAND die packages 506-536 has the same die density (“DD”). Figure 5 The value is shown as X. It is conceivable that the number of dies represented by X can be any number of dies suitable for a given application or memory device (e.g., four, eight, sixteen).

[0030] Once the layout of the NAND die package and / or other components of the memory device (such as memory device 500) is known, a thermal analysis is performed on the memory device. In some examples, the thermal analysis is a simulated thermal analysis. For example, a simulation program (such as ANSYS Icepak or FloTHERM) can be used to perform the thermal analysis. In other examples, the thermal analysis can be performed on the physical memory device, such as by using a thermal imager (e.g., an IR imager), multiple thermocouples, or other thermal analysis equipment.

[0031] Now go to Figure 7An exemplary thermal analysis 700 of a NAND die package 506-536 for a memory device 500 according to some embodiments is shown. Figure 7 As shown, the darker the shadow, the higher the defined junction temperature (T0) of a specific NAND die package 506-536. J The higher the junction temperature, the lower the junction temperature. Similarly, the junction temperatures of the lighter-colored NAND die packages 506-536 are lower than those of the darker-colored NAND die packages 506-536. As shown in thermal analysis 700, NAND die packages 522 and 524 are the coolest; NAND die packages 526, 528, 530, and 532 are warmer than NAND die packages 522 and 524 but cooler than NAND die packages 534, 536, 506, 508, 514, 516, 518, and 520; and NAND die packages 534, 536, 506, and 508 are cooler than NAND die packages 522, 524, and 526. NAND die packages 528, 530, and 532 are warmer than NAND die packages 514, 516, 518, and 520. NAND die packages 514 and 516 are warmer than NAND die packages 522, 524, 526, 528, 530, 532, 534, 536, 506, and 508, but cooler than NAND die packages 518 and 520. Furthermore, NAND die packages 518 and 520 are the hottest dies on memory device 500. NAND die packages 522-536 are generally cooler than NAND die packages 506-520 because NAND die packages 522-536 are positioned closer to the housing 538. Figure 6 As shown, this allows more heat to be transferred to the housing 538. In contrast, the NAND die packages 506-520 are positioned further away from the housing 538, resulting in less efficient heat transfer to the housing 538.

[0032] Similarly, NAND die packages 506, 508, 510, 512, 522, 524, 526, and 528 have a cooler average temperature than NAND die packages 514, 516, 518, 520, 530, 532, 534, and 536. This is likely because the airflow 702 first flows through NAND die packages 506, 508, 510, 512, 522, 524, 526, and 528, and thus becomes warmer before flowing through NAND die packages 514, 516, 518, 520, 530, 532, 534, and 536, thereby reducing heat transfer efficiency.

[0033] In one example, the temperature range of the NAND die package 506-536 can be between 54.5°C and 68.6°C. However, other temperature ranges are conceivable, and the exemplary ranges provided above should not be construed as limiting. Furthermore, thermal analysis 700 is for illustrative purposes only, and it should be understood that different memory devices with different components, different component layouts, case types and configurations, airflow characteristics, etc., will provide different thermal characteristics.

[0034] Based on thermal analysis, such as thermal analysis 700, the memory device 500 can be thermally leveled by optimizing the power supplied to each NAND die package 506-536, keeping the overall power the same or nearly the same, but redistributing it among the NAND die packages 506-536 so that more power is supplied to and consumed by packages in physically cooler locations compared to packages in physically warmer locations within the memory device 500. Power can be redistributed to the NAND die packages 506-536 in various ways. In one example, specific NAND die packages 506-536 are supplied with more power and configured to be accessed more frequently and / or configured to increase their data transfer rates to increase the power consumed by those NAND die packages 506-536. Similarly, NAND die packages 506-536 in the warmer regions of the memory device are supplied with less power, accessed less frequently, and / or configured to reduce their data transfer rates to decrease the power consumption of those NAND die packages 506-536. However, changing the access rate and / or the power supplied to different NAND die packages 506-536 can cause NAND die packages 506-536 with increased access frequency and / or increased data transfer rate to experience increased wear, resulting in a shorter lifespan. For example, overuse of some NAND die packages 506-536 can lead to increased bit error rate, shorter data retention time, etc.

[0035] In another embodiment, the density of NAND die packages 506-536 is varied to redistribute the power consumed by the NAND die packages. For example, NAND die packages, such as NAND die packages 506-536, may have multiple individual NAND dies (typically one stacked on top of another). Exemplary NAND die packages may include 2 dies, 4 dies, 8 dies, and 16 dies. However, NAND die packages with more than 16 dies or various numbers of dies between 1 and the maximum value are also contemplated. Generally speaking, the more dense the NAND die package (i.e., the greater the number of dies in the NAND die package), the more power the NAND die package consumes. For example, a NAND die package with 16 dies may consume approximately twice the power of a NAND die package with 8 dies. Therefore, by placing the NAND die packages 506-536 with higher die counts in cooler locations within the memory device, more power is allocated to the cooler areas of the memory device. Similarly, by placing the NAND die packages 506-536 with lower die counts in warmer locations within the memory device, less power is allocated to the cooler areas of the memory device, thus helping to prevent any single NAND die package from becoming too hot and degrading the performance of the memory device.

[0036] When the number of dies in a NAND die package is increased, additional channels can be provided to higher-density NAND die packages to ensure performance across NAND die packages. For example, an 8-die NAND die package may have two data channels, allowing one data channel to be available for every four dies. However, a 16-die NAND die package with only two data channels will only have one data channel available for every eight dies. Therefore, a 16-die NAND package may include four data channels to similarly have one data channel for every four dies. It is conceivable that different numbers of data channels may be used for different NAND die packages, and the above example is merely exemplary.

[0037] Now go to Figure 8 According to some implementations, the memory device 500 after hot-flattening is shown as a memory device 800. For example... Figure 8 As shown, the additional power has been redistributed to NAND die packages 822, 824, 826, 828, 830, and 832. Power to NAND die packages 806, 808, 810, 812, 814, 816, 834, and 836 remains the same, and power to NAND die packages 818 and 820 has been reduced. Figure 8In the thermally flattened memory device 800 shown, the total power is greater than that of the original memory device 500 configuration described above. However, in some examples, the total power may be the same as that of the non-thermally flattened memory device. For a given memory device configuration or application, this increase in power may be based on the ability of the NAND die package in a lower temperature region to transfer heat to the housing or ambient air.

[0038] like Figure 8 As further shown, the die density of die packages 806-836 is different for different die packages. The die density values ​​of die packages 806-836 are represented by values ​​W, X, Y, and Z, where W, X, Y, and Z represent different die density values. For example, die packages 806, 808, 810, 812, 814, 816, 834, and 836 have a die density X, similar to the values ​​mentioned above. Figure 5 The described die packages are 506, 508, 510, 512, 514, 516, 534, and 536. Die packages 818 and 820 have a die density W, which can be a lower die density than X, resulting in die packages 818 and 820 consuming less power. Conversely, die packages 826, 828, 830, and 832 can have a die density Y, which is a larger die density than die densities X and W (e.g., having more dies within the die package). Finally, die packages 822 and 824 can have a die density Z, which is a larger die density than W, X, and Y. It should be understood that the die densities represented by W, X, Y, and Z can be any positive integer die density value, such as four-die density, eight-die density, twelve-die density, sixteen-die density, and / or other die density values ​​suitable for a given memory device or application.

[0039] Now go to Figure 9 This illustrates a configuration based on some implementations. Figure 8 Thermal analysis 900 of the power redistribution memory device 800 shown. (As illustrated) Figure 9As shown, the temperature of the NAND die packages (806-836) (again shown as varying degrees of darkness (darker colors equal higher temperatures)) is more evenly distributed due to power redistribution. As mentioned above, the performance of memory devices (such as memory device 500) is typically limited by the temperature of the hottest NAND die. Therefore, by reducing the maximum temperature experienced by any of the NAND dies 806-836, the performance of memory device 800 can be increased accordingly. Additionally, by thermally flattening memory device 800, the fans associated with memory device 800 may be able to operate slower, or in some cases, be omitted, potentially reducing the power requirements of memory device 800. This can lead to an overall power reduction in large facilities such as server clusters, memory banks, etc. In one example, the power requirements of the memory device could be reduced by 3-5%. However, a power reduction greater than 5% is also conceivable.

[0040] While the thermal analysis 900 described above is the first iteration of thermal leveling performed on memory device 800, it is conceivable that multiple iterations can be performed to determine the optimal thermal leveling configuration. As will be described in more detail below, the thermal analysis and leveling described above can be performed using one or more computer programs, algorithms, machine learning algorithms, artificial intelligence (“AI”) programs, or other computer-implemented systems. For example, a resistive thermal network model combined with computational fluid dynamics simulation software (e.g., ANSYS Icepak or similar software) can be used to perform the thermal analysis described herein. Furthermore, one or more parameters or thresholds can be used to optimize thermal leveling. For example, thermal leveling aimed at maximizing data retention time may produce different results than thermal leveling aimed at maximizing performance (e.g., increased data throughput). For example, when the goal is to maximize data retention, reducing the maximum temperature of any given NAND die package may be prioritized. In contrast, when the goal is to maximize performance, maximizing the power to the NAND die package without overheating any particular NAND die package may be prioritized. In some examples, the performance target may be a percentage increase, such as a 10% performance increase. However, increases of more than 10% or less than 10% are also conceivable. Other combinations of performance and durability can be envisioned to enable optimal hot flattening.

[0041] Now go to Figure 10The present invention describes a process 1000 for hot-flattening a memory device, such as memory device 500, according to some embodiments. In some embodiments, process 1000 may be performed by a computer that performs analysis using various programs or algorithms, such as those described above. In some examples, a dedicated computing system may be used to perform process 1000. Any reference to “computer” should be understood to mean a computer, algorithm, processor, controller, or any other device or program configured to execute a series of instructions.

[0042] Process 1000 is described in relation to the aforementioned memory device 500. However, it should be understood that process 1000 can be applied to any memory device, such as solid-state drives, flash memory devices, consumer memory devices, etc.

[0043] At box 1002, a thermal profile of the memory device 500 is generated. As described above, one or more thermal simulation programs can be used to generate the thermal profile. In other examples, the thermal profile can be generated based on multiple temperature measurements performed on the physical memory device. The thermal profile can analyze certain components within the memory device 500, such as the NAND die packages 506-536. However, it is conceivable to perform thermal analysis on all components of the memory device 500 during thermal profile generation.

[0044] At process block 1004, the NAND die package is thermally flattened based on the generated thermal profile. As described above, the NAND die packages 506-536 can be thermally flattened based on one or more predetermined thresholds or other parameters, such as maximizing performance (e.g., data throughput), maximizing durability, balancing performance and durability, target power consumption, etc. In some examples, the NAND die packages are thermally flattened such that the average temperature of the NAND die packages is below a predetermined value. For example, the memory device 500 can be thermally flattened such that the average junction temperature of the NAND die packages is below 55°C. However, average junction temperatures above and below 55°C are also contemplated. In other examples, the memory device 500 can be thermally flattened such that the junction temperature of any individual NAND die package does not exceed a predetermined value. For example, the memory device 500 can be thermally flattened such that the junction temperature of each NAND die package does not exceed 55°C. However, temperatures above and below 55°C are also contemplated. The above example is for illustrative purposes only, and hot flattening can be performed to achieve any other objectives if applicable.

[0045] As described above, thermal flattening can alter the power consumed or supplied to individual NAND die packages 506-536. For example, the performance of the NAND die packages can be altered such that NAND die packages in hotter locations are reduced in size (e.g., data throughput is reduced), while NAND die packages in cooler locations are increased in size (e.g., data throughput is increased). In another embodiment, the density of NAND dies within the NAND die package can be varied to achieve the desired thermal flattening as described above. For example, the NAND die density of NAND die packages in cooler locations within the memory device 500 can be increased, and the NAND die density of NAND die packages in hotter locations within the memory device 500 can be decreased.

[0046] In response to the completion of thermal flattening, the thermal profile of the memory device 500 is updated at block 1006. In one embodiment, the thermal flattening configuration determined in block 1004 is used to perform the thermal profile performed in block 1002 again.

[0047] At block 1008, the performance of memory device 500 is determined. In one embodiment, the performance of memory device 500 is determined based on an updated thermal profile. In other embodiments, the performance of memory device 500 is determined based on an updated thermal profile and a thermally flattened configuration. For example, performance may be determined based on temperatures determined in the updated thermal profile, such as when the junction temperature of the die is targeted. In other examples, where the target is related to power consumption or the performance of the NAND die package (e.g., data throughput), performance may be determined based on the performance of the NAND die package or the power consumption of the thermally flattened memory device. In other examples, a combination of junction temperature, power consumption, and NAND die package performance may all be determined. In some examples, other factors such as fan power requirements, data storage capacity, etc., may also be used to determine the performance of memory device 500.

[0048] At box 1010, it is determined whether the performance of memory device 500 is satisfactory. Satisfactory performance is determined if the performance of memory device 500 meets or exceeds one or more thresholds (such as those mentioned above). In other examples, satisfactory performance is determined if the junction temperature of the average and / or individual NAND die packages is below a predetermined threshold. In yet another example, satisfactory performance is determined if the junction temperature of the NAND die packages is uniformly distributed across all or a predefined portion of the NAND die packages. Uniform temperature distribution among NAND die packages is determined when the junction temperatures are within ±5% of each other. However, uniform distribution values ​​greater than or less than 5% are also conceivable.

[0049] Other performance thresholds or targets may also be used to determine whether the performance of memory device 500 is satisfactory. In response to determining that the performance is unsatisfactory, memory device 500 is thermally flattened again at block 1004. In response to determining that the performance is satisfactory, a final design of memory device 500 is generated at block 1012 based on the thermally flattened configuration determined at block 1004. In some embodiments, the final design includes a redistribution of power to the NAND die package. For example, the final design may include the distribution of NAND die density in the NAND die package determined during the thermally flattening operation performed at block 1004.

[0050] Regarding the processes, systems, methods, heuristics, etc., described herein, it should be understood that although the steps of such processes are described as being performed according to an ordered sequence, such processes can be practiced with the steps performed in a sequence other than that described herein. It should also be understood that some steps may be performed simultaneously, other steps may be added, or some steps described herein may be omitted. In other words, the description of processes herein is provided for the purpose of illustrating certain specific implementations and should in no way be construed as limiting the claims.

[0051] Therefore, it should be understood that the above description is intended to be exemplary and not restrictive. Many embodiments and applications beyond the examples provided will be apparent upon reading the above description. The scope should not be determined by reference to the above description, but rather by reference to the full scope of the appended claims together with the equivalents to which such claims are entitled. It is anticipated and intended that the technology discussed herein will be further developed in the future, and the disclosed systems and methods will be incorporated into such future embodiments. In conclusion, it should be understood that modifications and variations are possible with this application.

[0052] All terms used in the claims are intended to be given their broadest reasonable construction and their common meaning as understood by one skilled in the art described herein, unless expressly indicated otherwise herein. Specifically, the use of singular articles such as “a,” “the,” “the,” etc., should be understood to mean one or more of the elements indicated in the statement, unless expressly limited to the contrary by the statement of the claims.

[0053] A summary of the specification is provided to allow readers to quickly determine the nature of the technical disclosure. It should be understood that the submitted content is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A data storage device, the data storage device comprising: a substrate; and a plurality of memory die packages disposed on the substrate, wherein each memory die package has a die density comprising one or more memory dies; wherein the die density of the memory die packages is configured to provide a uniform heat distribution across the plurality of memory die packages, and wherein respective die densities from two memory die packages of the plurality of memory die packages differ from each other, and wherein a thermal analysis is performed on the data storage device with an electronic processor, the data storage device having an initial data storage device design, a thermal flattening operation is performed on the data storage device, the thermal analysis is updated based on the thermal flattening operation; it is determined whether the updated thermal analysis satisfies a predetermined threshold; and in response to determining that the updated thermal analysis satisfies the predetermined threshold, a final data storage device design is generated.

2. The data storage device of claim 1, wherein a first die density from a first memory die package of the two memory die packages is greater than a second die density from a second memory die package of the two memory die packages.

3. The data storage device of claim 2, wherein the first memory die package is positioned in a first region of the data storage device and the second memory die package is positioned in a second region of the data storage device.

4. The data storage device of claim 3, wherein the first region is determined to be a lower temperature region than the second region based on a thermal analysis of the data storage device.

5. The data storage device of claim 2, wherein the first die density from the first memory die package of the two memory die packages comprises 16 memory dies.

6. The data storage device of claim 2, wherein the second die density from the second memory die package of the two memory die packages comprises 8 memory dies.

7. The data storage device of claim 1, wherein the uniform heat distribution is an average junction temperature of all of the plurality of memory die packages, the average junction temperature being below a predetermined threshold.

8. A method of operating a memory device, the method comprising: performing a thermal analysis on the memory device with an electronic processor, the memory device having an initial memory device design, the memory device comprising a plurality of memory die packages, each memory die package having a memory die density; performing a thermal flattening operation on the memory device; updating the thermal analysis based on the thermal flattening operation; determining whether the updated thermal analysis satisfies a predetermined threshold; and in response to determining that the updated thermal analysis satisfies the predetermined threshold, generating a final memory device design.

9. The method of claim 8, further comprising, in response to determining that the updated thermal analysis does not satisfy the predetermined threshold, performing a second thermal flattening operation of the memory device.

10. The method of claim 8, wherein the performing the thermal pull-up operation comprises reallocating power to one or more memory die packages of the plurality of memory die packages.

11. The method of claim 10, wherein the reallocating power to the one or more memory die packages of the memory device comprises changing respective memory die densities of the plurality of memory die packages.

12. The method of claim 11, wherein the respective memory die densities are selected from one or more of a group comprising: a two-die density, a four-die density, an eight-die density, and a sixteen-die density.

13. The method of claim 8, wherein the predetermined threshold comprises one or more of: a thermal threshold, a performance threshold, and a power consumption threshold.

14. The method of claim 13, wherein the thermal threshold comprises maintaining a junction temperature of each memory die package of the plurality of memory die packages below a predetermined value.

15. The method of claim 13, wherein the thermal threshold comprises maintaining an average junction temperature of all of the plurality of memory die packages below a predetermined value.

16. A non-transitory computer-readable medium having software instructions stored thereon that, when executed by an electronic processor, cause the electronic processor to perform a set of operations comprising: performing a thermal analysis of a memory device, the memory device comprising a plurality of memory die packages, each memory die package having a memory die density; performing a thermal pull-up operation of the memory device; updating the thermal analysis based on the thermal pull-up operation; determining whether the updated thermal analysis satisfies a predetermined threshold; and in response to determining that the updated thermal analysis satisfies the predetermined threshold, generating an updated memory device design.

17. The non-transitory computer-readable medium of claim 16, wherein performing the thermal pull-up operation comprises reallocating power to one or more memory die packages of the memory device.

18. The non-transitory computer-readable medium of claim 17, wherein the reallocating power to the one or more memory die packages of the memory device comprises changing respective memory die densities of the plurality of memory die packages.

19. The non-transitory computer-readable medium of claim 18, wherein the respective memory die densities are selected from one or more of a group comprising: a two-die density, a four-die density, an eight-die density, or a sixteen-die density.

20. The non-transitory computer-readable medium of claim 16, wherein the predetermined threshold comprises one or more of: a thermal threshold, a performance threshold, or a power consumption threshold.

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