Technology for die termination-based commands

Abstract

Examples include techniques for using die-based termination (ODT) commands. In some examples, values ​​are programmed into registers at the memory device to establish one or more internal resistor termination (RTT) settings for the ODT at the memory device. Values ​​are also programmed into registers at the memory device to establish one or more settings for ODT delay timing. The programmed values ​​can be changed to adjust the signal integrity of the memory device during read or write operations.

Description

[0001] This application is a divisional application of the same patent application filed on January 16, 2017, with application number 201780009831.7.

[0002] Related cases

[0003] This application claims priority under 35 USC §365(c) to U.S. Application No. 15 / 200,981, filed July 1, 2016, entitled “TECHNIQUES FOR COMMAND BASED ON DIE TERMINATION,” which in turn claims priority to U.S. Provisional Application No. 62 / 303,707, filed March 4, 2016, entitled “TECHNIQUES FOR COMMAND BASED ON DIE TERMINATION.” The entire disclosure of these documents is incorporated herein by reference for all purposes. Technical Field

[0004] The examples described in this article typically involve techniques for die termination at memory devices. Background Technology

[0005] In some memory systems coupled to a host computing device, multiple on-die termination (ODT) pins are provided to control the value of the internal resistance termination (RTT) and the on / off timing of the ODT. These ODT pins typically require coordination between the host computing device and the memory device to account for the appropriate amount of time for the RTT during read or write operations on the memory device. The ODT signal is often one of the largest components of the turnaround time delay or the delay between read or write operations. Attached Figure Description

[0006] Figure 1 An example memory device is shown.

[0007] Figure 2 An example of the first register encoding scheme is shown.

[0008] Figure 3 Example second register encoding scheme is shown.

[0009] Figure 4 Example first timing diagram is shown.

[0010] Figure 5 Example second timing diagram is shown.

[0011] Figure 6 Example third timing diagram is shown.

[0012] Figure 7An example block diagram of the device is shown.

[0013] Figure 8 An example of the logical flow is shown.

[0014] Figure 9 An example of a storage medium is shown.

[0015] Figure 10 An example computing platform is shown. Detailed Implementation

[0016] As anticipated in this disclosure, the ODT signal is typically one of the largest components of the turnaround time delay or latency between read or write operations at the memory device. Furthermore, the ODT pin, previously provided to the host computing device coupled to the memory device to adjust the RTT and the on / off time for the ODT, is being removed for new memory technologies under development, including but not limited to DDR5 (DDR version 5 is currently under discussion by JEDEC), LPDDR5 (LPDDR version 5, currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), and / or other new technologies based on derivatives or extensions of such specifications. Because the ODT pin is being removed, logic is being enabled at the memory device to allow ODT-related settings and / or adjustments to improve signal integrity for the memory device during read or write operations. Examples described herein are necessary to address the above and other challenges.

[0017] Figure 1 An exemplary memory device 100 is shown. In some examples, such as... Figure 1 As shown, memory device 100 includes various logic, features, or circuitry for accessing memory banks 130-1 to 130-n (where "n" is any positive integer > 2) in response to a received command. For example, memory device 100 may include peripheral circuitry for accessing memory banks 130-1 to 130-n, including a clock generator 101, an address command decoder 102, one or more mode registers 103, control logic 110, latch circuitry 140, an I / O buffer 150, or a DQ pin 160. Furthermore, each memory bank among memory banks 130-1 to 130-n may respectively include a memory bank control 120, a row address buffer 123, a column address buffer 121, a row decoder 123, a sense amplifier 125, a column decoder 122, or a data control 127.

[0018] According to some examples, control logic 110 may include logic and / or features capable of programming values ​​into one or more mode registers 103 and using those values ​​to adjust the RTT value of memory device 100 or to adjust one or more values ​​of ODT delay timing used to turn the corresponding RTT value (“tODTLon / off”) of memory device 100 on or off. For these examples, commands including information for programming values ​​into one or more mode registers 103 may be received via address command decoder 102. As described in more detail below, the various values ​​programmed into mode registers 103 may be based on one or more encoding schemes used to program values ​​into one or more mode registers 103. These values ​​may enable logic at memory device 100, such as control logic 110, to perform ODT-related settings and / or adjustments to improve signal integrity for memory device 100 during read or write operations, for example, by adjusting resistance values ​​or timing values ​​on the data bus to reduce bit errors.

[0019] In some examples, memory device 100 may include non-volatile memory types, such as DRAM memory. DRAM memory may be arranged to operate according to various developed memory technologies, which may include, but are not limited to, DDR4 (Double Data Rate (DDR) version 4, an initial specification released by JEDEC in September 2012), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, initially released by JEDEC in August 2014), WIO2 (WideI / O 2, JESD229-2, initially published by JEDEC in August 2014), HBM (High Bandwidth DRAM, JESD235, initially released by JEDEC in October 2013), and / or other technologies based on derivatives or extensions of these specifications. Memory device 100 may also include memory arranged to operate according to the aforementioned memory technologies currently under development, which may include, but are not limited to, DDR5, LPDDR5, or HBM2.

[0020] Although the example types of memory included in memory device 100 have been described as including volatile types of memory such as DRAM, this disclosure is not limited to DRAM. In some examples, this disclosure contemplates other volatile types of memory, including but not limited to Double Data Rate Synchronous Dynamic RAM (DDR SDRAM), Static Random Access Memory (SRAM), Thyristor RAM (T-RAM), or Zero Capacitor RAM (Z-RAM). Furthermore, this disclosure contemplates block-addressable, non-volatile types of memory, such as memory associated with NAND or NOR technologies. Additionally, this disclosure contemplates other non-volatile types of memory, such as byte-addressable 3-D cross-point memory. These block-addressable or byte-addressable non-volatile memory types may include, but are not limited to, non-volatile memory types using chalcogenide phase change materials (e.g., chalcogenide glass), multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque MRAM (STT-MRAM), or any combination thereof or other non-volatile memory types.

[0021] According to some examples, memory device 100 may be one of a plurality of memory devices or dies included on a dual in-line memory module (DIMM). The DIMM may be designed as a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM), or a small outline (SODIMM). Examples are not limited to these DIMM designs.

[0022] Figure 2 An exemplary register encoding scheme 200 is illustrated. In some examples, exemplary encoding scheme 200 may include a 3-bit value to program various RTT settings of a memory device such as memory device 100. Figure 2As shown, Table 210 includes programmable settings for RTT_PARK, Table 220 for RTT_WR (WR = Write), Table 230 for RTT_NOM_WR, and Table 240 for RTT_NOM_RD (RD = Read). For these examples, values ​​associated with various resistance settings in ohms (e.g., external resistance (RZQ)) can be programmed (e.g., via control logic 110) into one or more registers of the memory device, such as mode register 103 of memory device 100, based on Tables 210, 220, 230, or 240. The values ​​of RTT_PARK, RTT_WR, RTT_NOM_WR, or RTT_NOM_RD can then be adjusted (e.g., via control logic 110) using the values ​​included in each of these tables to improve or optimize the signal integrity of the memory device during read or write operations.

[0023] Figure 3 An example register encoding scheme 300 is shown. In some examples, example encoding scheme 300 may include a 3-bit value to program various tODTL / off settings of a memory device such as memory device 100. Figure 3 As shown, Table 310 includes programmable settings for tODTLon_WR, Table 320 for tODTLoff_WR, Table 330 for tODTLoff_WR_NT (NT = non-target), Table 340 for tODTLoff_WR_NT, Table 350 for tODTLon_RD, Table 360 ​​for tODTLoff_RD, Table 370 for tODTLon_RD_NT, and Table 380 for tODTLoff_RD_NT. For these examples, the values ​​in these tables can be adjustments to various default settings for tODTL based on clock units, which can be a clock cycle, a single clock cycle, or a portion of multiple clock cycles. Adjustments can be pushed out (+value) or pulled in (-value) for the settings for tODTLon / off, which can be programmed (e.g., via control logic 110) to one or more registers of a memory device, such as mode register 103 of memory device 100. As described in more detail below, these values ​​(e.g., via control logic 110) can then be used to adjust the settings for tODTLon_WR, tODTLoff_WR, tODTLoff_WR_NT, tODTLoff_WR_NT, tODTLon_RD, tODTLoff_RD, tODTLon_RD_NT, or tODTLoff_RD_NT to improve or adjust the signal integrity of the memory device during read or write operations.

[0024] Figure 4 Example timing diagram 400 is shown. In some examples, such as... Figure 4 The timing diagram 400 shown illustrates the timing of read-to-write turnarounds for the same row in two different rows. For these examples, the two different rows can be used for DIMM (D0) and are shown as R0 and R1. Figure 1 At least some of the elements of the memory device 100 shown can be used to describe the actions taken in relation to timing diagram 400. Examples are not limited to the elements of the memory device 100 used in timing diagram 400.

[0025] In some examples, the values ​​used to establish settings for RTT_PARK, RTT_WR, RTT_NOM_WR, and RTT_NOM_RD can be programmed or stored in mode register 103 for memory devices included in R0 or R1. These values ​​can be changed by programming different values ​​held in the mode register according to corresponding tables 210, 220, 230, and 240 of register encoding scheme 200, such as... Figure 2 As shown, this is to adjust or improve the signal integrity of the memory device. For example, the RZQ value of RTT_NOM_RD for D0 of R1 may include a mode register, such as mode register 103, which is initially programmed based on Table 240 to have a resistance setting of 80 ohms, which may negatively affect the signal integrity of the memory device included in R0 during read operations. To improve the signal integrity of the memory device included in R0 during read operations, mode register 103 for these memory devices may be reprogrammed to change the resistance setting to 40 ohms or 120 ohms according to Table 240 of register encoding scheme 200. Furthermore, the RTT_NOM_WR of the memory device included in R0 may include a mode register, such as mode register 103, which is initially programmed based on Table 330 to have a resistance of 240 ohms, which may negatively affect the signal integrity of the memory device included in R0 during write operations. To improve the signal integrity of memory devices included in R0 during read operations, mode registers such as mode register 103 for these memory devices can be reprogrammed according to Table 240 of register encoding scheme 200 to change the resistance setting below 240 ohms.

[0026] According to some examples, timing diagram 400 illustrates a Read-0 command on the command (CMD) bus, which is directed or targeted to D0 and row 0 (D0 R0 CS0), followed by a Write-0 command for the same row. For these examples, the values ​​of tODTLon_WR, tODTLoff_WR, tODTLon_WR_NT, and tODTLoff_WR_NT can be programmed or stored in the mode register (e.g., mode register 103) for the write command based on the corresponding tables 310, 320, 330, and 340 of register encoding scheme 300. Furthermore, tODTLon_RD, tODTLoff_RD, tODTLon_RD_NT, and tODTLoff_RD_NT can be programmed or stored in the mode register 103 for the read command based on the corresponding tables 350, 360, 370, and 380 of register encoding scheme 300.

[0027] According to some examples, the values ​​used to establish the settings for tODTLon / off can be changed by programming different values ​​into the mode register 103 to further improve the signal integrity of memory devices included in R0 during read operations. For example, when a read command is sent in signal form based on D0 R0 CS0, the read line (RL) can be activated for memory devices included in R0, and this can start timers for memory devices included in the target row R0 and for memory devices included in the non-target row R1, tODTLon_RD and tODTLoff_RD_NT. The setting for tODTLon_RD can indicate the amount of time before the ODT resistor value of RTT_RD is activated. The setting for tODTLoff_RD can indicate the amount of time before the ODT resistor value of RTT_RD is deactivated or disabled. The setting for tODTLon_RD_NT can indicate the amount of time before the ODT resistor value of RTT_NOM_RD is activated or enabled after RL is activated. The setting for tODTLoff_RD_NT can indicate the amount of time before the ODT resistor value of RTT_NOM_RD is deactivated or disabled.

[0028] Based on some examples, if the settings for tODTLon_RD_NT or tODTLoff_RD_NT are too short or too long, the signal integrity of the memory device included in R0 may be negatively affected during read operations. If negatively affected, then according to... Figure 3The register encoding scheme 300 shown allows mode registers, such as mode register 103 included in these memory devices, to be reprogrammed from default timing values ​​(e.g., 10 clock units) to push (+) or pull (-) a time length from the default timing value of tODTLon_RD_NT according to Table 370 and / or push (+) or pull (-) a time length from the default timing value of tODTLoff_RD_NT according to Table 380. This reprogramming allows RTT_NOM_RD to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 400 for read commands for memory devices included in R0.

[0029] In some examples, if the settings for tODTLon_RD or tODTLoff_RD are too short or too long, the signal integrity of the memory device included in R0 may also be negatively affected during read operations. If negatively affected, then according to Figure 3 The register encoding scheme 300 shown allows reprogramming of mode registers, such as mode register 103, included in these memory devices from default timing values ​​to push (+) or pull (-) a time length from the default timing value of tODTLon_RD according to Table 350 and / or push (+) or pull (-) a time length from the default timing value of tODTLoff_RD according to Table 360. This reprogramming allows RTT_RD to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 400 for read commands for memory devices included in R0.

[0030] According to some examples, the settings for tODTLon / off can be changed by programming different values ​​into the mode register 103 to further improve the signal integrity of memory devices included in R0 during write operations. For example, when a write command is sent in signal form based on D0 R0 CS0, the write line (WL) can be activated for memory devices included in R0, and this can start timers for memory devices with tODTLon_WR and tODTLoff_WR included in the target row R0 and for memory devices with tODTLon_WR_NT and tODTLoff_WR_NT included in the non-target row R1. The setting for tODTLon_WR can indicate the amount of time before the ODT resistor value of RTT_WR is activated. The setting for tODTLoff_WR can indicate the amount of time before the ODT resistor value of RTT_WR is deactivated or disabled. The setting for tODTLon_WR_NT can indicate the amount of time before the ODT resistor value of RTT_NOM_WR is activated or enabled after activating WL. The setting for tODTLoff_WR_NT can indicate the amount of time before the ODT resistor value of RTT_NOM_WR is deactivated or disabled.

[0031] In some examples, if the settings for tODTLon_WR_NT or tODTLoff_WR_NT are too short or too long, the signal integrity of the memory devices included in R0 may be negatively affected during write operations. If negatively affected, it can be determined according to... Figure 3 The register encoding scheme 300 shown reprograms the mode register 103 to change its value according to the default timing value for tODTLon_WR_NT in Table 330 to push out (+) or pull in (-) a time length and / or according to the default timing value for tODTLoff_WR_NT in Table 340 to push out (+) or pull in (-) a time length. This reprogramming allows RTT_NOM_WR to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 400 for write commands to memory devices included in R0.

[0032] Based on some examples, if the settings for tODTLon_WR or tODTLoff_WR are too short or too long, the signal integrity of the memory devices included in R0 may also be negatively affected during write operations. If negatively affected, it can be determined according to... Figure 3The register encoding scheme 300 shown reprograms the mode register 103 to change its value according to the default timing value for tODTLon_WR in Table 310 to push out (+) or pull in (-) a time length and / or according to the default timing value for tODTLoff_WR in Table 320 to push out (+) or pull in (-) a time length. This reprogramming allows RTT_WR to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 400 for write commands to memory devices included in R0.

[0033] Figure 5 Example timing diagram 500 is shown. In some examples, such as... Figure 5 The timing diagram 500 shown depicts the timing of write-to-write turnaround for different rows. For these examples, different rows can be used for DIMM (D0) and are shown as R0 and R1. Figure 1 At least some elements of the memory device 100 shown can be used to describe actions taken in relation to timing diagram 500. Examples are not limited to the elements of the memory device 100 used in timing diagram 500.

[0034] and Figure 4 Similar to what was mentioned earlier, the values ​​used to establish settings for RTT_PARK, RTT_WR, and RTT_NOM_WR can be programmed or stored in the mode register, such as mode register 103. This can be achieved by... Figure 2 The corresponding tables 210, 220, 230 and 240 of the register encoding scheme 200 shown program different values ​​held in the mode register to change these values.

[0035] According to some examples, timing diagram 500 illustrates a Write-0 command on the CMD bus, directed or targeted to D0 and R0 (D0 R0 CS0), followed by a Write-1 command for memory devices D0 and R1 (D0 R1 CS1). For these examples, the values ​​of tODTLon_WR, tODTLoff_WR, tODTLon_WR_NT, and tODTLoff_WR_NT can be programmed or stored in mode register 103 for use with write commands based on corresponding tables 310, 320, 330, and 340 of register encoding scheme 300. As previously described, these values ​​can be changed by programming different values ​​into mode register 103, according to one or more example register encoding schemes.

[0036] In some examples, similar to Figure 4The timing diagram 400 shown can be modified by programming different values ​​into the mode register 103 to change the values ​​used to establish the settings for tODTLon / off, further improving the signal integrity of the memory device included in R0 during write operations. For example, when a write command is sent in signal form based on DO R0 CS0, the write line (WL) can be activated for the memory device included in R0, and this can start timers for the target row RO for tODTLon_WR and tODTLoff_WR. The setting for tODTLon_WR can indicate the amount of time before the ODT resistor value of RTT_WR is activated or enabled after activating WL. The setting for tODTLoff_WR can indicate the amount of time before the ODT resistor value of RTT_WR is deactivated or disabled.

[0037] Based on some examples, if the settings for tODTLon_WR or tODTLoff_WR are too short or too long, the signal integrity of the memory devices included in R0 may be negatively affected during write operations. If this is negatively affected, it can be addressed according to... Figure 3 The register encoding scheme 300 shown reprograms mode register 103 from the default timing value to push (+) or pull (-) a time length from the default timing value of tODTLon_WR according to Table 330 and / or push (+) or pull (-) a time length from the default timing value of tODTLoff_WR according to Table 340. This reprogramming allows RTT_WR to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 400 for write commands to memory devices included in R0.

[0038] In some examples, adjustments can be made to the settings for tODTLon_WR_NT and tODTLoff_WR_NT, similar to those mentioned above for timing diagram 400, to further improve the signal integrity of memory devices included in R0 during write operations. When a write command is directed to a memory device included in R0, these adjustments may result in the RTT_NOM_WR of the memory device included in R0 being compressed or expanded.

[0039] According to some examples, when the target row is switched to R1, and when the write line of the memory device included in R1 is activated, settings can be initiated for the non-target row R0 and the new target row R1 for tODTLon_WR, tODTLon_WR_NT, tODTLoff_WR, and tODTLoff_WR_NT (for R1, tODTLon_WR and tODTLoff_WR are not in...). Figure 5(as shown in the diagram). If needed, these settings for tODTLon / off can be further adjusted or changed by programming different values ​​into the mode registers (such as mode register 103) included in these memory devices, potentially improving the signal integrity of the memory devices included in R1 during write operations.

[0040] Figure 6 Example timing diagram 600 is shown. In some examples, such as... Figure 6 The timing diagram 600 shown depicts the timing of read-to-read turnaround for different rows. For these examples, different rows can be used for DIMM (D0) and are shown as R0 and R1. Figure 1 At least some of the elements of the memory device 100 shown can be used to describe the actions associated with timing diagram 600. Examples are not limited to the elements of the memory device 100 used in timing diagram 600.

[0041] and Figure 4 Similar to what was mentioned earlier, the values ​​used to establish settings for RTT_PARK and RTT_NOM_RD can be programmed or stored in a mode register such as mode register 103. This can be achieved by... Figure 2 The corresponding tables 210, 220, 230 and 240 of the register encoding scheme 200 shown program the different values ​​held in these mode registers to adjust these values.

[0042] According to some examples, timing diagram 600 illustrates a Read-0 command on the CMD bus, directed or targeted to D0 and R0 (D0 R0 CS0), followed by a Read-1 command for memory devices D0 and R1 (D0 R1 CS1). For these examples, the values ​​of tODTLon_RD, tODTLoff_RD, tODTLon_RD_NT, and tODTLoff_RD_NT can be programmed or stored in mode registers (such as mode register 103) for use with read commands based on corresponding tables 350, 360, 370, and 380 of register encoding scheme 300. As previously described, these values ​​can be changed by programming different values ​​into mode registers (e.g., mode register 103) according to one or more example register encoding schemes.

[0043] In some examples, similar to Figure 4The timing diagram 400 shown illustrates that the values ​​used to establish the settings for tODTLon / off can be adjusted by programming different values ​​into the mode register 103 to further improve the signal integrity of memory devices included in R0 during read operations. For example, when a read command is sent in signal form based on DO R0 CS0, the read line (RL) can be activated for memory devices included in R0, and this can start timers for memory devices included in the target row R0 with tODTLon_RD and tODTLoff_RD and for memory devices included in the non-target row R1 with tODTLon_RD_NT and tODTLoff_RD_NT. As previously stated, if the settings for tODTLon_RD, tODTLoff_RD, tODTLon_RD_NT, or tODTLoff_RD_NT are too short or too long, the signal integrity of memory devices included in R0 during read operations may be negatively affected. If negatively affected, the mode register (e.g., mode register 103) can be reprogrammed to push (+) or pull (-) a time length against the default time value according to Table 350 for tODTLon_RD, Table 360 ​​for tODTLoff_RD, Table 370 for tODTLon_RD_NT, and / or Table 380 for tODTLoff_RD_NT, all within... Figure 3 As shown in the diagram. This reprogramming can cause RTT_RD and / or RTT_NOM_RD to be compressed (fewer clock units) or expanded (more clock units) in timing diagram 600 for read commands for memory devices included in R0.

[0044] Based on some examples, such as Figure 6 As shown, when the target row is switched to R1, settings for the non-target row R0 and the new target row R1 for tODTLon_RD, tODTLon_RD_NT, tODTLoff_RD, and tODTLoff_RD_NT can be initiated when the read line for the memory device included in R1 is activated (for R1, tODTLon_RD and tODTLoff_RD are set in...). Figure 6 (Not shown in the diagram). In other words, the memory device included in R0 is now included in the non-target row. If needed, the settings for tODTLon / off can be further adjusted by programming different values ​​to the mode register (e.g., mode register 103) to potentially improve the signal integrity of the memory device included in R1 during read operations.

[0045] Figure 7 An exemplary block diagram of device 700 is shown. Although Figure 7The device 700 shown has a limited number of elements in a particular topology, but it will be appreciated that the device 700 may include more or fewer elements in alternative topologies as needed for a given implementation.

[0046] Device 700 may be supported by circuit system 720, and device 700 may be a controller or controller logic maintained at a memory device or memory system. The memory device may be maintained on a DIMM that can be coupled to a host computing platform. Circuit system 720 may be arranged to execute one or more software or firmware implementations of a component, module, or logic 722-a (e.g., implemented at least partially by a memory controller of the memory device). It is noteworthy that the terms “a,” “b,” and “c,” and similar indicators used herein are intended to represent variables of any positive integer. Thus, for example, if the implementation sets a value of a = 3, the complete software or firmware set for logic, component, or module 722-a may include logic 722-1, 722-2, or 722-3. Furthermore, at least a portion of the “logic” may be software / firmware stored in a computer-readable medium, and although… Figure 7 The logic is shown as a discrete box, which does not limit the logic to storage in different computer-readable media components (e.g., separate memory, etc.).

[0047] According to some examples, circuit system 720 may include a processor or processor circuitry. The processor or processor circuitry may be any of a variety of commercially available processors, including but not limited to... and processor; Application, embedded, and security processors; and and Processors; IBM and Cell processor; Core(2) Core i3, Core i5, Core i7, Xeon and Processors; and similar processors. According to some examples, the circuit system 720 may also include one or more application-specific integrated circuits (ASICs), and at least some of the logic 722-a may be implemented as hardware elements of these ASICs.

[0048] According to some examples, device 700 may include program logic 722-1. Program logic 722-1 may be logic and / or features executed by circuit system 720 to program one or more sets of values ​​into registers at a memory device to establish one or more RTT settings for ODT and one or more settings for tODTLon / off at the memory device. For these examples, the one or more sets of values ​​may be RTT values ​​or tODTLon / off values. The values ​​may be based on RTT information 705 or tODTLon / off information 715.

[0049] In some examples, device 700 may also include RTT logic 722-2. RTT logic 722-2 may be a logical and / or characteristic executed by circuit system 720 to change one or more values ​​programmed by program logic 722-1, which establishes RTT settings to adjust the signal integrity of the memory device during read or write operations. For these examples, RTT settings 730 may include one or more RTT settings changed by RTT logic 722-2.

[0050] According to some examples, device 700 may also include tODTLon / off logic 722-3. tODTLon / off logic 722-3 may be executed by circuit system 720 to change one or more values ​​programmed by program logic 722-1 to adjust one or more settings for tODTLon / off to adjust the signal integrity of the memory device during read or write operations. For these examples, tODTLon / off timing 740 may include one or more tODTLon / off values ​​changed by tODTLon / off logic 722-3.

[0051] This document includes a set of logical flows representing example methods for performing novel aspects of the disclosed architecture. While one or more methods shown herein are presented and described as a series of actions for the purpose of illustrative simplicity, those skilled in the art will understand and appreciate that these methods are not limited to the order of actions. Accordingly, some actions may occur in a different order and / or concurrently with other actions shown and described herein. For example, those skilled in the art will understand and appreciate that methods may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all behaviors described in all methods may be necessary for a novel implementation.

[0052] The logical flow can be implemented using software, firmware, and / or hardware. In software and firmware embodiments, the logical flow can be implemented using computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium (such as optical, magnetic, or semiconductor memory). Embodiments are not limited in this context.

[0053] Figure 8 An example of logic flow 800 is shown. Logic flow 800 may represent some or all of the operations performed by one or more logics, features, or devices (e.g., apparatus 800) described herein. More specifically, logic flow 800 may be implemented by one or more of program logic 722-1, RTT logic 722-2, or tODTLon / off logic 722-3.

[0054] According to some examples, logic flow 800 at block 802 can program a first set of values ​​into a first set of registers at the memory device at the controller for the memory device, in order to establish one or more RTT settings for the ODT at the memory device. For these examples, program logic 722-1 can program the first set of values ​​into the first set of registers.

[0055] In some examples, logic flow 800 at block 804 can program a second set of values ​​into a second set of registers at the memory device to establish one or more settings from one or more RTT settings of the memory device for the ODT Delay Timing (tODTL) used to turn the corresponding RTT settings on or off. For these examples, program logic 722-1 can program the second set of values ​​into the second set of registers.

[0056] According to some examples, logic flow 800 at block 806 may change a first set of values ​​to a first set of registers or change a second set of values ​​to a second set of registers to adjust the signal integrity of the memory device during read or write operations. For these examples, RTT logic 722-2 may change one or more values ​​in the first set of values ​​to adjust signal integrity and / or tODTLon / off logic 722-3 may change one or more values ​​in the second set of values ​​to also adjust signal integrity.

[0057] Figure 9 An example of a first storage medium is shown. For example... Figure 9As shown, the first storage medium includes storage medium 900. Storage medium 900 may include article of manufacture. In some examples, storage medium 900 may include any non-transitory computer-readable or machine-readable medium, such as optical, magnetic, or semiconductor memory. Storage medium 900 may store various types of computer-executable instructions, such as instructions for implementing logic flow 800. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and so on. Examples are not limited in this respect.

[0058] Figure 10 An example computing platform 1000 is shown. In some examples, such as... Figure 10 As shown, the computing platform 1000 may include a memory system 1030, a processing component 1040, other platform components 1050, or a communication interface 1060. According to some examples, the computing platform 1000 may be implemented in a computing device.

[0059] According to some examples, memory system 1030 may include controller 1032 and memory device 1034. In these examples, logic and / or features residing at or located at controller 1032 may perform at least some processing operations or logic for device 700 and may include a storage medium comprising storage medium 900. Furthermore, memory device 1034 may include a similar type of volatile or non-volatile memory (not shown), which is configured above for… Figure 1 The memory device 100 shown is described. In some examples, the controller 1032 may be part of the same die as the memory device 1034. In other examples, the controller 1032 and the memory device 1034 may reside on the same die or integrated circuit as the processor (e.g., included in the processing component 1040). In still other examples, the controller 1032 may be in a separate die or integrated circuit coupled to the memory device 1034.

[0060] According to some examples, processing component 1040 may include a variety of hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs / programmable logic, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, programs, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether to use hardware elements and / or software elements to implement the example can vary based on any number of factors, such as desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints required by the given example.

[0061] In some examples, other platform components 1050 may include common computing elements such as one or more processors, multi-core processors, coprocessors, memory cells, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia I / O components (e.g., digital displays), power supplies, etc. Examples of memory cells associated with other platform components 1050 or storage system 1030 may include, but are not limited to, various types of computer-readable and / or machine-readable storage media in the form of one or more high-speed memory cells, such as read-only memory (ROM), RAM, DRAM, DDR DRAM, synchronous DRAM (SDRAM), DDR SDRAM, SRAM, programmable ROM (PROM), EPROM, EEPROM, flash memory, ferroelectric memory, SONOS memory, polymer memory such as ferroelectric polymer memory, nanowires, FeTRAM or FeRAM, bidirectional memory, phase-change memory, memristors, STT-MRAM, magnetic cards or optical cards, and any other type of storage medium suitable for storing information.

[0062] In some examples, communication interface 1060 may include logic and / or features for supporting the communication interface. For these examples, communication interface 1060 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate via direct or network communication links. Direct communication may occur via the direct interface using communication protocols or standards described in one or more industry standards (including their descendants and variants), such as those associated with the SMBus, PCIe, NVMe, SATA, SAS, or USB specifications. Network communication may occur via the network interface using communication protocols or standards (such as those described in one or more Ethernet standards published by IEEE). For example, one such Ethernet standard may include IEEE 802.3-2012, Carrier Sense Multiple Access with Collision Detection (CSMA / CD) access method and physical layer specification, published in December 2012 (hereinafter referred to as "IEEE 802.3").

[0063] The computing platform 1000 may be part of a computing device, which may be, for example, a user device, computer, personal computer (PC), desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, smartphone, embedded electronic product, gaming platform, server, server array or server cluster, web server, network server, internet server, workstation, minicomputer, mainframe computer, supercomputer, network device, web device, distributed computing system, multiprocessor system, processor-based system, or a combination thereof. Therefore, where appropriate, the functions and / or specific configurations of the computing platform 1000 described herein may be included or omitted in various embodiments of the computing platform 1000.

[0064] The components and features of the computing platform 1000 can be implemented using any combination of discrete circuits, ASICs, logic gates, and / or single-chip architectures. Furthermore, the features of the computing platform 1000 can be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any suitable combination thereof. Note that hardware, firmware, and / or software elements may be collectively or individually referred to herein as “logic,” “circuit,” or “circuit system.”

[0065] One or more aspects of at least one example can be implemented by representative instructions stored on at least one machine-readable medium representing various logic within a processor, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to manufacture the logic to perform the techniques described herein. Such a representation can be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities for loading into a manufacturing machine that actually manufactures the logic or processor.

[0066] Various examples can be implemented using hardware components, software components, or a combination of both. In some examples, hardware components may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, examples of software components may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, programs, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether to use hardware components and / or software components to implement an example can vary depending on any number of factors, such as desired computational speed, power levels, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints required for a given implementation.

[0067] Some examples may include an article of writing or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0068] According to some examples, a computer-readable medium may include a non-transitory storage medium for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to the examples. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to predefined computer languages, methods, or syntaxes to instruct a machine, computing device, or system to perform a function. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming languages.

[0069] Examples can be described using the expressions "an example" or "example" and their derivatives. These terms mean that a particular feature, structure, or property described in connection with the example is included in at least one example. The appearance of the phrase "in an example" in various places in the specification does not necessarily refer to the same example.

[0070] Examples can be described using the terms “coupling” and “connection” and their derivatives. These terms are not necessarily intended to be synonyms with each other. For example, descriptions using the terms “connection” and / or “coupling” can indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupling” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0071] The following examples are other examples of the techniques disclosed herein.

[0072] Example 1. An example apparatus may include a controller for a memory device, the controller including logic, at least a portion of which may include hardware. The logic may program a first set of values ​​into a first set of registers at the memory device to establish one or more RTT settings for ODT at the memory device. The logic may also program a second set of values ​​into a second set of registers at the memory device to establish one or more settings for tODTL for turning on or off a corresponding RTT setting from one or more RTT settings for the memory device. The logic may also change the first set of values ​​into the first set of registers or change the second set of values ​​into the second set of registers to adjust the signal integrity of the memory device during read or write operations.

[0073] Example 2. The apparatus of Example 1, wherein the first set of values ​​may include a first set of values, the first set of values ​​including a first resistance value of RTT_PARK, a second resistance value of RTT_WR, a third resistance value of RTT_NOM_WR, or a fourth resistance value of RTT_NOM_RD.

[0074] Example 3. The apparatus of Example 2, wherein the second set of values ​​may include a first timing value for tODTLon_WR for activating the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for deactivating the resistor of RTT_WR in response to a write command to the memory device, a third timing value for tODTLon_WR_NT for activating the resistor of RTT_NOM_WR in response to no write command to the memory device, and a third timing value for tODTLoff_WR for deactivating the resistor of RTT_NOM_WR in response to no write command to the memory device. The fourth timing value of _NT, the fifth timing value of tODTLon_RD for activating the resistor of RTT_RD in response to a read command for the memory device, the sixth timing value of tODTLoff_RD for deactivating the resistor of RTT_RD in response to a read command for the memory device, the seventh timing value of tODTLon_RD_NT for activating the resistor of RTT_NOM_RD in response to a read command not for the memory device, and the eighth timing value of tODTLoff_WR_NT for deactivating the resistor of RTT_NOM_WR in response to a write command not for the memory device.

[0075] Example 4. The device of Example 3, for one or more settings of tODTL, can turn on or off the corresponding RTT settings based on clock units, where a single clock unit includes one of the following: a single clock cycle, a portion of a single clock cycle, or multiple clock cycles.

[0076] Example 5. The apparatus of Example 4, the logic for changing the second set of values ​​may include logic for adding one or more clock units to one or more of the first, second, third, fourth, fifth, sixth, seventh or eighth timing values ​​or subtracting one or more clock units from one or more of the first, second, third, fourth, fifth, sixth, seventh or eighth timing values.

[0077] Example 6. The apparatus of Example 1, wherein the first set of registers and the second set of registers may be included in a mode register for a memory device.

[0078] Example 7. The apparatus of Example 1, wherein the memory device may be located at the DIMM. The memory device may be included in one row of multiple rows of memory devices located at the DIMM.

[0079] Example 8. The apparatus of Example 7, wherein the DIMM can be RDIMM, LRDIMM, FB-DIMM, UDIMM or SODIMM.

[0080] Example 9. The apparatus of Example 1, the memory device may include non-volatile memory or volatile memory.

[0081] Example 10. In the apparatus of Example 9, the volatile memory may be DRAM.

[0082] Example 11. The device of Example 9, the non-volatile memory may be a three-dimensional cross-point memory, a memory using chalcogenide phase change materials, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a bidirectional memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM) incorporating memristor technology, or a spin-transfer torque MRAM (STT-MRAM).

[0083] Example 12. An example method may include, at a controller for a memory device, programming a first set of values ​​into a first set of registers at the memory device to establish one or more RTT settings for ODT at the memory device. The method may further include programming a second set of values ​​into a second set of registers at the memory device to establish one or more settings for tODTL for turning on or off a corresponding RTT setting from one or more RTT settings for the memory device. The method may further include changing the first set of values ​​into the first set of registers or changing the second set of values ​​into the second set of registers to adjust the signal integrity of the memory device during read or write operations.

[0084] Example 13. The method of Example 12, the first set of values ​​may include the first resistance value of RTT_PARK, the second resistance value of RTT_WR, the third resistance value of RTT_NOM_WR, or the fourth resistance value of RTT_NOM_RD.

[0085] Example 14. The method of Example 13, wherein the second set of values ​​may include a first timing value for tODTLon_WR for activating the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for deactivating the resistor of RTT_WR in response to a write command to the memory device, a third timing value for tODTLon_WR_NT for activating the resistor of RTT_NOM_WR in response to no write command to the memory device, and a third timing value for tODTLoff_W for deactivating the resistor of RTT_NOM_WR in response to no write command to the memory device. The fourth timing value of R_NT, the fifth timing value of tODTLon_RD for activating the resistor of RTT_RD in response to a read command for the memory device, the sixth timing value of tODTLoff_RD for deactivating the resistor of RTT_RD in response to a read command for the memory device, the seventh timing value of tODTLon_RD_NT for activating the resistor of RTT_NOM_RD in response to a non-read command for the memory device, and the eighth timing value of tODTLoff_WR_NT for deactivating the resistor of RTT_NOM_WR in response to a non-write command for the memory device.

[0086] Example 15. The method of Example 14, for turning on or off one or more settings for tODTL of the corresponding RTT settings, can be based on clock units, where a single clock unit includes one of the following: a single clock cycle, a portion of a single clock cycle, or multiple clock cycles.

[0087] Example 16. According to the method of Example 15, the second set of values ​​can add one or more clock units to one or more of the first, second, third, fourth, fifth, sixth, seventh or eighth timing values, or subtract one or more clock units from one or more of the first, second, third, fourth, fifth, sixth, seventh or eighth timing values.

[0088] Example 17. The method of Example 12, the first set of registers and the second set of registers may be included in the mode register for the memory device.

[0089] Example 18. Method 12: The memory device may be located at the DIMM. The memory device may be included in one row of multiple rows of memory devices located at the DIMM.

[0090] Example 19. The method of Example 18, the DIMM can be RDIMM, LRDIMM, FB-DIMM, UDIMM or SODIMM.

[0091] Example 20. The method of Example 12, the memory device may include non-volatile memory or volatile memory.

[0092] Example 21. As described in Example 20, the volatile memory may be DRAM.

[0093] Example 22. The method of Example 20, wherein the non-volatile memory may be a three-dimensional crosspoint memory, a memory using chalcogenide phase change materials, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a bidirectional memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM) incorporating memristor technology, or a spin-transfer torque MRAM (STT-MRAM).

[0094] Example 23. An example of at least one machine-readable medium may include a plurality of instructions which, in response to execution by the system, may cause the system to perform a method according to any one of Examples 12 to 22.

[0095] Example 24. An example apparatus may include a unit for performing the method of any of Examples 12 to 22.

[0096] Example 25. An example system may include a DIMM. The system may also include multiple memory devices on the DIMM arranged in multiple rows. The system may also include memory devices from the multiple memory devices. The memory devices are included in one row of the multiple rows. The memory devices may include a controller, which includes logic, at least a portion of which may be hardware. The logic may program a first set of values ​​into a first set of registers at the memory device to establish one or more RTT settings for ODT at the memory device. The logic may also program a second set of values ​​into a second set of registers at the memory device to establish one or more settings for tODTL for turning on or off a corresponding RTT setting from one or more RTT settings for the memory device. The logic may also change the first set of values ​​to the first set of registers or change the second set of values ​​to the second set of registers to adjust the signal integrity of the memory device during read or write operations.

[0097] Example 26. In the system of Example 25, the first set of values ​​may include a first resistance value of RTT_PARK, a second resistance value of RTT_WR, a third resistance value of RTT_NOM_WR, or a fourth resistance value of RTT_NOM_RD.

[0098] Example 27. In the system of Example 26, the second set of values ​​may include a first timing value for tODTLon_WR for activating the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for deactivating the resistor of RTT_WR in response to a write command to the memory device, a third timing value for tODTLon_WR_NT for activating the resistor of RTT_NOM_WR in response to no write command to the memory device, and a third timing value for tODTLoff_W for deactivating the resistor of RTT_NOM_WR in response to no write command to the memory device. The fourth timing value of R_NT, the fifth timing value of tODTLon_RD for activating the resistor of RTT_RD in response to a read command for the memory device, the sixth timing value of tODTLoff_RD for deactivating the resistor of RTT_RD in response to a read command for the memory device, the seventh timing value of tODTLon_RD_NT for activating the resistor of RTT_NOM_RD in response to a non-read command for the memory device, and the eighth timing value of tODTLoff_WR_NT for deactivating the resistor of RTT_NOM_WR in response to a non-write command for the memory device.

[0099] In the system of Example 28 and Example 27, one or more settings for tODTL used to turn the corresponding RTT settings on or off can be based on clock units, where a single clock unit includes a single clock cycle, a portion of a single clock cycle, or one of multiple clock cycles.

[0100] In the system of Example 29 and Example 28, the logic for changing the second set of values ​​may include logic for adding one or more clock units to one or more of the first, second, third, fourth, fifth, sixth, seventh, or eighth timing values, or for subtracting one or more clock units from one or more of the first, second, third, fourth, fifth, sixth, seventh, or eighth timing values.

[0101] In the system of Example 30 and Example 25, the first set of registers and the second set of registers may be included in the mode register for the memory device.

[0102] Example 31. In the system described in Example 25, the DIMM can be an RDIMM, LRDIMM, FB-DIMM, UDIMM, or SODIMM.

[0103] Example 32. In the system described in Example 25, the plurality of memory devices may include non-volatile memory or volatile memory.

[0104] Example 33. In the system described in Example 32, the volatile memory may be DRAM.

[0105] Example 34. The system of Example 32 includes non-volatile memory including three-dimensional cross-point memory, memory using chalcogenide phase change materials, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level PCM, resistive memory, bidirectional memory, nanowire memory, FeTRAM, MRAM, memory incorporating memristor technology, or STT-MRAM.

[0106] It is important to emphasize that this abstract of the disclosure is provided to comply with Section 1.72(b) of 37 C.FR, requiring an abstract to allow the reader to quickly determine the essence of the technical disclosure. It should be understood that the abstract is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the foregoing detailed description, various features are combined in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be construed as reflecting an intention to claim more features than expressly recited in each claim. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer than all features of the disclosed examples. Therefore, the following claims are incorporated into the detailed description, wherein each claim is taken independently as a separate example. In the appended claims, the terms “including” and “inwhich” are used as common English equivalents to the respective terms “comprising” and “wherein”. Furthermore, the terms “first,” “second,” “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0107] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. An apparatus for controlling a memory device, comprising: A controller for a memory device includes logic, at least a portion of which comprises hardware, the logic being used for: Using a first set of values ​​programmed into a first set of registers at the memory device, one or more internal resistance termination (RTT) settings for on-die termination (ODT) are established at the memory device, the first set of values ​​including a first resistance value for RTT_PARK, a second resistance value for RTT_WR, a third resistance value for RTT_NOM_WR, or a fourth resistance value for RTT_NOM_RD. Using a second set of values ​​programmed into a second set of registers at the memory device, one or more settings for turning on or off ODT delay timing (tODTL) of a corresponding RTT setting from one or more RTT settings for the memory device are established, wherein the second set of values ​​includes a first timing value for tODTLon_WR for turning on the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for turning off the resistor of RTT_WR in response to a write command to the memory device, and a second timing value for not turning off the resistor of RTT_WR in response to a write command to the memory device. The third timing value for tODTLon_WR_NT is used to turn on the resistor of RTT_NOM_WR in response to a write command to the memory device; the fourth timing value for tODTLoff_WR_NT is used to turn off the resistor of RTT_NOM_WR in response to a write command not for the memory device; the fifth timing value for tODTLon_RD_NT is used to turn on the resistor of RTT_NOM_RD in response to a read command not for the memory device; and the sixth timing value for tODTLoff_RD_NT is used to turn off the resistor of RTT_NOM_RD in response to a read command not for the memory device. Change the use of the first set of values ​​programmed into the first set of registers or change the use of the second set of values ​​programmed into the second set of registers to adjust the signal integrity of the memory device during read or write operations.

2. The apparatus of claim 1, comprising: The one or more settings for tODTL used to turn the corresponding RTT settings on or off are based on clock units, where a single clock unit includes one of the following: a single clock cycle, a portion of a single clock cycle, or multiple clock cycles.

3. The apparatus of claim 2, wherein the logic for changing the use of the second set of values ​​programmed into the second set of registers includes logic for adding one or more clock units to one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value, or for subtracting one or more clock units from one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value.

4. The apparatus of claim 1, wherein the first set of registers and the second set of registers are contained in a mode register held at the memory device.

5. The apparatus of claim 1, comprising: The memory device is located at a dual in-line memory module (DIMM), and the memory device is included in one row of multiple rows of memory devices located at the DIMM.

6. The apparatus of claim 5, wherein the DIMM includes a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM), or a small outline DIMM (SODIMM).

7. The apparatus of claim 1, comprising: The memory device includes dynamic random access memory (DRAM).

8. A method for controlling a memory device, comprising: At the controller for the memory device, a first set of values ​​is used, programmed into the first set of registers at the memory device, to establish one or more internal resistance termination (RTT) settings for the on-die termination (ODT) at the memory device, the first set of values ​​including a first resistance value for RTT_PARK, a second resistance value for RTT_WR, a third resistance value for RTT_NOM_WR, or a fourth resistance value for RTT_NOM_RD. Using a second set of values ​​programmed into a second set of registers at the memory device, one or more settings for turning on or off ODT delay timing (tODTL) of a corresponding RTT setting from one or more RTT settings for the memory device are established, wherein the second set of values ​​includes a first timing value for tODTLon_WR for turning on the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for turning off the resistor of RTT_WR in response to a write command to the memory device, and a second timing value for not turning off the resistor of RTT_WR in response to a write command to the memory device. The third timing value for tODTLon_WR_NT is used to turn on the resistor of RTT_NOM_WR in response to a write command to the memory device; the fourth timing value for tODTLoff_WR_NT is used to turn off the resistor of RTT_NOM_WR in response to a write command not for the memory device; the fifth timing value for tODTLon_RD_NT is used to turn on the resistor of RTT_NOM_RD in response to a read command not for the memory device; and the sixth timing value for tODTLoff_RD_NT is used to turn off the resistor of RTT_NOM_RD in response to a read command not for the memory device. as well as Change the use of the first set of values ​​programmed into the first set of registers or change the use of the second set of values ​​programmed into the second set of registers to adjust the signal integrity of the memory device during read or write operations.

9. The method of claim 8, comprising: The one or more settings for tODTL used to turn the corresponding RTT settings on or off are based on clock units, where a single clock unit includes one of the following: a single clock cycle, a portion of a single clock cycle, or multiple clock cycles.

10. The method of claim 9, wherein changing the use of the second set of values ​​programmed into the second set of registers includes adding one or more clock units to one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value, or subtracting one or more clock units from one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value.

11. The method of claim 8, wherein the first set of registers and the second set of registers are contained in a mode register held at the memory device.

12. The method of claim 8, comprising: The memory device is located at a dual in-line memory module (DIMM), and the memory device is included in one row of multiple rows of memory devices located at the DIMM.

13. At least one machine-readable medium comprising a plurality of instructions, said plurality of instructions being responsive to execution by a system to cause the system to perform the method according to any one of claims 8 to 12.

14. An apparatus for controlling a memory device, the apparatus comprising a unit for performing the method of any one of claims 8 to 12.

15. A memory system comprising: Dual in-line memory modules (DIMMs); Multiple memory devices on the DIMM arranged in multiple rows; A memory device from the plurality of memory devices, the memory device being included in one of the plurality of rows, the memory device including a controller, the controller including logic, at least a portion of the logic including hardware, the logic being used for: Using a first set of values ​​programmed into a first set of registers at the memory device, one or more internal resistance termination (RTT) settings for on-die termination (ODT) are established at the memory device, the first set of values ​​including a first resistance value for RTT_PARK, a second resistance value for RTT_WR, a third resistance value for RTT_NOM_WR, or a fourth resistance value for RTT_NOM_RD. Using a second set of values ​​programmed into a second set of registers at the memory device, one or more settings for turning on or off ODT delay timing (tODTL) of a corresponding RTT setting from one or more RTT settings for the memory device are established, wherein the second set of values ​​includes a first timing value for tODTLon_WR for turning on the resistor of RTT_WR in response to a write command to the memory device, a second timing value for tODTLoff_WR for turning off the resistor of RTT_WR in response to a write command to the memory device, and a second timing value for not turning off the resistor of RTT_WR in response to a write command to the memory device. The third timing value for tODTLon_WR_NT is used to turn on the resistor of RTT_NOM_WR in response to a write command to the memory device; the fourth timing value for tODTLoff_WR_NT is used to turn off the resistor of RTT_NOM_WR in response to a write command not for the memory device; the fifth timing value for tODTLon_RD_NT is used to turn on the resistor of RTT_NOM_RD in response to a read command not for the memory device; and the sixth timing value for tODTLoff_RD_NT is used to turn off the resistor of RTT_NOM_RD in response to a read command not for the memory device. Change the use of the first set of values ​​programmed into the first set of registers or change the use of the second set of values ​​programmed into the second set of registers to adjust the signal integrity of the memory device during read or write operations.

16. The memory system of claim 15, comprising: The one or more settings for tODTL used to turn the corresponding RTT settings on or off are based on clock units, where a single clock unit includes one of the following: a single clock cycle, a portion of a single clock cycle, or multiple clock cycles.

17. The memory system of claim 15, wherein the logic for changing the use of the second set of values ​​programmed into the second set of registers includes logic for adding one or more clock units to one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value, or for subtracting one or more clock units from one or more of the first timing value, the second timing value, the third timing value, the fourth timing value, the fifth timing value, or the sixth timing value.

18. The memory system of claim 15, wherein the first set of registers and the second set of registers are contained in a mode register held at the memory device.

19. The memory system of claim 15, comprising: The plurality of memory devices include dynamic random access memory (DRAM).

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