Semiconductor storage device

Abstract

A semiconductor memory device is provided, which can suppress the occurrence of interference regardless of the position of the activated word line. A semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to any one of the plurality of word lines and the bit line, a sense amplifier connected to the bit line; and a control unit for controlling the timing of activating the sense amplifier to be later as the activated word line among the plurality of word lines is closer to the sense amplifier.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device. Background Art

[0002] A semiconductor memory device such as a dynamic random access memory (DRAM) is known to include a memory cell array having a plurality of memory cells arranged in a matrix (eg, Patent Document 1).

[0003] like Figure 1 As shown in (a), the memory cell array of the semiconductor memory device includes a sense amplifier column including a plurality of sense amplifiers arranged at a certain interval in the X direction, and a word line driver column including a plurality of sense amplifiers arranged at a certain interval in the Y direction.

[0004] Each word line driver drives the word line electrically connected to itself (in Figure 1 In the example, a circuit of wl(n), wl(n+1), wl(n+α), where n and α are arbitrary integers) is configured to control operation by a signal output from a column decoder, etc. In addition, a plurality of word lines connected to each word line driver are arranged at a certain interval in the Y direction and extend in the X direction.

[0005] Each sense amplifier drives the bit line to which it is electrically connected (in Figure 1 In the example, bl(k), bl(k+β), where n and β are arbitrary integers), for example, is configured to control the operation by a signal output from a row decoder, etc. In addition, a plurality of bit lines connected to the respective sense amplifiers are arranged at certain intervals in the X direction and extend in the Y direction.

[0006] Each memory cell MC is arranged at the intersection of a plurality of word lines and a plurality of bit lines. Each memory cell MC includes an N-channel metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor connected to the MOSFET. The gate of the MOSFET is electrically connected to the word line, and the drain of the MOSFET is electrically connected to the bit line. In addition, one terminal of the capacitor is connected to the source of the MOSFET, and the other terminal of the capacitor is connected to the plate line PL. A specific plate potential is given to the plate line PL.

[0007] Figure 1(b) is an example diagram of the activation timing of the word line and the bit line when accessing the memory cell MC in the memory cell array in the conventional semiconductor memory device. Here, the case of accessing the memory cell MC in the region R close to the word line driver column and close to the sense amplifier is represented as Case 1, and the case of accessing the memory cell MC in the region r far from the word line driver column and close to the sense amplifier line is represented as Case 2.

[0008] First, Case 1 will be described. At time t1, when the word line activation signal used to activate the word line (here wl(n)) is valid (becomes high), the word line driver connected to the word line wl(n) starts driving (activating) the word line wl(n). Further, here, the word line wl(n) voltage is represented as wl(n)[R]. Here, from the start to the completion of the activation of the word line wl(n), the word line wl(n+1) voltage rises due to crosstalk between the word line wl(n) and the adjacent word line (here wl(n+1)). Further, here, the word line wl(n+1) voltage is represented as wl(n+1)[R]. Then, when the activation of the word line wl(n) is completed, the word line wl(n+1) voltage gradually decreases and becomes a low level at time t2.

[0009] Afterwards, at time t3, when a sense amplifier activation signal saon for activating a bit line (here, b1(k)) is input to the memory cell array, the sense amplifier connected to the bit line bl(k) starts driving (activating) the bit line bl(k). Then, at time t4, the activation of the bit line b1(k) is completed.

[0010] On the other hand, in the case of case 2, since the region r is separated from the word line driver column, when the word line activation signal wlon is made valid at time t1, the time until the activation of the word line wl(n) is completed is longer than that in case 1. Here, the voltage of the word line wl(n) is expressed as wl(n)[r]. In addition, the voltage of the word line wl(n+1) that has risen due to the occurrence of crosstalk gradually decreases as in case 1, and becomes a low level at time t5 after time t4. Here, the voltage of the word line wl(n+1) is expressed as wl(n+1)[r].

[0011] However, in this case, if Figure 1As shown by the dotted line in , even after the activation of the bit line bl(k+β) in the region r is completed at time t4, since the voltage of the word line wl(n+1)[r] becomes higher than the low level state, an abnormality (disturbance) may occur, which is a decrease in the charge of the capacitor in the memory cell MC connected to the word line wl(n+1) and the bit line bl(k+β). Therefore, the farther the activated word line position (i.e., the position of the accessed memory cell) is from the word line driver column and the closer it is to the sense amplifier, the greater the possibility of disturbance.

[0012] [Patent document 1] Japanese Patent Application Publication No. 2011-146116. Summary of the invention

[0013] In view of the above problems, an object of the present invention is to provide a semiconductor memory device that can suppress the occurrence of disturbance regardless of the position of the activated word line.

[0014] In order to solve the above-mentioned problem, the present invention provides a semiconductor storage device, including multiple word lines, bit lines, multiple memory cells connected to any one of the multiple word lines and the bit lines, a sensing amplifier connected to the bit lines, and a control unit, which controls so that the closer the position of the activated word line among the multiple word lines is to the sensing amplifier, the later the timing of activating the sensing amplifier will be.

[0015] According to the semiconductor memory device of the present invention, when the position of the activated word line is close to the sense amplifier, the timing of activating the sense amplifier can be delayed. For example, even when a word line close to the sense amplifier is activated, the sense amplifier can be activated after the voltage of the word line adjacent to the word line drops to a low level. Therefore, the charge of the memory cell connected to the adjacent word line can be prevented from being reduced. Therefore, regardless of the position of the activated word line, the occurrence of interference can be suppressed.

[0016] According to the semiconductor memory device of the present invention, the control unit may control the timing of activating the sense amplifier based on a signal of an activated word line among the plurality of word lines.

[0017] According to the semiconductor memory device of the present invention, whether the activated word line is close to the sense amplifier can be easily determined based on the signal of the activated word line, so the timing of activating the sense amplifier can be easily controlled.

[0018] According to the semiconductor storage device of the present invention, the control unit includes a circuit unit, which delays the output of a signal for activating the sensing amplifier when a signal for activating any one of the multiple word lines is input, so that the closer the position of any one of the multiple word lines is to the sensing amplifier, the later the timing of activating the sensing amplifier will be.

[0019] According to the semiconductor memory device of the present invention, when a word line is activated close to a sense amplifier, since a signal for activating the sense amplifier is outputted with delay, the timing of activating the sense amplifier can be delayed.

[0020] According to the semiconductor memory device of the present invention, when the distances of the above-mentioned multiple word lines from the sensing amplifier are classified into multiple groups, the delay amount set for the activated word lines among the above-mentioned multiple word lines in the classified groups is larger when the distances of the above-mentioned sensing amplifier groups are shorter, and the above-mentioned control unit can control the timing of activating the sensing amplifier.

[0021] According to the semiconductor memory device of the present invention, the timing of activating the sensing amplifier can be controlled for the delay amount set for each of the multiple groups. For example, compared with the case where the delay amount is set in each of the multiple word lines, the circuit and device for storing the delay amount can be simplified, and the processing for setting the delay amount can be reduced, thereby making it easy to control the timing of activating the sensing amplifier.

[0022] According to the semiconductor memory device of the present invention, the information for identifying the group to which the activated word line among the plurality of word lines belongs includes a signal for indicating the activated word line among the plurality of word lines.

[0023] According to the semiconductor memory device of the present invention, it is easy to identify which group the activated word line is classified into based on the signal of the activated word line, so that the timing of activating the sense amplifier can be more easily controlled.

[0024] According to the semiconductor memory device of the present invention, the occurrence of disturbance can be suppressed regardless of the position of the activated word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 (a) is a diagram showing an example of a memory cell array configuration in a conventional semiconductor memory device. Figure 1 (b) is a timing diagram showing the activation timing of the word line and the bit line when accessing the memory cell in the memory cell array.

[0026] Figure 2 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

[0027] Figure 3 FIG. 1 is a diagram showing an example configuration of a memory cell array of the present invention.

[0028] Figure 4 The present invention Figure 3 A magnified view of a portion of .

[0029] Figure 5 FIG. 1 is an exemplary diagram of the relationship between multiple regions in the memory pad of the present invention and the delay time of sense amplifier activation.

[0030] Figure 6 2 is a diagram showing an example of the configuration of the circuit of the present invention.

[0031] Figure 7 It is a timing diagram of the operation of the circuit of the present invention.

[0032] Figure 8 (a) is a timing diagram showing activation timings of word lines and bit lines when accessing a memory cell located in a region far from a word line driver and close to a sense amplifier in a semiconductor memory device according to an embodiment of the present invention. Figure 8 (b) is a timing diagram showing activation timings of word lines and bit lines when accessing a memory cell located in a region far from a word line driver and a sense amplifier in the semiconductor memory device according to the embodiment of the present invention.

[0033] 100~Semiconductor storage device

[0034] 101~Address buffer

[0035] 102~Column pre-decoder

[0036] 103~Column decoder

[0037] 104~Instruction Buffer

[0038] 105~Instruction decoder

[0039] 106~Column control unit

[0040] 107~Sense amplifier control unit

[0041] 108~Line pre-decoder

[0042] 109~Line Control Unit

[0043] 110~Line decoder

[0044] 111~Sense amplifier

[0045] 112~Memory cell array

[0046] 200~Circuit Department

[0047] 201~P-channel MOSFET

[0048] 202~Resistance

[0049] 203~N-channel MOSFET

[0050] 204~Inverter

[0051] 205~MOS capacitor

[0052] 206~MOS capacitor

[0053] 207~NAND circuit

[0054] 208~Inverter

[0055] 209~NAND circuit

[0056] 210~Inverter

[0057] 211~NAND circuit

[0058] 212~NAND circuit

[0059] 213~Inverter

[0060] ADD~Address terminal

[0061] CMD~Command terminal

[0062] cmdi: a signal input from the command buffer 104

[0063] act~active signal

[0064] rd~Read signal

[0065] wr~write signal

[0066] ari~Signal input from address buffer 101

[0067] aci - signal input from address buffer 101

[0068] clon~Signal for activating the bit line

[0069] cl~ is used to activate the bit line signal indicated by the input row address signal caa

[0070] caa~row address signal

[0071] bl(k)~bit line

[0072] MC~Memory Cell

[0073] PL~Plate Line

[0074] wl(n), wl(n+1)~word line

[0075] wlon~word line activation signal

[0076] saon~Sense amplifier activation signal

[0077] raa[i], raa[i-1] ~ column address signal

[0078] eo10: Signal output from NAND circuit 207

[0079] eo01 - signal output from NAND circuit 209

[0080] eor: a signal output from the NAND circuit 211

[0081] N1 ~ Connection node between MOSFET 201 and resistor 202

[0082] dly~delayed signal input to inverter 204

[0083] td_saon~delay time

[0084] WLDA ~ Multiple Word Line Driver Columns

[0085] SAA~Multiple Sense Amplifier Arrays DETAILED DESCRIPTION

[0086] Hereinafter, a semiconductor memory device according to embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

[0087] Figure 2 1 is a block diagram of a configuration of a semiconductor memory device related to an embodiment of the present invention. The semiconductor memory device 100 related to the present embodiment includes an address buffer 101, a column pre-decoder 102, and a column decoder 103. In addition, the semiconductor memory device 100 includes an instruction buffer 104, an instruction decoder 105, a column control section 106, a sense amplifier control section 107, and a row pre-decoder 108. In addition, the semiconductor memory device 100 includes a row control section 109, a row decoder 110, a sense amplifier 111, and a memory cell array 112.

[0088] Each of the components 101 to 112 in the semiconductor memory device 100 may be composed of a dedicated hardware device or a logic circuit. Further, in this embodiment, for simplicity of description, other well-known configurations such as a power supply circuit, data input / output terminals, and a clock generator are not shown.

[0089] The address buffer 101 outputs a signal ari indicating a column address input from an external device (e.g., a memory controller, etc.) to an address terminal (ADD) to a column pre-decoder 102. In addition, the address buffer 101 outputs a signal aci indicating a row address input from the outside to an address terminal (ADD) to a row pre-decoder 108.

[0090] The column pre-decoder 102 pre-decodes the signal ari input from the address buffer 101 to generate a column address signal raa, which indicates a plurality of word lines ( Figure 4Then, the column pre-decoder 102 outputs the generated column address signal raa to the column decoder 103 and the sense amplifier control section 107.

[0091] When the word line activation signal wlon for activating the word line is input from the column control unit 106 in an effective state, the plurality of word line drivers 113 ( Figure 4 The column decoder 103 controls the word line driver 113 connected to the word line indicated by the column address signal raa as shown in the figure, and activates the word line.

[0092] The command buffer 104 outputs a signal cmdi indicating a command input from an external device to a command terminal (CMD) to the command decoder 105 .

[0093] The instruction decoder 105 decodes the signal cmdi input from the instruction buffer 104 and generates an internal instruction. Here, the generated internal instruction includes, for example, an active signal act, a read signal rd, a write signal wr, etc. In addition, although not shown in the figure, the instruction decoder 105 can generate a precharge signal and an update signal, etc. as internal instructions. In addition, when the signal cmdi generates an active signal act, the instruction decoder 105 outputs the active signal act to the column control unit 106. And when the signal cmdi generates a read signal rd or a write signal wr, the instruction decoder 105 outputs the generated read signal rd or write signal wr to the row control unit 109.

[0094] When the active signal act is input from the command decoder 105 , the column control unit 106 outputs a valid word line activation signal wlon to the column decoder 103 and the sense amplifier unit 107 .

[0095] When a valid word line activation signal wlon is input from the column control unit 106 , the sense amplifier control unit 107 makes a sense amplifier activation signal saon for activating the sense amplifier valid and outputs it to the sense amplifier 111 .

[0096] Here, when the position of the activated word line among the plurality of word lines wl(n), wl(n+1), . . . is closer to the sense amplifier 111, the sense amplifier control unit 107 controls so that the timing of activating the sense amplifier 111 becomes slower.

[0097] In addition, based on the column address signal raa (a signal indicating an activated word line among a plurality of word lines wl(n), wl(n+1) . . . ) input from the column pre-decoder 102, the sense amplifier control unit 107 controls the timing of activating the sense amplifier 111. Therefore, it is possible to easily discriminate whether the activated word line is close to the sense amplifier 111 based on the column address signal raa. Therefore, the timing of activating the sense amplifier can be easily controlled.

[0098] Furthermore, the sense amplifier control section 107 in the present invention is an example of a “control section.” In addition, the function of the sense amplifier control section 107 will be described in detail later.

[0099] The row pre-decoder 108 pre-decodes the signal aci input from the address buffer 101 to generate a row address signal caa indicating an activated bit line. Then, the row pre-decoder 108 outputs the generated row address signal caa to the row decoder 110.

[0100] When a read signal rd or a write signal wr is input from the command decoder 105 , the row control unit 109 asserts a signal clon for activating a bit line and outputs it to the row decoder 110 .

[0101] When the signal clon is input from the row control unit 109 to the row decoder 110 in a valid state, the column decoder 110 outputs a signal cl for activating a bit line indicated by the input row address signal caa among the plurality of bit lines in the memory cell array 112 to the sense amplifier 111 .

[0102] As described later Figure 4 As shown, a plurality of sense amplifiers 111 are arranged in the memory cell array 112. When the sense amplifier activation signal saon is input from the sense amplifier control unit 107, the sense amplifier 111 connected to the bit line represented by the signal c1 is activated among the plurality of sense amplifiers 111 to drive the bit line electrically connected to itself. Then, the sense amplifier 111 amplifies the signal (data) on the bit line.

[0103] Reference Figure 3 and Figure 4 , the configuration of the memory cell array 112 in this embodiment will be described. Figure 3 As shown, the memory cell array 112 includes a plurality of sense amplifier columns SAA extending in the X direction and arranged at a certain interval in the Y direction; and a plurality of word line driver columns WLDA extending in the Y direction and arranged at a certain interval in the X direction. Figure 4As shown, in each sense amplifier array SAA, a plurality of sense amplifiers 111 are arranged at regular intervals in the X direction, and in each word line driver array WLDA, a plurality of word line drivers 113 are arranged at regular intervals in the Y direction.

[0104] Each word line driver 113 is configured as a circuit driving a word line wl(n), wl(n+1), . . . electrically connected to the own word line, and drives the word line connected to the own word line when a signal for activating the word line is input from the column decoder 103 .

[0105] like Figure 4 As shown, a plurality of word lines wl(n), wl(n+1), ..., and a plurality of bit lines bl(k), ... (k is an arbitrary integer) are arranged in an area (memory pad) surrounded by sense amplifier columns SAA adjacent in the Y direction and word line driver columns WLDA adjacent in the X direction, and memory cells MC electrically connected to any one of the plurality of word lines wl(n), wl(n+1), ... and the plurality of bit lines bl(k), .... Furthermore, in order to avoid making the diagram complicated, Figure 4 Only a part of the memory cells MC are shown.

[0106] Each word line wl(n), wl(n+1) is arranged at a certain interval in the Y direction and extends in the X direction, and has one end (at Figure 4 In the example, the left end or the right end) is electrically connected to the corresponding word line driver 113. In addition, each bit line bl(k), ... is arranged at a certain interval in the X direction and extends in the Y direction, and is configured to perpendicularly intersect a plurality of word lines wl(n), wl(n+1), .... In addition, each bit line bl(k), ... has one end (at the end) in the extension direction. Figure 4 In the example, the upper end or the lower end) is electrically connected to the corresponding sense amplifier 111. Further, for example, at one end in the X direction (at Figure 4 The left side in the example) is connected to the word line of the word line driver 113 of the word line driver column WLDA, and the other end in the X direction (on the left side) Figure 4 The word lines of the word line driver 113 connected to the word line driver column WLDA (in the example on the right side) can be arranged alternately along the Y direction in the memory pad. In addition, for example, at one end in the Y direction (at Figure 4 The upper side in the example (in the Y direction) is connected to the bit line of the sense amplifier 111 of the sense amplifier column SAA, and the other end in the Y direction (in the Figure 4 The bit lines of the sense amplifiers 111 (lower side in the example) connected to the sense amplifier array SAA may be alternately arranged along the X direction in the memory mat.

[0107] Each memory cell MC is arranged at the intersection of any one of a plurality of word lines wl(n), wl(n+1), ... and any one of a plurality of bit lines bl(k), .... In addition, the arrangement of each memory cell MC may be different from the well-known arrangement (e.g., Figure 1 The configuration is the same as shown in (a) above.

[0108] Further, since the details on the data control of each memory cell MC are the same as the well-known technology, the description will be omitted in this embodiment.

[0109] In this embodiment, the area (memory pad) surrounded by the sense amplifier column SAA and the word line driver column WLDA is divided into a plurality of types of areas (RC, Rc, rC, rc in this example). When describing each type, RC indicates that the area is close to the word line driver 113 and close to the sense amplifier 111. In addition, Rc indicates that the area is close to the word line driver 113 and far from the sense amplifier 111. In addition, rC indicates that the area is far from the word line driver 113 and close to the sense amplifier 111. In addition, rc indicates that the area is far from the word line driver 113 and far from the sense amplifier 111. In this case, as Figure 4 As shown, multiple word lines wl(n), wl(n+1), ... are classified into a first group close to the sense amplifier 111 (a group of word lines configured in the RC region or the rC region), or a second group far from the sense amplifier 111 (a group of word lines configured in the Rc region or the rc region).

[0110] Next, the function of the sense amplifier control unit 107 in this embodiment will be described in detail. In this embodiment, when a plurality of word lines wl(n), wl(n+1), ... are classified into a plurality of groups according to the distance from the sense amplifier 111, there is a delay time td_saon (delay amount) for activating the sense amplifier 111, and the delay time td_saon is set in the activated word line among the plurality of word lines wl(n), wl(n+1), ... in the classified group, and the sense amplifier control unit 107 can control the timing of activating the sense amplifier 111 based on the fact that the set delay time td_saon is longer (larger) so that the group distance to the sense amplifier 111 is shorter. Therefore, the timing of activating the sense amplifier 111 can be controlled according to the delay time td_saon set in each of the plurality of groups. Therefore, compared with the case where the delay time td_saon is set for each of the plurality of word lines wl(n), wl(n+1), ..., the circuit and device for storing the delay time td_saon can be simplified, and the process of setting the delay time td_saon can be reduced. Therefore, the timing of activating the sense amplifier 111 can be easily controlled.

[0111] In addition, in the present embodiment, the information for identifying that the activated word line among the plurality of word lines wl(n), wl(n+1), ... is in the classified group includes the column address signal raa (a signal indicating the activated word line among the plurality of word lines wl(n), wl(n+1), ...). Therefore, it is easy to identify which group the activated word line is classified into based on the column address signal raa. Therefore, it is easier to control the timing of activating the sense amplifier 111.

[0112] Reference Figure 5 , the function of the sense amplifier control section 107 in this case will be described. Figure 5 1 is an example diagram of the relationship between a plurality of regions (RC region, rC region, Rc region, rc region) in the memory pad and the delay time td_saon for activating the sense amplifier 111. In this embodiment, the column address signal raa generated by the column pre-decoder 102 includes one or more bits (here 2 bits) of information raa[i], raa[i-1] (i is an arbitrary integer), and the one or more bits indicate which group (first group or second group) the activated word line is classified into. Figure 5 In the example, when the word lines in the upper RC region and the rC region configured in the memory pad are activated, the column address signal raa includes raa[i]=0 and raa[i-1]=0. In addition, when the word lines in the upper Rc region and the rc region configured in the memory pad are activated, the column address signal raa includes raa[i]=0 and raa[i-1]=1, and when the lower word lines in the Rc region and the rc region configured in the memory pad are activated, the column address signal raa includes raa[i]=1 and raa[i-1]=0. In addition, when the word lines in the lower RC region and the rC region configured in the memory pad are activated, the column address signal raa includes raa[i]=1 and raa[i-1]=1.

[0113] That is, in Figure 5 In the example, when the values ​​of raa[i] and raa[i-1] are the same, the activated word line is classified into the first group (the group close to the sense amplifier 111). In addition, when the values ​​of raa[i] and raa[i-1] are different, the activated word line is classified into the second group (the group far from the sense amplifier 111).

[0114] In addition, if Figure 5As shown, when the values ​​of raa[i] and raa[i-1] are the same (when activating a word line close to the sense amplifier 111), the delay time td_saon for activating the sense amplifier 111 is set to be longer, and when the values ​​of raa[i] and raa[i-1] are different (when activating a word line far away from the sense amplifier 111), the delay time td_saon for activating the sense amplifier 111 is set to be shorter.

[0115] The sense amplifier control unit 107 uses, for example, Figure 5 The output timing of the effective sense amplifier activation signal saon can be adjusted by using a lookup table showing the relationship between raa[i] and raa[i-1] and the delay time td_saon shown in the figure. In this way, the sense amplifier control unit 107 can control the timing of activating the sense amplifier 111 according to the delay time td_saon (delay amount) for activating the sense amplifier 111, which is set in the classified group among the plurality of word lines wl(n), wl(n+1), ..., and the longer the set delay time td_saon is, the shorter the group distance to the sense amplifier 111 is. In addition, in this way, the sense amplifier control unit 107 can control the timing of activating the sense amplifier 111 according to the column address signal raa (a signal indicating the activation word line among the plurality of word lines wl(n), wl(n+1), ...).

[0116] In addition, in the present embodiment, the sense amplifier control unit 107 includes a circuit unit 200, and when a word line activation signal wlon (a signal for activating any one of a plurality of word lines wl(n), wl(n+1), ...) is input, a signal for activating the sense amplifier 111 is outputted with delay, so that the closer the position of any word line is to the sense amplifier 111, the later the timing of activating the sense amplifier 111. Therefore, when the activated word line is close to the sense amplifier 111, the sense amplifier activation signal saon (a signal for activating the sense amplifier 111) is outputted with delay, and thus, the timing of activating the sense amplifier 111 can be delayed.

[0117] Reference Figure 6 , the configuration of the circuit section 200 will be described. The circuit section 200 includes a P-channel type MOSFET 201, a resistor 202, an N-channel type MOSFET 203, an inverter 204, MOS capacitors 205 and 206, a NAND circuit 207, an inverter 208, a NAND circuit 209, an inverter 210, NAND circuits 211 and 212, and an inverter 213.

[0118] MOSFET 201, resistor 202, and MOSFET 203 are connected in series between a power supply and a ground. In addition, a word line activation signal wlon is input to the gates of MOSFET 201 and MOSFET 203. A connection node N1 between MOSFET 201 and resistor 202 is connected to an input terminal of inverter 204. In addition, a gate of a MOS capacitor 205 composed of an N-channel type MOSFET is connected to the connection node N1. In addition, a drain and a source of the MOS capacitor 205 are grounded.

[0119] In addition, the gate of the MOS capacitor 206 composed of an N-channel type MOSFET is connected to the connection node N1. In addition, the drain and source of the MOS capacitor 206 are connected to the output terminal of the NAND circuit 211.

[0120] The information raa[i] included in the column address signal raa is input to one input terminal of the NAND circuit 207. In addition, the information raa[i-1] included in the column address signal raa is input to an input terminal of the inverter 208, and the output terminal of the inverter 208 is connected to the other input terminal of the NAND circuit 207.

[0121] One input terminal of the NAND circuit 209 is connected to the output terminal of the inverter 210. In addition, information raa[i-1] included in the column address signal raa is input to the other input terminal of the NAND circuit 209. Information raa[i] including the column address signal raa is input to the input terminal of the inverter 210.

[0122] One input terminal of the NAND circuit 211 is connected to the output terminal of the NAND circuit 207 , and the other input terminal of the NAND circuit 211 is connected to the output terminal of the NAND circuit 209 .

[0123] The word line activation signal wlon is input to one input terminal of the NAND circuit 212. In addition, the other input terminal of the NAND circuit 212 is connected to the output terminal of the inverter 204. In addition, the output terminal of the NAND circuit 212 is connected to the input terminal of the inverter 213.

[0124] The inverter 213 logically inverts the signal input from the NAND circuit 212, and outputs the logically inverted signal as a sense amplifier activation signal saon.

[0125] Next, the operation of the circuit section 200 will be described. First, when the word line activation signal wlon is low, the MOSFET 201 becomes the on state and the MOSFET 203 becomes the off state. In this case, the MOS capacitor 205 is charged via the MOSFET 201. In addition, in this case, the potential of one terminal of the NAND circuit 212 is high, and the potential of the other input terminal is low. Therefore, the output signal of the NAND circuit 212 is high, and the sense amplifier activation signal saon output from the inverter 213 is low.

[0126] Next, when the word line activation signal wlon becomes high, the MOSFET 201 becomes off and the MOSFET 203 becomes on. In this case, the MOS capacitor 205 starts to discharge. Then, as the discharge of the MOS capacitor 205 proceeds, when the potential of the delay signal dly input to the inverter 204 decreases, the potential of the other input terminal of the NAND circuit 212 becomes high. Therefore, the output signal of the NAND circuit 212 becomes low, and the sense amplifier activation signal saon output from the inverter 213 becomes high (valid).

[0127] Here, when the information raa[i]=0 and the information raa[i-1]=0, and when the information raa[i]=1 and the information raa[i-1]=1, the signal eo10 output from the NAND circuit 207 and the signal eo01 output from the NAND circuit 209 become high level. Therefore, the signal eor output from the NAND circuit 211 becomes low level. In this case, by charging the MOS capacitor 206, the charge amount of the delay signal dly becomes larger, and the potential drop of the delay signal dly becomes slower. Therefore, the timing of the sense amplifier activation signal saon output from the inverter 213 reaching the high level is delayed.

[0128] On the other hand, when the information raa[i]=0 and the information raa[i-1]=1, and when the information raa[i]=1 and the information raa[i-1]=0, the output signal eo10 output from the NAND circuit 207 or the signal eo01 output from the NAND circuit 209 becomes a low level. Therefore, the signal eor output from the NAND circuit 211 becomes a high level. In this case, since the MOS capacitor 206 is not charged, the charge amount of the delay signal dly becomes small, and the potential of the delay signal dly by the MOSFET 203 decreases rapidly. Therefore, the timing at which the sense amplifier activation signal saon output from the inverter 213 reaches a high level is earlier than when the MOS capacitor 206 is charged.

[0129] Figure 7This is a timing diagram of the operation example of the circuit diagram. Figure 5 and Figure 6 As described above, when the information raa[i]=0 and the information raa[i-1]=0, and when the information raa[i]=1 and the information raa[i-1]=1, the delay time td_saon from the rising edge of the word line activation signal wlon to the rising edge of the sense amplifier activation signal saon is longer than the case where the information raa[i]=0 and the information raa[i-1]=1, and the information raa[i]=1 and the information raa[i-1]=0. That is, when the activated word line is classified into the first group (the group close to the sense amplifier 111), the activation timing of the sense amplifier 111 is delayed. Further, the timing at which the sense amplifier activation signal saon becomes low (invalid) may be the timing after the falling edge of the word line activation signal wlon. In addition, regardless of whether the information raa[i] and the information raa[i-1] have the same value, the timing at which the sensing amplifier activation signal saon becomes a low level (invalid) can be the same timing or a different timing (for example, when the information raa[i] and the information raa[i-1] have the same value, it is later than when the values ​​of the information raa[i] and the information raa[i-1] are different values, etc.).

[0130] Figure 8 is a timing chart of an operation example of the semiconductor memory device 100 related to this embodiment. Figure 8 In (a), an example of the activation timing of word lines wl(n), wl(n+1) and bit lines bl(k) when accessing a memory cell MC in an area (rC area) far away from the word line driver 113 and close to the sense amplifier 111 will be described.

[0131] At time t11, when the word line activation signal wlon for activating the word line wl(n) becomes high level (valid), the word line driver 113 connected to the word line wl(n) becomes to start driving (activating) the word line wl(n). Here, the voltage of the word line wl(n) configured in the RC region is represented as wl(n)[R]. Here, during the period from the start of activation of the word line wl(n) configured in the RC region to completion, due to the crosstalk between the word line wl(n) configured in the RC region and the adjacent word line wl(n+1), the voltage of the word line wl(n+1) configured in the RC region rises. Further, here, the voltage of the word line wl(n+1) set in the RC region is represented as wl(n+1)[R]. Then, when the activation of the word line wl(n) configured in the RC region is completed, the voltage of the word line wl(n+1) configured in the RC region gradually decreases and becomes a low level.

[0132] In addition, after the activation of the word line wl(n) configured in the RC region is started, the activation of the word line wl(n) configured in the rC region is started. Further, here, the voltage of the word line wl(n) provided in the rC region is expressed as wl(n)[r]. In addition, during the period from the start of the activation of the word line wl(n) provided in the rC region to the completion, due to the crosstalk between the word line wl(n) configured in the rC region and the word line wl(n+1) adjacent thereto, the voltage of the word line wl(n+1) configured in the rC region rises. Here, the voltage of the word line wl(n+1) configured in the rC region is expressed as wl(n+1)[r]. Then, when the activation of the word line wl(n) configured in the rC region is completed, the voltage of the word line wl(n+1) configured in the rC region gradually decreases.

[0133] Here, as described above, when accessing the memory cell MC in the rC region, the information raa[i] and the information raa[i-1] are set to the same value. Therefore, the delay time td_saon from the rising edge of the word line activation signal wlon to the rising edge of the sense amplifier activation signal saon becomes longer. Then, at time t12, when the sense amplifier activation signal saon for activating the bit line bl(k) configured in the rC region becomes a high level (valid), the sense amplifier 111 connected to b1(k) configured in the rC region starts to drive (activate) the above-mentioned bit line b1(k). Further, here, the voltage of the bit line bl(k) configured in the rC region is expressed as bl(k)[R].

[0134] Thereafter, at time t13, the voltage of the word line wl(n+1) arranged in the rC region changes to a low level. Then, at the following time t14, the activation of the bit line bl(k) arranged in the rC region is completed.

[0135] In this way, when the position of the activated word line wl(n) is close to the sense amplifier 111, the timing of activation of the sense amplifier 111 can be delayed regardless of whether the position of the above word line wl(n) is close to the word line driver 113. Therefore, even when the word line wl(n) close to the sense amplifier 111 is activated, after the voltage of the word line wl(n+1) adjacent to the above word line wl(n) drops to a level, since the sense amplifier 111 can be activated, the charge of the memory cell MC connected to the adjacent word line wl(n+1) can be prevented from being reduced.

[0136] Next, refer to Figure 8In (b), an example of the activation timing of the word lines wl(n), wl(n+1) and the bit line b1(k) when accessing the memory cell MC in the region (rc region) far from the word line driver 113 and far from the sense amplifier 111 will be described. Further, at time t21, when the word line activation signal wlon becomes high level (valid), the voltage changes of the word lines wl(n) and wl(n+1) are the same as Figure 8 (a) is the same. In addition, here, the voltage of the word line wl(n) configured in the Rc region is expressed as wl(n)[R], and the voltage of the word line wl(n+1) configured in the Rc region is expressed as wl(n+1)[R]. In addition, the voltage of the word line wl(n) configured in the rc region is expressed as wl(n)[r], and the voltage of the word line wl(n+1) configured in the rc region is expressed as wl(n+1)[r].

[0137] Here, when accessing the memory cell MC in the rc region, the information raa[i] and the information raa[i-1] are set to different values. Therefore, the delay time td_saon from the rising edge of the word line activation signal wlon to the rising edge of the sense amplifier activation signal saon becomes shorter. Then, at time t22, when the sense amplifier activation signal saon for activating the bit line bl(k) configured in the rc region becomes a high level (valid), the sense amplifier 111 connected to b1(k) configured in the rC region starts to drive (activate) the above-mentioned bit line b1(k). Further, here, the voltage of the bit line bl(k) configured in the rc region is expressed as bl(k)[c].

[0138] Further, with Figure 8 Unlike the case shown in (a), since the RC region is far from the sense amplifier 111, the time to complete the activation of the bit line BL(k) configured in the RC region becomes longer. Therefore, in the time t23 until the activation of the bit line BL(k) configured in the RC region is completed, the voltage of the word line Wl(n+1) configured in the RC region becomes a low level. Then, in the subsequent time t24, the activation of the bit line BL(k) configured in the RC region is completed.

[0139] In this way, when the position of the activated word line wl(n) is far away from the sense amplifier 111, even if the delay time td_saon is set to be short, the sense amplifier 111 can be activated after the voltage of the word line wl(n+1) adjacent to the word line wl(n) drops to a low level. Therefore, the occurrence of interference can be suppressed.

[0140] As described above, according to the semiconductor memory device of the present embodiment, when the position of the activated word line wl(n) is close to the sense amplifier 111, the timing of activating the sense amplifier 111 is delayed. Therefore, for example, even when the word line wl(n) close to the sense amplifier 111 is activated, the voltage of the word line wl(n+1) adjacent to the word line wl(n) drops to a low level, and then the sense amplifier 111 can be activated. Therefore, the charge of the memory cell MC connected to the adjacent word line wl(n+1) can be prevented from being reduced. Therefore, regardless of the position of the activated word line wl9n), the occurrence of interference can be suppressed.

[0141] In addition, for example, at one end in the Y direction (at Figure 4 The upper side in the example (in the Y direction) is connected to the bit line of the sense amplifier 111 of the sense amplifier column SAA, and the other end in the Y direction (in the Figure 4 When the sense amplifiers 111 of the sense amplifier column SAA (lower side in the example) are alternately arranged along the X direction in the memory pad, the sense amplifiers 111 of the sense amplifier column SAA at one end in the Y direction can be used to access the memory cell MC storing any one of the even data (e.g., DQ0, DQ2, etc.) and the odd data (e.g., DQ1, DQ3, etc.) of a specific data column. In addition, the sense amplifiers 111 of the sense amplifier column SAA at the other end in the Y direction are used to access the memory cell MC storing any one of the even data (e.g., DQ0, DQ2, etc.) and the odd data (e.g., DQ1, DQ3, etc.) of the data column. In this case, in order to access each data in the data column, it is conceivable to activate the sense amplifiers 111 of each sense amplifier column SAA at both ends in the Y direction at the same time. Here, according to the semiconductor memory device of the present embodiment, even if the distances to the plurality of memory cells MC storing the respective data of the data column are different between the respective sense amplifier columns SAA at both ends of the Y direction (for example, when one end of the Y direction is close to the sense amplifier column SAA but the other end of the Y direction is far away from the sense amplifier column SAA), the activation timing of the sense amplifier 111 of each sense amplifier column SAA at both ends of the Y direction can be controlled individually according to the position of the accessed memory cell MC.

[0142] The above-mentioned embodiments are used to simply understand the present invention and are not described to limit the present invention. Therefore, the various features shown in the above-mentioned embodiments are intended to include all design changes and equivalent replacements belonging to the technical scope of the present invention.

[0143] For example, in the above embodiment, the semiconductor memory device 100 is described as a DRAM, but the present invention is not limited thereto. For example, if the semiconductor memory device 100 includes a plurality of word lines, a bit line, a plurality of memory cells connected to any one of the word lines and the bit line, and a sense amplifier connected to the bit line, other semiconductor memory devices (e.g., static random access memory (SRAM)) may also be used.

[0144] In addition, in the above-mentioned embodiment, the delay time td_saon (delay amount) is described by taking any one of the cases of being long or short as an example, but the present invention is not limited to this. For example, the delay amount degree can be classified into three or more. Further, in this case, the number of MOS capacitors similar to the MOS capacitor 206 of the circuit unit 200 can be increased according to the number of delay amount degrees.

[0145] In addition, in the above embodiment, the case where a plurality of word lines wl(n), wl(n+1), ... are classified into any one of two groups (a first group and a second group) is described as an example, but the present invention is not limited thereto. For example, a plurality of word lines wl(n), wl(n+1), ... may be classified into any one of three or more groups.

[0146] In addition, in the above embodiment, the case where the memory pad is divided into four types of regions (RC, Rc, rC, rc) is described as an example, but the present invention is not limited thereto. For example, the memory pad may be divided into a plurality of types of regions other than four.

[0147] In addition, in the above embodiment, if Figures 3 to 5 As shown, the ratio of the size of the RC region and the Rc region in the X direction to the size of the rC region and the rc region in the X direction is about 1:2, and the ratio of the size of the RC region and the rC region in the Y direction to the size of the Rc region and the rc region in the Y direction is about 1:2. However, the present invention is not limited thereto. For example, these ratios can be set arbitrarily.

[0148] In addition, in the above embodiment, the sense amplifier control unit 107 is described as a "control unit" in the present invention, but the present invention is not limited thereto. For example, a circuit or device that implements the same function as the sense amplifier control unit 107 can be configured as the control unit.

[0149] further, Figure 2 The semiconductor memory device 100 and Figure 6 The configuration of the circuit unit 200 shown is an example, and can be appropriately changed, and various other configurations can be adopted.

Claims

1. A semiconductor storage device, comprising: multiple word lines; bit line; a plurality of memory cells connected to any one of the plurality of word lines and the bit line; A plurality of sense amplifiers connected to the bit line and including a first sense amplifier column located on a first side of the plurality of memory cells and a second sense amplifier column located on a second side of the plurality of memory cells, wherein the second side is opposite to the first side across the plurality of memory cells; as well as a control unit configured to control so that the closer the position of the activated word line among the plurality of word lines is to the first sense amplifier column or the second sense amplifier column, the later the timing of activating the sense amplifier; Each of the plurality of memory cells is connected to a sense amplifier of the first sense amplifier column or the second sense amplifier column, whichever is closer, through the bit line; The control unit includes: a first MOS capacitor and a second MOS capacitor, wherein when the position of the activated word line among the plurality of word lines is closer to the sense amplifier, the control unit charges the first MOS capacitor and the second MOS capacitor to control the timing of activating the sense amplifier, wherein when the position of the activated word line among the plurality of word lines is farther away from the sense amplifier, the control unit charges one of the first MOS capacitor and the second MOS capacitor to control the timing of activating the sense amplifier; The control unit also includes: The circuit part includes a resistor, one end of which is connected to the first MOS capacitor and the second MOS capacitor through a first connection node.

2. The semiconductor memory device according to claim 1, wherein The control unit controls a timing of activating the sense amplifier according to a signal indicating an activated word line among the plurality of word lines.

3. The semiconductor memory device according to claim 1, wherein: When a signal for activating any one of the plurality of word lines is input, the circuit unit delays outputting a signal for activating a sense amplifier so that the closer the position of the word line is to the sense amplifier, the later the timing of activating the sense amplifier.

4. The semiconductor memory device according to claim 1, wherein: When the multiple word lines are classified into multiple groups according to the distances from the multiple word lines to the sensing amplifier, the delay amount set for the activated word lines among the multiple word lines in the classified groups can be set to be larger according to the shorter the distance from the group to the sensing amplifier, and the control unit controls the timing of activating the sensing amplifier.

5. The semiconductor memory device according to claim 4, wherein: The information for identifying that an activated word line among the plurality of word lines is in the classified group includes a signal indicative of the activated word line among the plurality of word lines.

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