Configuration control circuit for flash FPGA capable of suppressing programming disturbance

Abstract

The present application discloses a configuration control circuit of a flash type FPGA capable of suppressing programming interference, and relates to the field of flash type FPGA. Compared with a conventional configuration control circuit, the configuration control circuit adds a programming selection circuit. When performing a programming operation on a flash storage cell located in a target row and a target column, the programming selection circuit controls the path between the programming bit line voltage and the bit line voltage acquisition end of the flash storage cell located in the target row in the target column to be turned on, while the path between the programming bit line voltage acquisition end and the bit line voltage acquisition end of the flash storage cell in other rows in the target column is turned off, thereby preventing the high-voltage programming bit line voltage from acting on unselected flash storage cells, suppressing the programming interference caused thereby, and avoiding additional delay caused by the programming process.

Description

Technical Field

[0001] The present application relates to the field of flash type FPGA, and in particular to a configuration control circuit of a flash type FPGA capable of suppressing programming interference. Background Art

[0002] Flash FPGA is based on reconfigurable flash storage technology. By re-downloading the program, the circuit logic is configured to realize different functions for users. Compared with conventional SRAM-type programmable logic devices, it has the advantages of no loss of power-off information, fast power-on startup, simple peripheral circuits, and short development cycle. It is gradually becoming a new trend in programmable logic devices.

[0003] When designing a flash FPGA, similar to an SRAM programmable logic device, it is necessary to perform layout and routing and timing analysis according to the user's design, and finally obtain a design result that meets the timing requirements. However, in the process of manufacturing a flash FPGA according to the design results, applying high voltage to the flash switch to perform programming operations will affect the previously programmed flash switch, causing the threshold voltage of the previously programmed flash switch to drift, increasing the delay of the flash switch transmitting the signal. As a result, the design result that originally met the timing requirements no longer actually meets the timing requirements after the manufacturing is completed, causing the operating frequency of the circuit to decrease. Summary of the invention

[0004] In view of the above problems and technical requirements, the applicant has proposed a configuration control circuit of a flash type FPGA that can suppress programming interference. The technical solution of the present application is as follows:

[0005] A configuration control circuit of a flash type FPGA capable of suppressing programming interference, the configuration control circuit comprising a word line circuit, a bit line circuit and a programming selection circuit;

[0006] The word line circuit includes a plurality of word line channels, each word line channel corresponds to a row of the memory array and is used to provide a word line voltage to each flash memory cell in the corresponding row;

[0007] The bit line circuit includes a plurality of bit line channels, each bit line channel corresponds to a column of the memory array and is used to provide a bit line voltage to each flash memory cell in the corresponding column through a programming selection circuit;

[0008] When performing a programming operation on the flash memory cells located in the target row and the target column, a programming word line voltage is provided through the word line channel corresponding to the target row, and a programming bit line voltage is provided through the bit line channel corresponding to the target column. The programming selection circuit controls the path between the programming bit line voltage and the bit line voltage acquisition terminal of the flash memory cells located in the target row in the target column to be turned on, while the path between the programming bit line voltage and the bit line voltage acquisition terminals of the flash memory cells in other rows in the target column is turned off.

[0009] A further technical solution is that the programming selection circuit includes a plurality of selection channels and a plurality of selection tubes, each selection tube corresponds to a flash storage unit, the drain of the selection tube is connected to the bit line voltage acquisition terminal of the corresponding flash storage unit, the sources of the selection tubes connected to the flash storage units in the same column are all connected and connected to the bit line channels corresponding to the column; each selection channel corresponds to a row of the storage array, the gates of the selection tubes connected to the flash storage units in the same row are all connected and connected to the selection channel corresponding to the row;

[0010] The programming selection circuit outputs a selection voltage of a valid level through a selection channel corresponding to a target row, and outputs a selection voltage of an invalid level through selection channels corresponding to other rows.

[0011] Its further technical solution is that each selection channel includes a first programming switch tube, a pull-up selection switch tube, a second programming switch tube and a pull-down selection switch tube, the power supply voltage VDD, the pull-up selection switch tube, the first programming switch tube, the second programming switch tube and the pull-down selection switch tube and the negative high voltage LV1 are connected in sequence, and the common end of the first programming switch tube and the second programming switch tube is connected to the gate of the selection tube connected to each flash storage unit of the corresponding row;

[0012] The second programming switch tube is controlled by a programming operation signal, the first programming switch tube is controlled by a complementary signal of the programming operation signal, and the pull-up selection switch tube and the pull-down selection switch tube are both controlled by a gating trigger signal;

[0013] When a programming operation is performed on a flash type FPGA, the programming operation signal is at a valid level, the second programming switch tubes in all selection channels are turned on, and the first programming switch tubes in all selection channels are turned on;

[0014] The strobe trigger signal in the selection channel corresponding to the target row is at a valid level, the pull-down selection switch in the current selection channel is turned on, the pull-up selection switch in the current selection channel is turned off, and the current selection channel outputs negative high voltage LV1 to the gate of the selection tube connected to the flash storage unit of the target row to control its conduction;

[0015] The selection trigger signal in the selection channel corresponding to other rows is at an invalid level, the pull-up selection switch tube in the selection channel is turned on, and the pull-down selection switch tube in the selection channel is turned off. Other selection channels output the power supply voltage VDD to the gate of the selection tube connected to the flash storage unit of each row to control its shutdown.

[0016] A further technical solution is that each selection channel further includes an erase read switch tube, a common end of the first programming switch tube and the second programming switch tube is grounded through the erase read switch tube, and the erase read switch tube is controlled by an erase read signal;

[0017] When a programming operation is performed on a flash type FPGA, the programming operation signal is a valid level and the erase read signal is an invalid level; when a flash type FPGA performs an erase operation or a data read operation, the programming operation signal is an invalid level, the second programming switch tubes in all selection channels are turned off, and the first programming switch tubes in all selection channels are turned off; the erase read signal is a valid level, the erase read switch tubes in all selection channels are turned on, and all selection channels output 0V.

[0018] Its further technical solution is that the pull-up selection switch tube includes a PMOS tube P9, the pull-down selection switch tube includes an NMOS tube N13, the source of P9 is connected to the power supply voltage VDD, the drain of P9 is connected to the first programming switch tube, and the gate of P9 is connected to the selection trigger signal ADDR; the second programming switch tube is connected to the drain of N13, the source of N13 is connected to the negative high voltage LV1, and the gate of N13 is connected to the ADDR signal;

[0019] The ADDR signal in the selection channel corresponding to the target row is at a valid level, and the ADDR signals in the selection channels corresponding to other rows are at an invalid level.

[0020] A further technical solution is that the flash type FPGA includes a plurality of configuration control circuits, and each configuration control circuit is connected to a storage array in a BANK in the flash type FPGA;

[0021] Each selection channel also includes a first BANK selection tube and a second BANK selection tube, the first BANK selection tube is connected between the power supply voltage VDD and the output end of the selection channel, and the second BANK selection tube is connected between the output end of the selection channel and the negative high voltage LV1;

[0022] When a configuration operation is performed on a storage array in a BANK, the BANK signal obtained by the configuration control circuit in the BANK is at a valid level, and the first BANK selection tubes and the second BANK selection tubes in all selection channels in the BANK are turned on.

[0023] The beneficial technical effects of this application are:

[0024] The present application discloses a configuration control circuit of a flash type FPGA capable of suppressing programming interference. Compared with a conventional configuration control circuit, the configuration control circuit adds a programming selection circuit. The programming selection circuit can disconnect the path between the BL voltage and the flash storage cells of a non-selected row during programming, thereby avoiding the high-voltage programming bit line voltage from acting on the unselected flash storage cells, suppressing the programming interference caused thereby, and by sacrificing part of the chip area, improving the consistency of the threshold voltage distribution of the flash storage cells after programming, avoiding the drift of the threshold voltage of the flash storage cells, avoiding the additional delay caused by the programming process, ensuring the accuracy of the signal delay when the flash storage cells are used as signal switches, and being suitable for flash type FPGAs with high performance and high resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of the storage array and configuration control circuit inside a conventional flash-type FPGA.

[0026] Figure 2 It is another structural diagram of the flash storage unit.

[0027] Figure 3 It is a structural diagram of a storage array and a configuration control circuit inside a flash-type FPGA in one embodiment of the present application.

[0028] Figure 4 The circuit structure diagram of a channel selection in an embodiment.

[0029] Figure 5 is a circuit structure diagram of selecting a channel in another embodiment.

[0030] Figure 6 The diagram is a circuit connection diagram of a flash storage unit and a configuration control circuit in an embodiment. DETAILED DESCRIPTION

[0031] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0032] Please refer to Figure 1 As shown in the structure diagram, in the conventional flash type FPGA including the storage array and the configuration control circuit, taking the storage array including the flash storage cells of P rows and Q columns as an example, the word line circuit is connected through the word line WL <1> ~WL The flash memory cells connected from the first row to the Pth row are connected by the bit line circuit through the bit line BL <1> ~BL <q>The bit line voltage acquisition terminal of the flash storage unit connected to the first column to the Qth column is also connected to the bit line voltage acquisition terminal of the flash storage unit connected to the first column to the Qth column. <1> ~BLN <q>The BLN terminals of the flash memory cells in the first column to the Qth column are connected. The substrate circuit is connected to the substrate SUB of each flash memory cell. The data reading circuit is connected to the bit line voltage acquisition terminal of each flash memory cell.

[0033] exist Figure 1 In the conventional flash type FPGA including the conventional configuration control circuit shown, the bit line circuit directly provides the bit line voltage BL to each flash storage cell. When the programming operation is performed in the order from the first row to the last row, when the programming operation is performed on the flash storage cells in each row, the bit line voltage BL provided by the bit line channel will act on all the flash storage cells in the same column. When performing the programming operation, the bit line voltage BL is a high voltage, which will cause programming interference when it acts on the already programmed flash storage cells, causing the threshold voltage of the previously programmed flash switch to drift. For example, when performing the programming operation on each flash storage cell in the first column, the bit line circuit will pass the bit line BL <1> When a high voltage is applied to the P flash memory cells in the column, when a programming operation is performed on the flash memory cells in the second row of the first column, programming interference will be generated on the flash memory cells in the first row of the first column that have been programmed. Similarly, when a programming operation is performed on the flash memory cells in the third row of the first column, programming interference will be generated on the flash memory cells in the first row of the first column and the second row of the first column that have been programmed, and so on.

[0034] In the above Figure 1 As shown in the structure, each flash storage unit can be Figure 1 The structure shown is a single tube, the drain of the flash memory cell is connected to BL as the bit line voltage acquisition terminal, the source of the flash memory cell is connected to BLN, the gate of the flash memory cell is connected to the word line circuit, and the substrate of the flash memory cell is connected to the substrate circuit. Alternatively, each flash memory cell can be as follows Figure 2 The double-tube structure is shown, and the flash storage unit includes a programming tube T1 and a switch tube T2. The floating gates of the programming tube T1 and the switch tube T2 are connected and used as the control gate CG of the switch unit to connect the word line circuit. The source of the programming tube T1 is connected to the bit line voltage BL as the bit line voltage acquisition terminal, and the drain of the programming tube T1 is connected to BLN. The substrate is connected to the substrate potential circuit. The source and drain of the switch tube T2 are used as the signal input terminal Signal_in and the other as the signal output terminal Signal_out, which can realize bidirectional communication.

[0035] In order to suppress programming interference, the configuration control circuit of the present application is optimized on the basis of the configuration control circuit, and a programming selection circuit is added to the conventional configuration control circuit. The storage array in the flash type FPGA including the configuration control circuit of the present application also includes a plurality of flash storage units. Similar to the conventional structure, the flash storage unit can be as follows: Figure 1 With a single tube structure, it can also be Figure 2 It adopts a dual-tube structure. In addition to the conventional word line circuit, bit line circuit, substrate circuit and data reading circuit, the configuration control circuit also includes a programming selection circuit. The configuration control circuit is used to perform configuration operations on the flash storage cells in the storage array, including programming operations, erasing operations and data reading operations.

[0036] The connection method between the word line circuit and the flash storage unit is similar to the conventional method. The word line circuit includes a plurality of word line channels, each word line channel corresponds to a row of the storage array, and is used to provide a word line voltage to each flash storage unit in the corresponding row. When performing different configuration operations, the voltage value of the word line voltage is different. The connection method between the substrate circuit and the data reading circuit and the storage array is also the same as the conventional method, and this application will not repeat it.

[0037] The bit line circuit includes a plurality of bit line channels, each of which corresponds to a column of the storage array and is used to provide a bit line voltage BL to each flash storage cell in the corresponding column. When performing different configuration operations, the voltage value of the bit line voltage BL is different. The connection method between the bit line circuit and the flash storage cell is different from the conventional method. Each bit line channel is no longer directly connected to each flash storage cell in the column through BL, but provides a bit line voltage to each flash storage cell in the corresponding column through a programming selection circuit. The BLN provided by the bit line channel to each flash storage cell is similar to the conventional one, and will not be repeated in this application.

[0038] In the process of performing programming operation on the storage array, the flash storage cells are selected in sequence to perform programming operation. When the programming operation is performed on the selected flash storage cells located in the target row and the target column, the programming word line voltage is provided through the word line channel corresponding to the target row, and the programming bit line voltage is provided through the bit line channel corresponding to the target column. The programming word line voltage and the programming bit line voltage are respectively the word line voltage and the bit line voltage required for programming. The programming selection circuit is used to control the path between the programming bit line voltage and the bit line voltage acquisition terminal of the flash storage cell located in the target row in the target column to be connected, and the path between the programming bit line voltage and the bit line voltage acquisition terminal of the flash storage cell in other rows in the target column to be disconnected.

[0039] For example, the same Figure 1 In this memory array, when a programming operation is performed on the flash memory cell in row 5 and column 6, word line channel 5 is connected via WL <5> Provide programming word line voltage to all flash memory cells in row 5, bit line channel 6 through BL <6> Output programming bit line voltage. Figure 1 In the conventional structure shown, the programming bit line voltage will act on all P flash memory cells in the 6th column, causing programming interference to the flash memory cells in the first 4 rows of the 6th column that have been programmed. In the structure of the present application, the programming selection circuit controls the path between the programming bit line voltage and the bit line voltage acquisition terminal of the flash memory cells in the 5th row in the 6th column to be turned on, so that the programming bit line voltage can be normally output to the flash memory cells in the 5th row and the 6th column. However, the programming selection circuit controls the path between the programming bit line voltage and the flash memory cells in other rows in the target column to be disconnected, so that the programming bit line voltage will not be output to the flash memory cells in other rows of the 6th column. That is, the high voltage when performing the programming operation will not act on the flash memory cells in the rows that do not need to perform the programming operation, thereby suppressing programming interference.

[0040] The method of using a programming selection circuit to control the BL voltage of the flash storage cells in the selected row and the non-selected row to suppress programming interference in the present application can be applied to p-type flash storage cells and n-type flash storage cells, but the n-type flash storage cells are turned on by adding a positive voltage to the gate. When programming, the gate of the selected row is added with a high voltage, and the gate of the non-selected row is added with a low voltage, which just turns off the flash storage cell, so no channel current is formed, and the programming interference is relatively small. However, the p-type flash storage cell is different. The flash storage cell in the non-selected row is added with a low voltage to form a channel current. The p-type current forms channel hot holes, and the channel hot holes induce hot electrons, which may cause a small amount of hot electrons to be injected into the floating gate, and the interference is relatively large. Therefore, for the chip area and performance balance of the entire programmable logic device, the general n-type flash storage cell can not consider adding a programming selection circuit, but the p-type flash storage cell is more obviously affected by the above-mentioned programming interference, so the advantage of adding a programming selection circuit is more significant, so the present application is described with the flash storage cell as a p-type flash storage cell.

[0041] In order to realize the above functions, the programming selection circuit includes several selection channels and several selection tubes T0, each selection tube T0 corresponds to a flash storage unit, the drain of the selection tube T0 is connected to the bit line voltage acquisition terminal of the corresponding flash storage unit, and the sources of the selection tubes T0 connected to the flash storage units in the same column are all connected and connected to the BL of the bit line channel corresponding to the column. Each selection channel corresponds to a row of the storage array, and the gates of the selection tubes connected to the flash storage units in the same row are all connected and connected to the selection channel corresponding to the row. For example Figure 3 In the example, the sources of the selection tubes T0 connected to the flash storage cells in the first column are all connected and connected to the bit line channel BL. <1> , the selection channel 1 is connected to the gate SG of the selection tube T0 connected to each flash storage unit in the first row. When a programming operation is performed on the flash storage unit located in the target row and the target column, the programming selection circuit outputs a selection voltage of a valid level through the selection channel corresponding to the target row, and outputs a selection voltage of an invalid level through the selection channels corresponding to other rows.

[0042] Please refer to Figure 4 , which shows the connection structure of a single flash storage unit, Figure 4 The substrate circuit and the data reading circuit are not shown. Each selection channel includes a first programming switch tube, a pull-up selection switch tube, a second programming switch tube and a pull-down selection switch tube. These switch tubes can be implemented by PMOS or NMOS tubes. The second programming switch tube is controlled by the programming operation signal PROGRAM, the first programming switch tube is controlled by the complementary signal PROGRAM_B of the programming operation signal, and the pull-up selection switch tube and the pull-down selection switch tube are both controlled by the selection trigger signal ADDR. Based on the fact that the programming operation signal PROGRAM and the selection trigger signal ADDR are both effective at high levels, the first programming tube uses PMOS tube P10, the pull-up selection switch tube uses PMOS tube P9, the second programming switch tube uses NMOS tube N12, and the pull-down selection switch tube uses NMOS tube N13. Figure 4 As shown, the power supply voltage VDD, the pull-up selection switch tube P9, the first programming switch tube P10, the second programming switch tube N12, the pull-down selection switch tube N13 and the negative high voltage LV1 are connected in sequence, and the common end of the first programming switch tube P10 and the second programming switch tube N12 is led out to connect the gate SG of the selection tube T0 connected to each flash storage unit of the corresponding row.

[0043] Based on Figure 4 When a programming operation is performed on a flash type FPGA, the programming operation signal PROGRAM is at a valid level, the second programming switch tubes N12 in all selection channels are turned on, and the first programming switch tubes P10 in all selection channels are turned on.

[0044] The strobe trigger signal ADDR in the selection channel corresponding to the target row is at an effective level, the pull-down selection switch tube N13 in the current selection channel is turned on, and the pull-up selection switch tube P9 in the current selection channel is turned off, forming a path of LV1, N13, and N12. The current selection channel outputs a negative high voltage LV1 to the gate SG of the selection tube T0 connected to the flash storage unit of the target row, so that the selection tube T0 connected to the flash storage unit of the target row is turned on. The strobe trigger signal ADDR in the selection channel corresponding to other rows is at an invalid level, the pull-up selection switch tube P9 in the selection channel is turned on, and the pull-down selection switch tube N13 in the selection channel is turned off, then the other selection channels all form paths of VDD, P9, and P10, and output the power supply voltage VDD to the gate SG of the selection tube T0 connected to the flash storage unit of each row, so that the selection tube T0 connected to the flash storage unit of other rows is turned off.

[0045] Specifically, the pull-up selection switch tube includes a PMOS tube P9, the pull-down selection switch tube includes an NMOS tube N13, the source of P9 is connected to the power supply voltage VDD, the drain of P9 is connected to the first programming switch tube, and the gate of P9 is connected to the gate trigger signal ADDR; the second programming switch tube is connected to the drain of N13, the source of N13 is connected to the negative high voltage LV1, and the gate of N13 is connected to the ADDR signal. The ADDR signal in the selection channel corresponding to the target row is a valid level, and the ADDR signals in the selection channels corresponding to other rows are invalid levels.

[0046] Furthermore, in actual application, the flash type FPGA includes several BANKs, each of which contains a storage array. Then the flash type FPGA includes several configuration control circuits of the present application, and each configuration control circuit is connected to a storage array in a BANK. Figure 5 As shown, each selection channel also includes a first BANK selection tube and a second BANK selection tube. The first BANK selection tube is connected between the power supply voltage VDD and the output end of the selection channel, and the second BANK selection tube is connected between the output end of the selection channel and the negative high voltage LV1. Taking the high level of the BANK signal as an example, Figure 5 As shown, the first BANK selection tube is implemented by a PMOS tube P8, and the second BANK selection tube is implemented by an NMOS tube N14, N14 is controlled by a BANK signal, and P8 is controlled by a BANK_B signal. When configuring a storage array in a BANK, the BANK signal obtained by the configuration control circuit in the BANK is at an effective level, and the first BANK selection tube N14 and the second BANK selection tube P8 in all selection channels in the BANK are turned on. Thus, a path of LV1, N14, N13, N12 or a path of VDD, P8, P9, P10 can be formed.

[0047] like Figure 4 and 5 As shown, each selection channel also includes an erase and read switch tube. Figure 4 and 5 Take the erasing and reading switch tube implemented by NMOS tube N15 as an example. The common end of the first programming switch tube P10 and the second programming switch tube N12 is grounded through the erasing and reading switch tube N15, and the erasing and reading switch tube N15 is controlled by the erasing and reading signal ERASE||READ. When a programming operation is performed on a flash type FPGA, the programming operation signal PROGRAM is a valid level and the erasing and reading signal ERASE||READ is an invalid level. When a flash type FPGA performs an erasing operation or a data reading operation, the programming operation signal PROGRAM is an invalid level and the erasing and reading signal ERASE||READ is a valid level. At this time, the second programming switch tube N12 in all selection channels is turned off, and the first programming switch tube P10 in all selection channels is turned off. The erasing and reading switch tube N15 in all selection channels is turned on, and all selection channels output 0V. Thus, an erasing operation or a data reading operation can be implemented.

[0048] Figure 6 In one embodiment, a schematic diagram of the specific connection between a single flash storage unit and a configuration control circuit is shown. In this application, ERASE=1 indicates that the ERASE signal is at a high level, PROGRAM=0 indicates that the PROGRAM signal is at a low level, PROGRAM and PROGRAM_B are complementary signals, that is, PROGRAM=-PROGRAM_B, and the rest of the expressions are similar, and the following uses this expression. Moreover, for each PMOS tube, when the signal at its gate end is "0", it indicates that the PMOS tube is turned on, and when the signal at the gate end is "1", it indicates that the PMOS tube is turned off. For each NMOS tube, when the signal at its gate end is "1", it indicates that the NMOS tube is turned on, and when the signal at the gate end is "0", it indicates that the NMOS tube is turned off. The configuration control circuit performs the following configuration operations on the flash storage unit:

[0049] 1. When performing an erase operation on all flash storage units

[0050] In all configuration control circuits in the BANK performing the erase operation, ERASE=BANK=1, ERASE||READ=1, PROGRAM=READ=0, PROGRAM||READ=0, and all ADDR=1.

[0051] (1) For the word line channel, HV0 = +1.5V, LV0 = -10.0V. At this time, N3, N4 and N5 form a path in the word line channel, and the output signal of the word line channel CG = LV0 is -10.0V.

[0052] (2) For the selection channel, VDD = +1.5V, LV1 = 0V. At this time, N15 forms a path in the selection channel, and the selection channel outputs a signal of SG = GND, which is 0V.

[0053] (3) For the substrate channel, HV1 = +8.0 V, VDD = +1.5 V. At this time, P11 is turned on, P11 and N16 are turned off, and the output SUB of the substrate channel = the signal of HV1, that is, +8.0 V.

[0054] (4) For the bit line channel, HV1 = +8.0V, LV2 = 0V, LV3 = 0V. At this time, P4 and P5 are turned on, and the output signals BL and BLN of the bit line channel = the signal of HV1, that is, +8.0V.

[0055] (5) For the data read channel, since READ=0, N17 is not conducting.

[0056] 2. When performing programming operations:

[0057] PROGRAM=BANK=1, ERASE||READ=0, ERASE=READ=0, PROGRAM||READ=0 in all configuration control circuits in the BANK that performs the programming operation.

[0058] 1. ADDR of the flash storage unit of the target row = 1;

[0059] (1) For the word line channel, HV0 = +9.5V, LV0 = -2.5V. At this time, P0, P1 and P2 form a path, and the output signal of the word line channel CG = HV0, that is, +9.5V.

[0060] (2) For the selection channel, VDD = +1.5V, LV1 = -9.0V. At this time, N12, N13 and N14 in the selection channel form a path, and the selection channel output SG = LV1, that is, -9.0V.

[0061] (3) For the substrate channel, HV1 = +1.5 V, VDD = +1.5 V. At this time, N16 is turned on, and P11 and P12 are both turned off. Then, the output SUB signal of the substrate channel is grounded, that is, 0 V.

[0062] (4) For the bit line channel, HV1 = +1.5V, LV2 = -0.9V, LV3 = -8.0V. Then N8 is turned on, and the output BLN of the bit line channel = LV2, i.e. -0.9V; and at this time, N9, N10 and N11 form a path, and the output BL of the bit line channel = LV3, i.e. -8.0V.

[0063] (5) For the data read channel, since READ=0, N17 is not conducting.

[0064] 2. ADDR of unselected flash storage cells in other rows = 0;

[0065] (1) For the word line channel, HV0 = +9.5V, LV0 = -2.5V. At this time, N0, N1 and N2 form a path, and the output signal of the word line channel CG = LV0, that is, -2.5V.

[0066] (2) For the selection channel, VDD = +1.5V, LV1 = -9.0V. At this time, P8, P9 and P10 in the selection channel form a path, and the selection channel output SG = VDD, that is, +1.5V.

[0067] (3) For the substrate channel, HV2 = +1.5V, VDD = +1.5V, at this time N16 is turned on, P11 and P12 are both turned off, and the output SUB signal of the substrate channel is grounded, that is, 0V.

[0068] (4) For the bit line channel, HV1 = +1.5V, LV2 = -0.9V, LV3 = -8.0V. Then N8 is turned on, and the output BLN of the bit line channel = LV2, i.e. -0.9V; and at this time, N9, N10 and N11 form a path, and the output BL of the bit line channel = LV3, i.e. -8.0V.

[0069] (5) For the data read channel, since READ=0, N17 is not conducting.

[0070] 3. When performing data reading operations:

[0071] READ=BANK=1,ERASE||READ=1,PRG||READ=1,PROGRAM=0,ERASE=0 in all configuration control circuits in the BANK performing the read operation;

[0072] 1. ADDR of the flash storage unit of the target row = 1;

[0073] (1) For the word line channel, HV0 = +5.0V, LV0 = LV1 = 0V, at this time N3, N4 and N6 form a path, and the output signal CG of the word line channel is the ground signal, that is, 0V.

[0074] (2) For the selection channel, VDD = +1.5V, LV1 = 0V. At this time, N15 forms a path in the selection channel, and the selection channel outputs the SG ground signal, that is, 0V.

[0075] (3) For the substrate channel, HV1 = 1.5 V, VDD = +1.5 V. At this time, P12 is turned on, P11 and N16 are both turned off, and the output signal of the substrate channel SUB = VDD, that is, +1.5 V.

[0076] (4) For the bit line channel, HV1 = +1.5V, LV2 = 0V, LV3 = 0V. At this time, N9 and N17 in the bit line channel are turned on, and the drain end of the T0 tube in the p_flash storage unit is connected to BL, which is transmitted to the data reading end of the bit line channel through N9 and N17 and then to the corresponding data reading channel. In addition, N7 is turned on, so the BLN signal is grounded, that is, 0V.

[0077] (5) For the data read channel, since READ=1 at this time, N17 is turned on, and the data read channel is connected to the data read end of the corresponding bit line channel to obtain the current of the corresponding p_flash storage unit. When the corresponding p_flash storage unit is turned on, the gate end of the eighteenth NMOS tube N18 in the data read channel will become high, higher than the second reference voltage VREF1, and the output end of the voltage comparator CMP, that is, the data output end DATA_OUT, outputs a high level. When the corresponding p_flash storage unit is turned off, the gate end of the eighteenth NMOS tube N18 in the data read channel will become low, lower than the second reference voltage VREF1, and the output end of the voltage comparator CMP, that is, the data output end DATA_OUT, outputs a low level, thereby realizing the reading of the p_flash storage unit.

[0078] 2. ADDR of unselected flash storage cells in other rows = 0;

[0079] In the word line channel, HV0=+5.0V, LV0=LV1=0V, at this time P0, P1 and P3 form a path, and the output signal SG=HV1 of the word line channel is +5.0V.

[0080] The signal conditions of the remaining selection channels, substrate channels, bit line channels and data read channels are the same as those in the above selected case. Since the flash memory cell is not selected by the word line channel, the flash memory cell will not be read.

[0081] In summary, when the configuration control circuit performs programming operation, erasing operation and data reading operation, the voltages of the various connection terminals of the flash storage unit are shown in the following table. In the following table, when performing the erasing operation, the control gate CG of the flash storage unit is defined as a maximum value of -10.0V, the bit line voltage BL is defined as a maximum value of 8.0V, the BLN voltage is defined as a maximum value of 8.0V, and the substrate voltage (SUB) is defined as a maximum value of 8.0V. When performing the programming operation, the control gate CG of the flash storage unit is defined as a maximum value of 9.5V, the gate SG of the selection tube T0 is defined as a maximum value of -9.0V, and the bit line voltage BL is defined as a maximum value of -8.0V.

[0082]

[0083] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.< / q> < / q>

Claims

1. A configuration control circuit for a flash type FPGA capable of suppressing programming interference, characterized in that: The configuration control circuit includes a word line circuit, a bit line circuit and a programming selection circuit; The word line circuit includes a plurality of word line channels, each of which corresponds to a row of the storage array and is used to provide a word line voltage to each flash storage unit in the corresponding row; The bit line circuit includes a plurality of bit line channels, each of which corresponds to a column of the memory array and is used to provide a bit line voltage to each flash memory cell in the corresponding column through the programming selection circuit; When performing a programming operation on the flash memory cells located in the target row and the target column, a programming word line voltage is provided through the word line channel corresponding to the target row, a programming bit line voltage is provided through the bit line channel corresponding to the target column, and a path between the programming bit line voltage and the bit line voltage acquisition terminal of the flash memory cells located in the target row in the target column is controlled by the programming selection circuit to be connected, while the path between the programming bit line voltage and the bit line voltage acquisition terminals of the flash memory cells in other rows in the target column is disconnected; The programming selection circuit includes a plurality of selection channels and a plurality of selection tubes, each selection tube corresponds to a flash storage unit, the drain of the selection tube is connected to the bit line voltage acquisition terminal of the corresponding flash storage unit, the sources of the selection tubes connected to the flash storage units in the same column are all connected and connected to the bit line channel corresponding to the column; each selection channel corresponds to a row of the storage array, the gates of the selection tubes connected to the flash storage units in the same row are all connected and connected to the selection channel corresponding to the row; The programming selection circuit outputs a selection voltage of a valid level through a selection channel corresponding to the target row, and outputs a selection voltage of an invalid level through selection channels corresponding to other rows; Each selection channel includes a first programming switch tube, a pull-up selection switch tube, a second programming switch tube and a pull-down selection switch tube, the power supply voltage VDD, the pull-up selection switch tube, the first programming switch tube, the second programming switch tube and the pull-down selection switch tube and the negative high voltage LV1 are connected in sequence, and the common end of the first programming switch tube and the second programming switch tube is connected to the gate of the selection tube connected to each flash storage unit of the corresponding row; The second programming switch tube is controlled by a programming operation signal, the first programming switch tube is controlled by a complementary signal of the programming operation signal, and the pull-up selection switch tube and the pull-down selection switch tube are both controlled by a strobe trigger signal; when a programming operation is performed on the flash type FPGA, the programming operation signal is at a valid level, the second programming switch tubes in all selection channels are turned on, and the first programming switch tubes in all selection channels are turned on; the strobe trigger signal in the selection channel corresponding to the target row is at a valid level, the pull-down selection switch tube in the current selection channel is turned on, and the pull-up selection switch tube in the current selection channel is turned off, and the current selection channel outputs a negative high voltage LV1 to the gate of the selection tube connected to the flash storage unit of the target row to control its conduction; the strobe trigger signal in the selection channel corresponding to other rows is at an invalid level, the pull-up selection switch tube in the selection channel is turned on, and the pull-down selection switch tube in the selection channel is turned off, and other selection channels all output a power supply voltage VDD to the gate of the selection tube connected to the flash storage unit of each corresponding row to control its turn-off.

2. The configuration control circuit according to claim 1, characterized in that: Each selection channel also includes an erase read switch tube, a common end of the first programming switch tube and the second programming switch tube is grounded through the erase read switch tube, and the erase read switch tube is controlled by an erase read signal; When a programming operation is performed on the flash type FPGA, the programming operation signal is a valid level and the erase read signal is an invalid level; when the flash type FPGA performs an erase operation or a data read operation, the programming operation signal is an invalid level, the second programming switch tubes in all selection channels are turned off, and the first programming switch tubes in all selection channels are turned off; the erase read signal is a valid level, the erase read switch tubes in all selection channels are turned on, and all selection channels output 0V.

3. The configuration control circuit according to claim 1, characterized in that: The pull-up selection switch tube includes a PMOS tube P9, and the pull-down selection switch tube includes an NMOS tube N13, the source of P9 is connected to the power supply voltage VDD, the drain of P9 is connected to the first programming switch tube, and the gate of P9 is connected to the selection trigger signal ADDR; the second programming switch tube is connected to the drain of N13, the source of N13 is connected to the negative high voltage LV1, and the gate of N13 is connected to the ADDR signal; The ADDR signal in the selection channel corresponding to the target row is at a valid level, and the ADDR signals in the selection channels corresponding to other rows are at an invalid level.

4. The configuration control circuit according to claim 1, characterized in that: The flash type FPGA includes a plurality of the configuration control circuits, and each of the configuration control circuits is correspondingly connected to a storage array in a BANK in the flash type FPGA; Each selection channel further includes a first BANK selection tube and a second BANK selection tube, wherein the first BANK selection tube is connected between a power supply voltage VDD and an output end of the selection channel, and the second BANK selection tube is connected between the output end of the selection channel and a negative high voltage LV1; When a configuration operation is performed on a storage array in a BANK, the BANK signal acquired by the configuration control circuit in the BANK is at a valid level, and the first BANK selection tubes and the second BANK selection tubes in all selection channels in the BANK are turned on.

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