Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure, a forming method thereof and a memory. The forming method comprises the following steps: providing a substrate, the substrate comprising a shallow trench isolation structure and an active region separated by the shallow trench isolation structure; forming a gate structure on a surface of the active region and forming a support layer on a top of the gate structure, a top projection of the support layer on the substrate penetrating a top projection of the gate structure on the substrate; sequentially forming a first isolation layer, a second isolation layer and a third isolation layer on a sidewall of the gate structure, the second isolation layer being connected to the support layer through a contact surface; removing the support layer to expose the contact surface of the second isolation layer; and removing the second isolation layer to form a gap between the first isolation layer and the second isolation layer. The forming method disclosed by the present disclosure can reduce parasitic capacitance and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] With the continuous development of mobile devices, battery-powered mobile devices such as mobile phones, tablets, and wearable devices are increasingly used in our lives. As an indispensable component in mobile devices, memory has generated huge demands for smaller size and integration.

[0003] Currently, Dynamic Random Access Memory (DRAM) is widely used in mobile devices due to its fast data transfer speed. However, as DRAM size continues to shrink, the number of gate structures per unit area increases, leading to smaller spacing between gate structures. This results in a significant increase in parasitic capacitance between gate structures and between the conductive plugs of the gate structure and the capacitor.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce parasitic capacitance and improve product yield.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] A substrate is provided, the substrate including a shallow trench isolation structure and an active region separated by the shallow trench isolation structure;

[0008] A gate structure is formed on the surface of the active region, and a support layer is formed on top of the gate structure, wherein the orthogonal projection of the support layer on the substrate passes through the orthogonal projection of the gate structure on the substrate;

[0009] A first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the sidewall of the gate structure, and the second isolation layer is in contact with the support layer through a contact surface;

[0010] Remove the support layer to expose the contact surface of the second insulating layer;

[0011] Remove the second isolation layer to create a gap between the first isolation layer and the third isolation layer.

[0012] In an exemplary embodiment of this disclosure, forming a gate structure on the surface of the active region and forming a support layer on top of the gate structure, wherein the orthographic projection of the support layer on the substrate passes through the orthographic projection of the gate structure on the substrate, includes:

[0013] A gate material layer is formed on the surface of the substrate;

[0014] A support material layer is formed on the surface of the gate material layer;

[0015] The support material layer is patterned to form a support layer, wherein the support layer is flush with both ends of the gate material layer in a direction parallel to the substrate.

[0016] A gate top layer is formed on the surface of the gate material layer, and the upper surface of the gate top layer is higher than or flush with the upper surface of the support layer;

[0017] The gate top layer and the gate material layer are selectively etched to form multiple spaced gate structures, with the top of each gate structure in contact with the support layer.

[0018] In an exemplary embodiment of this disclosure, forming a gate structure on the surface of the active region and forming a support layer on top of the gate structure, wherein the orthographic projection of the support layer on the substrate passes through the orthographic projection of the gate structure on the substrate, includes:

[0019] A gate material layer is formed on the surface of the substrate, the gate material layer including a gate top layer;

[0020] The top layer of the gate is patterned to form a top trench;

[0021] A support layer is formed in the top trench, and the support layer is flush with both ends of the gate material layer in a direction parallel to the substrate;

[0022] The gate material layer is selectively etched to form multiple spaced gate structures, with the top of each gate structure in contact with the support layer.

[0023] In one exemplary embodiment of this disclosure, the gate structure includes a first gate structure and a second gate structure spaced apart, and the formation method further includes, before removing the support layer:

[0024] An insulating material is filled between the first gate structure and the second gate structure to form an insulating layer, the upper surface of which is flush with the upper surfaces of the first gate structure and the second gate structure.

[0025] In one exemplary embodiment of this disclosure, the width of the gap is 3nm to 15nm.

[0026] In one exemplary embodiment of this disclosure, after removing the second isolation layer, the forming method further includes:

[0027] A sealing layer is formed, which seals the opening of the void.

[0028] In one exemplary embodiment of this disclosure, the top of the gate structure includes a passivation layer, the passivation layer being made of a different material than the support layer, and the removal of the support layer includes:

[0029] The support layer is selectively etched.

[0030] In one exemplary embodiment of this disclosure, the material of the second isolation layer is different from the materials of the first isolation layer and the third isolation layer.

[0031] In one exemplary embodiment of this disclosure, the first isolation layer and the third isolation layer are made of the same material.

[0032] In one exemplary embodiment of this disclosure, removing the second isolation layer includes:

[0033] The second isolation layer is selectively etched through the exposed contact surface using an acidic solution.

[0034] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0035] The substrate includes a shallow trench isolation structure and an active region separated by the shallow trench isolation structure;

[0036] A gate structure is located on the surface of the active region;

[0037] A first isolation layer and a third isolation layer are formed on the sidewall of the gate structure, and a gap exists between the first isolation layer and the third isolation layer.

[0038] In one exemplary embodiment of this disclosure, the gate structure includes a first gate structure and a second gate structure spaced apart, and the semiconductor structure further includes:

[0039] An insulating layer is filled between the first gate structure and the second gate structure, and the surface of the insulating layer is flush with the upper surface of the first gate structure and the upper surface of the second gate structure.

[0040] In one exemplary embodiment of this disclosure, the width of the gap is 3nm to 15nm.

[0041] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0042] A sealing layer is located on top of the insulating layer, the gate structure, the first isolation layer and the third isolation layer, and the sealing layer seals the opening of the gap;

[0043] The orthographic projection of the sealing layer on the substrate passes through the orthographic projection of the gate structure on the substrate.

[0044] In one exemplary embodiment of this disclosure, the first isolation layer and the third isolation layer are made of the same material.

[0045] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0046] The semiconductor structure and its formation method disclosed herein, as well as the memory, have several advantages. First, since the support layer is connected to the top of the gate structure, the support layer can provide lateral support for the gate structure, reducing the probability of gate structure collapse during subsequent manufacturing, which helps improve product yield and reduce process difficulty. Second, since the dielectric constant of the gaps located on the sidewalls of the gate structure is relatively small, the parasitic capacitance between gate structures and between the gate structure and other surrounding structures (e.g., conductive plugs) can be reduced by setting the gaps, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the DRAM. Furthermore, since the first isolation layer and the second isolation layer are located on the sidewalls of the gate structure, the first isolation layer and the second isolation layer can provide insulation protection for the sidewalls of the gate structure, thereby reducing the probability of coupling between the gate structure and other structures and further improving product yield.

[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0049] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0050] Figure 2 This is a schematic diagram of the substrate and gate material layer in the embodiments of this disclosure;

[0051] Figure 3 This is a schematic diagram of the gate structure in an embodiment of the present disclosure;

[0052] Figure 4 As described in the embodiments of this disclosure Figure 3 A schematic diagram of the structure after being cut open by the dashed line;

[0053] Figure 5 This is a schematic diagram of the support layer in the embodiments of this disclosure;

[0054] Figure 6 This is a schematic diagram of the support material layer in the embodiments of this disclosure;

[0055] Figure 7 This is a schematic diagram of the mask material layer in the embodiments of this disclosure;

[0056] Figure 8 This is a schematic diagram of the photoresist layer used to define the support layer in an embodiment of this disclosure;

[0057] Figure 9 This is a schematic diagram showing the backfilling of insulating material in the embodiments of this disclosure;

[0058] Figure 10 This is a schematic diagram of the photoresist layer used to define the gate structure in an embodiment of this disclosure;

[0059] Figure 11 This is a schematic diagram of the first isolation layer in the embodiments of this disclosure;

[0060] Figure 12 This is a schematic diagram of the second isolation layer in the embodiments of this disclosure;

[0061] Figure 13 This is a schematic diagram of the first insulating layer in the embodiments of this disclosure;

[0062] Figure 14 This is a schematic diagram of the second insulating layer in the embodiments of this disclosure;

[0063] Figure 15 As described in the embodiments of this disclosure Figure 14 A schematic diagram of the structure after being cut open by the dashed line;

[0064] Figure 16 This is a schematic diagram of the structure after step S140 is completed in the embodiment of this disclosure;

[0065] Figure 17 This is a schematic diagram of the structure after step S150 is completed in the embodiment of this disclosure;

[0066] Figure 18 This is a schematic diagram of the structure after step S160 is completed in the embodiment of this disclosure;

[0067] Figure 19 This is a schematic diagram of the structure after removing the sealing layer located on the surface of the second insulating layer in the embodiment of this disclosure.

[0068] Explanation of reference numerals in the attached figures:

[0069] 1. Substrate; 11. Shallow trench isolation structure; 12. Active region; 2. Gate structure; 21. First conductive layer; 22. Second conductive layer; 23. Passivation layer; 3. Support layer; 4. Gate top layer; 5. First insulating layer; 51. First isolation layer; 52. Second isolation layer; 53. Third isolation layer; 6. Second insulating layer; 7. Void; 8. Sealing layer; 200. Gate material layer; 201. First conductive material layer; 202. Second conductive material layer; 203. Passivation material layer; 300. Support material layer; 400. Mask material layer; 500. Photoresist layer. Detailed Implementation

[0070] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0071] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0072] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0073] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the forming method may include steps S110-S150, wherein:

[0074] Step S110: Provide a substrate, the substrate including a shallow trench isolation structure and an active region separated by the shallow trench isolation structure;

[0075] Step S120: A gate structure is formed on the surface of the active region, and a support layer is formed on top of the gate structure, wherein the orthogonal projection of the support layer on the substrate passes through the orthogonal projection of the gate structure on the substrate;

[0076] Step S130: A first isolation layer, a second isolation layer and a third isolation layer are sequentially formed on the sidewall of the gate structure, wherein the second isolation layer is in contact with the support layer through a contact surface;

[0077] Step S140: Remove the support layer to expose the contact surface of the second isolation layer;

[0078] Step S150: Remove the second isolation layer to form a gap between the first isolation layer and the third isolation layer.

[0079] The semiconductor structure formation method disclosed herein has several advantages. First, since the support layer is connected to the top of the gate structure, the support layer can provide lateral support for the gate structure, reducing the probability of gate structure collapse during subsequent manufacturing, which helps improve product yield and reduce process difficulty. Second, since the dielectric constant of the gaps located on the sidewalls of the gate structure is relatively small, the parasitic capacitance between gate structures and between the gate structure and other surrounding structures (e.g., conductive plugs) can be reduced by setting the gaps, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the DRAM. Furthermore, since the first isolation layer and the second isolation layer are located on the sidewalls of the gate structure, the first isolation layer and the second isolation layer can provide insulation protection for the sidewalls of the gate structure, thereby reducing the probability of coupling between the gate structure and other structures and further improving product yield.

[0080] like Figure 1 As shown, in step S110, a substrate is provided, the substrate including a shallow trench isolation structure and an active region separated by the shallow trench isolation structure.

[0081] like Figure 2 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0082] In one embodiment, the substrate 1 may be a silicon substrate 1, with a shallow trench isolation structure 11 formed therein. The shallow trench isolation structure 11 is formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs. The shallow trench isolation structure 11 divides a plurality of active regions 12 on the substrate 1, and each active region 12 may include a first doped region and a second doped region arranged at intervals.

[0083] Substrate 1 can be an n-type substrate 1, and a first doped region and a second doped region can be doped to form the source and drain, respectively. For example, both the first and second doped regions can be p-type doped to form p-type doped regions, which can form a pn junction with the n-type substrate 1. For example, p-type doping material can be doped into the first and second doped regions to form p-type semiconductors. The p-type doping material can be an element located in Group III of the periodic table, for example, boron, but it can also be other elements, which will not be listed here.

[0084] The first doped region can be used as the source and the second doped region can be used as the drain; or, the first doped region can be used as the drain and the second doped region can be used as the source.

[0085] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and / or the second doped region, and no special limitation is made here.

[0086] The area between the first doped region and the second doped region can be a channel region, which allows current to flow. The current in the channel region can be controlled by the voltage of the gate structure 2 above it to achieve gate control function. In some embodiments of this disclosure, the first doped region, the second doped region, and the channel region together constitute the active region 12.

[0087] In one embodiment of this disclosure, a shallow doped region can be formed on the side of the first doped region and the second doped region near the channel region, and the short-channel effect of the semiconductor structure can be reduced by setting the shallow doped region.

[0088] like Figure 1 As shown, in step S120, a gate structure is formed on the surface of the active region, and a support layer is formed on top of the gate structure. The orthogonal projection of the support layer on the substrate passes through the orthogonal projection of the gate structure on the substrate.

[0089] like Figure 3 and Figure 4As shown, the gate structure 2 can be formed on the surface of the channel region of the active region 12. In one embodiment, the gate structure 2 can be formed on the surface of multiple channel regions simultaneously by the same etching process, and the gate structures 2 can be spaced apart; that is, in the same etching process, at least one gate structure 2 can be formed on the surface of each channel region.

[0090] In some embodiments of this disclosure, among the plurality of gate structures 2, adjacent gate structures 2 may be independent of each other, and each gate structure 2 may be used to form an independent transistor; in other embodiments of this disclosure, the plurality of gate structures 2 may include a plurality of spaced gate structure groups, each gate structure group may include two interconnected gate structures 2, the two interconnected gate structures 2 may be distributed adjacently and may be connected together in a ring to form two common gate transistors.

[0091] In one exemplary embodiment of this disclosure, the gate structure 2 may include a first conductive layer 21, a second conductive layer 22, and a passivation layer 23 stacked along a direction perpendicular to the substrate 1, wherein:

[0092] The first conductive layer 21 can be a thin film or a coating formed on the surface of the substrate 1. No particular limitation is made on the form of the first conductive layer 21. The first conductive layer 21 can cover the surface of the channel region.

[0093] The second conductive layer 22 can be a thin film formed on the side of the first conductive layer 21 away from the substrate 1, or it can be a coating formed on the surface of the first conductive layer 21. The form of the second conductive layer 22 is not specifically limited here. The second conductive layer 22 can be in contact with the first conductive layer 21, and its orthographic projection on the substrate 1 can coincide with the orthographic projection of the first conductive layer 21 on the substrate 1, that is, the second conductive layer 22 can be flush with the end of the first conductive layer 21.

[0094] The passivation layer 23 can be a thin film formed on the side of the second conductive layer 22 opposite to the first conductive layer 21, or it can be a coating formed on the side of the second conductive layer 22 opposite to the first conductive layer 21. No particular limitation is made to the form of the passivation layer 23. The passivation layer 23 can cover the entire surface of the second conductive layer 22, that is, the orthogonal projection of the passivation layer 23 on the substrate 1 can coincide with the orthogonal projection of the second conductive layer 22 on the substrate 1, or the orthogonal projection of the second conductive layer 22 on the substrate 1 is within the orthogonal projection of the passivation layer 23 on the substrate 1. The passivation layer 23 can protect the surface of the second conductive layer 22 to avoid damage to the surface of the second conductive layer 22; at the same time, the passivation layer 23 can also serve as an insulating layer, isolating the second conductive layer 22 from other structures, preventing coupling or short circuits between the second conductive layer 22 and other structures, and improving product yield.

[0095] The support layer 3 can be located on top of the gate structure 2. The support layer 3 can be strip-shaped. In the direction parallel to the substrate 1, the support layer 3 can be in contact with the upper surface of multiple gate structures 2. The orthogonal projection of the support layer 3 on the substrate 1 can penetrate the orthogonal projection of each gate structure 2 on the substrate 1. The support layer 3 can provide lateral support for each gate structure 2, reducing the probability of each gate structure 2 collapsing during subsequent manufacturing and helping to improve product yield.

[0096] like Figure 5 As shown, before etching to form the gate structure 2, the film layer to be etched to form the gate structure 2 can be defined as the gate material layer 200. Before etching the gate material layer 200 to form the gate structure 2, a support layer 3 can be formed on the surface of the gate material layer 200. Then, during the etching process of the gate material layer 200 to form the gate structure 2, the top of the gate structure 2 to be formed can be laterally supported by the support layer 3 to prevent the etched part from collapsing during the etching process, thereby improving the product yield. In addition, under the support of the support layer 3, the thickness of the gate material layer 200 can be appropriately increased, which helps to increase the height of the gate structure 2, improve the aspect ratio of the gate structure 2, and thus improve the electrical performance of the transistor.

[0097] The thickness of the support layer 3 can be 5nm to 50nm. For example, it can be 5nm, 10nm, 20nm, 30nm, 40nm or 50nm. Of course, the support layer 3 can also be other thicknesses, which will not be listed here.

[0098] In an exemplary embodiment of this disclosure, a gate structure 2 is formed on the surface of the active region 12, and a support layer 3 is formed on top of the gate structure 2. The orthographic projection of the support layer 3 on the substrate 1 passes through the orthographic projection of the gate structure 2 on the substrate 1 (i.e., step S120). This may include steps S210-S250, wherein:

[0099] Step S210: A gate material layer 200 is formed on the surface of the substrate 1.

[0100] like Figure 2 As shown, a first conductive material layer 201, a second conductive material layer 202, and a passivation material layer 203 can be sequentially formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. The material of the first conductive material layer 201 can be polycrystalline silicon, the material of the second conductive material layer 202 can be tungsten, and the material of the passivation material layer 203 can be silicon nitride.

[0101] The orthographic projections of the first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 on the substrate 1 can completely overlap, and the first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 can all cover each active region 12 and the shallow trench isolation structure 11 between each active region 12. The first conductive material layer 201, the second conductive material layer 202, and the passivation material layer 203 together constitute the gate material layer 200.

[0102] Step S220: A support material layer 300 is formed on the surface of the gate material layer 200.

[0103] like Figure 6 As shown, a support material layer 300 can be formed on the side of the gate material layer 200 facing away from the substrate 1. The support material layer 300 can be a thin film or a coating formed on the surface of the gate material layer 200. No specific limitation is made to the specific form of the support material layer 300 here. For example, the support material layer 300 can be formed on the surface of the gate material layer 200 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering.

[0104] The material of the support material layer 300 can be a material with a relatively large modulus. For example, it can be silicon nitride carbon. Of course, it can also be other materials with a large modulus, which will not be listed here.

[0105] In step S230, the support material layer 300 is patterned to form a support layer 3, which is flush with both ends of the gate material layer 200 in a direction parallel to the substrate 1.

[0106] The support material layer 300 can be etched using an etching process to form the support layer 3. The support layer 3 may include at least one support portion, which may be strip-shaped. In a direction parallel to the substrate 1, the two ends of the strip-shaped support portion may be flush with the two ends of the gate material layer 200. For example, the width of the support portion may be 2nm to 10nm, such as 2nm, 4nm, 6nm, 8nm, or 10nm. Of course, the support portion may also have other widths, which will not be listed here.

[0107] like Figure 7 As shown, a mask material layer 400 can be formed on the surface of the support material layer 300 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods. The material of the mask material layer 400 can be at least one of silicon, silicon oxynitride, or carbon; of course, other materials are also possible, which will not be listed here. The mask material layer 400 can be a single-layer structure or a multi-layer structure, without special limitations. Figure 8As shown, a photoresist layer 500 can be formed on the mask material layer 400 by spin coating or other methods. The material of the photoresist layer 500 can be positive or negative photoresist, and no special limitation is made here.

[0108] A photomask can be used to expose the photoresist layer 500. The mask pattern of the photomask can match the pattern required for the support layer 3. The mask pattern can be strip-shaped. The orthogonal projection of the strip-shaped mask pattern on the substrate 1 can pass through multiple channel regions and the shallow trench isolation structure 11 between each channel region.

[0109] The exposed photoresist layer 500 can be developed to form a developing area, which exposes the mask material layer 400. The mask material layer 400 and the support material layer 300 are etched in the developing area to form the support layer 3.

[0110] After the support layer 3 is formed, the photoresist layer 500 can be ashed to remove the photoresist layer 500, and the mask material layer 400 can be removed by dry etching process so that the mask material layer 400 no longer covers the surface of the support layer 3.

[0111] In step S240, a gate top layer 4 is formed on the surface of the gate material layer 200, and the upper surface of the gate top layer 4 is higher than or flush with the upper surface of the support layer 3.

[0112] After forming the support layer 3, insulating material can be backfilled onto the surface of the structure jointly formed by the support and the gate material layer 200 to form the gate top layer 4 on the surface of the gate material layer 200. For example... Figure 9 As shown, the insulating material can be the same as the material of the passivation material layer 203. For example, the insulating material can be deposited on the surface of the structure jointly formed by the support and the gate material layer 200 by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form the gate top layer 4. In some embodiments of this disclosure, the support can be buried in the gate top layer 4, that is, the upper surface of the gate top layer 4 can be higher than the upper surface of the support layer 3. In other embodiments of this disclosure, after the insulating material is deposited, the surface of the insulating material can be chemically mechanically polished to obtain the gate top layer 4. At this time, the surface of the gate top layer 4 is flush with the upper surface of the support layer 3. In this process, a flat surface can be formed to provide a flat reference for subsequent etching to form the gate structure 2.

[0113] In step S250, the gate top layer 4 and the gate material layer 200 are selectively etched to form a plurality of spaced gate structures 2, the top of each gate structure 2 being in contact with the support layer 3.

[0114] The gate top layer 4 and the gate material layer 200 can be selectively etched to form gate structures 2 in each active region 12. For example... Figure 10 As shown, a photoresist layer 500 can be formed on the surface of the structure jointly formed by the gate top layer 4 and the support layer 3 by spin coating or other methods. The material of the photoresist layer 500 can be positive or negative photoresist, and no special limitation is made here. A mask can be used to expose the photoresist layer 500, and the mask pattern of the mask can be matched with the pattern required for the gate structure 2.

[0115] The exposed photoresist layer 500 can be developed to form a developing region, which exposes the surface of the structure jointly formed by the gate top layer 4 and the support layer 3. The gate top layer 4 and the gate material layer 200 are selectively etched in the developing region to form the gate structure 2.

[0116] After the gate structure 2 is formed, the photoresist layer 500 can be ashed to remove the photoresist layer 500, thereby exposing the support layer 3 and the gate structure 2.

[0117] It should be noted that the top of each gate structure 2 can be in contact with the support layer 3. For example, the passivation layer 23 of each gate structure 2 can be in contact with the support layer 3. During the subsequent cleaning of the gate structure 2, the support layer 3 can provide lateral support for each gate structure 2, which can reduce the probability of the gate structure 2 collapsing and improve the product yield.

[0118] In an exemplary embodiment of this disclosure, a gate structure 2 is formed on the surface of the active region 12, and a support layer 3 is formed on top of the gate structure 2. The orthographic projection of the support layer 3 on the substrate 1 passes through the orthographic projection of the gate structure 2 on the substrate 1 (i.e., step S120). This may include steps S310-S340, wherein:

[0119] Step S310: A gate material layer 200 is formed on the surface of the substrate 1, the gate material layer 200 including a gate top layer 4.

[0120] like Figure 2 As shown, a first conductive material layer 201, a second conductive material layer 202, a passivation material layer 203, and a gate top material layer can be sequentially formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering. The material of the first conductive material layer 201 can be polysilicon, the material of the second conductive material layer 202 can be tungsten, the material of the passivation material layer 203 can be silicon nitride or silicon carbide nitride, and the material of the gate top material layer can be an insulating material. Its material can be the same as or different from the material of the passivation layer 23, and no special limitation is made here.

[0121] The first conductive material layer 201, the second conductive material layer 202, the passivation material layer 203, and the gate top material layer can be completely overlapped on the substrate 1 by their orthogonal projections. Furthermore, the first conductive material layer 201, the second conductive material layer 202, the passivation material layer 203, and the gate top material layer can all cover each active region 12 and the shallow trench isolation structure 11 between each active region 12. The first conductive material layer 201, the second conductive material layer 202, the passivation material layer 203, and the gate top material layer together constitute the gate material layer 200.

[0122] Step S320: Pattern the top layer 4 of the gate to form a top trench;

[0123] The gate top layer 4 can be patterned using photolithography, thereby forming at least one top trench in the gate top layer 4. In the direction perpendicular to the substrate 1, the top trench can penetrate the gate top layer 4 and expose the passivation layer 23; in the direction parallel to the substrate 1, the top trench can be flush with both ends of the gate top layer. When there are multiple top trenches, the multiple top trenches can be distributed at intervals and can be arranged in parallel.

[0124] In one exemplary embodiment of this disclosure, the width of the top trench is the same as the width of the support portion to be formed subsequently, and the number of top trenches can be the same as the number of support portions to be formed subsequently. For example, the width of the top trench can be 2nm to 10nm, such as 2nm, 4nm, 6nm, 8nm or 10nm. Of course, the top trench can also be other widths, which will not be listed here.

[0125] In step S330, a support layer 3 is formed in the top trench, and the support layer 3 is flush with both ends of the gate material layer 200 in a direction parallel to the substrate 1.

[0126] A support material can be filled into the top trench to form the support layer 3. For example, the support material can be filled into the top trench by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation, or magnetron sputtering to form the support layer 3. In some embodiments, the support material is different from the material of the passivation layer 23. For example, the material of the passivation layer 23 is silicon nitride, and the material of the support layer 3 is silicon carbide nitride; or, the material of the passivation layer 23 is silicon carbide nitride, and the material of the support layer 3 is silicon nitride.

[0127] In step S340, the gate material layer 200 is selectively etched to form a plurality of spaced gate structures 2, the top of each gate structure 2 being in contact with the support layer 3.

[0128] The gate material layer 200 can be selectively etched to form gate structures 2 in each active region 12. For example... Figure 10 As shown, a photoresist layer 500 can be formed on the surface of the structure jointly formed by the gate material layer 200 and the support layer 3 by spin coating or other methods. The material of the photoresist layer 500 can be positive or negative photoresist, without special limitation. A mask can be used to expose the photoresist layer 500, and the mask pattern of the mask can be matched with the pattern required for the gate structure 2.

[0129] The exposed photoresist layer 500 can be developed to form a developing region, which exposes the surface of the structure jointly formed by the gate material layer 200 and the support layer 3. The gate material layer 200 and the gate material layer 200 are selectively etched in the developing region to form the gate structure 2.

[0130] After the gate structure 2 is formed, the photoresist layer 500 can be ashed to remove the photoresist layer 500, thereby exposing the support layer 3 and each gate structure 2.

[0131] It should be noted that the top of each gate structure 2 can be in contact with the support layer 3. For example, the upper surface of the passivation layer 23 of each gate structure 2 can be in contact with the support layer 3. At the same time, the gate top layer 4 of each gate structure 2 can be embedded within the support layer 3 and in contact with the sidewall of the support layer 3. During the subsequent cleaning process of the gate structure 2, the support layer 3 can provide lateral support for each gate structure 2, which can reduce the probability of the gate structure 2 collapsing and improve the product yield.

[0132] like Figure 1 As shown, in step S130, a first isolation layer, a second isolation layer and a third isolation layer are sequentially formed on the sidewall of the gate structure, and the second isolation layer is in contact with the support layer through a contact surface.

[0133] A first insulating layer 5 can be formed on the sidewall of the gate structure 2. The first insulating layer 5 can provide insulation protection for the sidewall of the gate structure 2, preventing coupling or short circuit between the gate structure 2 and other surrounding structures, thereby improving product yield. At the same time, the first insulating layer 5 can also isolate the source and / or drain from the sidewall of the gate structure 2 by a non-zero distance, thereby reducing the GIDL effect and reducing standby power consumption.

[0134] The first insulating layer 5 can be a single-layer film or a multi-layer film, and no special limitation is made here. Preferably, the first insulating layer 5 has a multi-layer structure, such as... Figures 11-13As shown, it may include a first isolation layer 51, a second isolation layer 52, and a third isolation layer 53 sequentially formed on the sidewall of the gate structure 2, wherein: the first isolation layer 51 may be conformally attached to the sidewall surface of the gate structure 2, the second isolation layer 52 may cover the surface of the first isolation layer 51, and the third isolation layer 53 may cover the surface of the second isolation layer 52. The first isolation layer 51, the second isolation layer 52, and the third isolation layer 53 can form triple protection for the sidewall of the gate structure 2, which can enhance the insulation effect, reduce the possibility of coupling between the gate structure 2 and other surrounding structures, and improve the product yield.

[0135] In one exemplary embodiment of this disclosure, the material of the second isolation layer 52 is different from the materials of the first isolation layer 51 and the third isolation layer 53, so as to facilitate selective etching of the second isolation layer 52. In some embodiments, the materials of the first isolation layer 51 and the third isolation layer 53 are the same, and the materials of the second isolation layer 52 are different from those of the first isolation layer 51 and the third isolation layer 53. For example, the materials of the first isolation layer 51 and the third isolation layer 53 may be silicon nitride, and the material of the second isolation layer 52 may be silicon oxide. Of course, the materials of the first isolation layer 51, the second isolation layer 52, and the third isolation layer 53 may also be other, which will not be listed here, as long as the second isolation layer 52 can be distinguished from the first isolation layer 51 and the third isolation layer 53.

[0136] In one exemplary embodiment of this disclosure, the end of the second isolation layer 52 away from the substrate 1 can be contacted and connected to the surface of the support layer 3 near the substrate 1 through a contact surface, so that the end of the second isolation layer 52 away from the substrate 1 can be exposed after the support layer 3 is removed, thereby facilitating the subsequent removal of the second isolation layer 52.

[0137] In an exemplary embodiment of this disclosure, the contact surface between the support layer 3 and the second isolation layer 52 in the direction perpendicular to the substrate can be U-shaped. The contact area between the second isolation layer 52 and the support layer 3 can be increased by the U-shaped contact surface. After the support layer 3 is removed in the future, the U-shaped contact surface can be exposed. The design of the U-shaped contact surface can increase the exposed area of ​​the isolation layer, thereby facilitating the subsequent removal of the second isolation layer 52.

[0138] In one embodiment, the two opposite sidewalls of the U-shaped contact surface may be located on the sidewalls of the gate top layer 4 of the gate structure 2, and the bottom of the U-shape in the U-shaped contact surface may be located on the upper surface of the gate top layer 4 of the gate structure 2.

[0139] In an exemplary embodiment of this disclosure, for ease of process, forming a first insulating layer 5 on the sidewall of the gate structure 2 may include: after forming the gate structure 2, forming an insulating material layer on the surface of the structure jointly formed by the gate structure 2 and the substrate 1, that is: the insulating material layer can simultaneously cover the sidewall of the gate structure 2 and the surface of the substrate 1, and then the insulating material layer covering the surface of the substrate 1 can be removed while the insulating material layer covering the sidewall of the gate structure 2 is retained. The sidewall of the gate structure 2 can be insulated and protected by the insulating material layer to prevent the gate structure 2 from coupling or short-circuiting with other structures.

[0140] The insulating material layer can be a single-layer film or a multi-layer film, without any particular limitation. Preferably, the insulating material layer is a multi-layer structure, which may include a first isolation material layer, a second isolation material layer and a third isolation material layer formed sequentially on the sidewall of the gate structure 2, wherein the first isolation material layer is formed on the sidewall of the gate structure 2 and the surface of the substrate 1; the second isolation material layer may cover the surface of the first isolation material layer, and the third isolation material layer may cover the surface of the second isolation material layer.

[0141] In one embodiment of this disclosure, the material of the second isolation material layer is different from the materials of the first and third isolation material layers to facilitate selective etching of the second isolation material layer subsequently. In some embodiments, the materials of the first and third isolation material layers are the same, while the materials of the second isolation material layer are different from those of the first and third isolation material layers. For example, the materials of the first and third isolation material layers may be silicon nitride, and the material of the second isolation material layer may be silicon oxide. Of course, the materials of the first, second, and third isolation material layers may also be other than those listed here.

[0142] For example, a first isolation material layer, a second isolation material layer, and a third isolation material layer can be sequentially formed on the sidewall of the gate structure 2 and the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other methods. Of course, the first isolation material layer, the second isolation material layer, and the third isolation material layer can also be sequentially formed on the sidewall of the gate structure 2 and the surface of the substrate 1 by other methods. No special limitation is made here on the formation method of the first isolation material layer, the second isolation material layer, and the third isolation material layer.

[0143] In one embodiment, the substrate 1 can be used as an etch stop layer. The first isolation material layer, the second isolation material layer and the third isolation material layer covering the top of the substrate 1 can be removed simultaneously by the same etching process, leaving only the first isolation material layer, the second isolation material layer and the third isolation material layer covering the sidewall of the gate structure 2. The first isolation material layer, the second isolation material layer and the third isolation material layer covering the sidewall of the gate structure 2 can be used as the first isolation layer 51, the second isolation layer 52 and the third isolation layer 53, respectively.

[0144] It should be noted that when etching away the insulating material layer on the surface of substrate 1, the ends of the insulating material layer formed on the sidewall of gate structure 2 that are in contact with substrate 1 can be retained. The substrate 1 can support the insulating material layer formed on the sidewall of gate structure 2, reducing the possibility of peeling off the insulating material layer and helping to improve product yield. For example, when etching away the first, second, and third isolation material layers on the surface of substrate 1, the ends of the first, second, and third isolation material layers formed on the sidewall of gate structure 2 that are in contact with substrate 1 can be retained.

[0145] In one exemplary embodiment of this disclosure, the gate structure 2 may include a first gate structure and a second gate structure spaced apart. In some embodiments of this disclosure, the first gate structure and the second gate structure may be independent of each other and may be used to form independent transistors respectively. In other embodiments of this disclosure, the first gate structure and the second gate structure may be connected to each other. For example, the first gate structure and the second gate structure may be distributed adjacently and may be connected together in a ring to form two common-gate transistors.

[0146] The method for forming the semiconductor structure disclosed herein may further include:

[0147] Step S1310: Fill the space between the first gate structure and the second gate structure with insulating material to form an insulating layer, wherein the upper surface of the insulating layer is flush with the upper surface of the first gate structure and the upper surface of the second gate structure.

[0148] like Figure 14 and Figure 15As shown, for ease of distinction, the insulating layer formed between the first gate structure and the second gate structure can be defined as the second insulating layer 6. The second insulating layer 6 can be formed on the surface of the substrate 1 and can fill the gap between the first gate structure and the second gate structure. When multiple gate structures 2 are formed on the surface of the substrate 1, the second insulating layer 6 can also fill the gap between each gate structure 2. For example, the second insulating layer 6 can be in contact with the third isolation layer 53 on the sidewall of the gate structure 2. In subsequent processes, the second insulating layer 6 can provide lateral support for the gate structure 2, reducing the possibility of the gate structure 2 collapsing during subsequent processes and further improving product yield.

[0149] The second insulating layer 6 can be made of insulating material, thereby isolating the first gate structure and the second gate structure and preventing coupling between them. At the same time, the second insulating layer 6 can also isolate each gate structure 2 and prevent coupling between them. Furthermore, it can prevent coupling between the gate structure 2 and other surrounding structures, which helps to improve the electrical performance of the gate structure 2.

[0150] In one embodiment, the second insulating layer 6 may be made of a material with a low dielectric constant to reduce the parasitic capacitance between the gate structures 2. For example, the material of the second insulating layer 6 may be SOD, and the second insulating layer 6 may be formed on the surface of the substrate 1 by spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition or other methods. The thickness of the second insulating layer 6 may be equal to the height of the gate structure 2, that is, the surface of the second insulating layer 6 may be flush with the upper surface of the first gate structure and the upper surface of the second gate structure.

[0151] like Figure 1 As shown, in step S140, the support layer is removed to expose the contact surface of the second isolation layer.

[0152] Selective etching can be used to remove the support layer 3 and expose the contact surface of the second isolation layer. For example, selective etching can be used to selectively etch the support layer 3, the gate top layer 4 on top of the gate structure 2, and the second insulating layer 6 to remove the support layer 3 and expose the contact surface of the second isolation layer 52. In this embodiment, the structure after step S140 is as follows: Figure 16 As shown.

[0153] In one embodiment, the support layer 3 can be removed by a wet etching process. During the etching process, the etching ratio of the support layer 3, the gate top layer 4 on the top of the gate structure 2 and the second insulating layer 6 can be 10:8:1 to 20:18:1. For example, the selective etching ratio of the support layer 3, the gate top layer 4 and the second insulating layer 6 can be 10:8:1, 12:10:1, 14:12:1, 16:14:1, 18:16:1 or 20:18:1. Of course, other selective etching ratios are also possible, which will not be listed here.

[0154] It should be noted that the etching solution can be selected based on the materials of the support layer 3, the gate top layer 4, and the second insulating layer 6, thereby achieving the desired selective etching ratio. For example, when the support layer 3 is made of silicon carbide, the gate top layer 4 is made of silicon nitride, and the second insulating layer 6 is made of silicon oxide, the etching solution is an acidic solution. That is, the acidic solution can be used to selectively etch the support layer 3 through the contact surface exposed by the second insulating layer 52.

[0155] For example, the acidic solution can be hydrofluoric acid, such as buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the acidic solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No special restrictions are placed on the ratio and concentration of the acidic solution.

[0156] like Figure 1 As shown, in step S150, the second isolation layer is removed to form a gap between the first isolation layer and the third isolation layer.

[0157] A gap 7 can be formed on the sidewall of the gate structure 2, for example, the gap 7 can be formed in the first insulating layer 5. Since the dielectric constant of the gap 7 is relatively small, the parasitic capacitance between the gate structures 2 and the gate structures 2, as well as the parasitic capacitance between the gate structure 2 and other surrounding structures (e.g., conductive plugs in the substrate 1) can be reduced by setting the gap 7, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the DRAM.

[0158] When the first insulating layer 5 is a single-layer film, a gap 7 can be formed in the central region of the film in a direction parallel to the substrate 1. When the first insulating layer 5 is a multilayer film, for example, when the first insulating layer 5 includes a first isolation layer 51, a second isolation layer 52, and a third isolation layer, a gap 7 can be formed between the first isolation layer 51 and the third isolation layer by removing the second isolation layer 52. The opening of the gap 7 can be located at the contact surface between the original support layer 3 and the second isolation layer 52. That is, the opening of the gap 7 can be a U-shaped opening, and the sidewall of the U-shaped opening is jointly formed by the first isolation layer 51 and the third isolation layer 53. After removing the second isolation layer 52, the opening of the gap 7 between the first isolation layer 51 and the third isolation layer 53 can serve as a U-shaped opening. In this embodiment, the structure after completing step S150 is as follows: Figure 17 As shown.

[0159] A gap 7 is formed, and the width of the gap 7 can be equal to the width of the second isolation layer 52. For example, the width of the gap 7 can be 3nm to 15nm, such as 3nm, 6nm, 9nm, 12nm or 15nm. Of course, it can also be other widths, which are not specifically limited here.

[0160] In one exemplary embodiment of this disclosure, an acidic solution can be used to selectively etch the second isolation layer 52, thereby removing the second isolation layer 52. During this process, the second isolation layer 52 has a high selective etching ratio compared to the first isolation layer 51, the third isolation layer 53, and the second insulating layer 6. For example, the selective etching ratio of the second isolation layer 52 to the first isolation layer 51, the third isolation layer 53, and the second insulating layer 6 can be 10:1:1:1. In some embodiments of this disclosure, the acidic solution can be hydrofluoric acid.

[0161] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure of this disclosure may further include:

[0162] Step S160: A sealing layer 8 is formed, which seals the opening of the gap 7.

[0163] The sealing layer 8 is located on the surface of the structure formed by the second insulating layer 6, the gate structure 2, the first isolation layer 51 and the third isolation layer 53, and can fill the opening of the gap 7 to seal the opening of the gap 7. At the same time, it can also prevent the final semiconductor structure from breaking at the opening of the gap 7, thereby improving the product yield.

[0164] For example, a sealing layer 8 can be formed on the surface of the structure jointly formed by the second insulating layer 6, the gate structure 2, the first isolation layer 51, and the third isolation layer 53 using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. The material of the sealing layer 8 can be an insulating material, for example, silicon nitride. The thickness of the sealing layer 8 can be set according to actual needs, and no special limitation is made on the thickness of the sealing layer 8 here. In this embodiment, the structure after step S160 is as follows: Figure 18 As shown.

[0165] In some embodiments of this disclosure, such as Figure 19 As shown, after sealing the gap 7, the sealing layer 8 located on the surface of the second insulating layer 6 can be removed, thereby exposing the second insulating layer 6.

[0166] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0167] This disclosure also provides a semiconductor structure, which may be a transistor in a memory, such as... Figure 19 As shown, the semiconductor structure may include a substrate 1, a gate structure 2, and a first insulating layer 5, wherein:

[0168] The substrate 1 may include a shallow trench isolation structure 11 and an active region 12 separated by the shallow trench isolation structure 11;

[0169] Gate structure 2 can be located on the surface of each active region 12;

[0170] A first isolation layer 51 and a third isolation layer 53 are formed on the sidewall of the gate structure 2, and a gap 7 is formed between the first isolation layer 51 and the third isolation layer 53.

[0171] The semiconductor structure disclosed herein has several advantages. First, since the support layer 3 is connected to the top of each gate structure 2, the support layer 3 can provide lateral support for each gate structure 2, reducing the probability of each gate structure 2 collapsing during subsequent manufacturing and helping to improve product yield. Second, since the dielectric constant of the gap 7 located on the sidewall of the gate structure 2 is relatively small, the parasitic capacitance between gate structures 2 and between gate structures 2 and other surrounding structures (e.g., conductive plugs) can be reduced by setting the gap 7, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the DRAM. Furthermore, since the first isolation layer 51 and the second isolation layer 52 are located on the sidewall of the gate structure 2, the first isolation layer 51 and the second isolation layer 52 can provide insulation protection for the sidewall of the gate structure 2, thereby reducing the probability of coupling between the gate structure 2 and other structures and further improving product yield.

[0172] The specific details of the semiconductor structure in the embodiments of this disclosure are described in detail below:

[0173] like Figure 2 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0174] In one embodiment, the substrate 1 may be a silicon substrate 1, with a shallow trench isolation structure 11 formed therein. The shallow trench isolation structure 11 is formed by forming trenches in the substrate 1 and then filling the trenches with an isolation material layer. The material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, etc., and is not specifically limited thereto. The cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs. The shallow trench isolation structure 11 can separate a plurality of active regions 12 on the substrate 1, and each active region 12 may include a first doped region and a second doped region arranged at intervals.

[0175] Substrate 1 can be an n-type substrate 1, and a first doped region and a second doped region can be doped to form the source and drain, respectively. For example, both the first and second doped regions can be p-type doped to form p-type doped regions, which can form a pn junction with the n-type substrate 1. For example, p-type doping material can be doped into the first and second doped regions to form p-type semiconductors. The p-type doping material can be an element located in Group III of the periodic table, for example, boron, but it can also be other elements, which will not be listed here.

[0176] The first doped region can be used as the source and the second doped region can be used as the drain; or, the first doped region can be used as the drain and the second doped region can be used as the source.

[0177] In one embodiment, boron ions can be implanted into the first doped region and the second doped region by ion implantation. Of course, other processes can also be used to dope the first doped region and / or the second doped region, and no special limitation is made here.

[0178] The area between the first doped region and the second doped region can be a channel region, which allows current to flow. The current in the channel region can be controlled by the voltage of the gate structure 2 above it to achieve gate control function. In some embodiments of this disclosure, the first doped region, the second doped region, and the channel region together constitute the active region 12.

[0179] In one embodiment of this disclosure, a shallow doped region can be formed on the side of the first doped region and the second doped region near the channel region, and the short-channel effect of the semiconductor structure can be reduced by setting the shallow doped region.

[0180] The gate structure 2 can be formed on the surface of the channel region of the active region 12. In one embodiment, the gate structure 2 can be formed on the surface of multiple channel regions simultaneously by the same etching process, and the gate structures 2 can be spaced apart; that is, in the same etching process, a gate structure 2 can be formed on the surface of each channel region.

[0181] In some embodiments of this disclosure, among the plurality of gate structures 2, adjacent gate structures 2 may be independent of each other, and each gate structure 2 may be used to form an independent transistor; in other embodiments of this disclosure, the plurality of gate structures 2 may include a plurality of spaced gate structure groups, each gate structure group may include two interconnected gate structures 2, the two interconnected gate structures 2 may be distributed adjacently and may be connected together in a ring to form two common gate transistors.

[0182] In one exemplary embodiment of this disclosure, the gate structure 2 may include a first conductive layer 21, a second conductive layer 22, and a passivation layer 23 stacked along a direction perpendicular to the substrate 1, wherein:

[0183] The first conductive layer 21 can be a thin film or a coating formed on the surface of the substrate 1. No particular limitation is made on the form of the first conductive layer 21. The first conductive layer 21 can cover the surface of the channel region.

[0184] The second conductive layer 22 can be a thin film formed on the side of the first conductive layer 21 away from the substrate 1, or it can be a coating formed on the surface of the first conductive layer 21. The form of the second conductive layer 22 is not specifically limited here. The second conductive layer 22 can be in contact with the first conductive layer 21, and its orthographic projection on the substrate 1 can coincide with the orthographic projection of the first conductive layer 21 on the substrate 1, that is, the second conductive layer 22 can be flush with the end of the first conductive layer 21.

[0185] The passivation layer 23 can be a thin film formed on the side of the second conductive layer 22 opposite to the first conductive layer 21, or it can be a coating formed on the side of the second conductive layer 22 opposite to the first conductive layer 21. No particular limitation is made to the form of the passivation layer 23. The passivation layer 23 can cover the entire surface of the second conductive layer 22, that is, the orthogonal projection of the passivation layer 23 on the substrate 1 can coincide with the orthogonal projection of the second conductive layer 22 on the substrate 1, or the orthogonal projection of the second conductive layer 22 on the substrate 1 is within the orthogonal projection of the passivation layer 23 on the substrate 1. The passivation layer 23 can protect the surface of the second conductive layer 22 to avoid damage to the surface of the second conductive layer 22; at the same time, the passivation layer 23 can also serve as an insulating layer, isolating the second conductive layer 22 from other structures, preventing coupling or short circuits between the second conductive layer 22 and other structures, and improving product yield.

[0186] In one exemplary embodiment of this disclosure, the gate structure may further include a gate top layer 4, which is located on top of the passivation layer 23. The gate top layer 4 may be made of the same material as the passivation layer 23 or may be made of a different material than the passivation layer 23, and no special limitation is made here.

[0187] In one exemplary embodiment of this disclosure, the gate structure may include a first gate structure and a second gate structure spaced apart. In some embodiments of this disclosure, the first gate structure and the second gate structure may be independent of each other and may be used to form independent transistors respectively. In other embodiments of this disclosure, the first gate structure and the second gate structure may be connected to each other. For example, the first gate structure and the second gate structure may be distributed adjacently and may be connected together in a ring to form two common-gate transistors.

[0188] A first insulating layer 5 can be formed on the sidewall of the gate structure 2. The first insulating layer 5 can provide insulation protection for the sidewall of the gate structure 2, preventing coupling or short circuit between the gate structure 2 and other surrounding structures, thereby improving product yield. At the same time, the first insulating layer 5 can also isolate the source and / or drain from the sidewall of the gate structure 2 by a non-zero distance, thereby reducing the GIDL effect and reducing standby power consumption.

[0189] The first insulating layer 5 may have a gap 7. Since the dielectric constant of the gap 7 is relatively small, the parasitic capacitance between the gate structure 2 and the gate structure 2, as well as the parasitic capacitance between the gate structure 2 and other surrounding structures (e.g., conductive plugs in the substrate 1) can be reduced by setting the gap 7, thereby reducing power consumption and improving the electrical performance and signal transmission performance of the DRAM.

[0190] The first insulating layer 5 can be a single-layer film or a multi-layer film, and no special limitation is made here. Preferably, the first insulating layer 5 has a multi-layer structure, such as... Figures 11-13 As shown, it may include a first isolation layer 51 and a third isolation layer 53 sequentially formed on the sidewall of the gate structure 2, wherein: the first isolation layer 51 may be conformally attached to the sidewall surface of the gate structure 2, and the third isolation layer 53 may be located on the side of the first isolation layer 51 away from the sidewall of the gate structure 2. The first isolation layer 51 and the third isolation layer 53 can form a double protection for the sidewall of the gate structure 2, which can enhance the insulation effect, reduce the possibility of the gate structure 2 coupling with other surrounding structures, and improve the product yield.

[0191] When the first insulating layer 5 is a single-layer film, a gap 7 can be formed in the central region of the film in a direction parallel to the substrate 1. When the first insulating layer 5 is a multilayer film, for example, when the first insulating layer 5 includes a first isolation layer 51 and a third isolation layer, the gap 7 can be formed between the first isolation layer 51 and the third isolation layer 53, and the opening of the gap 7 can be located on top of the passivation layer 23. The opening of the gap 7 can be a U-shaped opening, and the sidewalls of the U-shaped opening are jointly formed by the first isolation layer 51 and the third isolation layer 53. The opening of the gap 7 between the first isolation layer 51 and the third isolation layer 53 can serve as a U-shaped opening.

[0192] In one exemplary embodiment of this disclosure, the width of the gap 7 can be 3nm to 15nm, for example, it can be 3nm, 6nm, 9nm, 12nm or 15nm, and of course, it can also be other widths, which are not specifically limited here.

[0193] In some embodiments, the first isolation layer 51 and the third isolation layer 53 are made of the same material. For example, the first isolation layer 51 and the third isolation layer 53 may be made of silicon nitride. Of course, the materials of the first isolation layer 51 and the third isolation layer 53 may also be other materials, which will not be listed here.

[0194] In some embodiments of this disclosure, the semiconductor structure may further include an insulating layer. A second insulating layer 6 may be formed on the surface of the substrate 1. For ease of distinction, the insulating layer formed between the first gate structure and the second gate structure may be defined as the second insulating layer 6. The second insulating layer 6 may be formed on the surface of the substrate 1 and may fill the gap between the first gate structure and the second gate structure. When multiple gate structures are formed on the surface of the substrate 1, the second insulating layer 6 may also fill the gap between each gate structure. For example, the second insulating layer 6 may be in contact with the third isolation layer 53 on the sidewall of the gate structure 2. In subsequent processes, the second insulating layer 6 can provide lateral support for the gate structure 2, reducing the possibility of the gate structure 2 collapsing during subsequent processes and further improving product yield.

[0195] The second insulating layer 6 can be made of insulating material, thereby isolating the first gate structure and the second gate structure and preventing coupling between them. At the same time, the second insulating layer 6 can also isolate each gate structure 2 and prevent coupling between them. Furthermore, it can prevent coupling between the gate structure 2 and other surrounding structures, which helps to improve the electrical performance of the gate structure 2.

[0196] In one embodiment, the thickness of the second insulating layer 6 may be equal to the height of the gate structure 2, that is, the surface of the second insulating layer 6 may be flush with the upper surfaces of the first gate structure and the second gate structure. The second insulating layer 6 may be made of a material with a low dielectric constant to reduce the parasitic capacitance between the gate structures 2. For example, the material of the second insulating layer 6 may be SOD. Of course, the second insulating layer 6 may also be other materials with good insulating properties, which will not be listed here.

[0197] In some embodiments of this disclosure, the semiconductor structure may further include a sealing layer 8, which seals the opening of the gap 7. For example, the sealing layer 8 may be located on the surface of the structure formed by the second insulating layer 6, the gate structure 2, the first isolation layer 51, and the third isolation layer 53, and may fill the opening of the gap 7 to seal the opening of the gap 7. This also prevents the final semiconductor structure from breaking at the opening of the gap 7, thereby improving product yield.

[0198] In an exemplary embodiment of this disclosure, the orthogonal projection of the sealing layer 8 on the substrate 1 can pass through the orthogonal projection of the gate structure 2 on the substrate 1, and when a plurality of spaced gate structures 2 are formed on the substrate 1, the orthogonal projection of the sealing layer 8 on the substrate 1 can simultaneously pass through the orthogonal projections of the plurality of gate structures 2 on the substrate 1.

[0199] The sealing layer 8 can be made of an insulating material, such as silicon nitride. The thickness of the sealing layer 8 can be set according to actual needs, and no special limit is made here.

[0200] This disclosure also provides a memory, which may include the semiconductor structure of any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and the method of forming the semiconductor structure, and will not be repeated here.

[0201] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0202] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a shallow trench isolation structure and an active region separated by the shallow trench isolation structure; A gate structure is formed on the surface of the active region, and a support layer is formed on top of the gate structure, wherein the orthogonal projection of the support layer on the substrate passes through the orthogonal projection of the gate structure on the substrate; A first isolation layer, a second isolation layer, and a third isolation layer are sequentially formed on the sidewall of the gate structure, and the second isolation layer is in contact with the support layer through a contact surface; Remove the support layer to expose the contact surface of the second insulating layer; Remove the second isolation layer to form a gap between the first isolation layer and the third isolation layer; A sealing layer is formed, which seals the opening of the void.

2. The forming method according to claim 1, characterized in that, The step of forming a gate structure on the surface of the active region and forming a support layer on top of the gate structure, wherein the orthogonal projection of the support layer on the substrate extends through the orthogonal projection of the gate structure on the substrate, includes: A gate material layer is formed on the surface of the substrate; A support material layer is formed on the surface of the gate material layer; The support material layer is patterned to form a support layer, wherein the support layer is flush with both ends of the gate material layer in a direction parallel to the substrate. A gate top layer is formed on the surface of the gate material layer, and the upper surface of the gate top layer is higher than or flush with the upper surface of the support layer; The gate top layer and the gate material layer are selectively etched to form multiple spaced gate structures, with the top of each gate structure in contact with the support layer.

3. The forming method according to claim 1, characterized in that, The step of forming a gate structure on the surface of the active region and forming a support layer on top of the gate structure, wherein the orthogonal projection of the support layer on the substrate extends through the orthogonal projection of the gate structure on the substrate, includes: A gate material layer is formed on the surface of the substrate, the gate material layer including a gate top layer; The top layer of the gate is patterned to form a top trench; A support layer is formed in the top trench, and the support layer is flush with both ends of the gate material layer in a direction parallel to the substrate; The gate material layer is selectively etched to form multiple spaced gate structures, with the top of each gate structure in contact with the support layer.

4. The forming method according to claim 1, characterized in that, The gate structure includes a first gate structure and a second gate structure spaced apart. Before removing the support layer, the formation method further includes: An insulating material is filled between the first gate structure and the second gate structure to form an insulating layer, the upper surface of which is flush with the upper surfaces of the first gate structure and the second gate structure.

5. The forming method according to claim 1, characterized in that, The width of the gap is 3nm~15nm.

6. The forming method according to claim 1, characterized in that, The top of the gate structure includes a passivation layer, the passivation layer being made of a different material than the support layer, and the removal of the support layer includes: The support layer is selectively etched.

7. The forming method according to any one of claims 1-6, characterized in that, The material of the second isolation layer is different from the materials of the first isolation layer and the third isolation layer.

8. The forming method according to claim 7, characterized in that, The first isolation layer and the third isolation layer are made of the same material.

9. The forming method according to claim 8, characterized in that, The removal of the second isolation layer includes: The second isolation layer is selectively etched through the exposed contact surface using an acidic solution.

10. A semiconductor structure, characterized in that, include: The substrate includes a shallow trench isolation structure and an active region separated by the shallow trench isolation structure; A gate structure is located on the surface of the active region; A first isolation layer and a third isolation layer are formed on the sidewall of the gate structure, and a gap exists between the first isolation layer and the third isolation layer; A sealing layer is located on top of the gate structure, the first isolation layer and the third isolation layer, and the sealing layer seals the opening of the gap; The orthographic projection of the sealing layer on the substrate passes through the orthographic projection of the gate structure on the substrate.

11. The semiconductor structure according to claim 10, characterized in that, The gate structure includes a first gate structure and a second gate structure spaced apart, and the semiconductor structure further includes: An insulating layer is filled between the first gate structure and the second gate structure, and the surface of the insulating layer is flush with the upper surface of the first gate structure and the upper surface of the second gate structure.

12. The semiconductor structure according to claim 10, characterized in that, The width of the gap is 3nm~15nm.

13. The semiconductor structure according to any one of claims 11-12, characterized in that, The first isolation layer and the third isolation layer are made of the same material.

14. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 10-13.

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