Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure, which comprises the following steps: providing a substrate; forming a plurality of interval distributed trench gate structures in the substrate; forming interval source region structures on the top of the substrate between adjacent trench gate structures to form a power device structure; and forming a medium layer with a preset thickness on the surface of the substrate far from the trench gate structure. The application can improve the warping problem of a silicon wafer process, and different stress medium layers can be used according to different warping states of the silicon wafer, so that the device performance is improved and the process becomes a batch production process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the continuous advancement of semiconductor technology, the functions of devices are becoming increasingly powerful, and the integration level of devices is getting higher and higher. Trench MOSFETs and trench IGBTs often use high-temperature processes to process silicon wafers. However, high-temperature processes usually have a significant impact on the warpage of silicon wafers. Excessive silicon wafer warpage can lead to frequent equipment shutdowns and prevent subsequent processes from being carried out. Moreover, this problem will prevent this type of product from being mass-produced.

[0003] Furthermore, as power MOSFETs and IGBTs demand increasingly higher switching power densities and switching losses, increasing trench density has become a crucial means and approach for optimizing device performance. To address the issue of increased silicon wafer warpage caused by high-temperature processes, existing technologies typically employ methods such as increasing the trench density of the front-side structure or optimizing high-temperature thermal processes. However, these two approaches can negatively impact other performance parameters of the product, leading to performance defects. Summary of the Invention

[0004] Based on this, it is necessary to address the problems mentioned above by providing a method and structure for fabricating a semiconductor structure that can increase the trench density on the front side of trench MOSFETs and trench IGBTs while ensuring that the excessive silicon wafer warpage caused by high-temperature processes is reduced, and at the same time improve the product performance parameters.

[0005] To achieve the above and other related objectives, one aspect of this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0006] Provide substrate;

[0007] Multiple spaced trench gate structures are formed within the substrate;

[0008] A spaced source region structure is formed at the top of the substrate between adjacent trench gate structures to form a power device structure;

[0009] A dielectric layer of a predetermined thickness is formed on the surface of the substrate away from the trench gate structure.

[0010] In the semiconductor structure fabrication method described in the above embodiments, a substrate is first provided, and then multiple spaced trench gate structures are formed in the substrate. Spaced source region structures are formed at the top of the substrate between adjacent trench gate structures to form a power device structure. After forming the spaced source region structures to form the power device structure, a dielectric layer of a predetermined thickness is formed on the surface of the substrate away from the trench gate structures. The dielectric layer can generate tensile stress on the surface of the substrate away from the trench gate structures. The tensile stress improves the warpage of the substrate, increases the radius of curvature of the substrate, and increases the trench density of the semiconductor device. This limits the radius of curvature of the substrate to a certain range, thereby improving the problem of excessive silicon wafer warpage caused by the high-temperature process in the aforementioned operation and improving the performance parameters of the semiconductor device. Because improving the warpage of the silicon substrate simultaneously enhances the device's performance parameters, this application effectively optimizes device performance compared to existing technologies that optimize high-temperature thermal processes, which can negatively impact product performance. Furthermore, this application introduces a new process design without requiring complex high-temperature processes or alterations to previous process flows, thus mitigating the problem of excessive silicon substrate warpage at minimal cost. Additionally, since the dielectric layer completely covers the substrate surface away from the trench gate structure, symmetrical stress distribution across the silicon wafer is ensured, preventing excessive stress in any one direction. This method also results in more uniform warpage across the silicon wafer, further reducing excessive warpage. Therefore, this application optimizes product performance, increases trench density, ensures smooth process flow, and improves the yield of manufactured semiconductor devices while simultaneously addressing excessive silicon substrate warpage.

[0011] In one embodiment, the step of forming a plurality of spaced trench gate structures within a substrate includes:

[0012] Multiple spaced trench gate structures are formed within the substrate.

[0013] In one embodiment, the dielectric layer is used to generate tensile stress on the substrate. The tensile stress of the dielectric layer is changed by changing the material and thickness of the dielectric layer, so that the radius of curvature of the substrate is greater than or equal to the target radius of curvature.

[0014] In one embodiment, the tensile stress is 50 MPa-300 MPa.

[0015] In one embodiment, the preset thickness is 0.1μm-5μm.

[0016] In one embodiment, the material of the dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

[0017] In one embodiment, the substrate top between adjacent source region structures includes a body region structure; the step of forming spaced source region structures in the substrate top between adjacent trench gate structures to form a power device structure includes:

[0018] A first-type well region is formed in the substrate on both sides of the trench gate structure using an ion implantation process;

[0019] A second type of heavily doped region is formed in the first type of well region on both sides of the trench gate structure using an ion implantation process to form the source region structure;

[0020] A first-type heavily doped region is formed in the substrate between adjacent second-type heavily doped regions using an ion implantation process to form a bulk structure.

[0021] In one embodiment, the step of forming spaced source region structures at the top of the substrate between adjacent trench gate structures to form a power device structure further includes:

[0022] A spaced dielectric isolation layer is formed, which covers a trench gate structure and the top surface of a second type of heavily doped region located on opposite sides of the trench gate structure; the gap between adjacent dielectric isolation layers exposes the top surface of the first type of heavily doped region.

[0023] In one embodiment, the step of forming spaced source region structures at the top of the substrate between adjacent trench gate structures to form a power device structure further includes:

[0024] A front metal layer is formed, which covers the top surface of the exposed type I heavily doped region and the top surface of the dielectric isolation layer.

[0025] Another aspect of this application provides a semiconductor structure fabricated using the method described in any one of the foregoing embodiments. The semiconductor structure includes a substrate, a power device structure, and a dielectric layer. A plurality of spaced trench gate structures are formed in the substrate. The power device structure is formed on the top of the substrate between adjacent trench gate structures. The power device structure also includes a first type well region, a second type heavily doped region, a first type heavily doped region, a dielectric isolation layer, and a front metal layer. The first type well regions are formed in the substrate on opposite sides of the trench gate structures. The second type heavily doped regions are formed in the first type well regions on opposite sides of the trench gate structures. The first type heavily doped regions are formed in the substrate between adjacent second type heavily doped regions. The dielectric isolation layer covers a trench gate structure and the top surfaces of the second type heavily doped regions located on opposite sides of the trench gate structure and is spaced apart, with the gaps exposing the top surfaces of the first type heavily doped regions. The front metal layer covers the exposed top surfaces of the first type heavily doped regions and the top surface of the dielectric isolation layer. The dielectric layer is formed on the surface of the substrate away from the trench gate structure and has a predetermined thickness to generate tensile stress on the substrate on the surface of the substrate away from the trench gate structure.

[0026] In the semiconductor structure described above, the dielectric layer generates tensile stress on the substrate at the surface of the substrate away from the trench gate structure. The material and thickness of the dielectric layer can be changed to adjust the magnitude of the tensile stress, so that the radius of curvature of the substrate is greater than or equal to the target radius of curvature. At the same time, the parameter performance of the semiconductor device is improved by increasing the trench density. Furthermore, this application introduces a new process design without introducing complex high-temperature processes. While ensuring the improvement of excessive warpage of the silicon wafer substrate, it also optimizes product performance and increases the trench density of the device, thereby ensuring the smooth progress of the process and improving the yield of the manufactured semiconductor device. Attached Figure Description

[0027] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0028] Figure 1 The flowchart shown is a method for fabricating a semiconductor structure according to an embodiment of this application.

[0029] Figure 2a The diagram shown is a cross-sectional view of the structure obtained in a semiconductor structure fabrication method provided in one embodiment of this application.

[0030] Figure 2bThe diagram shown is a cross-sectional view of the structure obtained in a semiconductor structure fabrication method provided in another embodiment of this application.

[0031] Figure 3 The flowchart shown is a process flow chart of steps S30-S32 in a method for preparing a semiconductor structure provided in an embodiment of this application.

[0032] Figure 4 The flowchart shown is a process flow chart of steps S30-S34 in a method for preparing a semiconductor structure provided in an embodiment of this application.

[0033] Figure 5 The image shown is a comparison of the cross-sectional structure of a silicon wafer before and after process optimization, as provided in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10. Substrate; 20. Epitaxial structure; 30. Trench gate structure; 31. Gate oxide layer; 32. Gate dielectric layer; 40. Type I well region; 50. Type II heavily doped region; 60. Type I heavily doped region; 70. Dielectric isolation layer; 80. Front metal layer; 90. Dielectric layer. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] Embodiments of the application are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the areas shown herein, but include shape deviations due to, for example, manufacturing processes. The areas shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of the application.

[0042] Please see Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] The high-temperature processes and metal-layer stresses involved in the fabrication of trench MOSFETs and trench IGBTs can cause silicon wafer warpage during manufacturing. Excessive warpage can lead to frequent equipment downtime, preventing subsequent processes and hindering mass production. Traditional techniques often optimize high-temperature thermal processes to mitigate excessive warpage, but this approach can negatively impact product performance and yield. This application provides a method for fabricating a semiconductor structure and the semiconductor structure itself. Please refer to [link to relevant documentation]. Figures 2a-2b Traditional processes can cause severe warping of silicon wafers after front-side metal deposition. In this application, a dielectric layer 90 is formed on the surface of the substrate 10 away from the trench gate structure 30 after the front-side metal deposition step. This dielectric layer 90 will generate tensile stress on the substrate 10 on this surface to improve the warping of the substrate 10, increase the trench density, increase the radius of curvature of the substrate 10, optimize the performance parameters of semiconductor devices, ensure the smooth progress of subsequent processes, and improve the yield of semiconductor products.

[0044] Please see Figure 1 In one embodiment of this application, a method for fabricating a semiconductor structure includes the following steps:

[0045] Step S1: Provide a substrate;

[0046] Step S2: Form multiple spaced trench gate structures within the substrate;

[0047] Step S3: Form a spaced source region structure at the top of the substrate between adjacent trench gate structures to form a power device structure;

[0048] Step S4: Form a dielectric layer of a predetermined thickness on the surface of the substrate away from the trench gate structure.

[0049] Specifically, please refer to Figure 2a In the semiconductor structure fabrication method described in the above embodiments, a substrate 10 is first provided, and then a plurality of spaced trench gate structures 30 are formed in the substrate 10. Spaced source region structures are formed at the top of the substrate 10 between adjacent trench gate structures 30 to form a power device structure. After forming the spaced source region structures to form the power device structure, a dielectric layer 90 of a predetermined thickness is formed on the surface of the substrate 10 away from the trench gate structures 30. The dielectric layer 90 can generate tensile stress on the surface of the substrate 10 away from the trench gate structures 30. The tensile stress reduces the warpage of the substrate 10, increases the radius of curvature, and increases the trench density, thereby limiting the radius of curvature of the substrate 10 to a certain range. This improves the problem of excessive silicon wafer warpage caused by the high-temperature process in the aforementioned operation and improves the performance of various parameters of the semiconductor device. Because improving silicon wafer warpage simultaneously enhances device performance parameters, this application effectively optimizes device performance compared to existing technologies that optimize high-temperature thermal processes, which can negatively impact product performance. Furthermore, this application introduces a new process design without requiring complex high-temperature processes or alterations to previous process flows, thus mitigating excessive silicon wafer warpage at minimal cost. Additionally, since the dielectric layer 90 completely covers the surface of the substrate 10 away from the trench gate structure 30, symmetrical stress distribution across the silicon wafer is ensured, preventing excessive stress in any single direction. This method also results in more uniform warpage across the silicon wafer, further reducing excessive warpage. Therefore, this application optimizes product performance, increases trench density, ensures smooth process flow, and improves the yield of manufactured semiconductor devices while simultaneously addressing excessive warpage of the silicon substrate 10.

[0050] In step S1, please refer to Figure 1 Step S1 in the middle and Figure 2a Substrate 10 is provided.

[0051] As an example, substrate 10 may be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, substrate 10 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, substrate 10 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the substrate type based on the type of transistors formed on substrate 10; therefore, the type of substrate 10 should not limit the scope of protection of this application.

[0052] In step S2, please refer to Figure 1 S2 step and Figure 2a A plurality of spaced trench gate structures 30 are formed within the substrate 10. The trench gate structure 30 may include a gate dielectric layer 32 formed within the substrate 10 and a gate oxide layer 31 located between the gate dielectric layer 32 and the substrate 10.

[0053] As an example, step S2 may include the following steps:

[0054] Step S20: A first patterned mask layer (not shown) is formed on the upper surface of the substrate 10. An opening (not shown) is formed in the patterned mask layer, and the opening defines the position and shape of the gate trench (not shown).

[0055] Step S21: Based on the first patterned mask layer, the upper surface of the substrate 10 is etched using a dry etching process or a wet etching process to obtain the gate trench.

[0056] Step S22: A gate oxide layer 31 covering the bottom and sidewalls of the gate trench is formed in the gate trench, and a gate dielectric layer 32 is filled in the trench. The gate oxide layer 31 and the gate dielectric layer 32 together fill the gate trench.

[0057] In this embodiment, the parameters of the dry etching process include: the gas includes one or more of fluorocarbon gas, HBr, and Cl2, and the carrier gas includes CF4, CHF3, CH2F2, or CH3F; the carrier gas is an inert gas, such as He; the gas flow rate is 50 sccm-400 sccm; and the pressure is 3 mTorr-8 mTorr. The etching solution used in the wet etching process can be a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0058] As an example, in step S21, there are multiple gate trenches, each with the same depth h, ranging from 2.5 μm to 8 μm; each with the same width w, ranging from 0.3 μm to 1.2 μm; and each with the same spacing d between adjacent gate trenches, ranging from 1.2 μm to 4.0 μm.

[0059] As an example, the formed first patterned mask layer (not shown) may include a hard mask layer, which may be a single-layer structure or a multi-layer stacked structure, and its material may be silicon oxide. Then, photoresist is coated on the hard mask layer, and after a series of steps such as exposure and development, a patterned photoresist layer is formed. The patterned photoresist layer defines the position and shape of the gate trench. The hard mask layer is then etched based on the patterned photoresist layer to form the patterned mask layer, and then the patterned photoresist layer is removed. Of course, in other embodiments of this application, the patterned photoresist layer may be retained during the formation of the first patterned mask layer, and then removed after etching the substrate 10.

[0060] As an example, step S22 may employ one or more of atomic layer deposition, plasma vapor deposition, and rapid thermal oxidation (RTO) processes to form a gate oxide layer 31 covering the bottom and sidewalls of the gate trench. The material of the gate oxide layer 31 may include, but is not limited to, silicon dioxide. The deposition process may include, but is not limited to, one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD) processes. The material of the gate dielectric layer 32 may include, but is not limited to, polysilicon.

[0061] In step S3, please refer to Figure 1 Step S3 in the middle and Figure 2a A spaced source region structure is formed at the top of the substrate 10 between adjacent trench gate structures 30 to form a power device structure.

[0062] As an example, the power device structure can be processed using an ion implantation process. After the resulting device structure is formed, the high-temperature thermal process and the occurrence of metal layer stress in the aforementioned process will cause the silicon substrate 10 to exhibit tensile stress, and the substrate 10 will warp to a certain extent. When the warping reaches a curvature radius less than the target curvature radius, such as 20m, it will cause the process-related equipment to frequently shut down, making it impossible to carry out subsequent processes, and causing this type of product to fail to meet the needs of mass production, thus reducing the production efficiency of semiconductor devices.

[0063] In step S4, please refer to Figure 1 Step S4 in the middle and Figure 2a A dielectric layer 90 of a predetermined thickness is formed on the surface of the substrate 10 away from the trench gate structure 30.

[0064] Another method for fabricating a semiconductor structure is provided in one embodiment of this application; please refer to [link to relevant documentation]. Figure 2b Specifically, it includes the following steps:

[0065] Step S'1: Provide a substrate 10, on which an epitaxial structure 20 is formed;

[0066] Step S'2: A plurality of spaced trench gate structures 30 are formed in the epitaxial structure 20. The trench gate structure 30 may include a gate dielectric layer 32 formed in the epitaxial structure 20 and a gate oxide layer 31 located between the gate dielectric layer 32 and the epitaxial structure 20.

[0067] Step S'3: Form a spaced source region structure at the top of the epitaxial structure 20 between adjacent trench gate structures 30 to form a power device structure;

[0068] Step S'4: A dielectric layer 90 of a predetermined thickness is formed on the surface of the substrate 10 away from the trench gate structure 30.

[0069] In the above embodiment, specifically, an epitaxial structure 20 is first formed on the substrate 10, and then a plurality of spaced trench gate structures 30 are formed within the epitaxial structure 20. Spaced source region structures are formed at the top of the epitaxial structure 20 between adjacent trench gate structures 30 to form a power device structure. After forming the spaced source region structures to form the power device structure, a dielectric layer 90 of a predetermined thickness is formed on the surface of the substrate 10 away from the trench gate structures 30. The dielectric layer 90 generates tensile stress on the surface of the substrate 10 away from the trench gate structures 30. This tensile stress reduces the warpage of the substrate 10, increases the radius of curvature, and increases the trench density. The depth of the trench gate structure 30 is greater than the depth of the epitaxial structure 20.

[0070] For example, please refer to Figure 2a and Figure 2bThe dielectric layer 90 generates tensile stress on the substrate 10 on the surface away from the trench gate structure 30. The tensile stress of the dielectric layer 90 can be changed by changing the material and thickness of the dielectric layer 90, so that the radius of curvature of the substrate 10 is greater than or equal to the target radius of curvature. At this time, the warpage of the substrate 10 is reduced to the point that it will not affect the operation of the relevant process equipment and the smooth progress of subsequent processes. The setting of the dielectric layer 90 increases the trench density on the front side of the device and has good parameter performance improvement.

[0071] As an example, the tensile stress generated by the dielectric layer 90 on the surface of the substrate 10 away from the trench gate structure 30 is 50 MPa to 300 MPa. For example, the tensile stress generated by the dielectric layer 90 on the surface of the substrate 10 away from the trench gate structure 30 is 50 MPa, 100 MPa, 150 MPa, 200 MPa, 250 MPa, or 300 MPa, etc., so that the tensile stress of the dielectric layer 90 on the surface of the substrate 10 away from the trench gate structure 30 cancels out the tensile stress on the surface of the substrate 10 near the trench gate structure 30, making the warpage of the silicon wafer more uniform in all directions, thereby improving the phenomenon of excessive warpage of the silicon wafer.

[0072] As an example, the preset thickness of the dielectric layer 90 can be 0.1 μm to 5 μm, and the material used can include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. For example, the preset thickness of the dielectric layer 90 can be 0.1 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm, etc.

[0073] Please see Figure 3 In one embodiment of this application, the step of forming a spaced source region structure at the top of the substrate between adjacent trench gate structures to form a power device structure includes:

[0074] Step S30: Form a first type of well region in the substrate on both sides of the trench gate structure using an ion implantation process;

[0075] Step S31: Using ion implantation, a second type of heavily doped region is formed in the first type of well region on both sides of the trench gate structure to form the source region structure;

[0076] Step S32: Use ion implantation to form a first type of heavily doped region in the substrate between adjacent second type heavily doped regions to form a bulk structure.

[0077] In step S30, please refer to Figure 2a and Figure 3 In step S30, a first type of well region 40 is formed in the substrate 10 on both sides of the trench gate structure 30 using an ion implantation process.

[0078] As an example, in the process of forming a first type well region 40 in the substrate 10 on both sides of the trench gate structure 30 using an ion implantation process, a thin layer of silicon dioxide is first oxidized on the substrate 10 to protect the substrate 10. Then, photoresist is formed on the surface of the substrate 10 and etched to form an implantation window for the first type well region 40. Then, first type ion implantation is performed through the implantation window to form the first type well region 40.

[0079] In step S31, please refer to Figure 2a and Figure 3 In step S31, a second type of heavily doped region 50 is formed in the first type of well region 40 on both sides of the trench gate structure 30 using an ion implantation process.

[0080] In step S32, please refer to Figure 2a and Figure 3 In step S32, a first type of heavily doped region 60 is formed in the substrate 10 between adjacent second type heavily doped regions 50 using an ion implantation process.

[0081] As an example, the process of forming heavily doped regions in the first type well regions 40 on opposite sides of the trench gate structure 30 using ion implantation allows for precise control of the concentration and uniformity of doped ions. The first type is P-type and the second type is N-type, or vice versa. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. N-type impurity ions can include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0082] Please see Figure 4 In one embodiment of this application, the step of forming spaced source region structures at the top of the substrate between adjacent trench gate structures to form a power device structure further includes:

[0083] Step S33: Forming spaced dielectric isolation layers, the dielectric isolation layers covering a trench gate structure and the top surfaces of the second type heavily doped regions located on opposite sides of the trench gate structure; the gaps between adjacent dielectric isolation layers expose the top surfaces of the first type heavily doped regions;

[0084] Step S34: Form a front metal layer that covers the top surface of the first type of heavily doped region and the top surface of the dielectric isolation layer.

[0085] In step S33, please refer to Figure 2a and Figure 4In step S33, a spaced dielectric isolation layer 70 is formed, which covers a trench gate structure 30 and the top surface of a second type heavily doped region 50 located on opposite sides of the trench gate structure 30; the gap between adjacent dielectric isolation layers 70 exposes the top surface of a first type heavily doped region 60.

[0086] As an example, the dielectric isolation layer 70 can be deposited using plasma-enhanced chemical vapor deposition, and the material of the dielectric isolation layer 70 includes silicon dioxide, silicon nitride, etc. High-quality insulating dielectric isolation layer 70 can be obtained by using plasma-enhanced chemical vapor deposition.

[0087] In step S34, please refer to Figure 2a and Figure 4 In step S34, a front metal layer 80 is formed, which covers the top surface of the first type heavily doped region 60 and the top surface of the dielectric isolation layer 70.

[0088] Please see Figure 2b In one embodiment of this application, another method for fabricating a semiconductor structure is provided, in which the formation of a power device structure further includes the following steps:

[0089] Step S'30: A first type of well region 40 is formed in the epitaxial structure 20 on both sides of the trench gate structure 30 using an ion implantation process;

[0090] Step S'31: Using ion implantation, a second type of heavily doped region 50 is formed in the first type of well region 40 on both sides of the trench gate structure 30 to form a source region structure;

[0091] Step S'32: Using an ion implantation process, a first type of heavily doped region 60 is formed in the epitaxial structure 20 between adjacent second type heavily doped regions 50 to form a bulk structure.

[0092] Step S'33: Forming spaced dielectric isolation layers 70, the dielectric isolation layers 70 covering a trench gate structure 30 and the top surfaces of second-type heavily doped regions 50 located on opposite sides of the trench gate structure 30; the gaps between adjacent dielectric isolation layers 70 expose the top surfaces of first-type heavily doped regions 60;

[0093] Step S'34: Form a front metal layer 80, which covers the top surface of the first type heavily doped region 60 and the top surface of the dielectric isolation layer 70.

[0094] As an example, in conventional processes, the power device structure is formed after the front-side metal layer is deposited. However, excessive wafer warpage often occurs after this step. Please refer to [link to relevant documentation]. Figure 5At this point, due to the high-temperature thermal process and the presence of layered stress in the metal, the silicon wafer exhibits a large tensile stress. The radius of curvature of the silicon wafer substrate 10 is R0, which is usually less than 20m. Under these circumstances, it will affect the subsequent processes.

[0095] For example, please refer to Figure 2a , Figure 2b and Figure 5 The cross-sectional view of the silicon wafer fabricated using the semiconductor fabrication method described above in this application is similar to the cross-sectional view of the semiconductor silicon wafer fabricated using conventional processes. Figure 5 As shown, when a dielectric layer 90 is not formed on the surface of the silicon substrate 10 away from the trench gate structure 30, the radius of curvature of the silicon substrate 10 is R0, which is less than 20m. At this time, the radius of curvature of the silicon wafer is less than the target radius of curvature, that is, the silicon wafer warpage is too large. This will cause the equipment related to the process to stop frequently, making it impossible to continue the subsequent process and also making it impossible to meet the requirements for mass production of the manufactured products, thus reducing the yield of semiconductor devices. After adopting the semiconductor fabrication method provided in this application, a dielectric layer 90 is formed on the surface of the silicon substrate 10 away from the trench gate structure 30. The dielectric layer 90 generates tensile stress on the substrate 10 on the surface away from the trench gate structure 30. The tensile stress of the dielectric layer 90 can be changed by changing the material and thickness of the dielectric layer 90. The radius of curvature of the formed silicon substrate 10 is R, which is greater than or equal to 20 μm. At this time, the radius of curvature of the substrate 10 is greater than or equal to the target radius of curvature. At this time, the warpage of the substrate 10 is reduced to a level that will not affect the operation of related process equipment and the smooth progress of subsequent processes. When the dielectric layer 90 is set, the trench density on the front side of the device increases and has good parameter performance improvement, which can improve the yield of semiconductor devices.

[0096] Another aspect of this application provides a semiconductor structure fabricated using any of the methods described in the foregoing embodiments. Please refer to [link to relevant documentation]. Figure 2a and Figure 2bThe semiconductor structure includes a substrate 10, a power device structure, and a dielectric layer 90. Multiple spaced trench gate structures 30 are formed within the substrate 10. The power device structure is formed at the top of the substrate 10 between adjacent trench gate structures 30. The power device structure also includes a first-type well region 40, a second-type heavily doped region 50, a first-type heavily doped region 60, a dielectric isolation layer 70, and a front-side metal layer 80. The first-type well regions 40 are formed within the substrate 10 on opposite sides of the trench gate structures 30, and the second-type heavily doped regions 50 are formed within the first-type well regions 40 on opposite sides of the trench gate structures 30. A first type of heavily doped region 60 is formed in the substrate 10 between adjacent second type of heavily doped regions 50. A dielectric isolation layer 70 covers a trench gate structure 30 and the top surfaces of the first type of heavily doped regions 60 located on opposite sides of the trench gate structure 30 and is spaced apart, with the gaps exposing the top surfaces of the second type of heavily doped regions 50. A front metal layer 80 covers the exposed top surfaces of the second type of heavily doped regions 50 and the top surface of the dielectric isolation layer 70. A dielectric layer 90 is formed on the surface of the substrate 10 away from the trench gate structure 30 and has a preset thickness to generate tensile stress on the surface of the substrate 10 away from the trench gate structure 30.

[0097] In the semiconductor structure described above, the dielectric layer 90 generates tensile stress on the surface of the substrate 10 away from the trench gate structure 30. The material and thickness of the dielectric layer 90 can be changed to adjust the magnitude of the tensile stress, making the radius of curvature of the substrate 10 greater than or equal to the target radius of curvature. Simultaneously, the trench density is increased to improve the parameter performance of the semiconductor device. Furthermore, this application introduces a new process design without requiring complex high-temperature processes or changes to any previous process flow operations, thus improving the problem of excessive silicon wafer warpage at minimal cost. Additionally, since the dielectric layer 90 completely covers the surface of the substrate 10 away from the trench gate structure 30, it ensures a symmetrical stress distribution in all directions on the silicon wafer, preventing excessive stress in any one direction. This method also makes the warpage of the silicon wafer more uniform in all directions, thereby improving the phenomenon of excessive silicon wafer warpage. Therefore, this application optimizes product performance and increases the trench density of the device while improving the excessive warpage of the silicon wafer substrate 10, thereby ensuring smooth process flow and improving the yield of manufactured semiconductor devices.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; Multiple trench gate structures are formed in the substrate at intervals; the trench gate structures have the same width and the spacing between adjacent trench gate structures is the same; A spaced source region structure is formed at the top of the substrate between adjacent trench gate structures to form a power device structure; A dielectric layer of a predetermined thickness is formed on the surface of the substrate away from the trench gate structure; the dielectric layer is used to generate tensile stress on the substrate, such that the radius of curvature of the substrate is greater than or equal to the target radius of curvature. The step of forming spaced source region structures on top of the substrate between adjacent trench gate structures to form a power device structure includes: A first type of well region is formed in the substrate on both sides of the trench gate structure using an ion implantation process; A second type of heavily doped region is formed in the first type of well region on both sides of the trench gate structure using an ion implantation process to form the source region structure; A first type of heavily doped region is formed in the substrate between adjacent second type heavily doped regions using an ion implantation process to form a bulk structure; the second type of heavily doped regions adjacent to the trench gate structure are isolated from each other via the first type of heavily doped region; A front metal layer is formed, which is electrically connected to a plurality of first-type heavily doped regions directly beneath it, and the front metal layer is insulated from the second-type heavily doped regions via a dielectric isolation layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a plurality of spaced trench gate structures within the substrate includes: An epitaxial structure is formed on the substrate, and a plurality of spaced trench gate structures are formed within the epitaxial structure.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, By changing the material and thickness of the dielectric layer, the tensile stress of the dielectric layer is altered, so that the radius of curvature of the substrate is greater than or equal to the target radius of curvature.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The tensile stress is 50 MPa-300 MPa.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The preset thickness is 0.1µm-5µm.

6. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The material of the dielectric layer includes at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that, The depth of the trench gate structure is greater than the depth of the epitaxial structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Also includes: A spaced dielectric isolation layer is formed, the dielectric isolation layer covering the trench gate structure and the top surface of the second type of heavily doped regions located on opposite sides of the trench gate structure; The gap between adjacent dielectric isolation layers exposes the top surface of the first type of heavily doped region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, Also includes: A front metal layer is formed, which covers the top surface of the first type of heavily doped region and the top surface of the dielectric isolation layer.

10. A semiconductor structure, characterized in that, It is prepared by the method described in any one of claims 1-9.

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