Semiconductor structure and method of testing the same

Abstract

Semiconductor structures and methods of testing thereof are provided. A semiconductor structure according to the present invention includes a substrate, a semiconductor device located above the substrate, wherein the semiconductor device includes an interconnect structure including a plurality of metallization layers disposed in a dielectric layer, and a layered sensor. The layered sensor includes a connection structure and a plurality of contact vias located in at least one of the plurality of metallization layers. The connection structure joins the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertically projected area of the connection structure but do not overlap a second region of the vertically projected area.

Description

Technical Field

[0001] The embodiments of this application relate to semiconductor structures and their testing methods. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while its geometry (i.e., the smallest element (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down generally benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] In the semiconductor industry, IC chips are bonded to a packaging substrate before being bonded to a printed circuit board (PCB). The IC chip and the packaging substrate have different coefficients of thermal expansion (CTE). During or after the manufacturing process, the expansion and contraction of the IC chip and the packaging substrate may differ, leading to chip-package interaction (CPI) problems. CPI problems include delamination of the metallization layer, which can cause device failure. CPI problems can be difficult to detect, and performing a full-chip scan using C-mode scanning acoustic microscopy (C-SAM) can be time-consuming and costly.

[0004] As functional density continues to increase, parasitic capacitance plays an increasingly important role in device performance. To reduce parasitic capacitance, extremely low-k (ELK) dielectric materials are used in interconnect structures to reduce resistive-capacitive (RC) delay. The use of ELK materials exacerbates the CPI problem because ELK materials do not withstand stress as well as non-ELK materials. While existing chip packages are generally sufficient for their intended use, they are not satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this application provide a method for testing a semiconductor structure, comprising: providing a semiconductor device package, the semiconductor device package including: a package substrate, a semiconductor device located above the package substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer, and at least one layer sensor, including: a connection structure bonding the semiconductor device to the package substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers, wherein the plurality of contact vias fall within a first region of a vertically projected area of ​​the connection structure, but do not overlap with a second region of the vertically projected area; and screening the layers of the entire semiconductor device package by testing only the at least one layer sensor.

[0006] Other embodiments of this application provide a method for testing a semiconductor structure, comprising: providing a semiconductor device package including: a package substrate, a semiconductor device located above the package substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer, and at least one layering sensor, comprising: a connection structure bonding the semiconductor device to the package substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers, wherein the plurality of contact vias fall within a first region of a vertically projected region of the connection structure but do not overlap with a second region of the vertically projected region; screening the entire semiconductor device package for layering by testing only the at least one layering sensor; modifying the semiconductor device to form a modified semiconductor device when layering occurs during the screening; and wherein no layering occurs during the screening, thereby mass-producing the semiconductor device.

[0007] Some embodiments of this application provide a semiconductor structure, including: a packaging substrate; a semiconductor device located above the packaging substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a layered sensor, including: a connection structure for bonding the semiconductor device to the packaging substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers, wherein the plurality of contact vias fall within a first region of a vertically projected region of the connection structure, but do not overlap with a second region of the vertically projected region. Attached Figure Description

[0008] When with attachment Figure 1 When reading this invention, the various aspects will be best understood in the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1 This is a cross-sectional view of a semiconductor device package according to various aspects of the present invention.

[0010] Figure 2 This is a partial cross-sectional view of a semiconductor device package according to various aspects of the present invention.

[0011] Figure 3 This is an enlarged partial cross-sectional view of a connection structure for bonding a semiconductor device package to a semiconductor device according to various aspects of the present invention.

[0012] Figure 4This is an enlarged partial cross-sectional view of the interconnect structure in a semiconductor device according to various aspects of the present invention.

[0013] Figure 5 This is a top view of a semiconductor device package according to one or more aspects of the present invention.

[0014] Figures 6 to 10 Various embodiments of a layered sensor according to one or more aspects of the present invention are shown.

[0015] Figure 11 An exemplary design-for-testability (DFT) component that can be implemented using the layered sensor of the present invention is shown.

[0016] Figure 12 This is a flowchart of a method for testing a semiconductor device package equipped with the layered sensor of the present invention.

[0017] Figure 13 This is a flowchart of a method for designing semiconductor device packages according to various aspects of the present invention. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of elements and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. Spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used therein may be interpreted accordingly.

[0020] Furthermore, as those skilled in the art will understand, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with a manufactured component, the component possesses characteristics associated with a numerical value, and the numerical value or range encompasses a reasonable range including the described numerical value, such as within + / - 10% of the described value. For instance, the size range of a material layer with a thickness of "about 5 nm" may be between 4.25 nm and 5.75 nm, where, those skilled in the art know, the manufacturing tolerance associated with the deposited material layer is + / - 15%. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] In some device packaging technologies, semiconductor chips (or IC chips) are bonded to a packaging substrate to form a semiconductor device package, which is then bonded to a printed circuit board (PCB). Semiconductor chips and packaging substrates have different material properties. On one hand, semiconductor chips are primarily formed from semiconductor materials (such as silicon, germanium, silicon-germanium, or III-V semiconductors), semiconductor oxides (such as silicon oxide), and semiconductor nitrides (such as silicon nitride). On the other hand, packaging substrates can be laminated substrates comprising polymeric materials and metals. For example, packaging substrates can be made of, for example, polyimide, PTFE, polymer composite laminates (such as FR-2 and FR-4), organic (laminated) materials (such as bismaleimide-triazine (BT)), polymer-based materials (such as liquid crystal polymers (LCP)), etc. Packaging substrates may also include traces / lines formed from suitable conductive materials such as copper, aluminum, silver, gold, other metals, alloys, or combinations thereof. As a result, the CTE of the packaging substrate can be approximately 2 to approximately 10 times that of the IC chip.

[0022] Figure 1 An exemplary semiconductor device package 100 is shown. The semiconductor device package 100 includes an IC chip 102, which is flipped and bonded to a package substrate 150 via solder bumps 130. The IC chip 102 may also be referred to as a semiconductor chip 102 or a semiconductor device 102. For example, during a solder reflow process, the semiconductor device package 100 may be subjected to elevated temperatures. When the semiconductor device package 100 cools to room temperature, the package substrate 150 may shrink further along the Y direction than the IC chip 102, such as... Figure 1 As shown by the arrow in the image. Now refer to... Figure 2The diagram shows an enlarged cross-sectional view of the edges of the IC chip 102 and the package substrate 150. As indicated by the arrows, since the IC chip 102 is bonded to the package substrate 150, deformation can stress the IC chip 102 through the solder joints. As a result, the IC chip is subjected to tensile stress along the Z-direction. Because thermal expansion increases with distance from the stress neutral point (typically the geometric center of the IC chip 102), the tensile stress can reach its maximum near the edges and corners of the IC chip 102. In simpler terms, a mismatch in the CTE (Coefficient of Thermal Expansion) between the IC chip 102 and the package substrate 150 can pull down the edges and corners of the IC chip 102 through the solder joints.

[0023] Figure 3 An enlarged partial cross-sectional view of the solder joint between IC chip 102 and package substrate 150 is shown. IC chip 102 includes a semiconductor substrate 104, an interconnect structure 106 above the semiconductor substrate 104, contact pads 108 above the interconnect structure 106, a passivation layer 110 above the contact pads 108, under-bump metallization (UBM) components 120 coupled to the contact pads 108, and solder components 130 above the UBM components 120. Semiconductor substrate 104 may include crystalline silicon, crystalline germanium, crystalline silicon-germanium, and / or III-V compound semiconductors, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. Although... Figure 3 Not explicitly shown, but the semiconductor substrate 104 may include front-end process (FEOL) semiconductor components, such as transistors, and MEOL contact components, such as gate contact vias, source / drain contacts, and source / drain contact vias. The interconnect structure 106 may include about 10 and about 15 metallization layers, such as about 13 metallization layers. Figure 3 The document also provides a representative local interconnect structure 106. The metallization layer of interconnect structure 106 is embedded in multiple inter-metal dielectric (IMD) layers, which may be formed of low-k (LK) or very low-k (ELK) dielectric materials. Low-k dielectric materials are those with a dielectric constant less than that of silicon dioxide (i.e., approximately 3.9). Exemplary low-k dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), and tetraethyl orthosilicate (TEOS). ELK dielectric materials are those with a dielectric constant less than 2.7. Exemplary ELK dielectric materials include porous organosilicon glass. The metallization layer may include copper (Cu) or titanium nitride (TiN).

[0024] Contact pads 108 may be formed of aluminum (Al) or aluminum-copper (Al-Cu) and may be referred to as aluminum pads. Passivation layer 110 may be a multilayer comprising one or more polyimide layers, one or more silicon nitride layers, or a combination of both. UBM component 120 may include multiple layers, such as barrier layers, seed layers, and metal bumps. In some embodiments, UBM component may include titanium, titanium nitride, nickel, cupronickel, cobalt, copper, or a combination thereof. Solder component 130 may also be referred to as solder bump 130. In some embodiments, solder component 130 may include Pb-Sn, InSb, tin, silver, copper, or a combination thereof. UBM component 120 and solder component 130 may be collectively referred to as a connection structure. The connection structure contacts package substrate 150 via pre-soldering component 154 comprising an alloy comprising tin, lead, silver, copper, nickel, bismuth, or a combination thereof. Pre-soldering component 154 may be embedded in solder mask layer 153, which is formed of solder mask material layer, dielectric layer, polymer layer, or any other material that does not chemically react with solder material. A pre-soldered component 154 is disposed on a contact pad 152 above the package substrate 150. The contact pad 152 may be made of copper, aluminum, or aluminum-copper.

[0025] Still referencing Figure 3 In some instances, via empty regions 106E may exist within the interconnect structure 106. For example... Figure 3 As shown, the via void 106E refers to the vertical projection area through a continuous layer of metallization, in which there is no contact via 160. Experimental and field data indicate that when the via void 106E falls within a chip corner or chip edge area where the tensile stress is higher than the rest of the IC chip, it is more likely to cause [problems]. Figure 4 The layering 106D is representatively shown in the diagram. However, layering is not unavoidable in the central region of an IC chip for various reasons. In some instances, the polymer material in the package substrate 150 may expand, causing layering in the central region. Layering 106D can lead to interconnect failures and device malfunctions. Since tensile stress may dissipate from the UBM component 120, layering 106D is more likely to occur within six metallization layers from the UBM component 120. For example, when the interconnect structure 106 includes 13 metallization layers and the 13th layer is closer to the UBM component 120, layering 106D is more likely to occur within the 13th, 12th, 11th, 10th, 9th, and 8th metallization layers, provided they are embedded in LK or ELK dielectric materials. In instances where higher layers (such as the 13th and 12th layers) are embedded in silicon oxide or other non-ELK dielectric materials, layering 106D is more likely to occur in the 11th, 10th, 9th, or 8th layers.

[0026] C-mode scanning acoustic microscopy (C-SAM) can be used to detect faults related to chip-package interaction (CPI), such as Figure 4The layering shown is illustrated. Layering appears as a visible white halo or circle around the interconnect structure in a C-SAM scan. For this reason, layering may be referred to as white bumps (WB). WB is an indicator of CPI-related failure events in semiconductor device packages. An exemplary local layering or white bump 130D is shown. Figure 5 As shown in the figure, Figure 5 This represents a top view of a C-SAM image or semiconductor device package 100. As robust as modern C-SAM, a complete IC chip C-SAM scan can take approximately 15 to 30 minutes. This explains why most manufacturers likely test random samples, rather than all IC chips. Otherwise, testing could significantly reduce production volume and increase the production cost of the semiconductor device package 100. Existing electrical tests are ineffective at detecting delamination because the detected UBM components are rarely those directly above the delamination. In other words, a semiconductor device package 100 that passes electrical testing is likely susceptible to delamination and open circuits.

[0027] This invention provides a layering sensor capable of reliably detecting CPI-related faults (such as layering) and provides a method for inspecting semiconductor device packages (such as those similar to...). Figure 1 , Figure 2 and Figure 5 The semiconductor device package 100 shown is presented in a cost-effective manner to improve the quality of the semiconductor device package. Since delamination defects are also known as white bumps or white bump defects, the delamination sensor of the present invention can also be referred to as a white bump (WB) sensor. The sensitivity of the WB sensor of the present invention is adjustable to meet different design needs and provide reliable WB fault readings. The WB sensor can be coupled to testability design components (such as electrical continuity loops) to allow direct electrical probing. In addition to direct electrical testing, the WB sensor can also be tested using C-SAM. According to the present invention, since the WB sensor is the most likely site of delamination, only scanning or probing of the WB sensor is required to verify the quality of the entire semiconductor device package. Compared to full-chip C-SAM scanning or electrical testing, which can hardly detect delamination, the testing method of the present invention is more cost-effective and reliable.

[0028] Generally, the WB sensor or delamination sensor of this invention is analogous to a canary in a coal mine or chemical plant. Canaries are far more sensitive to toxic gases than humans. A canary's sudden agitation or cessation of loud chirping can reliably indicate the presence of toxic gases. The WB sensor of this invention is a UBM connection structure located directly above a deliberately weakened structure. The deliberately weakened underlying structure causes the WB sensor to fail before other UBM connection structures fail. As described above, tensile stress is applied to the interconnect structure 106 through the UBM component 120. Experimental and field data show that the location of the UBM component 120, the size of the via empty area, and the orientation of the via empty area determine whether the UBM component 120 will exhibit white bumps during C-SAM. First, the tensile stress causing delamination increases with distance from the neutral stress geometry center of the IC chip 102. This means that UBM components 120 near the edges or corners of the IC chip 102 tend to apply the greatest tensile stress to the portions of the interconnect structure 106 to which they are connected. Greater stress means a higher probability of white bumps appearing. Second, contact vias are crucial for holding the metallization layers together. The likelihood of delamination is lower when there are many or densely packed contact vias. Conversely, when there is a lack of contact vias in a continuous metallization layer region, that region may be weaker in terms of tensile stress resistance. Third, the orientation of the via empty area relative to the geometric center of the IC chip is important. The likelihood of delamination is lower when the via empty area is located between the geometric center of the IC chip and the geometric center of the UBM component. However, when the via empty area is far from the geometric center of the IC chip, the probability of delamination may increase by 10% to about 25%. According to the present invention, the UBM component 120 of the WB sensor may be a dummy UBM component, a filled UBM component, or a redundant UBM component that provides functionality similar to at least one other UBM component.

[0029] exist Figure 6In some embodiments shown, the semiconductor device package 100 may include one or more corner WB sensors 200V adjacent to one or more corners of the IC chip 102. In the depicted embodiment, the IC chip 102 is rectangular in shape and its four corners are the areas furthest from the geometric center C, which is typically a stress neutral point. When deployed, the corner WB sensors 200V are placed near the four corners of the IC chip 102. The corner WB sensors 200V are placed closer to the four corners than to the geometric center C. In the depicted embodiment, multiple corner WB sensors 200V (such as three corner WB sensors 200V) are placed near one corner. Each corner WB sensor 200V includes a UBM component 120, multiple contact vias 160 falling within the vertical projection area of ​​the UBM component 120, and a corner via empty area 300V. The multiple contact vias 160 falling within the vertical projection area of ​​the UBM component 120 are disposed in multiple metallization layers in the interconnect structure 106. The corner via void 300V is the area in the vertical projection region that does not overlap with any contact vias in at least two consecutive metallization layers of the first six metallization layers of the UBM component 120.

[0030] The corner via empty area 300V overlaps with the quadrant between the geometric center of UBM component 120 and the nearest corner of IC chip 102. For example, the corner via empty area 300V overlaps with the lower left quadrant of the projection area of ​​UBM component 120 at the lower left corner. Figure 6 The semiconductor device package 100 includes corner WB sensors 200V located at three other corners (upper left corner, lower right corner, and upper right corner). Corner via empty areas 300V overlap with the upper left quadrant of the projection area of ​​the UBM component 120 at the upper left corner. Corner via empty areas 300V overlap with the lower left quadrant of the projection area of ​​the UBM component 120 at the lower left corner. Corner via empty areas 300V overlap with the lower right quadrant of the projection area of ​​the UBM component 120. In some embodiments, each corner via empty area 300V may be rectangular in shape and may extend beyond the quadrants of the projection area of ​​the UBM component 120.

[0031] Now for reference Figure 7The sensitivity of the corner WB sensor 200V is adjustable. For example, for a UBM component 120 with a diameter L, the corner via empty area 300V can have equal sides, each side being a portion of the diameter L, such as 0.11L, 0.20L, 0.32L, 0.46L, and 0.62L. The sensitivity of the corner WB sensor 200V increases as the area of ​​the corner via empty area 300V increases. Furthermore, the sensitivity of the corner WB sensor 200V increases when the number of consecutive via-less layers in the corner via empty area 300V increases or when the consecutive via-less layers are closer to the UBM component 120. For example, among two other identical corner WB sensors 200V, a corner WB sensor with four consecutive via-less layers is more sensitive than another corner WB sensor with two consecutive via-less layers. For example, between two other identical corner WB sensors 200V, the corner WB sensor having two consecutive via-less layers in the 10th and 11th metallization layers is more sensitive than the other corner WB sensor having two consecutive via-less layers in the 8th and 9th metallization layers. It should be noted that while these adjustable parameters are described with respect to the corner WB sensor 200V, they can be applied to adjust the sensitivity of other WB sensors of the present invention.

[0032] exist Figure 8In some embodiments shown, the semiconductor device package 100 may include an edge WB sensor 200E adjacent to the edge of an IC chip 102. In the depicted embodiment, the IC chip 102 is rectangular in shape, and its four edges / sides are relatively far from the geometric center C, which is typically a stress neutral point. When deployed, at least one edge WB sensor 200E is placed near at least one of the four edges of the IC chip 102. The edge WB sensor 200E according to the invention is placed closer to the edge rather than the geometric center C. In the depicted embodiment, the edge WB sensor 200E is placed near the right-hand side edge. The edge WB sensor 200E includes a UBM component 120, a plurality of contact vias 160 falling within the vertical projection area of ​​the UBM component 120, and an edge via empty area 300E. The plurality of contact vias 160 falling within the vertical projection area of ​​the UBM component 120 are disposed in a plurality of metallization layers in the interconnect structure 106. The edge via empty area 300E is a region of the vertically projected area that does not overlap with any contact vias in at least two consecutive metallization layers of the first six metallization layers of the UBM component 120. The edge via empty area 300E overlaps with approximately one semicircle of the projected area of ​​the UBM component 120 and is located between the geometric center of the UBM component 120 and the nearest edge of the IC chip 102. For example, the edge via empty area 300E near the left side of the IC chip 102 largely overlaps with the left semicircle of the projected area of ​​the UBM component 120. The edge via empty area 300E near the right side of the IC chip 102 largely overlaps with the right semicircle of the projected area of ​​the UBM component 120. Figure 8 In some embodiments shown, the edge via empty area 300E can be rectangular in shape and can extend beyond the right semicircle of the projected area of ​​UBM component 120.

[0033] exist Figure 9 In some embodiments shown, the semiconductor device package 100 may include a central WB sensor 200C adjacent to the geometric center C of the IC chip 102. More than one central WB sensor 200C may be placed around the edge. The central WB sensor 200C of the present invention includes a UBM component 120, a plurality of contact vias 160 falling within the vertical projection region of the UBM component 120, and a central via empty region 300C. The plurality of contact vias 160 falling within the vertical projection region of the UBM component 120 are disposed in a plurality of metallization layers in the interconnect structure 106. The central via empty region 300C may include a plurality of polygonal regions symmetrical about the geometric center C. The central via empty region is a region in the vertical projection region that does not overlap with any contact vias in at least two consecutive metallization layers of the first six metallization layers of the UBM component 120. In the depicted embodiment, the central via empty region 300C includes four elliptical or olive-shaped regions symmetrical about the geometric center C.

[0034] exist Figure 10 In some embodiments shown, two or more of the corner WB sensor 200V, edge WB sensor 200E, and center WB sensor 200C may be implemented in a semiconductor device package 100. Figure 10 A semiconductor device package 100 including all three types of WB sensors is shown; however, it should be understood that the semiconductor device package 100 may include only corner WB sensors 200V and edge WB sensors 200E, or only corner WB sensors 200V and center WB sensors 200C, or only edge WB sensors 200E and center WB sensors 200C. In one embodiment, at least one corner WB sensor 200V is deployed at each of the four corners, as layering is most likely to occur around the corners.

[0035] exist Figure 11 In some embodiments illustrated, the BW sensor of the present invention can be integrated with a design-for-testability (DFT) component. For example, Figure 11 An electrical test circuit 400 is shown. In the test circuit 400, an input signal entering from an input port at the package substrate 150 is passed to a first corner WB sensor 200V-1, then to a second corner WB sensor 200V-2, and finally output from an output port at the package substrate 150. In the depicted embodiment, when delamination 106D occurs at the first corner WB sensor, probes contacting the input and output ports will detect an open circuit in the electrical test circuit 400, indicating that at least one of the first corner WB sensor 200V-1 and the second corner WB sensor 200V-2 has delamination. Other DFT functions involving one or more WB sensors are entirely predictable.

[0036] exist Figure 12 The flowchart illustrates a method 500 for testing a semiconductor device package. Method 500 is merely an example and is not intended to limit the invention, nor is it limited to what is expressly stated in the claims. Additional operations may be provided before, during, and after method 500, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of method 500. Method 500 will now be described in more detail.

[0037] Method 500 includes block 502, wherein multiple layered sensors with different sensitivities are incorporated into the design of an IC chip. Instead of performing a series of experiments and simulations to identify the optimal WB sensor sensitivity level for the IC chip design, multiple WB sensors with different sensitivities are incorporated into the IC chip design. As described above, the sensitivity of the WB sensor of the present invention can be adjusted by varying the fall-into-UBM component (such as...) Figure 6 , Figure 8 , Figure 9 and Figure 10 The area (i.e., percentage of the projected area of ​​the UBM component 120) and depth (i.e., the number of consecutive layers without contact vias) of the via empty area within the projected region of the UBM component 120 are adjusted. For example, three corner WB sensors 200V with three different sensitivity levels can be set in each of the four corners of a rectangular IC chip. As another example, four edge WB sensors 200E with four different sensitivity levels can be set in each of the four corners adjacent to the IC chip. It should be noted that multiple WB sensors with different sensitivities allow the IC chip to function normally even when all these WB sensors are activated.

[0038] Method 500 includes block 504, in which an IC chip is manufactured based on a design. The IC chip produced at block 504 includes multiple layered sensors with different sensitivities.

[0039] Method 500 includes block 506, wherein an IC chip generated at block 504 is bonded to a packaging substrate to form a semiconductor device package.

[0040] Method 500 includes block 508, where one of a plurality of layered sensors is selected from a plurality of layered sensors based on initial WB data. At block 508, a predetermined number of semiconductor device packages generated at block 506 are then subjected to full-chip C-SAM to identify white bumps that are part of the WB sensor (i.e., WB sensor white bumps) and white bumps that are not part of the WB sensor (i.e., non-WB sensor white bumps). Above the predetermined number of semiconductor device packages, the WB sensor white bumps and non-WB sensor white bumps are analyzed to identify a pre-selected group of WB sensor white bumps most relevant to the occurrence of non-WB sensor white bumps. Generally, an ultra-sensitive WB sensor does not indicate the quality of the semiconductor device package and may represent unrealistic quality control targets. The objective of the operation at block 508 is to find a WB sensor that is equally sensitive to the most faulty areas of the semiconductor device package. The pre-selected group of WB sensors can be further redundancy-filtered to identify the selected group of WB sensors. The selected WB sensor group may include multiple WB sensors located in different locations or only a single WB sensor.

[0041] Method 500 includes block 510, in which the presence of layering is tested by examining a selected set of layered sensor groups. Except for a predetermined number of semiconductor device packages that undergo full-chip C-SAM scanning at block 508, the remaining semiconductor device packages and all semiconductor device packages to be manufactured are tested by examining a selected set of WB sensor groups for each semiconductor device package. At block 510, the selected WB sensor group is tested by probing the DFT component electrically coupled to one of the WB sensors in the final selected WB sensor group, by scanning the selected WB sensor group using C-SAM, or by both. It should be noted that in some embodiments, only one of electrical testing and C-SAM is required to test the selected WB sensor group. Furthermore, since the selected WB sensor group represents the quality of the semiconductor device package, electrical testing of the final selected WB sensor group alone can reliably predict the presence of non-WB sensor white bumps. If the WB sensor group is deemed not to represent the quality of the semiconductor device package, the operation at block 508 can be repeated to select a different WB sensor group.

[0042] The WB sensors and methods for testing delamination in semiconductor device packages of the present invention offer several benefits. For example, the WB sensors of the present invention provide useful testing tools to cost-effectively measure how the design of the IC chip and package substrate affects the occurrence and location of WB (i.e., local delamination) or even other types of CPI failures. Their tunability allows them to better quantify the ability of a semiconductor device package to withstand CTE mismatch. Furthermore, once a set of WB sensors identified to represent the CPI quality of a semiconductor device package is selected, CPI failures of the semiconductor device package can be reliably tested by testing the selected set of WB sensors.

[0043] Figure 13 The flowchart illustrates a method 600 for designing a semiconductor device package. As described below, while method 600 shares some common operations with method 500, method 600 uses only a plurality of layered sensors as design tools, and at least some of these layered sensors are not present in the final structure. Method 600 is merely an example and is not intended to limit the invention, nor is it intended to be limited by the contents expressly recited in the claims. Additional operations may be provided before, during, and after method 600, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of method 600. Method 600 will now be described in more detail.

[0044] Method 600 includes boxes 602, 604, 606, 608, 610, 612, 614, and 616. In these boxes, the operation in box 602 is similar to the operation in box 502, the operation in box 604 is similar to the operation in box 504, the operation in box 606 is similar to the operation in box 506, the operation in box 608 is similar to the operation in box 508, and the operation in box 610 is similar to the operation in box 510. Due to their similarities, the operations in boxes 602, 604, 606, 608, and 610 will not be described in detail.

[0045] Method 600 includes block 612, in which a decision is made regarding the existence of layering. In other words, block 612 is a decision block that determines whether to make changes to the design to remedy the layering or whether to manufacture the IC package without multiple layering sensors. In some embodiments, the decision made at block 612 may be based on the strict presence of any layering. That is, layering is considered present when any of the multiple layering sensors tested at block 610 is triggered. In some other embodiments, the decision made at block 612 may be based on a predetermined threshold level. That is, layering is considered present when the layering detected at block 610 reaches the threshold level. Conversely, layering is considered absent when the layering detected at block 610 is below the threshold level. When layering exists, method 600 proceeds to block 614. When layering does not exist, method 600 proceeds to block 616.

[0046] refer to Figure 13 Method 600 includes block 614, where design implementation changes are made. The test results in block 610 indicate the most likely locations and severity of delamination. Based on this information, design implementation changes can be made to the IC chip to enhance the bonding between the IC chip and the package substrate. Figure 13 As shown, an IC chip based on the improved design can be manufactured at block 604. The IC chip based on the improved design can be manufactured by operations at blocks 606, 608, and 610 to determine whether layering has been resolved. If not, the cycle can be repeated until no layering exists or the layering falls below a predetermined threshold level.

[0047] like Figure 13As shown, method 600 includes block 616, in which multiple layered sensors are removed and an IC package is manufactured. When it is determined at block 612 that no layering exists, at least a portion of the multiple layered sensors can be removed to produce a final design, and the IC chip and IC package are mass-produced based on the final design. The removal of the multiple layered sensors can be based on how the presence of the multiple layered sensors affects cost, yield, and the functionality of the IC package. For example, multiple layered sensors are removed when removal would improve yield or process window. Multiple layered sensors are not removed when removal would increase cost. In some instances, only a portion of the multiple layered sensors is removed.

[0048] In one embodiment, the present invention provides a method. The method includes providing a semiconductor device package, the semiconductor device package including a package substrate, a semiconductor device disposed above the package substrate, and at least one layer sensor. The semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer. The at least one layer sensor includes: a connection structure for bonding the semiconductor device to the package substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers. The plurality of contact vias fall within a first region of a vertically projected area of ​​the connection structure, but do not overlap with a second region of the vertically projected area. The method further includes screening the layers of the entire semiconductor device package by testing only the at least one layer sensor.

[0049] In some embodiments, the at least one layered sensor comprises a plurality of layered sensors with different sensitivities. In some embodiments, the dielectric layer comprises a dielectric material with a dielectric constant less than 2.7. In some instances, the connection structure is adjacent to a corner of the semiconductor device. In some embodiments, the vertically projected region is circular and includes a center, and the second region is disposed between the center and the corner of the semiconductor device.

[0050] In another embodiment, the present invention also provides a method. The method includes providing a semiconductor device package, the semiconductor device package including a package substrate, a semiconductor device located above the package substrate, and at least one layer sensor. The semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer. The at least one layer sensor includes: a connection structure for bonding the semiconductor device to the package substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers. The plurality of contact vias fall within a first region of a vertically projected area of ​​the connection structure, but do not overlap with a second region of the vertically projected area. The method further includes screening the entire semiconductor device package for layering by testing only the at least one layer sensor. When layering occurs during the screening, the method includes modifying the semiconductor device to form a modified semiconductor device. When no layering occurs during the screening, the method further includes mass-producing the semiconductor device.

[0051] In some embodiments, the method further includes, after implementing the changes, providing a modified semiconductor device package including another substrate, and the modified semiconductor device including at least one layer sensor. The method may also include screening the layers of the entire modified semiconductor device package by testing only the at least one layer sensor. In some embodiments, the implemented changes are based on the layers identified during the screening. In some embodiments, the connection structure is adjacent to a corner of the semiconductor device. In some instances, the connection structure is an under-bump metallization (UBM) structure.

[0052] In another embodiment, the present invention provides a semiconductor structure. The semiconductor structure includes a packaging substrate, a semiconductor device located above the packaging substrate, and a layered sensor. The semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer. The layered sensor includes: a connection structure for bonding the semiconductor device to the packaging substrate, and a plurality of contact vias located in at least one of the plurality of metallization layers. The plurality of contact vias fall within a first region of the vertically projected area of ​​the connection structure, but do not overlap with a second region of the vertically projected area.

[0053] In some embodiments, the dielectric layer is an extremely low-k dielectric layer with a dielectric constant less than 2.7. In some embodiments, the dielectric layer is porous. In some embodiments, the connection structure is adjacent to a corner of the semiconductor device. In some instances, the vertical projection region is circular and includes a center, and the second region is disposed between the center and the corner of the semiconductor device. In some embodiments, the connection structure is adjacent to the edge of the semiconductor device. In some embodiments, the vertical projection region is circular and includes a center, and the second region is disposed between the center and the edge of the semiconductor device. In some instances, the connection structure is adjacent to the geometric center of the semiconductor device. In some embodiments, the vertical projection region is circular and includes a center, and the second region is symmetrical with respect to the center. In some embodiments, the connection structure is an under-bump metallization (UBM) structure.

[0054] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the following detailed description. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of the invention.

Claims

1. A method for testing semiconductor structures, comprising: A semiconductor device package is provided, the semiconductor device package comprising: Packaging substrate, A semiconductor device is located above the packaging substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer, and At least one layered sensor, including: A connection structure is provided to bond the semiconductor device to the packaging substrate, and A plurality of contact vias are located in at least one of the plurality of metallization layers, wherein the plurality of contact vias fall within a first region of the vertical projection area of ​​the connection structure, but do not overlap with a second region of the vertical projection area; and The entire semiconductor device package is screened by testing only the at least one layer sensor.

2. The method according to claim 1, wherein, The at least one layered sensor includes multiple layered sensors with different sensitivities.

3. The method according to claim 1, wherein, The dielectric layer comprises a dielectric material with a dielectric constant of less than 2.

7.

4. The method according to claim 1, wherein, The connection structure is located near the corner of the semiconductor device.

5. The method according to claim 4, in, The vertical projection area is circular and includes a center. The second region is located between the center and the corner of the semiconductor device.

6. A method for testing semiconductor structures, comprising: A semiconductor device package is provided, the semiconductor device package comprising: Packaging substrate, A semiconductor device is located above the packaging substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer, and At least one layered sensor, including: A connection structure is provided to bond the semiconductor device to the packaging substrate, and Multiple contact vias are located in at least one of the multiple metallization layers, wherein the multiple contact vias fall within a first region of the vertical projection area of ​​the connection structure, but do not overlap with a second region of the vertical projection area; The entire semiconductor device package is screened by testing only the at least one layer sensor; When stratification occurs during the screening process, modifications are made to the semiconductor device to form a modified semiconductor device; and In this process, no stratification occurs during the screening, thereby enabling the mass production of the semiconductor devices.

7. The method according to claim 6, further comprising: Following the implementation changes, a modified semiconductor device package is provided, the modified semiconductor device package comprising: Another substrate, and The modified semiconductor device includes at least one layered sensor; and The entire layering of the modified semiconductor device package is screened by testing only the at least one layering sensor.

8. The method according to claim 6, wherein, The changes implemented are based on the stratification identified during the screening process.

9. The method according to claim 6, wherein, The connection structure is located near the corner of the semiconductor device.

10. The method according to claim 6, wherein, The connection structure is an under-bump metallization (UBM) structure.

11. A semiconductor structure, comprising: Packaging substrate; A semiconductor device is located above the packaging substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and Layered sensors, including: A connection structure is provided to bond the semiconductor device to the packaging substrate, and Multiple contact vias are located in at least one of the multiple metallization layers, wherein the multiple contact vias fall within a first region of the vertical projection area of ​​the connection structure, but do not overlap with a second region of the vertical projection area.

12. The semiconductor structure according to claim 11, wherein, The dielectric layer is an extremely low-k dielectric layer with a dielectric constant of less than 2.

7.

13. The semiconductor structure according to claim 11, wherein, The dielectric layer is porous.

14. The semiconductor structure according to claim 11, wherein, The connection structure is located near the corner of the semiconductor device.

15. The semiconductor structure according to claim 14, in, The vertical projection area is circular and includes a center. The second region is located between the center and the corner of the semiconductor device.

16. The semiconductor structure according to claim 11, wherein, The connection structure is located near the edge of the semiconductor device.

17. The semiconductor structure according to claim 16, in, The vertical projection area is circular and includes a center. The second region is disposed between the center and the edge of the semiconductor device.

18. The semiconductor structure according to claim 11, wherein, The connection structure is located near the geometric center of the semiconductor device.

19. The semiconductor structure according to claim 18, in, The vertical projection area is circular and includes a center. The second region is symmetrical about the center.

20. The semiconductor structure according to claim 11, wherein, The connection structure is an under-bump metallization (UBM) structure.

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