Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The semiconductor structure includes: a gate structure located on a substrate; source / drain doped layers located within the substrate on both sides of the gate structure; a dielectric layer covering the top of the gate structure and the source / drain doped layers; a source / drain plug penetrating the dielectric layers on both sides of the gate structure and electrically connected to the top of the source / drain doped layers, the source / drain plug including a first end and a second end along the extension direction of the gate structure, the source / drain plug including an adjacent first region and a second region, the second region being located on one side of the first end or on one side of the second end, the top of the source / drain plug in the first region being lower than the top of the source / drain plug in the second region; a source / drain capping layer located on the top of the source / drain plug in the first region and covering the sidewall of the source / drain plug in the second region; and a gate plug located between the source / drain capping layers and penetrating the dielectric layer on the top of the gate structure, the gate plug being electrically connected to the top of the gate structure. This invention simplifies the process steps and reduces the process difficulty while using COAG technology to form the gate plug.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry.

[0004] Currently, to further reduce transistor area, the ContactOver Active Gate (COAG) process has been introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which simplifies the process steps and reduces the process difficulty while forming the gate plug using the COAG process.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; source / drain doped layers located within the substrate on both sides of the gate structure; a dielectric layer located on the substrate and covering the top of the gate structure and the top of the source / drain doped layers; a source / drain plug penetrating the dielectric layers on both sides of the gate structure and electrically connected to the top of the source / drain doped layers, wherein along the extension direction of the gate structure, the source / drain plug includes opposing first and second ends, and the source / drain plug includes adjacent first and second regions, the second region being located on one side of the first end or on one side of the second end, and the top of the source / drain plug in the first region being lower than the top of the source / drain plug in the second region; a source / drain capping layer located on the top of the source / drain plug in the first region and covering the sidewall of the source / drain plug in the second region; and a gate plug located between the source / drain capping layers and penetrating the dielectric layer on the top of the gate structure, the gate plug being electrically connected to the top of the gate structure.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, and a dielectric layer is formed on the substrate covering the top of the gate structure and the top of the source and drain doped layers; forming source and drain plugs on both sides of the gate structure, penetrating the dielectric layer and electrically connected to the top of the source and drain doped layers, wherein along the extension direction of the gate structure, the source and drain plugs include opposing first and second ends, and the source and drain plugs include adjacent first and second regions, the second region being located on one side of the first end or on one side of the second end; removing a portion of the thickness of the source and drain plugs of the first region, forming a first opening in the source and drain plugs; forming a source and drain capping layer in the first opening; forming a gate plug in the dielectric layer between the source and drain capping layers, the gate plug penetrating the dielectric layer at the top of the gate structure and electrically connected to the top of the gate structure.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, the source / drain plug penetrates the dielectric layers on both sides of the gate structure and is electrically connected to the top of the source / drain doped layer. Along the extension direction of the gate structure, the source / drain plug includes a first end and a second end opposite to each other, and the source / drain plug includes an adjacent first region and a second region. The second region is located on one side of the first end or on one side of the second end. The top of the source / drain plug in the first region is lower than the top of the source / drain plug in the second region. A source / drain capping layer is located on the top of the source / drain plug in the first region and covers the sidewall of the source / drain plug in the second region. The source and drain plugs are integrated into a single structure. The electrical properties of the source and drain doped regions are brought out through the source and drain plugs. By making the top of the source and drain plug in the first region lower than the top of the source and drain plug in the second region, space is reserved for the source and drain capping layer. Under the action of the source and drain capping layer, the probability of short circuit between the gate plug and the source and drain plug is reduced. Therefore, the semiconductor structure can use active gate contact hole plugs (COAG), thereby further saving chip area. Moreover, the source and drain plugs are integrated into a single structure, which simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process.

[0010] In the semiconductor structure formation method provided by this embodiment of the invention, after forming source / drain plugs that penetrate the dielectric layer and are electrically connected to the top of the source / drain doped layer on both sides of the gate structure, a portion of the thickness of the source / drain plug in the first region is removed, a first opening is formed in the dielectric layer, and a source / drain capping layer is formed in the first opening. This embodiment of the invention performs only one source / drain plug formation process, and by removing a portion of the thickness of the source / drain plug in the first region, space is reserved for the formation of the source / drain capping layer. Under the action of the source / drain capping layer, the probability of short circuit between the gate plug and the source / drain plug is reduced. Therefore, the formation method can use active gate contact hole plugs (…). The COAG process further saves chip area. Moreover, compared with the current approach of first forming a source-drain interconnect layer with its top lower than the top of the dielectric layer and electrically connected to the source-drain doped layer, then covering the source-drain interconnect layer with a source-drain cap layer, and finally forming a source-drain plug that penetrates the source-drain cap layer and is electrically connected to the top of the source-drain interconnect layer, the present invention combines the current steps of forming the source-drain interconnect layer and forming the source-drain plug into the same step. That is, the source-drain plug with an integral structure is formed in the same step, and the source-drain cap layer is formed after the source-drain plug is formed. This simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process. Attached Figure Description

[0011] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 5 to 7This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 8 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] Currently, when using the COAG process to form gate plugs, the process is cumbersome and quite difficult.

[0015] This paper analyzes the reasons for the complex and challenging process of forming a semiconductor structure. Specifically, refer to... Figures 1 to 4 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, on which a gate structure 11 is formed. A gate capping layer 13 is formed on the top of the gate structure 11. Source and drain doped layers 14 are formed in the substrate 10 on both sides of the gate structure 11. Sidewalls 12 are formed on the sidewalls of the gate structure 11. The sidewalls 12 also extend to cover the sidewalls of the gate capping layer 13. A first interlayer dielectric layer 15 covering the top of the gate structure 11 is also formed on the substrate 10. An initial source and drain interconnect layer 16 is formed on both sides of the gate structure 11, penetrating the first interlayer dielectric layer 15 and electrically connected to the top of the source and drain doped layers 14.

[0017] refer to Figure 2 The initial source-drain interconnect layer 16 with a partial thickness is etched back, and a groove 18 is formed in the first interlayer dielectric layer 15. The remaining initial source-drain interconnect layer 16 after the etch back serves as the source-drain interconnect layer 17, and the top of the source-drain interconnect layer 17 is higher than the top of the gate structure 11.

[0018] refer to Figure 3 The source / drain cap material layer (not shown) is filled in the groove 18; the source / drain cap material layer and the first interlayer dielectric layer 15 are planarized until the thickness of the remaining source / drain cap material layer reaches the target thickness, and the remaining source / drain cap material layer serves as the source / drain cap layer 18.

[0019] refer to Figure 4 A second interlayer dielectric layer 19 is formed to cover the source / drain capping layer 18 and the first interlayer dielectric layer 15; a source / drain plug 21 is formed that penetrates the top of the second interlayer dielectric layer 19 and the source / drain capping layer 18; and a gate plug 22 is formed that penetrates the top of the second interlayer dielectric layer 19 and the gate capping layer 13.

[0020] An active drain capping layer 18 is formed on the top of the source-drain interconnect layer 17, and a gate capping layer 13 is formed on the top of the gate structure 11, thereby enabling the gate plug 22 to be formed using the COAG process.

[0021] Currently, one approach is to form the source / drain plug 21 and the gate plug 22 before forming the first metal interconnect (M1). However, in this approach, after forming the source / drain cap layer 18, a second interlayer dielectric layer 19 needs to be formed, and the source / drain plug 21 also needs to be formed in order to bring out the electrical properties of the source / drain doped layer 14. In other words, the source / drain interconnect layer 17 and the source / drain plug 21 need to be formed in different steps to bring out the electrical properties of the source / drain doped layer 14, which leads to a cumbersome process.

[0022] Furthermore, since the source / drain capping layer 18 needs to be etched during the formation of the source / drain plug 21, and the gate capping layer 13 needs to be etched during the formation of the gate plug 22, the etching selectivity ratio between the source / drain capping layer 18 and the gate capping layer 13 is required to achieve self-aligned etching. That is, when etching the source / drain capping layer 18, the etching rate of the source / drain capping layer 18 is much greater than the etching rate of the gate capping layer 13, and when etching the gate capping layer 13, the etching rate of the gate capping layer 13 is much greater than the etching rate of the source / drain capping layer 18, which leads to greater process difficulty.

[0023] Another approach is to utilize the damascus process in the back-end process (BEOL) to form the source / drain plugs 21 and the gate plugs 22. That is, the source / drain plugs 21, the gate plugs 22, and the first layer of metal interconnects (M1) are formed in the same step. The opening formed using the damascus process includes trenches and vias located at the bottom of the trenches and connected to the bottom of the trenches. The first layer of metal interconnects are formed in the trenches, and the source / drain plugs 21 and the gate plugs 22 are formed in the vias. However, this also requires consideration of the etching selectivity between the gate cap layer 13 and the drain cap layer 18, as well as compatibility with the back-end process, making the process still quite challenging.

[0024] Therefore, the current COAG process for forming gate plugs is cumbersome and difficult.

[0025] To address the aforementioned technical problem, the semiconductor structure formation method provided in this embodiment of the invention involves forming source / drain plugs that penetrate the dielectric layer and are electrically connected to the top of the source / drain doped layers on both sides of the gate structure. Then, a portion of the thickness of the source / drain plugs in the first region is removed, forming a first opening in the dielectric layer, and a source / drain capping layer is formed in the first opening. This embodiment of the invention performs only one source / drain plug formation process and reserves space for the formation of the source / drain capping layer by removing a portion of the thickness of the source / drain plugs in the first region. Under the action of the source / drain capping layer, the probability of a short circuit between the gate plug and the source / drain plug is reduced. Therefore, the formation method can adopt… Using the COAG process further saves chip area. Moreover, compared with the current approach of first forming a source-drain interconnect layer with its top lower than the top of the dielectric layer and electrically connected to the source-drain doped layer, then covering the source-drain interconnect layer with a source-drain cap layer, and finally forming a source-drain plug that penetrates the source-drain cap layer and is electrically connected to the top of the source-drain interconnect layer, this embodiment of the invention combines the current steps of forming the source-drain interconnect layer and forming the source-drain plug into the same step. That is, the source-drain plug with an integral structure is formed in the same step, and the source-drain cap layer is formed after the source-drain plug is formed. This simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 5 It is a top view; Figure 6 This is a cross-sectional view along the direction of the gate structure at the top of the source / drain plug. For ease of illustration, only the substrate, source / drain doped layer, source / drain plug, and source / drain capping layer are shown. Figure 7 yes Figure 6 A cross-sectional view at the top of the gate plug, in a direction perpendicular to the direction of the gate structure extension.

[0028] The semiconductor structure includes: a substrate 300; a gate structure 310 located on the substrate 300; a source / drain doped layer 340 located within the substrate 300 on both sides of the gate structure 310; a dielectric layer 305 located on the substrate 300 and covering the top of the gate structure 310 and the top of the source / drain doped layer 340; and a source / drain plug 400 penetrating the dielectric layer 305 on both sides of the gate structure 310 and electrically connected to the top of the source / drain doped layer 340. Along the extending direction of the gate structure 310, the source / drain plug 400 includes opposing first ends 400a (e.g., ...). Figure 5 (as shown) and the second end 400b (as shown) Figure 5As shown), and the source / drain plug 400 includes an adjacent first region 400D (as shown). Figure 5 (as shown) and the second area 400C (as shown) Figure 5 As shown), the second region 400C is located on one side of the first end 400a or on one side of the second end 400b. The top of the source / drain plug 400 of the first region 400D is lower than the top of the source / drain plug 400 of the second region 400C. The source / drain capping layer 430 is located on top of the source / drain plug 400 of the first region 400D and covers the sidewall of the source / drain plug 400 of the second region 400C. The gate plug 440 is located between the source / drain capping layers 430 and penetrates the dielectric layer 305 on top of the gate structure 310. The gate plug 440 is electrically connected to the top of the gate structure 310.

[0029] In this embodiment, the source / drain plug 400 is an integral structure. The source / drain doped region 340 is electrically led out through the source / drain plug 400. By making the top of the source / drain plug 400 in the first region 400D lower than the top of the source / drain plug 400 in the second region 400C, space is reserved for the source / drain capping layer 430. Under the action of the source / drain capping layer 430, the probability of a short circuit between the gate plug 440 and the source / drain plug 400 is reduced. Therefore, the semiconductor structure can use an active gate contact via (COAG), thereby further saving chip area. Furthermore, compared to the current method of electrically connecting the source and drain through a source / drain interconnect layer... Compared to the previous method of forming a doped layer, covering the top of the source-drain interconnect layer with a source-drain cap layer, and then using a source-drain plug that penetrates the source-drain cap layer and is electrically connected to the top of the source-drain interconnect layer to bring out the electrical properties of the source-drain doped region, the source-drain plug 400 in this embodiment is an integral structure. Accordingly, the steps of forming the source-drain interconnect layer and forming the source-drain plug can be combined into the same step. The source-drain cap layer 430 is embedded in the source-drain plug 400 of the first region 400D and covers the top of the source-drain plug 400 of the first region 400D. This simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process.

[0030] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the substrate 300 correspondingly includes a substrate 301 and fins 302 located on the substrate 301. In this embodiment, the material of the substrate 301 is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The fins 302 are discretely disposed on the substrate 301. In this embodiment, the material of the fins 302 is the same as that of the substrate 301, which is silicon. In other embodiments, when the semiconductor structure is a planar transistor, the substrate may also be a planar substrate.

[0031] In this embodiment, the substrate further includes an isolation layer (not shown) located on the substrate 301 exposed by the fin 302, the isolation layer covering a portion of the sidewall of the fin 302. Specifically, the isolation layer is a shallow trench isolation structure, and the material of the isolation layer is an insulating material. As an example, the material of the isolation layer is silicon oxide.

[0032] The gate structure 310 spans the fin 302 and covers part of the top and sidewalls of the fin 302. The gate structure 310 is a device gate structure used to control the opening and closing of the transistor channel. In this embodiment, the gate structure 310 is a metal gate structure, specifically including a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0033] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0034] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0035] The gate electrode layer is used to conduct electrical signals from the metal gate structure. The material of the gate electrode layer includes Al, Au, Pt, Ni, Ti, or W. As an example, the material of the gate electrode layer is W.

[0036] In other embodiments, depending on process requirements, the gate structure may also be other types of device gate structures such as polysilicon gate structures.

[0037] In this embodiment, a gate cap layer 330 is also formed on the top of the gate structure 310. The gate cap layer 330 covers the top of the gate structure 310 and serves to protect the top of the gate structure 310. Moreover, during the process of forming source / drain plugs 400 that penetrate the dielectric layer 305 and are electrically connected to the top of the source / drain doped layer 340 on both sides of the gate structure 310, a self-aligned etching process is typically used to form an opening for accommodating the source / drain plugs 400. The gate cap layer 330 can also act as an etching stop layer during the self-aligned etching process, which helps to reduce the probability of damage to the gate structure 310 and short circuit between the source / drain plugs 400 and the gate structure 310.

[0038] The gate cap layer 330 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate cap layer 330 is made of silicon nitride.

[0039] In this embodiment, the sidewalls of the gate structure 310 are formed with sidewalls 320. Specifically, the sidewalls 320 also extend to cover the sidewalls of the gate cap layer 330. The sidewalls 320 are used to protect the sidewalls of the gate structure 310 and also to define the formation locations of the source / drain doped layers 340.

[0040] The sidewall 320 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. The sidewall 320 may be a single-layer structure or a multilayer structure. As an example, the sidewall 320 is a single-layer structure made of silicon nitride. In other embodiments, the dielectric constant of the sidewall material is less than that of silicon oxide. Using a sidewall with a lower dielectric constant helps to reduce parasitic capacitance between the gate structure and subsequent source / drain plugs. Specifically, the sidewall material may be one or more of low-k dielectric materials or ultra-low-k dielectric materials; wherein, low-k dielectric materials refer to dielectric materials with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9, and ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6.

[0041] In this embodiment, the source / drain doped layers 340 are located in the fins 302 on both sides of the gate structure 310. The source / drain doped layer 340 on one side of the gate structure 310 serves as the source, and the source / drain doped layer 340 on the other side of the gate structure 310 serves as the drain. When the semiconductor structure is a PMOS transistor, the material of the source / drain doped layer 340 includes silicon germanide doped with P-type ions, where the P-type ions include B, Ga, or In. When the semiconductor structure is an NMOS transistor, the material of the source / drain doped layer 340 includes silicon or silicon carbide doped with N-type ions, where the N-type ions include P, As, or Sb.

[0042] The dielectric layer 305 is an interlayer dielectric (ILD) used to isolate adjacent transistors and also to provide a process basis for the formation of the source / drain plug 400, the source / drain cap layer 430, and the gate plug 440. The dielectric layer 305 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the dielectric layer 305 is made of silicon oxide.

[0043] The source / drain plug 400 is used to bring out the electrical properties of the source / drain doped layer 340, thereby realizing the electrical connection between the source / drain doped layer 340 and external circuits or other interconnect structures. For example, the source / drain plug 400 is used to realize the electrical connection between the source / drain doped layer 340 and the first metal interconnect (M1) in the subsequent process.

[0044] In this embodiment, the source / drain plug 400 is an integral structure.

[0045] like Figure 5 and Figure 6 As shown, in this embodiment, along the extending direction of the gate structure 310, the source / drain plug 400 includes a first end 400a and a second end 400b, and the source / drain plug 400 includes an adjacent first region 400D and a second region 400C, wherein the second region 400C is located on the side of the first end 400a or on the side of the second end 400b. That is, along the extending direction of the gate structure 310, the second region 400C is located at either end of the source / drain plug 400, and the remaining region is the first region 400D.

[0046] Furthermore, the top of the source / drain plug 400 in the first region 400D is lower than the top of the source / drain plug 400 in the second region 400C, thereby providing space for the formation of the source / drain cap layer 430.

[0047] In this embodiment, the second region 400C of the source / drain plug 400 on one side of the gate structure 310 is located on the side of the first end 400a, and the second region 400C of the source / drain plug 400 on the other side of the gate structure 310 is located on the side of the second end 400b. For the source / drain plugs 400 on both sides of the gate structure 310, by setting the second region 400C at different end positions of the source / drain plug 400, the top of the source / drain plug 400 exposed by the source / drain cap layer 430 is correspondingly located at different end positions of the source / drain plug 400.

[0048] Specifically, the first metal interconnect is located on the dielectric layer 305 and electrically connected to the top of the source-drain plug 400. The source and drain of the transistor are electrically connected to different first metal interconnects, and the first metal interconnect connected to the source is parallel to the first metal interconnect connected to the drain. Correspondingly, the source-drain plug 400 on one side of the gate structure 310 is electrically connected to one first metal interconnect, and the source-drain plug 400 on the other side of the gate structure 310 is electrically connected to another first metal interconnect. By setting the second region 400C at different end positions of the source-drain plug 400, the spacing between the first metal interconnects electrically connected to the source and drain is increased, thereby providing a larger process window for forming the first metal interconnect exposed on the top of the source-drain plug 400 through the drain cap layer.

[0049] In other embodiments, depending on the actual situation, the second regions of the source and drain plugs on both sides of the gate structure may also be located at the same end position of the source and drain plugs.

[0050] As an example, along the extension direction of the gate structure 310, the source / drain plug 400 is elongated, covering the top and sidewalls of the source / drain doped layer 340, as well as the tops of the isolation layers on both sides of the source / drain doped layer 340. For example, when the gate structure 310 spans multiple fins 302, the source / drain plug 400 can simultaneously cover each source / drain doped layer 340 between the gate structures 310, as well as the isolation layers between adjacent fins 302.

[0051] The source / drain plug 400 also covers the sidewalls of the source / drain doped layer 340, thereby increasing the contact area between the source / drain plug 400 and the source / drain doped layer 340 and reducing the contact resistance. Furthermore, the elongated shape of the source / drain plug 400 provides sufficient space for the shape of the source / drain cap layer 430 and ensures that the length of the source / drain cap layer 430 meets process requirements, thus enabling self-alignment during the formation of the gate plug 440.

[0052] As an example, the top dimension of the source / drain plug 400 is larger than its bottom dimension. Specifically, the source / drain plug 400 also covers a portion of the top of the sidewall 320. The source / drain plug 400 is used to establish an electrical connection with the first metal interconnect. By making the top dimension of the source / drain plug 400 larger than its bottom opening dimension, the top dimension of the source / drain plug 400 is increased, thereby reducing the contact resistance between the source / drain plug 400 and the first metal interconnect.

[0053] A gate cap layer 330 is formed on the top of the gate structure 310. Therefore, self-aligned etching is easy to achieve during the formation of the source-drain plug 400, which is conducive to precise control of the formation position of the source-drain plug 400 and makes it easy to increase the top size of the source-drain plug 400.

[0054] In this embodiment, the source / drain plug 400 is made of conductive materials such as cobalt, ruthenium, or tungsten.

[0055] It should be noted that the sidewalls and bottom of the source / drain plug 400 are covered with an adhesion barrier layer (not shown). For example, the adhesion barrier layer includes a tantalum nitride layer and a titanium nitride layer covering the tantalum nitride layer. This embodiment will not be described in detail here.

[0056] It should also be noted that the source / drain plug 400 is a single-piece structure, and the distance from the top of the source / drain plug 400 to the top of the source / drain doped layer 340 has reached the target distance. Compared with the current approach of first electrically connecting the source / drain doped layer through the source / drain interconnect layer, covering the top of the source / drain interconnect layer with a source / drain cap layer, and then using a source / drain plug that penetrates the source / drain cap layer and is electrically connected to the top of the source / drain interconnect layer to bring out the electrical properties of the source / drain doped region, this embodiment forms the source / drain plug 400 for bringing out the electrical properties of the source / drain doped layer 340 in the same step. In other words, this embodiment combines the current steps of forming the source / drain interconnect layer and forming the source / drain plug into the same step, thereby simplifying the process steps.

[0057] It should be noted that the distance (not shown) between the top of the source / drain plug 400 in the second region 400C and the top of the source / drain plug 400 in the first region 400D, relative to the total height of the source / drain plug 400, should not be too small or too large. The distance between the top of the source / drain plug 400 in the second region 400C and the top of the source / drain plug 400 in the first region 400D determines the thickness of the source / drain capping layer 430. If the distance (not shown) between the top of the source / drain plug 400 in the second region 400C and the top of the source / drain plug 400 in the first region 400D, relative to the total height of the source / drain plug 400, is too small, the thickness of the source / drain capping layer 430 will be too small. During the formation of the gate plug 440, this can easily lead to poor protection of the source / drain plug 400 by the source / drain capping layer 430, and the thickness of the source / drain capping layer 430 will be insufficient to achieve self-aligned etching, making it difficult to form the gate plug 440 using the COAG process. If the distance (not shown) between the top of the source / drain plug 400 in the second region 400C and the top of the source / drain plug 400 in the first region 400D is too large as a proportion of the total height of the source / drain plug 400, then during the process of removing part of the thickness of the source / drain plug 400 in the first region 400D, the amount of thickness removed from the source / drain plug 400 will be too large. This will not only easily lead to an excessive impact on the resistance of the source / drain plug 400 itself, but also easily increase the probability of damage to the gate structure 310 when the top of the source / drain plug 400 in the first region 400D is lower than the top of the gate cap layer 330 (for example, due to the gate cap layer 330 or the sidewall 320 being mistakenly etched, causing the gate structure 310 to be exposed to the etching environment). Therefore, in this embodiment, the distance between the top of the source / drain plug 400 in the second region 400C and the top of the source / drain plug 400 in the first region 400D is 10% to 50% of the total height of the source / drain plug 400.

[0058] As an example, the top of the source / drain plug 400 of the second region 400C is lower than or flush with the top of the gate cap layer 330, which helps to increase the distance between the gate plug 440 located on top of the gate structure 310 and the source / drain plug 400 of the second region 400C, thereby reducing the probability of a short circuit between the gate plug 440 and the source / drain plug 400. Figure 7 As shown in the figure, this embodiment illustrates the case where the top of the source / drain plug 400 of the second region 400C is flush with the top of the gate cap layer 330.

[0059] The source / drain cap layer 430 covers the top of the source / drain plug 400 in the first region 400D and serves to protect the top of the source / drain interconnect layer 400.

[0060] Furthermore, during the process of forming a gate plug 440 that penetrates the dielectric layer 305 on the top of the gate structure 310, a self-aligned etching process is typically used to form an opening for accommodating the gate plug 440. The source / drain cap layer 430 can also act as an etching stop layer during the self-aligned etching process, which helps to reduce the probability of damage to the source / drain plug 400 and short circuit between the gate plug 440 and the source / drain plug 400.

[0061] Furthermore, under the action of the source / drain capping layer 430, the gate plug 440 can be disposed above the gate structure 310 in the active region, that is, the gate plug can be formed using the COAG process. The gate plug is the active gate contact plug. Compared with the scheme where the gate plug is located above the gate structure in the isolation region, this embodiment eliminates the part of the gate structure 310 located in the isolation region, which is beneficial to save the chip area and thus achieve further reduction in chip size.

[0062] It should be noted that in the current process, a source-drain interconnect layer is usually formed first, with its top lower than the top of the dielectric layer and electrically connected to the source-drain doped layer. A source-drain capping layer is then placed on top of the source-drain interconnect layer. A source-drain plug is then formed that penetrates the source-drain capping layer and is electrically connected to the top of the source-drain interconnect layer. Since the source-drain capping layer needs to be etched during the formation of the source-drain plug, and the gate capping layer needs to be etched during the formation of the gate plug, the etching selectivity between the source-drain capping layer and the gate capping layer is required to be high. It must simultaneously satisfy the following: when etching the source-drain capping layer, the etching rate of the source-drain capping layer is much greater than that of the gate capping layer, and when etching the gate capping layer, the etching rate of the gate capping layer is much greater than that of the source-drain capping layer. In this embodiment, the source / drain capping layer 430 is located within the source / drain plug 400. This means that there is no step of etching the source / drain capping layer 430 during the formation of the source / drain plug 400. This reduces the requirement for the etching selectivity ratio between the source / drain capping layer 430 and the gate capping layer 330. For example, it is only necessary to ensure that the etching rate of the gate capping layer 330 is greater than the etching rate of the source / drain capping layer 430 when etching the gate capping layer 330, without having to consider the etching selectivity ratio between the source / drain capping layer 430 and the gate capping layer 330 when etching the source / drain capping layer 430, thereby reducing the process difficulty.

[0063] Moreover, the source / drain plug 400 in this embodiment is an integral structure. Accordingly, during the formation of the semiconductor structure, only one process of forming the source / drain plug 400 is performed. After forming the source / drain plug 400, by removing part of the thickness of the source / drain plug 400 in the first region 400D, space is reserved for the formation of the source / drain cap layer 430, thereby simplifying the process steps and reducing the process difficulty.

[0064] In summary, this embodiment simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process.

[0065] It should be noted that in this embodiment, the thickness of the source / drain capping layer 430 is greater than that of the gate capping layer 330. Therefore, even if the source / drain capping layer 430 and the gate capping layer 330 are made of the same material, the probability of the source / drain capping layer 430 being completely consumed during the formation of the gate plug 440 is low, and the source / drain capping layer 430 can still play its corresponding role. Therefore, the source / drain capping layer 430 and the gate capping layer 330 can be made of the same material or different materials, allowing for greater process flexibility. The material of the source / drain capping layer 430 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the source / drain capping layer 430 and the gate capping layer 330 are made of different materials to ensure an etching selectivity ratio between them and reduce process risk. For example, the material of the source / drain capping layer 430 is silicon carbide.

[0066] In this embodiment, the source / drain cap layer 430 is also located in the dielectric layer 305, and the top of the source / drain cap layer 430 is flush with the top of the source / drain plug 400 in the second region 400C.

[0067] Moreover, in this embodiment, the source / drain capping layer 430 exposes the top of the source / drain plug 400 in the second region 400C, so that the source / drain plug 400 can realize the electrical connection between the source / drain doped layer 340 and external circuits or other interconnection structures.

[0068] The gate plug 440 is used to bring out the electrical properties of the gate structure 310, thereby realizing the electrical connection between the gate structure 310 and external circuits or other interconnect structures. For example, the gate plug 440 is used to realize the electrical connection between the gate structure 310 and the first metal interconnect (M1) in the back-end process. In this embodiment, the material of the gate plug 440 includes conductive materials such as tungsten, ruthenium, or cobalt.

[0069] It should be noted that a gate cap layer 330 is also formed on the top of the gate structure 310. Therefore, the gate plug 440 penetrates the dielectric layer 305 and the gate cap layer 330 on the top of the gate structure 310 in the longitudinal direction. Here, longitudinal direction refers to the height direction of the gate structure 310.

[0070] It should also be noted that the second region 400C is located on the side of the first end 400a of the source-drain plug 400 or on the side of the second end 400b, and the source-drain cap layer 430 is exposed on the top of the source-drain plug 400 in the second region 400C. Therefore, the source-drain plug 400 exposed by the source-drain cap layer 430 is located at the end position of the source-drain plug 400, while the gate plug 440 is located between the source-drain cap layers 430 and penetrates the dielectric layer 305 on the top of the gate structure 310. Therefore, the distance between the gate plug 440 and the source-drain plug 400 in the second region 400C is large, and the probability of short-circuiting between the gate plug 440 and the source-drain plug 400 is correspondingly low.

[0071] Furthermore, in this embodiment, the electrical properties of the source / drain doped layer 340 and the gate structure 310 are brought out before the back-end process. Therefore, it is not necessary to use a dual damascene process to form the first metal interconnect. Accordingly, the first metal interconnect is directly electrically connected to the gate plug 440 and the source / drain plug 400, respectively. The bottom of the first metal interconnect does not have a via interconnect structure, which simplifies the process steps for forming the first metal interconnect and has little impact on the traditional back-end process. The semiconductor structure formation process has high compatibility with the traditional process flow.

[0072] Figures 8 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0073] refer to Figure 8 A substrate 100 is provided, on which a gate structure 110 is formed, and source / drain doped layers 140 are formed in the substrate 100 on both sides of the gate structure 110. A dielectric layer 105 is formed on the substrate 100 covering the top of the gate structure 110 and the top of the source / drain doped layers 140.

[0074] In this embodiment, the formation method is used to form a fin field-effect transistor, and the substrate 100 correspondingly includes a substrate 101 and fins 102 located on the substrate 101. In this embodiment, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The fins 102 are discretely disposed on the substrate 101. In this embodiment, the material of the fins 102 is the same as the material of the substrate 101, which is silicon. In other embodiments, when the semiconductor structure is a planar transistor, the substrate may also be a planar substrate.

[0075] In this embodiment, the substrate further includes an isolation layer (not shown) located on the substrate 101 exposed by the fin 102, the isolation layer covering a portion of the sidewall of the fin 102. Specifically, the isolation layer is a shallow trench isolation structure, and the material of the isolation layer is an insulating material. As an example, the material of the isolation layer is silicon oxide.

[0076] The gate structure 110 spans the fin 102 and covers part of the top and sidewalls of the fin 102. The gate structure 110 is a device gate structure used to control the turning on and off of the transistor channel. In this embodiment, the gate structure 110 is a metal gate structure. A detailed description of the metal gate structure can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here. In other embodiments, depending on process requirements, the gate structure may also be other types of device gate structures such as a polysilicon gate structure.

[0077] In this embodiment, a gate cap layer 130 is also formed on the top of the gate structure 110. The gate cap layer 130 covers the top of the gate structure 110 and serves to protect the top of the gate structure 110. Moreover, in the subsequent process of forming source / drain plugs that penetrate the dielectric layer 105 and are electrically connected to the top of the source / drain doped layer 140 on both sides of the gate structure 110, a self-aligned etching process is usually used to form a second opening for accommodating the source / drain plugs. The gate cap layer 130 can also act as an etching stop layer in the self-aligned etching process, which helps to reduce the probability of damage to the gate structure 110 and short circuit between the source / drain plugs and the gate structure 110.

[0078] The gate cap layer 130 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate cap layer 130 is made of silicon nitride.

[0079] In this embodiment, the sidewalls of the gate structure 110 are formed with sidewalls 120. Specifically, the gate capping layer 130 is formed on top of the remaining gate structure 110 after etching back a portion of the gate structure 110. Therefore, the sidewalls 120 also extend to cover the sidewalls of the gate capping layer 130. The sidewalls 120 are used to protect the sidewalls of the gate structure 110 and also to define the formation locations of the source / drain doped layers 140.

[0080] In this embodiment, the source / drain doped layer 140 is formed in the fins 102 on both sides of the gate structure 110. The source / drain doped layer 140 on one side of the gate structure 110 is used as the source, and the source / drain doped layer 140 on the other side of the gate structure 110 is used as the drain.

[0081] For a detailed description of the sidewall 120 and the source / drain doped layer 140, please refer to the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0082] The dielectric layer 105 is an interlayer dielectric (ILD) used to isolate adjacent transistors and also provides a process basis for subsequent formation of source / drain plugs, source / drain cap layers, and gate plugs. The dielectric layer 105 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the dielectric layer 105 is made of silicon oxide.

[0083] As an example, the metal gate structure is formed using a post-formation metal gate last process. Therefore, the dielectric layer 105 includes: a first dielectric layer 103 formed on the substrate 100 exposed by the gate structure 110, with the top of the first dielectric layer 103 flush with the top of the sidewall 120; and a second dielectric layer 104 covering the top of the first dielectric layer 103 and the gate cap layer 130. In other embodiments, depending on the actual process flow, the dielectric layer may also be a single-layer film, meaning that the dielectric layer is formed in the same step.

[0084] Reference Figures 8 to 12 Source / drain plugs 200 are formed on both sides of the gate structure 110, penetrating the dielectric layer 105 and electrically connected to the top of the source / drain doped layer 140. Along the extending direction of the gate structure 110, the source / drain plugs 200 include opposing first ends 200a (e.g., ...). Figure 11 (as shown) and the second end 200b (as shown) Figure 11 As shown), and the source / drain plug 200 includes an adjacent first region 200D (as shown). Figure 11 (as shown) and the second area 200C (as shown) Figure 11 As shown), the second region 200C is located on one side of the first end 200a or on the other side of the second end 200b.

[0085] in, Figures 8 to 10 Based on Figure 9 Cross-sectional view; Figure 11 This is a top view, and for ease of illustration, Figure 11 The dielectric layer is not shown; Figure 12 yes Figure 11 A cross-sectional view at the top of the source / drain plug 200, in a direction perpendicular to the extension direction of the gate structure 110.

[0086] The source / drain plug 200 is used to bring out the electrical properties of the source / drain doped layer 140, thereby realizing the electrical connection between the source / drain doped layer 140 and external circuits or other interconnect structures. For example, the source / drain plug 200 is used to realize the electrical connection between the source / drain doped layer 140 and the first metal interconnect (M1) in the subsequent process.

[0087] In this embodiment, the source / drain plug 200 is an integral structure.

[0088] like Figure 11 As shown, in this embodiment, along the extending direction of the gate structure 110, the source / drain plug 200 includes a first end 200a and a second end 200b, and the source / drain plug 200 includes an adjacent first region 200D and a second region 200C, wherein the second region 200C is located on one side of the first end 200a or on one side of the second end 200b. That is, along the extending direction of the gate structure 110, the second region 200C is located at either end of the source / drain plug 200, and the remaining region is the first region 200D.

[0089] The first region 200D is used to form the source / drain capping layer. Specifically, the first region 200D is the region where the source / drain plug 200 will be etched back, thereby providing space for the subsequent formation of the source / drain capping layer.

[0090] In this embodiment, during the step of forming the source / drain plug 200, the second region 200C of the source / drain plug 200 on one side of the gate structure 110 is located on the side of the first end 200a, and the second region 200C of the source / drain plug 200 on the other side of the gate structure 110 is located on the side of the second end 200b. For the source / drain plugs 200 on both sides of the gate structure 110, by setting the second region 200C at different end positions of the source / drain plug 200, after the source / drain capping layer is subsequently formed in the source / drain plug 200 in the first region 200D, the remaining top of the source / drain plug 200 exposed by the source / drain capping layer is correspondingly located at different end positions of the source / drain plug 200.

[0091] Specifically, a first metal interconnect line for electrically connecting the top of the source-drain plug 200 needs to be formed on the dielectric layer 105. The source and drain of the transistor are electrically connected to different first metal interconnect lines respectively, and the first metal interconnect line electrically connected to the source is parallel to the first metal interconnect line electrically connected to the drain. Correspondingly, the source-drain plug 200 on one side of the gate structure 110 is electrically connected to one first metal interconnect line, and the source-drain plug 200 on the other side of the gate structure 110 is electrically connected to another first metal interconnect line. By setting the second region 200C at different end positions of the source-drain plug 200, the spacing between the first metal interconnect lines electrically connected to the source and drain respectively is increased, thereby providing a larger process window for the subsequent formation of the first metal interconnect line on the top of the source-drain plug 200 exposed by the electrically connected drain cap layer.

[0092] In other embodiments, depending on the actual situation, the second regions of the source and drain plugs on both sides of the gate structure may also be located at the same end position of the source and drain plugs.

[0093] The steps for forming the source / drain plug 200 are described in detail below with reference to the accompanying drawings.

[0094] Reference Figure 8 and Figure 9 A second opening 160 is formed on both sides of the gate structure 110, penetrating the dielectric layer 105 and exposing the top of the source / drain doped layer 140.

[0095] The second opening 160 is used to provide space for the subsequent formation of the source drain plug.

[0096] As an example, along the extending direction of the gate structure 110, the second opening 160 is elongated, and the second opening 160 also exposes the sidewalls of the source / drain doped layers 140 and the top of the isolation layer (not shown) on the side of the source / drain doped layers 140. For example, when the gate structure 110 spans multiple fins 102, the second opening 160 can simultaneously expose each source / drain doped layer 140 between the gate structures 110 and the isolation layer between adjacent fins 102.

[0097] The second opening 160 also exposes the sidewalls of the source / drain doped layer 140, thereby increasing the contact area between the source / drain plug and the source / drain doped layer 140 and reducing the contact resistance. Furthermore, the elongated shape of the second opening 160 corresponds to the elongated shape of the source / drain plug, providing sufficient space for the subsequent source / drain capping layer and ensuring that the length of the capping layer meets process requirements, thus enabling self-alignment during the formation of the gate plug 440.

[0098] Specifically, the steps for forming the second opening 160 include: Figure 8 As shown, a mask layer 150 is formed on the dielectric layer 105, exposing the dielectric layer 105 above the top of the source / drain doped layers 140; as Figure 9 As shown, the dielectric layer 105 is etched using the mask layer 150 as a mask, exposing the source / drain doped layer 140.

[0099] The material of the mask layer 150 is selected to be suitable as an etching mask, that is, there is an etching selectivity between the dielectric layer 105 and the mask layer 150. The material of the mask layer 150 can be a hard mask material or a photoresist. Specifically, the hard mask material is a dielectric material, such as silicon nitride.

[0100] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to etch the dielectric layer 105 to form the second opening 160. The dry etching process has anisotropic etching characteristics, which makes it easier to obtain a better etching profile for the second opening 160.

[0101] As an example, the top opening size of the second opening 160 is larger than its bottom opening size. Specifically, the second opening 160 also exposes a portion of the top of the sidewall 120. The source-drain plug is used to achieve electrical connection with the first metal interconnect. By making the top opening size of the second opening 160 larger than its bottom opening size, the top size of the source-drain plug is increased, thereby reducing the contact resistance between the source-drain plug and the first metal interconnect.

[0102] Specifically, the step of forming the second opening 160 includes: using the gate cap layer 130 as an etch stop layer, etching the dielectric layers 105 on both sides of the gate structure 110.

[0103] A gate cap layer 130 is formed on the top of the gate structure 110. During the etching of the dielectric layer 105, there is an etching selectivity between the dielectric layer 105, the sidewall 120, and the gate cap layer 130. Therefore, the probability of the second opening 160 exposing the gate structure 110 is low, thereby achieving self-aligned etching. This is beneficial for accurately controlling the formation position of the source and drain plugs and makes it easier to increase the top opening size of the second opening 160.

[0104] In this embodiment, after forming the second opening 160, the process further includes removing the mask layer 150. Specifically, the mask layer 150 is removed using a suitable process based on its material. In other embodiments, when the mask layer is made of a dielectric material, it can be retained and removed during the subsequent planarization process for forming the source / drain plugs, thus saving process steps.

[0105] Reference Figures 10 to 12 A source / drain plug 200 is formed in the second opening 160.

[0106] Specifically, such as Figure 10 As shown, the second opening 160 is filled with source / drain plug material 205; as Figure 11 and Figure 12 As shown, the source / drain plug material 205 is planarized by removing the portion of the source / drain plug material 205 above the top of the dielectric layer 105, leaving the remaining source / drain plug material 205 in the second opening 160 as the source / drain plug 200. In this embodiment, a chemical mechanical polishing process is used for the planarization process to achieve global planarization of the source / drain plug material 205.

[0107] In this embodiment, the source / drain plug 200 is made of conductive materials such as cobalt, ruthenium, or tungsten.

[0108] In this embodiment, the second opening 160 also exposes part of the top of the side wall 120, therefore, the source drain plug 200 also covers part of the top of the side wall 120.

[0109] It should be noted that before filling the source / drain plug material 205 into the second opening 160, an adhesion barrier layer (not shown) may be formed on the sidewalls and bottom of the second opening 160. For example, the adhesion barrier layer includes a tantalum nitride layer and a titanium nitride layer covering the tantalum nitride layer. This embodiment will not be described in detail here.

[0110] It should also be noted that the source / drain plug 200 is a single-piece structure, and the distance from the top of the source / drain plug 200 to the top of the source / drain doped layer 140 has reached the target distance. Compared with the current approach of first forming a source / drain interconnect layer whose top is lower than the top of the dielectric layer and electrically connected to the source / drain doped layer, and then forming the source / drain plug on top of the source / drain interconnect layer, this embodiment forms the source / drain plug 200 for electrically leading out the source / drain doped layer 140 in the same step. In other words, this embodiment combines the current steps of forming the source / drain interconnect layer and forming the source / drain plug into the same step, thereby simplifying the process steps.

[0111] Reference Figures 13 to 17 The source drain plug 200 with a portion of its thickness removed from the first region 200D is used to form a first opening 220 in the source drain plug 200.

[0112] The first opening 220 is used to provide space for the subsequent formation of the source leak cap layer.

[0113] It should be noted that the proportion of the depth of the first opening 220 (not indicated) to the total height of the source / drain plug 200 should not be too small or too large. The source / drain capping layer is formed in the first opening 220. If the proportion of the depth of the first opening 220 to the total height of the source / drain plug 200 is too small, the depth of the first opening 220 will be too small, resulting in a correspondingly thin source / drain capping layer. During the subsequent formation of the gate plug, this can easily lead to poor protection of the source / drain plug 200 by the capping layer, and the thickness of the capping layer will be insufficient to achieve self-aligned etching, making it difficult to form the gate plug using the COAG process. If the depth of the first opening 220 is too small, the proportion of the depth of the source / drain plug 200 to the total height of the source / drain plug 200 will be too large. If the proportion of the total height of the source / drain plug 200 is too large, then during the process of removing part of the thickness of the source / drain plug 200 in the first region 200D, the amount of thickness removed from the source / drain plug 200 will be too large. This not only easily leads to an excessive impact on the resistance of the source / drain plug 200 itself, but also easily increases the probability of damage to the gate structure 110 when the bottom of the first opening 220 is lower than the top of the gate cap layer 130 (for example, due to the gate cap layer 130 or the sidewall 120 being accidentally etched, the gate structure 110 is exposed to the etching environment). Therefore, in this embodiment, the depth of the first opening 220 (not shown) is 10% to 50% of the total height of the source / drain plug 200.

[0114] As an example, the bottom of the first opening 220 is lower than or flush with the top of the gate cap layer 130, thereby increasing the distance between the gate plug subsequently formed on the top of the gate structure 110 and the source / drain plug 200 at the bottom of the first opening 220, thereby reducing the probability of short circuit between the gate plug and the source / drain plug 200. Figure 17 This illustrates the situation where the bottom of the first opening 220 is flush with the top of the gate cap layer 130.

[0115] The following, in conjunction with the accompanying drawings, details the steps for removing a portion of the thickness of the source / drain plug 200 in the first region 200D.

[0116] Reference Figure 13 and Figure 14 This forms a shielding layer 210 covering the top of the source / drain plug 200 of the second region 200C.

[0117] in, Figure 13 This is a top view, and for ease of illustration, Figure 13 The dielectric layer is not shown; Figure 14 yes Figure 13 A cross-sectional view at the top of the second region 200C of the source-drain plug 200, in a direction perpendicular to the extension direction of the gate structure 110.

[0118] The shielding layer 210 is used to protect the top of the source / drain plug 200 of the second region 200C, so that a subsequent second opening is formed in the first region 200D.

[0119] The material of the masking layer 210 is selected to be suitable as an etching mask, meaning there is an etching selectivity between the source / drain plugs 200 and the masking layer 210. The material of the masking layer 210 can be a hard mask material or a photoresist. Specifically, the hard mask material is a dielectric material, such as silicon nitride. Specifically, when the material of the masking layer 210 is a hard mask material, a patterned masking layer 210 is formed by using a photoresist material in conjunction with photolithography and etching processes; when the masking layer 210 is a photoresist material, a patterned masking layer 210 is formed by photolithography.

[0120] It should be noted that the masking layer 210 is removed in a separate step. Therefore, when the masking layer 210 is made of dielectric material, the process of removing the masking layer 210 causes less damage to the dielectric layer 105. In other words, there is an etching selectivity between the masking layer 210 and the dielectric layer 105 in the step of removing the masking layer 210.

[0121] In this embodiment, in order to increase the process window for forming the shielding layer 210, the shielding layer 210 also extends to both sides above the top of a portion of the gate structure 110 in a direction perpendicular to the extension direction of the gate structure 110.

[0122] Reference Figures 15 to 17 Using the shielding layer 210 as a mask, a portion of the thickness of the source / drain plug 200 in the first region 200D is etched back to form the first opening 220.

[0123] in, Figure 15 This is a top view, and for ease of illustration, Figure 15 The dielectric layer is not shown; Figure 16 This is a cross-sectional view along the direction of the gate structure at the top of the source / drain plug, and for ease of illustration, only the substrate, source / drain doped layer and source / drain plug are shown. Figure 17 yes Figure 15 A cross-sectional view at the top of the second region 200C of the source-drain plug 200, in a direction perpendicular to the extension direction of the gate structure 110.

[0124] The first opening 220 is formed by etching back, which is highly compatible with current process flows and allows for easy control of the morphology and depth of the first opening 220. In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to etch back a portion of the thickness of the source / drain plug 200 in the first region 200D. The dry etching process has anisotropic etching characteristics, which makes it easy to obtain a better etching profile for the first opening 220 and to easily control the etching depth.

[0125] like Figure 16 As shown, in this embodiment, after etching back a portion of the thickness of the source / drain plug 200 in the first region 200D, the top of the remaining source / drain plug 200 in the first region 200D is lower than the top of the source / drain plug 200 in the second region 200C.

[0126] In this embodiment, after forming the first opening 220, the method further includes removing the shielding layer 210. As an example, the shielding layer 210 is removed before forming the source / drain capping layer in the first opening 220. Specifically, the shielding layer 210 is removed using a suitable process depending on its material. In other embodiments, when the shielding layer is made of a dielectric material, it can be retained and removed during the subsequent planarization process to save process steps.

[0127] Reference Figures 18 to 20 A source / drain capping layer 230 is formed in the first opening 220.

[0128] in, Figure 18 Based on Figure 17 Cross-sectional view, Figure 19 This is a top view, and for ease of illustration, Figure 19 The dielectric layer is not shown; Figure 20 yes Figure 19A cross-sectional view at the top of the second region 200C of the source-drain plug 200, in a direction perpendicular to the extension direction of the gate structure 110.

[0129] The source / drain capping layer 230 covers the top of the remaining source / drain plugs 200 in the first region 200D, providing protection for the top of the source / drain plugs 200 in the first region 200D. Furthermore, during the subsequent formation of the gate plug penetrating the dielectric layer 105 on top of the gate structure 110, a self-aligned etching process is typically used to form a third opening for accommodating the gate plug. The source / drain capping layer 230 also acts as an etching stop layer during the self-aligned etching process, which helps reduce the probability of damage to the source / drain plugs 200 and short circuits between the gate plugs and source / drain plugs 200. In addition, the source / drain capping layer 230 allows the gate plugs to be positioned above the gate structure 110 in the active region, meaning the gate plugs can be formed using a COAG process. These gate plugs are active gate contact plugs. Compared to the scheme where the gate plugs are located above the gate structure in the isolation region, this embodiment eliminates the portion of the gate structure 110 located in the isolation region, saving chip area and further reducing chip size.

[0130] It should be noted that in the current process, a source-drain interconnect layer is usually formed first, with its top lower than the top of the dielectric layer and electrically connected to the source-drain doped layer. A source-drain capping layer is then placed on top of the source-drain interconnect layer. A source-drain plug is then formed that penetrates the source-drain capping layer and is electrically connected to the top of the source-drain interconnect layer. Since the source-drain capping layer needs to be etched during the formation of the source-drain plug, and the gate capping layer needs to be etched during the formation of the gate plug, the etching selectivity between the source-drain capping layer and the gate capping layer is required to be high. It must simultaneously satisfy the following: when etching the source-drain capping layer, the etching rate of the source-drain capping layer is much greater than that of the gate capping layer, and when etching the gate capping layer, the etching rate of the gate capping layer is much greater than that of the source-drain capping layer. In this embodiment, the source / drain plug 200 is formed before the source / drain capping layer 230 is formed. That is, there is no step of etching the source / drain capping layer 230 during the formation of the source / drain plug 200. Therefore, this reduces the requirement for the etching selectivity ratio between the source / drain capping layer 230 and the gate capping layer 130. For example, it is only necessary to meet the requirement that the etching rate of the gate capping layer 130 is greater than the etching rate of the source / drain capping layer 230 when etching the gate capping layer 130, without having to consider the etching selectivity ratio between the source / drain capping layer 230 and the gate capping layer 130 when etching the source / drain capping layer 230, thereby reducing the process difficulty.

[0131] Moreover, in this embodiment, the source / drain plug 200 is formed only once. After the source / drain plug 200 is formed, space is reserved for the formation of the source / drain cap layer 230 by removing part of the thickness of the source / drain plug 200 in the first region 200D. This simplifies the process steps and also helps to reduce the difficulty of the process.

[0132] In summary, this embodiment simplifies the process steps and reduces the process difficulty while ensuring that the gate plug can be formed using the COAG process.

[0133] It should be noted that in this embodiment, the thickness of the source / drain capping layer 230 is greater than that of the gate capping layer 130. Therefore, even if the source / drain capping layer 230 and the gate capping layer 130 are made of the same material, the probability of the source / drain capping layer 230 being completely consumed during the formation of the gate plug is low, and the source / drain capping layer 230 can still play its corresponding role. Therefore, the source / drain capping layer 230 and the gate capping layer 130 can be made of the same material or different materials, allowing for greater process flexibility. The material of the source / drain capping layer 230 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the source / drain capping layer 230 and the gate capping layer 130 are made of different materials to ensure an etching selectivity ratio between them and reduce process risk. For example, the material of the source / drain capping layer 230 is silicon carbide.

[0134] Specifically, the steps for forming the source / drain cap layer 230 include: Figure 18 As shown, the source leak cap material 235 is filled into the first opening 220; as Figure 19 and Figure 20 As shown, the source / drain cap material 235 is planarized, and the source / drain cap material 235 above the top of the dielectric layer 105 is removed, while the remaining source / drain cap material 235 in the first opening 220 is retained as the source / drain cap layer 230.

[0135] In this embodiment, one or more of atomic layer deposition, chemical vapor deposition, and spin coating processes are used to fill the first opening 220 with source / drain capping material 235 to achieve a better filling effect and high compatibility with current processes. In this embodiment, chemical mechanical polishing is used to remove the source / drain capping material 235 above the top of the dielectric layer 105 to achieve global planarization of the source / drain capping material 235.

[0136] In other embodiments, when the shielding layer is made of a dielectric material, the shielding layer is removed simultaneously during the planarization process of forming the source / drain cap layer, thus saving process steps. Both the shielding layer and the drain cap material are inorganic, making it easy to planarize both simultaneously, resulting in high process compatibility.

[0137] In this embodiment, the source / drain capping layer 230 is also located in the dielectric layer 105, and the top of the source / drain capping layer 230 is flush with the top of the source / drain plug 200 in the second region 200C. Furthermore, in this embodiment, the source / drain capping layer 230 exposes the top of the source / drain plug 200 in the second region 200C, so that the source / drain plug 200 can achieve electrical connection between the source / drain doped layer 140 and external circuits or other interconnect structures.

[0138] Reference Figures 21 to 22 A gate plug 240 is formed in the dielectric layer 105 between the source and drain cap layers 230. The gate plug 240 penetrates the dielectric layer 105 at the top of the gate structure 110 and is electrically connected to the top of the gate structure 110.

[0139] in, Figure 21 This is a top view, and for ease of illustration, Figure 21 The dielectric layer is not shown; Figure 22 yes Figure 21 A cross-sectional view at the top of the gate plug 240, in a direction perpendicular to the extending direction of the gate structure 110.

[0140] The gate plug 240 is used to bring out the electrical properties of the gate structure 110, thereby realizing the electrical connection between the gate structure 110 and external circuits or other interconnect structures. For example, the gate plug 240 is used to realize the electrical connection between the gate structure 110 and the first metal interconnect (M1) in the back-end process. In this embodiment, the material of the gate plug 240 includes conductive materials such as tungsten, ruthenium, or cobalt.

[0141] Specifically, the steps for forming the gate plug 240 include: using the source / drain cap layer 230 as an etch stop layer, etching the dielectric layer 105 at the top of the gate structure 110 to form a third opening (not shown) that penetrates the dielectric layer 105 and exposes the top of the gate structure 110; and forming the gate plug 240 in the third opening. The steps for forming the gate plug 240 are similar to those for forming the source / drain plug 200, and will not be described again here.

[0142] It should be noted that a gate cap layer 130 is also formed on the top of the gate structure 110. Therefore, in the step of forming the gate plug 240, the gate plug 240 also penetrates the gate cap layer 130 in the vertical direction. Here, vertical direction refers to the height direction of the gate structure 110. Correspondingly, in the process of forming the third opening, after etching the dielectric layer 105 on the top of the gate structure 110, the gate cap layer 130 is further etched vertically to expose the top of the gate structure 110.

[0143] It should also be noted that the second region 200C is located on one side of the first end 200a of the source-drain plug 200 or on one side of the second end 200b, and the source-drain cap layer 230 is exposed on the top of the source-drain plug 200 in the second region 200C. That is, the source-drain plug 200 exposed by the source-drain cap layer 230 is located at the end of the source-drain plug 200, while the gate plug 240 is located between the source-drain cap layers 230 and penetrates the dielectric layer 105 on the top of the gate structure 110. Therefore, the distance between the gate plug 240 and the source-drain plug 200 in the second region 200C is relatively large, and the probability of short-circuiting between the gate plug 240 and the source-drain plug 200 is correspondingly low.

[0144] Furthermore, in this embodiment, the electrical properties of the source / drain doped layer 140 and the gate structure 110 are brought out before the back-end process. Therefore, it is not necessary to use a dual damascene process to form the first metal interconnect, nor is it necessary to form a via interconnect structure at the bottom of the first metal interconnect. This simplifies the process steps for forming the first metal interconnect and has little impact on the traditional back-end process. The semiconductor structure formation method is highly compatible with traditional process flows.

[0145] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a gate structure on the substrate; a source-drain doped layer in the substrate on both sides of the gate structure; a dielectric layer on the substrate covering the top of the gate structure and the top of the source-drain doped layer; a source-drain plug penetrating the dielectric layer on both sides of the gate structure and electrically connected to the top of the source-drain doped layer, the source-drain plug comprising opposite first and second ends along the extension direction of the gate structure, and the source-drain plug comprising adjacent first and second regions, the second region being on one side of the first end or on one side of the second end, the top of the source-drain plug in the first region being lower than the top of the source-drain plug in the second region; a source-drain cap layer on the top of the source-drain plug in the first region and covering the sidewall of the source-drain plug in the second region; a gate plug between the source-drain cap layers and penetrating the dielectric layer on the top of the gate structure, the gate plug being electrically connected to the top of the gate structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a gate cap layer on the top of the gate structure. The gate plug longitudinally penetrates the dielectric layer on the top of the gate structure and the gate cap layer.

3. The semiconductor structure of claim 1, wherein, The second region of the source-drain plug on one side of the gate structure is on one side of the first end, and the second region of the source-drain plug on the other side of the gate structure is on one side of the second end.

4. The semiconductor structure of claim 1, wherein, The shape of the source-drain plug along the extension direction of the gate structure is a long strip, and the source-drain plug covers the top and sidewall of the source-drain doped layer.

5. The semiconductor structure of claim 1, wherein, The top size of the source-drain plug is greater than the bottom size of the source-drain plug.

6. The semiconductor structure of claim 1, wherein, The distance from the top of the source-drain plug in the second region to the top of the source-drain plug in the first region is 10% to 50% of the total height of the source-drain plug.

7. The semiconductor structure of claim 2, wherein, The top of the source-drain plug in the first region is lower than or flush with the top of the gate cap layer.

8. The semiconductor structure of claim 1, wherein, The material of the source-drain cap layer comprises one or more of silicon oxide, silicon nitride, aluminum oxide, titanium oxide, carbon-doped silicon nitride, carbon-doped silicon oxide, and silicon carbide.

9. The semiconductor structure of claim 1, wherein, The material of the source-drain plug comprises tungsten, cobalt, or ruthenium, and the material of the gate plug comprises tungsten, cobalt, or ruthenium.

10. The semiconductor structure of claim 2, wherein, The material of the gate cap layer comprises one or more of silicon oxide, silicon nitride, aluminum oxide, titanium oxide, carbon-doped silicon nitride, carbon-doped silicon oxide, and silicon carbide.

11. The semiconductor structure of claim 1, wherein, The gate structure comprises a metal gate structure.

12. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: providing a substrate, a gate structure being formed on the substrate, a source-drain doped layer being formed in the substrate on both sides of the gate structure, and a dielectric layer being formed on the substrate covering the top of the gate structure and the top of the source-drain doped layer; forming a source-drain plug on both sides of the gate structure penetrating the dielectric layer and electrically connected to the top of the source-drain doped layer, the source-drain plug comprising opposite first and second ends along the extension direction of the gate structure, and the source-drain plug comprising adjacent first and second regions, the second region being on one side of the first end or on one side of the second end; removing part of the thickness of the source-drain plug in the first region to form a first opening in the source-drain plug; forming a source-drain cap layer in the first opening; forming gate plugs in the dielectric layer between the source / drain cap layers, the gate plugs penetrating the dielectric layer on top of the gate structure and electrically connecting with the top of the gate structure.

13. The method of forming a semiconductor structure of claim 12, wherein, forming source / drain plugs in the dielectric layer on both sides of the gate structure and electrically connecting with the top of the source / drain doped layer includes: forming second openings in the dielectric layer on both sides of the gate structure and exposing the top of the source / drain doped layer; forming source / drain plugs in the second openings.

14. The method of forming a semiconductor structure of claim 13, wherein, forming source / drain plugs in the second openings includes: filling source / drain plug material in the second openings; planarizing the source / drain plug material, removing the source / drain plug material above the top of the dielectric layer, and leaving the remaining source / drain plug material in the second openings as source / drain plugs.

15. The method of forming a semiconductor structure of claim 13, wherein, in the step of providing the substrate, a gate cap layer is also formed on top of the gate structure; forming the second openings includes etching the dielectric layer on both sides of the gate structure with the gate cap layer as an etching stop layer; in the step of forming gate plugs in the dielectric layer between the source / drain cap layers, the gate plugs also penetrate the gate cap layer in the longitudinal direction.

16. The method of forming a semiconductor structure of claim 12, wherein, the step of removing a partial thickness of the source / drain plugs in the first region includes forming a shielding layer covering the top of the source / drain plugs in the second region, and etching back the source / drain plugs in the first region with the shielding layer as a mask; the forming method further includes removing the shielding layer.

17. The method of forming a semiconductor structure of claim 16, wherein, the shielding layer is removed before forming the source / drain cap layers in the first openings; alternatively, the shielding layer is removed during the process of forming the source / drain cap layers in the first openings.

18. The method of forming a semiconductor structure of claim 12, wherein, the step of removing a partial thickness of the source / drain plugs in the first region includes etching back the source / drain plugs in the first region using a dry etching process.

19. The method of forming a semiconductor structure of claim 12, wherein, the step of forming source / drain cap layers in the first openings includes: filling source / drain cap material in the first openings; planarizing the source / drain cap material, removing the source / drain cap material above the top of the dielectric layer, and leaving the remaining source / drain cap material in the first openings as source / drain cap layers.

20. The method of forming a semiconductor structure of claim 19, wherein, the source / drain cap material is formed using one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin coating process.

21. The method of forming a semiconductor structure of claim 13, wherein, in the step of forming gate plugs in the dielectric layer between the source / drain cap layers includes: etching the dielectric layer on top of the gate structure with the source / drain cap layers as etching stop layers, forming third openings penetrating the dielectric layer and exposing the gate structure; forming gate plugs in the third openings.

22. The method of forming a semiconductor structure of claim 13, wherein, in the step of forming the source / drain plugs, the second region of the source / drain plug on one side of the gate structure is located on one side of the first end, and the second region of the source / drain plug on the other side of the gate structure is located on one side of the second end.

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