Method for improving wafer warpage

Abstract

The present invention provides a method for improving wafer warpage, comprising: providing a wafer having positioning marks, the wafer including multiple semiconductor device structures, wherein the openings of the positioning marks are calibrated in a first direction, and a direction perpendicular to the first direction is a second direction; and forming at least one contact hole field plate above the semiconductor device structures, wherein the contact hole field plate is strip-shaped and extends along the second direction. This method solves the existing problem of wafer warpage in a specific direction being significantly increased due to the stress of the contact hole field plate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for improving wafer warpage. Background Art

[0002] Field plates can be used to reduce peak electric fields and improve the withstand voltage performance of semiconductor devices. Therefore, they are widely used in LDMOS (laterally diffused metal oxide semiconductor) integration processes. However, the strip contact hole (CT) field plate structure used in the LDMOS integration process is directional. After metal filling, the increase in wafer warpage in the second direction (the direction perpendicular to the opening calibration direction of the wafer positioning mark) is significantly greater than the increase in the first direction (the opening calibration direction of the wafer positioning mark). In addition, the warpage in the second direction of the wafer is already greater than the warpage in the first direction when it leaves the factory. The superposition of warpage in the same direction leads to a significant increase in wafer warpage, which affects the wafer's lithography accuracy and may even cause insufficient suction force on the wafer during operation, making lithography impossible. Summary of the Invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving wafer warpage, so as to solve the problem that the warpage of the prior art wafer in a specific direction increases significantly due to the stress of the contact hole field plate.

[0004] To achieve the above objectives and other related objectives, the present invention provides a method for improving wafer warpage, the method comprising:

[0005] Providing a wafer with a positioning mark, the wafer comprising a plurality of semiconductor device structures, wherein an opening marking direction of the positioning mark is a first direction, and a direction perpendicular to the first direction is a second direction;

[0006] At least one contact hole field plate is formed above the semiconductor device structure, wherein the contact hole field plate is in a strip shape and extends along the second direction.

[0007] Optionally, the width of the upper end of the cross section of the contact hole field plate is greater than the width of the lower end thereof.

[0008] Optionally, when there are multiple contact hole field plates, the multiple contact hole field plates are arranged at intervals.

[0009] Optionally, the contact hole field plate is formed by filling tungsten or a compound thereof.

[0010] Optionally, the method further includes forming a contact hole above the semiconductor structure, and the contact hole is trench-shaped.

[0011] Optionally, the contact trench of the contact hole is parallel to the field plate trench of the contact hole field plate.

[0012] Optionally, the semiconductor structure includes a substrate, a body region and a drift region formed in the substrate, a source region formed in the body region, a drain region formed in the drift region, and a gate structure formed above the substrate.

[0013] Optionally, the contact hole field plate is formed above the drift region and is located between the gate structure and the drain region.

[0014] Optionally, the contact hole is formed above the source region, the drain region and the gate structure.

[0015] As described above, the present invention provides a method for improving wafer warpage, which extends the contact hole field plate and the contact hole in the second direction of the wafer (a direction perpendicular to the opening calibration direction of the wafer positioning mark) so that the direction of the maximum stress generated by the contact hole field plate is perpendicular to the direction (the second direction) where the maximum wafer warpage is located, thereby reducing the increase in the wafer warpage in the first direction, thereby achieving the purpose of improving the wafer warpage.

[0016] Component number description

[0017] 10 Semiconductor Structure

[0018] 11 substrate

[0019] 12 body zones

[0020] 13 Drift Zone

[0021] 14 Source area

[0022] 15 Drain area

[0023] 16 Gate structure

[0024] 20 Contact hole field plate

[0025] 21 Field plate groove

[0026] 30 interlayer dielectric layer

[0027] 31 First Oxide Layer

[0028] 32 Second oxide layer

[0029] 33 Nitride layer

[0030] 34 Third Oxide Layer

[0031] 40 contact holes

[0032] 41 contact groove BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a flow chart of the method for improving wafer warpage of the present invention.

[0034] Figure 2 Shown is a schematic diagram of a semiconductor structure formed in a wafer according to the present invention.

[0035] Figure 3 It is a schematic diagram of a semiconductor structure with a contact hole field plate according to the present invention.

[0036] Figure 4 Shown is a schematic diagram of an existing contact hole field plate setting method.

[0037] Figure 5 Shown is a schematic diagram of the contact hole field plate arrangement method of the present invention. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0040] like Figure 1 As shown, this embodiment provides a method for improving wafer warpage, the method comprising:

[0041] 1) Providing a wafer with positioning marks, the wafer including a plurality of semiconductor device structures 10, wherein the opening marking direction of the positioning marks is a first direction, and a direction perpendicular to the first direction is a second direction;

[0042] 2) forming at least one contact hole field plate 20 above the semiconductor device structure 10 , wherein the contact hole field plate 20 is strip-shaped and extends along the second direction.

[0043] The method for improving wafer warpage provided by this embodiment will be described below.

[0044] Step 1) providing a wafer with positioning marks, wherein the wafer includes a plurality of semiconductor device structures 10, wherein the opening of the positioning marks is oriented in a first direction, and a direction perpendicular to the first direction is a second direction.

[0045] In this embodiment, the positioning mark includes a positioning notch, which is triangular and has an opening located at the edge of the wafer. Moreover, due to process reasons when the wafer is shipped, the warpage of the wafer in the second direction is greater than the warpage of the wafer in the first direction.

[0046] As an example, the semiconductor structure 10 includes a substrate 11, a body region 12 and a drift region 13 formed in the substrate, a source region 14 formed in the body region, a drain region 15 formed in the drift region, and a gate structure 16 formed above the substrate 11 (e.g., Figure 2 shown).

[0047] In this embodiment, the body region 12, the drift region 13, the source region 14, and the drain region 15 are all formed by an ion implantation process. The gate structure 16 includes a gate dielectric layer (not shown), a polysilicon gate formed above the gate dielectric layer, and sidewalls formed on both sides of the gate dielectric layer and the polysilicon gate. In this embodiment, the substrate 11 includes, but is not limited to, a silicon substrate.

[0048] Step 2) forming at least one contact hole field plate 20 above the semiconductor device structure 10 , wherein the contact hole field plate 20 is strip-shaped and extends along the second direction.

[0049] As an example, the contact hole field plate 20 is formed by filling tungsten or a compound thereof.

[0050] like Figure 3 As shown, the method for preparing the contact hole field plate 20 in this embodiment is as follows: an interlayer dielectric layer 30 is formed on the upper surface of the semiconductor structure 10, the interlayer dielectric layer including a first oxide layer 31, a second oxide layer 32 and a nitride layer 33, and the nitride layer 33 is disposed between the first oxide layer 31 and the second oxide layer 32; the interlayer dielectric layer 30 is etched to a preset depth based on a pattern mask layer to form a field plate trench 21, and a dry etching process or a wet etching process can be used for etching; a third oxide layer 34 is deposited as a mask layer in the unetched area of the upper surface of the interlayer dielectric layer 30 to protect the unetched area of the interlayer dielectric layer 30; then, the field plate trench 21 is filled with metal tungsten or its compound by deposition and chemical mechanical polishing is performed to form the contact hole field plate 20. Optionally, in this embodiment, a dry etching process is selected to etch the interlayer dielectric layer 30, and the contact hole field plate 20 is formed by filling the metal tungsten.

[0051] As an example, the width of the upper end of the cross section of the contact hole field plate 20 is greater than the width of the lower end thereof.

[0052] As an example, when there are multiple contact hole field plates 20 , the multiple contact hole field plates 20 are arranged at intervals.

[0053] As an example, the contact hole field plate 20 is formed above the drift region 13 and located between the gate structure 16 and the drain region 15 .

[0054] As an example, the method further includes forming a contact hole 40 above the semiconductor structure 10 , wherein the contact hole is in a trench shape.

[0055] As an example, the contact trench 41 of the contact hole 40 is parallel to the field plate trench 21 of the contact hole field plate 20 .

[0056] In this embodiment, the contact trench 41 of the contact hole 40 has the same shape as the field plate trench 21 of the contact hole field plate 20. Therefore, the two can be prepared at the same time. Of course, they can also be prepared separately, which has no effect on this embodiment. From the perspective of saving process costs, optionally, this embodiment chooses to prepare the contact hole 40 and the contact hole field plate 20 at the same time. When preparing the contact hole 40, the interlayer dielectric layer 30 formed on the semiconductor structure 10 is etched based on the graphic mask layer until the source region 14, the drain region 15 and the gate structure 16 are leaked, thereby forming the contact trench 41. After the contact trench 41 is filled, the contact hole 40 is formed to achieve connection with the source region 14, the drain region 15 and the gate structure 16. In this embodiment, the material filled in the contact trench 41 is metal tungsten.

[0057] The effect of the method for improving wafer warpage provided by this embodiment is described below.

[0058] Figure 4 An existing contact hole field plate setting method is shown, wherein the first direction is the same as the extension direction of the contact hole field plate. In this case, the first direction is the Y coordinate direction and the second direction is the X coordinate direction.

[0059] Figure 5 The contact hole field plate arrangement method of this embodiment is shown, wherein the first direction is perpendicular to the extension direction of the contact hole field plate. In this case, the first direction is the X coordinate direction and the second direction is the Y coordinate direction.

[0060] Table 1 shows the measured values of wafer warpage, where BSL represents the existing contact hole field plate setting method, notch rotated 90° represents the contact hole field plate setting method provided by this embodiment (wafer rotated 90°), and light sheet represents the wafer not being operated. As can be seen from the table, when the wafer is a light sheet, the maximum warpage is 42.77μm, and in the second direction (X coordinate direction); when the wafer is not rotated 90° ( Figure 4 (As shown in the arrangement), after the contact hole field plate is formed through the chemical mechanical polishing process, the maximum warpage is 161.82 μm, and in the second direction (X coordinate direction), at this time, the direction of the maximum stress generated by the contact hole field plate is consistent with the direction of the maximum warpage; when the notch is rotated 90° ( Figure 5 (The setting shown in the figure) After the contact hole field plate is formed by the chemical mechanical polishing process, the maximum warpage is 114.28μm, and in the second direction (Y coordinate direction), at this time, the direction of the maximum stress generated by the contact hole field plate is perpendicular to the direction of the maximum wafer warpage. The stress of the contact hole field plate will cause the wafer warpage to increase sharply. Therefore, the situation where the maximum stress direction is perpendicular to the direction of the maximum wafer warpage is compared with the situation where the direction is the same as the direction of the maximum wafer warpage. The increase in wafer warpage is much smaller. It can be seen that when the notch is rotated 90°, not only the maximum value of the wafer warpage is reduced by 47.54μm, but also the increase in wafer warpage is reduced, thereby effectively improving the warpage of the wafer.

[0061] Table 1:

[0062]

[0063] In summary, the present invention provides a method for improving wafer warpage by extending the contact hole field plate and contact hole in the second direction of the wafer (a direction perpendicular to the opening direction of the wafer positioning notch). This allows the direction of maximum stress generated by the contact hole field plate to be perpendicular to the direction of maximum wafer warpage (the second direction), thereby reducing the increase in wafer warpage in the first direction and achieving the purpose of improving wafer warpage. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving wafer warpage, characterized in that: The method comprises: Providing a wafer with a positioning mark, the wafer comprising a plurality of semiconductor device structures, wherein an opening marking direction of the positioning mark is a first direction, and a direction perpendicular to the first direction is a second direction; At least one contact hole field plate is formed above the semiconductor device structure, wherein the contact hole field plate is in a strip shape and extends along the second direction.

2. The method for improving wafer warpage according to claim 1, wherein: The width of the upper end of the cross section of the contact hole field plate is greater than the width of the lower end thereof.

3. The method for improving wafer warpage according to claim 1, wherein: When there are multiple contact hole field plates, the multiple contact hole field plates are arranged at intervals.

4. The method for improving wafer warpage according to claim 1, wherein: The contact hole field plate is formed by filling tungsten or a compound thereof.

5. The method for improving wafer warpage according to claim 1, wherein: The method further includes forming a contact hole above the semiconductor device structure, wherein the contact hole is in a trench shape.

6. The method for improving wafer warpage according to claim 5, wherein: The contact trench of the contact hole is parallel to the field plate trench of the contact hole field plate.

7. The method for improving wafer warpage according to any one of claims 1 to 6, wherein: The semiconductor device structure includes a substrate, a body region and a drift region formed in the substrate, a source region formed in the body region, a drain region formed in the drift region, and a gate structure formed above the substrate.

8. The method for improving wafer warpage according to claim 7, wherein: The contact hole field plate is formed above the drift region and is located between the gate structure and the drain region.

9. The method for improving wafer warpage according to claim 7, wherein: The contact hole is formed above the source region, the drain region and the gate structure.

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