A method of manufacturing a semiconductor device
By depositing and removing the sacrificial film layer before the bit line contact plug is formed, the problem of linewidth reduction at the bit line contact plug is solved, and the stability and reliability of the bit line are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-03-11
- Publication Date
- 2026-04-24
AI Technical Summary
In the manufacturing of bit line contact plugs, existing technology causes the bit line width to be reduced at the contact plug, resulting in adverse phenomena such as increased bit line resistance or breakage.
Before forming bit line contact plugs, a sacrificial film layer is deposited on the substrate surface and removed after the bit line contact plug pattern is formed to ensure that the bit line contact plugs are flush with other locations on the substrate and to prevent the bit line sides from being etched.
It effectively prevents the line width of the bit line from shrinking at the bit line contact plug, avoids the bit line resistance from increasing or breaking, and improves the reliability of the manufacturing process.
Smart Images

Figure CN115084032B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology
[0002] In memories such as dynamic random access memory (DRAM), bit lines and bit line contacts are crucial structures. Bit lines are electrically connected to the source of transistors via bit line contacts to enable read and write operations. Currently, during the manufacturing of bit line contacts and bit lines, due to the characteristics of the manufacturing process, over-etching is necessary to completely separate the bit line contact nodes, resulting in a relatively low height of the bit line contact relative to other locations. Subsequently, when depositing the bit line material layer, the height of the bit line material layer at the bit line contact is also low. During the subsequent etching of the bit line material layer to form the bit line, the low height of the bit line material layer at the bit line contact causes the sides of the bit line at the bit line contact to be etched, leading to a reduction in the linewidth of the bit line at the bit line contact, resulting in increased bit line resistance or bit line breakage, among other undesirable phenomena. Summary of the Invention
[0003] This invention provides a method for manufacturing a semiconductor device to prevent the linewidth reduction of bit lines at bit line contact plugs, and to prevent adverse phenomena such as increased bit line resistance or bit line breakage.
[0004] The present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; depositing a sacrificial film layer on the substrate; forming a bit line contact plug pattern in the sacrificial film layer and the substrate, wherein the bit line contact plug pattern includes a plurality of bit line contact plugs; removing the sacrificial film layer; and forming a bit line pattern on the substrate, wherein the bit line pattern includes a plurality of bit lines, and each bit line contact plug contacts a bit line.
[0005] In the above scheme, a sacrificial film layer is deposited on the substrate surface before forming the bit line contact plug pattern; after forming the bit line contact plug pattern, the sacrificial film layer is removed. This prevents the height of the bit line contact plug from being lower than other positions on the substrate, eliminates the height difference between the bit line contact plug and other positions on the substrate, and makes the height of the bit line contact plug flush with the height of other positions on the substrate. Therefore, during subsequent bit line pattern formation, it can prevent the sides of the bit lines at the bit line contact plug from being etched, prevent the linewidth reduction of the bit lines at the bit line contact plug, and prevent adverse phenomena such as increased bit line resistance or bit line breakage.
[0006] In one specific embodiment, forming a bit line contact plug pattern in the sacrificial film layer and the substrate includes: sequentially etching the sacrificial film layer and the substrate from top to bottom; forming a bit line contact hole pattern in the substrate and the sacrificial film layer, wherein the bit line contact hole pattern includes a plurality of bit line contact holes; and forming a bit line contact plug pattern in the bit line contact hole pattern, wherein the bit line contact plug pattern includes a bit line contact plug filling each bit line contact hole. This facilitates the formation of the bit line contact plug pattern.
[0007] In one specific embodiment, forming a bit line contact plug pattern in a bit line contact hole pattern includes: filling the bit line contact hole pattern with bit line contact plug material to completely fill the bit line contact hole pattern, and forming a bit line contact plug material layer on the surface of the sacrificial film layer; removing the bit line contact plug material layer formed on the surface of the sacrificial film layer to obtain a bit line contact plug pattern formed in the bit line contact hole pattern. This facilitates the formation of a bit line contact plug pattern in the bit line contact hole pattern.
[0008] In one specific embodiment, before forming the sacrificial film layer on the substrate, the manufacturing method further includes: depositing a first barrier layer on the substrate, wherein the sacrificial film layer is deposited on the first barrier layer. Etching the sacrificial film layer and the substrate sequentially from top to bottom to form a bit line contact hole pattern in the substrate and the sacrificial film layer includes: sequentially etching the sacrificial film layer, the first barrier layer, and the substrate from top to bottom, thereby forming a bit line contact hole pattern in the substrate, the first barrier layer, and the sacrificial film layer. The first barrier layer protects the substrate, preventing damage to the substrate surface during the etching of the sacrificial film layer.
[0009] In one specific embodiment, forming a bitline pattern on a substrate includes: depositing a bitline material layer on the substrate and a bitline contact plug pattern; depositing a second barrier layer on the bitline material layer; and sequentially etching the second barrier layer and the bitline material layer from top to bottom to form a bitline pattern on the substrate. This facilitates the formation of the bitline pattern.
[0010] In one specific implementation, the thickness of the sacrificial film layer is 5nm~100nm, so that the height of the bit line contact plug can be aligned with the height of other locations on the substrate by adjusting the thickness of the sacrificial film layer.
[0011] In one specific implementation, the sacrificial film is made of an oxide or metal material to facilitate subsequent removal of the sacrificial film.
[0012] In one specific implementation, the material of the sacrificial film is titanium nitride, aluminum, or tungsten.
[0013] In one specific embodiment, removing the sacrificial film layer includes: removing the sacrificial film layer by wet etching or dry etching, so as to facilitate the removal of the sacrificial film layer.
[0014] In one specific embodiment, when the sacrificial film is made of an oxide, removing the sacrificial film using wet etching includes: etching the sacrificial film with hydrofluoric acid to remove it. When the sacrificial film is made of a metal, removing the sacrificial film using wet etching includes: etching the sacrificial film with hydrogen peroxide to remove it. This improves the effectiveness and efficiency of wet etching. Attached Figure Description
[0015] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0016] Figure 2 A cross-sectional schematic diagram of one step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0017] Figure 3 A cross-sectional schematic diagram illustrating another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0018] Figure 4 A cross-sectional schematic diagram illustrating another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0019] Figure 5 A cross-sectional schematic diagram illustrating another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0020] Figure 6 A cross-sectional schematic diagram illustrating another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0021] Figure 7 The semiconductor device is manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0022] Figure label:
[0023] 10-Substrate 20-Sacrificial membrane layer 30-Substrate contact plug
[0024] 31 - Position line contact hole; 32 - Position line contact plug material layer
[0025] 40-bit line 51-first barrier layer 52-second barrier layer Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0027] To facilitate understanding of the semiconductor device manufacturing method provided in this embodiment of the invention, the application scenario of the manufacturing method provided in this embodiment of the invention is first described below. This manufacturing method is used to manufacture semiconductor devices, wherein the semiconductor device can be any memory including bit line contacts and bit lines. For example, the semiconductor device can be DRAM (Dynamic Random Access Memory) including bit line contacts and bit lines. The manufacturing method of the semiconductor device will now be described in detail with reference to the accompanying drawings.
[0028] refer to Figures 1-7 The manufacturing method provided in this embodiment of the invention includes:
[0029] S10: Provides a substrate 10;
[0030] S20: Deposit sacrificial film layer 20 on substrate 10;
[0031] S30: A pattern of bit line contact plugs 30 is formed in the sacrificial film layer 20 and the substrate 10, wherein the pattern of bit line contact plugs 30 includes a plurality of bit line contact plugs 30.
[0032] S40: Remove sacrificial film layer 20;
[0033] S50: A bit line 40 pattern is formed on the substrate 10, wherein the bit line 40 pattern includes multiple bit lines 40, and each bit line contact plug 30 contacts a bit line 40.
[0034] In the above scheme, a sacrificial film layer 20 is deposited on the surface of the substrate 10 before forming the bit line contact plug 30 pattern; after forming the bit line contact plug 30 pattern, the sacrificial film layer 20 is removed, thereby preventing the bit line contact plug 30 from being lower in height than other positions on the substrate 10, eliminating the height difference between the bit line contact plug 30 and other positions on the substrate 10, and making the height of the bit line contact plug 30 flush with the height of other positions on the substrate 10. Therefore, during the subsequent formation of the bit line 40 pattern, it is possible to prevent the side of the bit line 40 at the bit line contact plug 30 from being etched, to prevent the linewidth of the bit line 40 from shrinking at the bit line contact plug 30, and to prevent defects such as increased resistance or breakage of the bit line 40. The following will use the bit line contact formation method in DRAM manufacturing as an example to describe each of the above steps in detail with reference to the accompanying drawings.
[0035] First, refer to Figure 2 A substrate 10 is provided. The substrate 10 can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate or a polycrystalline silicon substrate. The substrate 10 can also be a stacked structure with partially formed semiconductor structures. For example, the substrate 10 can include at least a semiconductor substrate 10, transistors, and word lines. Transistors can be formed in the semiconductor substrate 10 of the semiconductor device, and word lines can be formed above the transistors. For DRAM, source and drain doping can be performed in the substrate 10, and buried gates can be formed, thereby constituting a buried channel array transistor.
[0036] Next, continue to refer to Figure 2 A sacrificial film layer 20 is deposited on the substrate 10. The thickness of the sacrificial film layer 20 can be from 5 nm to 100 nm. Specifically, the thickness can be any value between 5 nm and 100 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or 100 nm. This allows for adjusting the thickness of the sacrificial film layer 20 to ensure that the height of the bit line contact plug 30 is flush with the height of other locations on the substrate 10. The material of the sacrificial film layer 20 can be an oxide or a metal to facilitate subsequent removal. The material of the sacrificial film layer 20 can be titanium nitride, aluminum, or tungsten.
[0037] In addition, continue to refer to Figure 2Before forming the sacrificial film layer 20 on the substrate 10, a first barrier layer 51 can be deposited on the substrate 10, allowing the sacrificial film layer 20 to be deposited on the first barrier layer 51. Specifically, the material of the first barrier layer 51 can be silicon nitride. The first barrier layer 51 protects the substrate 10, preventing damage to the surface of the substrate 10 during subsequent etching of the sacrificial film layer 20.
[0038] Next, refer to Figures 3-5 A pattern of bit line contact plugs 30 is formed in the sacrificial film layer 20 and the substrate 10, wherein the pattern of bit line contact plugs 30 includes multiple bit line contact plugs 30. During processing, a pattern of bit line contact holes 31 can be formed on the substrate 10 first, and then the pattern of bit line contact plugs 30 can be formed within the pattern of bit line contact holes 31. For details, refer to... Figure 3 The sacrificial film layer 20 and the substrate 10 can be etched sequentially from top to bottom to form a bit line contact hole 31 pattern in the substrate 10 and the sacrificial film layer 20. The bit line contact hole 31 pattern includes multiple bit line contact holes 31. Then, refer to... Figures 4-5 A bit line contact plug 30 pattern is formed in the bit line contact hole 31 pattern, wherein the bit line contact plug 30 pattern includes bit line contact plugs 30 filling each bit line contact hole 31. This facilitates the formation of the bit line contact plug 30 pattern. Of course, if a first barrier layer 51 is deposited between the sacrificial film layer 20 and the substrate 10, when etching to form the bit line contact hole 31 pattern, the sacrificial film layer 20, the first barrier layer 51, and the substrate 10 need to be etched sequentially from top to bottom to form the bit line contact hole 31 pattern in the substrate 10, the first barrier layer 51, and the sacrificial film layer 20.
[0039] When forming the bit line contact plug 30 pattern in the bit line contact hole 31 pattern, refer to Figure 4 First, bit line contact plug 30 material can be filled into the bit line contact hole 31 pattern to completely fill the bit line contact hole 31 pattern, and then a bit line contact plug material layer 32 can be formed on the surface of the sacrificial film layer 20. This bit line contact plug 30 material can be polysilicon. Then, refer to... Figure 5 The bit line contact plug material layer 32 formed on the surface of the sacrificial film layer 20 is removed to obtain a bit line contact plug 30 pattern formed in the bit line contact hole 31 pattern. This facilitates the formation of the bit line contact plug 30 pattern in the bit line contact hole 31 pattern. Specifically, the bit line contact plug material layer 32 formed on the surface of the sacrificial film layer 20 can be removed by dry etching to separate the bit line contact nodes, thereby obtaining the bit line contact plug 30 formed in the bit line contact hole 31 pattern. (Reference) Figure 5Because the material hardness of the bit line contact plug 30 is lower than that of the sacrificial film layer 20, and due to the processing technology, when removing the bit line contact plug material layer 32 formed on the sacrificial film layer 20 and completely separating the bit line contact node, over-etching must be performed to make the height of the bit line contact plug 30 relative to the upper surface of the sacrificial film layer 20 lower, so that there is a height difference between the upper surface of the bit line contact plug 30 and the upper surface of the sacrificial film layer 20, and it is flush with the top of the first barrier layer 51.
[0040] Next, refer to Figure 6 The sacrificial film layer 20 is removed to eliminate the height difference between the bit line contact plug 30 and other locations on the substrate 10, making the height of the bit line contact plug 30 flush with the height of other locations on the substrate 10. This prevents the sides of the bit line 40 at the bit line contact plug 30 from being etched during subsequent bit line pattern formation, prevents linewidth reduction at the bit line contact plug 30, and prevents adverse phenomena such as increased resistance or breakage of the bit line 40. Specifically, the sacrificial film layer 20 can be removed using either wet etching or dry etching methods. Specifically, when the sacrificial film layer 20 is made of oxide and wet etching is used, hydrofluoric acid can be used to etch the sacrificial film layer 20 to remove it. When the sacrificial film 20 is made of metal and is removed by wet etching, hydrogen peroxide can be used to etch the sacrificial film 20 to remove it, thereby improving the effect and efficiency of wet etching.
[0041] Next, refer to Figure 7 A bit line 40 pattern is formed on the substrate 10, wherein the bit line 40 pattern includes multiple bit lines 40, and each bit line contact plug 30 contacts one bit line 40. For specific processing, refer to... Figure 7 First, a bit line material layer can be deposited on the substrate 10 and the bit line contact plug 30 pattern, and then the bit line material layer can be etched to form the bit line 40 pattern. This facilitates the formation of the bit line 40 pattern. The material of this bit line material layer can be tungsten. (Continue to refer to...) Figure 7 A second barrier layer 52 can be deposited on the bit line material layer. When etching the bit line material layer, the second barrier layer 52 and the bit line material layer need to be etched sequentially from top to bottom to form a bit line 40 pattern on the substrate 10. This protects the upper surface of the bit line material layer. Since the height of the aforementioned bit line contact plug 30 is flush with the height of other locations on the substrate 10, the height of the deposited bit line material layer at the bit line contact plug 30 is also flush with the height of other locations, and the height of the second barrier layer 52 at the bit line contact plug 30 is also flush with the height of other locations. This prevents the side of the bit line 40 at the bit line contact plug 30 from being etched, prevents the linewidth of the bit line 40 at the bit line contact plug 30 from shrinking, and prevents adverse phenomena such as increased resistance or breakage of the bit line 40.
[0042] It should be noted that the semiconductor device manufacturing method described above, using DRAM as an example, is not limited to the formation of DRAM, but can also be applied to the formation of other memories that include bit line contact plugs and bit lines. For example, the memory can also be SRAM (Static Random-Access Memory) or MRAM (Magnetoresistive Random Access Memory).
[0043] Before forming the bit line contact plug 30 pattern, a sacrificial film layer 20 is deposited on the surface of the substrate 10; after forming the bit line contact plug 30 pattern, the sacrificial film layer 20 is removed, thereby preventing the bit line contact plug 30 from being lower in height than other positions on the substrate 10, eliminating the height difference between the bit line contact plug 30 and other positions on the substrate 10, and making the height of the bit line contact plug 30 flush with the height of other positions on the substrate 10. This prevents the sidewalls of the bit line 40 at the bit line contact plug 30 from being etched during subsequent bit line pattern formation, prevents linewidth reduction of the bit line 40 at the bit line contact plug 30, and prevents adverse phenomena such as increased resistance or breakage of the bit line 40.
[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A sacrificial film layer is deposited on the substrate; Before forming the sacrificial film layer on the substrate, the manufacturing method further includes: depositing a first barrier layer on the substrate to prevent damage to the substrate surface during subsequent etching of the sacrificial film layer; the sacrificial film layer is deposited on the first barrier layer; A bit line contact plug pattern is formed in the sacrificial film layer and the substrate; wherein the bit line contact plug pattern comprises a plurality of bit line contact plugs; Remove the sacrificial film layer so that the upper surface of the bit line contact plug is flush with the upper surface of the first barrier layer; A bit line pattern is formed on the substrate, wherein the bit line pattern comprises multiple bit lines, and each bit line contact plug contacts one bit line.
2. The manufacturing method as described in claim 1, characterized in that, Forming a bit line contact plug pattern in the sacrificial film layer and the substrate includes: The sacrificial film layer and the substrate are etched sequentially from top to bottom to form a bit line contact hole pattern in the substrate and the sacrificial film layer, wherein the bit line contact hole pattern includes a plurality of bit line contact holes; The bit line contact plug pattern is formed in the bit line contact hole pattern, wherein the bit line contact plug pattern includes bit line contact plugs filling each bit line contact hole.
3. The manufacturing method as described in claim 2, characterized in that, The step of forming the bit line contact plug pattern in the bit line contact hole pattern includes: Fill the bit line contact hole pattern with bit line contact plug material to completely fill the bit line contact hole pattern, and form a bit line contact plug material layer on the surface of the sacrificial film layer. Remove the bit line contact plug material layer formed on the surface of the sacrificial film layer to obtain the bit line contact plug pattern formed in the bit line contact hole pattern.
4. The manufacturing method as described in claim 2, characterized in that, The step of etching the sacrificial film layer and the substrate sequentially from top to bottom to form a bit line contact hole pattern in the substrate and the sacrificial film layer includes: The sacrificial film layer, the first barrier layer, and the substrate are etched sequentially from top to bottom, and the bit line contact hole pattern is formed in the substrate, the first barrier layer, and the sacrificial film layer.
5. The manufacturing method as described in claim 1, characterized in that, The formation of the bit line pattern on the substrate includes: A bit line material layer is deposited on the substrate and bit line contact plug pattern; A second barrier layer is deposited on the bit line material layer; The second barrier layer and the bit line material layer are etched sequentially from top to bottom to form the bit line pattern on the substrate.
6. The manufacturing method as described in claim 1, characterized in that, The thickness of the sacrificial film is 5nm~100nm.
7. The manufacturing method as described in claim 6, characterized in that, The material of the sacrificial film layer is an oxide or a metal.
8. The manufacturing method as described in claim 6, characterized in that, The material of the sacrificial film is titanium nitride, aluminum, or tungsten.
9. The manufacturing method as described in claim 7, characterized in that, The removal of the sacrificial film layer includes: removing the sacrificial film layer by wet etching or dry etching.
10. The manufacturing method as described in claim 9, characterized in that, When the material of the sacrificial film layer is an oxide, the step of removing the sacrificial film layer by wet etching includes: etching the sacrificial film layer with hydrofluoric acid to remove the sacrificial film layer; When the material of the sacrificial film is a metallic material, the step of removing the sacrificial film by wet etching includes: etching the sacrificial film with hydrogen peroxide to remove the sacrificial film.
Citation Information
Patent Citations
Semiconductor device and forming method thereof and memory
CN111640746A