Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention relates to a semiconductor package structure and a method for manufacturing the same, wherein the semiconductor package structure comprises a chip, a plurality of first and second bumps, an encapsulant, and a redistribution layer; the chip comprises an active region, the first and second bumps being formed in a first region and a second region of the active region, respectively; each of the first bumps being electrically connected to a plurality of chip pads of the chip; each of the second bumps comprising a first layer and a second layer having different widths; the encapsulant covering the chip and the first and second bumps; therefore, after grinding the encapsulant to expose the first and second bumps, the width of the exposed second bumps can be used to determine whether the first bumps are completely exposed from the encapsulant, thereby ensuring smooth electrical connection with the redistribution layer and avoiding insufficient or excessive grinding depth.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure and a manufacturing method thereof, and in particular to a chip-first semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] In the process of wafer-level packaging of chip-first semiconductor packaging structure, such as Figure 7A As shown, a plurality of chip pads 82 are formed on an active surface 81 of a chip 80, and a plurality of metal bumps 83 are respectively formed on the chip pads 82. Then, a sealing process is performed to cover the chip 80 and the metal bumps 83 with a sealing body 90. Finally, the sealing body 90 is ground to expose the metal bumps 83 to facilitate the subsequent redistribution layer process.

[0003] However, during the grinding process, the grinding depth is difficult to control. Figure 7A As shown, the grinding depth of the encapsulation body 90 is insufficient, and part of the metal bump 83 is exposed from the encapsulation body 90, while part of the metal bump 83a is not exposed from the encapsulation body 90, or as shown in FIG. Figure 7B The grinding depth of the encapsulant 90 is too deep, so that some metal bumps 83 b are ground too much, or even the metal bumps 83 are ground away, leaving only the chip pads 82 .

[0004] Therefore, it is necessary to further improve the existing semiconductor packaging structure. Summary of the Invention

[0005] In view of the above-mentioned defects of the existing semiconductor package structure, the main object of the present invention is to provide a new semiconductor package structure and a manufacturing method thereof to solve the defects of the prior art.

[0006] The main technical means used to achieve the above-mentioned purpose of the invention is to make the semiconductor package structure include:

[0007] A chip includes an active surface, the active surface including a first area and a second area, wherein the second area surrounds the first area, and a plurality of chip pads are formed on the first area;

[0008] A plurality of first bumps are respectively formed on the corresponding chip pads in the first region, and each of the first bumps includes a first surface away from the chip pad;

[0009] A plurality of second bumps are formed in the second region, each of the second bumps including a first layer and a second layer from top to bottom, wherein the first layer and the second layer have different sizes so that the second bumps are stepped, and the first layer is away from the chip and includes a second surface;

[0010] an encapsulation body covering the chip, the first bumps, and the second bumps, wherein the first surface of each first bump and the second surface of each second bump are flush with a third surface of the encapsulation body to form a first plane; and

[0011] A redistribution layer is formed on the first plane and electrically connected to the first bumps.

[0012] The advantage of the present invention is that a plurality of first bumps and a plurality of second bumps are formed on the active surface of the chip, wherein the first layer width and the second layer width of the second bumps are different. By judging the width of the second bumps exposed from the encapsulant, it is possible to determine whether the grinding depth is sufficient, thereby ensuring that the first bumps located on the chip pads are completely exposed from the encapsulant so as to smoothly connect electrically with the redistribution layer without causing insufficient or over-grinding depth. At the same time, the encapsulant covers the periphery of the chip to prevent the chip from being broken during the pickup process.

[0013] The main technical means used to achieve the above-mentioned purpose of the invention is to make the method for manufacturing the semiconductor package structure include:

[0014] (a) providing a wafer, the wafer comprising a plurality of chip regions, each of the chip regions comprising an active surface, the active surface comprising a first region and a second region, wherein a plurality of chip pads are formed in the first region;

[0015] (b) forming a first bump on each of the chip pads in the first regions, and forming a plurality of second bumps in the second regions, wherein each of the second bumps comprises a first layer, a second layer, and a third layer from top to bottom;

[0016] (c) cutting adjacent boundaries of the chip regions to form a plurality of chips;

[0017] (d) providing a carrier board, fixing the chips on the carrier board, wherein the active surfaces of the chips are away from the carrier board;

[0018] (e) forming a sealing body on the carrier, wherein the sealing body covers the chips, the first bumps and the second bumps on the chips; and

[0019] (f) grinding the encapsulant until the first layer of the second bumps disappears, and the second layer of the second bumps and the first bumps are exposed; at this time, the ground surface of the encapsulant, the exposed surfaces of the first bumps, and the exposed second layer surfaces of the second bumps form a plane.

[0020] The advantages of the present invention are that a plurality of first bumps are formed in the first area of ​​the active surface of the chip regions, and a plurality of second bumps are formed in the second area. Each of the second bumps comprises the first layer, the second layer, and the third layer from top to bottom. The encapsulation body is ground until the first layer of the second bumps disappears. By virtue of the size of the second bumps exposed from the encapsulation body, the first bumps located on the chip pads are ensured to be completely exposed from the encapsulation body. At the same time, the third layer of the second bumps is not ground, ensuring that the first bumps are not over-ground.

[0021] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this does not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A : A cross-sectional view of a first embodiment of a semiconductor package structure of the present invention.

[0023] Figure 1B : Figure 1A A partial enlarged view of .

[0024] Figure 2A : A cross-sectional view of a second embodiment of the semiconductor package structure of the present invention.

[0025] Figure 2B : A cross-sectional view of a third embodiment of a semiconductor package structure of the present invention.

[0026] Figure 2C : A cross-sectional view of a fourth embodiment of a semiconductor package structure of the present invention.

[0027] Figures 3A to 3D : Cross-sectional views of different steps in the bump manufacturing process of the semiconductor packaging structure manufacturing method of the present invention.

[0028] Figure 4A : A side plan view of the second bump of the first embodiment of the method for manufacturing the semiconductor package structure of the present invention.

[0029] Figure 4B : A side plan view of a second bump of a second embodiment of a method for manufacturing a semiconductor package structure of the present invention.

[0030] Figures 5A to 5G : Cross-sectional views of different steps in the packaging process of the method for manufacturing the semiconductor packaging structure of the present invention.

[0031] Figure 6A : Figure 5B A top plan view of one of the chips.

[0032] Figure 6B : Figure 5C A top plan view of one of the chips.

[0033] Figure 7A 、 Figure 7B : A cross-sectional view of a semiconductor packaging structure in the prior art.

[0034] Wherein, the reference numerals:

[0035] 1a, 1b, 1c, 1d: semiconductor package structure 10, 10': chip

[0036] 11: active surface 110: passivation layer

[0037] 12: First area 121: Chip pad

[0038] 122: first bump 122a: first bump

[0039] 123: first surface 123': surface

[0040] 124: Metal Line 13: Second Zone

[0041] 130: second bump 131: first layer

[0042] 132: Second layer 133: Second surface

[0043] 133': surface 130a: second bump

[0044] 131a: second layer 132a: third layer

[0045] 134a: first layer 130a': second bump

[0046] 131a': second layer 132a': third layer

[0047] 134a': first layer 14: back

[0048] 15: dielectric layer 20: sealing glue

[0049] 200, 200': Sealing body 21: Third surface

[0050] 210: Surface 22: First plane

[0051] 220: plane 23: fourth surface

[0052] 230: bottom surface 30, 30': redistribution layer

[0053] 31, 31': Metal circuit layer 32: Dielectric layer

[0054] 300: redistribution layer 40: solder ball

[0055] 50: protective layer 60: wafer

[0056] 61: Chip area 70: Carrier board

[0057] 71: Adhesive layer 80: Chip

[0058] 81: Active surface 82: Chip pad

[0059] 83, 83a, 83b: metal bumps 90: sealing glue DETAILED DESCRIPTION

[0060] The structural principle and working principle of the present invention are described in detail below with reference to the accompanying drawings:

[0061] First see Figure 1A , is a first embodiment of the semiconductor package structure 1a of the present invention, which includes a chip 10, a plurality of first bumps 122, a plurality of second bumps 130, an encapsulation body 20 and a redistribution layer 30; wherein the first bumps 122 and the second bumps 130 are formed on the chip 10 and covered by the encapsulation body 20, and the redistribution layer 30 is formed on the encapsulation body 20.

[0062] The chip 10 includes an active surface 11 and a back surface 14. The active surface 11 further includes a first region 12 and a second region 13. In this embodiment, the second region 13 is located around the first region 12. A plurality of chip pads 121 are formed in the first region 12. A dielectric layer 15 is formed on the active surface 11. The dielectric layer 15 partially covers the chip pads 121, leaving the chip pads 121 partially exposed from the dielectric layer 15. In one embodiment, a passivation layer 110 is formed in the first and second regions 12 and 13. The passivation layer 110 has a plurality of openings corresponding to the chip pads 121 in the first region 12, exposing the chip pads 121. The passivation layer 110 partially covers the chip pads 121. The dielectric layer 15 is formed on the passivation layer 110 and partially covers the chip pads 121.

[0063] The plurality of first bumps 122 are formed on the chip pads 121 respectively; in this embodiment, please refer to Figure 1B Each of the first bumps 122 includes a first surface 123 away from the chip 10 and has a width D1.

[0064] The plurality of second bumps 130 are respectively formed on the second region 13 of the chip 10; in this embodiment, please refer to Figure 1BEach of the second bumps 130 is stepped, and thus includes a first layer 131 and a second layer 132 from top to bottom, wherein the first layer 131 further includes a second surface 133 away from the chip 10 and has a width D2; the second layer 132 has a width D3, wherein the width D2 of the first layer 131 is different from the width D3 of the second layer 132; preferably, the width D2 of the first layer 131 is greater than the width D3 of the second layer 132, and the width D1 of the first bump 122 is substantially equal to the width D2 of the first layer 131 of the second bump 130.

[0065] The encapsulant 20 covers the chip 10, the first bumps 122 and the second bumps 130, and includes a third surface 21 and a fourth surface 23; in this embodiment, please refer to Figure 1B The third surface 21 is flush with the first surfaces 123 of the first bumps 122 and the second surfaces 133 of the second bumps 130 to form a first plane 22 ; the fourth surface 23 is flush with the back surface 14 of the chip 10 , so that the back surface 14 of the chip 10 is exposed.

[0066] The redistribution layer 30 is formed on the first plane 22 of the encapsulation body 20 and includes a metal circuit layer 31 and a plurality of dielectric layers 32. Figure 1A As shown, the metal circuit layer 31 of the redistribution layer 30 is electrically connected to the first bumps 122 and forms a plurality of solder balls 40; preferably, the redistribution layer 30 is a fan-out redistribution layer (Fan-outRDL), that is, the layout area of ​​the metal circuit layer 31 of the redistribution layer 30 is larger than the active surface 11 of the chip 10, and the distribution area of ​​the solder balls 40 formed on the redistribution layer 30 is also larger than the active surface 11.

[0067] See also Figure 2A FIG. 2 is a second embodiment of the semiconductor package structure 1b of the present invention; the semiconductor package structure 1b of this embodiment is Figure 1A The semiconductor package structure 1 a shown is substantially the same, but the redistribution layer 30 ′ is a fan-in redistribution layer (Fan-in RDL), ie, the layout area of ​​the metal wiring layer 31 ′ of the redistribution layer 30 ′ is no larger than the active surface 11 of the chip 10 .

[0068] As can be seen from the above description of the first and second embodiments of the present invention, the semiconductor package structures 1a and 1b of these two embodiments form a plurality of first bumps 122 in the first region 12 of the active surface 11 of the chip 10, and form a plurality of second bumps 130 in the second region 13, wherein the width D2 of the first layer 131 of the second bumps 130 is greater than the width D3 of the second layer 132, and the width D1 of the first bumps 122 is substantially equal to the width D2 of the first layer 131 of the second bumps 130. The width of the second bumps 130 exposed from the encapsulant 20 is used to determine whether the grinding depth is sufficient to fully expose the first bumps 122 and electrically connect them to the redistribution layers 30 and 30', thereby avoiding insufficient or excessive grinding depth. At the same time, the encapsulant 20 further covers the chip 10, protecting the chip 10 from breakage during the pickup process.

[0069] See also Figure 2B FIG. 1 is a third embodiment of the semiconductor package structure 1c of the present invention; the semiconductor package structure 1c of this embodiment is Figure 1A The semiconductor package structure 1 a shown is substantially the same as that shown in FIG. 1 . However, a protective layer 50 is further formed on the back surface 14 of the chip 10 and the fourth surface 23 of the encapsulation body 20 in the semiconductor package structure 1 c .

[0070] As can be seen from the above description, the semiconductor package structure 1c of the present invention further forms the protection layer 50 on the back surface 14 of the chip 10 and the fourth surface 23 of the encapsulation body 20 to protect the back surface of the semiconductor package structure 1c and prevent the back surface of the semiconductor package structure 1c from being scratched.

[0071] See also Figure 2C FIG. 4 is a fourth embodiment of the semiconductor package structure 1d of the present invention; the semiconductor package structure 1d of this embodiment is Figure 1A The semiconductor package structure 1 a shown is substantially the same as that of FIG. 1 . However, the semiconductor package structure 1 d further forms a metal line 124 in the first region 12 and electrically connects the first bump 122 corresponding to the first region 12 .

[0072] From the above description, the semiconductor package structure 1d of the present invention further forms the metal line 124 in the first region 12 to be electrically connected to the first bump 122 , thereby simplifying the circuit design of the redistribution layer 30 and reducing the number of layers of the redistribution layer 30 .

[0073] The above is a structural description of the semiconductor package structure of the present invention. The following further describes a detailed method for completing the semiconductor package element.

[0074] See also Figures 3A to 3D and Figures 5A to 5G, is an embodiment of a method for manufacturing a semiconductor package structure of the present invention, which includes the following steps (a) to (j); wherein Figures 3A to 3D The front-end wafer bumping process in the manufacturing method (corresponding to steps (a) to (c)), and Figures 5A to 5G This is the packaging process in the manufacturing method (ie, corresponding to steps (d) to (j)).

[0075] In step (a), if Figure 3A As shown, a wafer 60 is provided, which includes a plurality of chip areas 61, each of the chip areas 61 includes an active surface 11, and the active surface 11 includes a first area 12 and a second area 13, wherein a plurality of chip pads 121 are formed in the first area 12, and a passivation layer 110 is formed in the first area 12 and the second area 13, and the passivation layer 110 is formed with a plurality of openings corresponding to the chip pads 121 in the first area 12, so that the chip pads 121 are exposed; in this embodiment, the passivation layer 110 partially covers the chip pads 121.

[0076] In step (b), if Figure 3B As shown, a dielectric layer 15 is formed on the passivation layer 110 of the chip regions 61, and can partially cover the chip pads 121, so that the chip pads 121 are partially exposed from the dielectric layer 15; then a first bump 122a is formed on each chip pad 121, and a plurality of second bumps 130a are formed on the second regions 13; in this embodiment, as shown Figure 4A As shown, each of the second protrusions 130a is in a stepped shape and includes, from top to bottom, a first layer 134a, a second layer 131a, and a third layer 132a. The first layer 134a has a width D4 and a thickness L1, the second layer 131a has a width D5 and a thickness L2, and the third layer 132a has a width D6 and a thickness L3. The width D4 of the first layer 134a, the width D5 of the second layer 131a, and the width D6 of the third layer 132a are all different. , the thickness L1 of the first layer 134a, the thickness L2 of the second layer 131a, and the thickness L3 of the third layer 132a are all different; preferably, the width D4 of the first layer 134a is greater than the width D5 of the second layer 131a, the width D5 of the second layer 131a is greater than the width D6 of the third layer 132a, the thickness L1 of the first layer 134a is greater than the thickness L2 of the second layer 131a, and the thickness L2 of the second layer 131a is greater than the thickness L3 of the third layer 132a; in another embodiment, Figure 4B As shown, the second bump 130a' of this embodiment is Figure 4AThe second bump 130a shown is substantially the same, but the thickness L1' of the first layer 134a' and the thickness L2' of the second layer 131a' of the second bump 130a' are different from the thickness L1 and the thickness L2 of the first layer 134a of the second bump 130a. In this embodiment, the thickness L1' of the first layer 134a' is less than the thickness L2' of the second layer 131a'. In another embodiment, as shown in FIG. Figure 2C As shown, while forming the first bumps 122 and the second bumps 130 , a plurality of metal lines 124 may be further formed in each of the first regions 12 of the chip areas 61 to electrically connect to the first bumps 122 corresponding to the first regions 12 .

[0077] In step (c), if Figure 3C As shown, the boundaries of adjacent chip regions 61 are cut to form Figure 3D A plurality of chips 10 are shown.

[0078] In step (d), if Figure 5A As shown, a carrier 70 is first provided, and the back surfaces 14 of the chips 10 are fixed on the carrier 70. In this embodiment, the chips 10 are fixed on the carrier 70 by an adhesive layer 71, wherein the adhesive layer 71 can be an adhesive layer or a release layer.

[0079] In step (e), if Figure 5B As shown, a sealing body 200 is formed on the carrier 70, wherein the sealing body 200 covers the chips 10, the first bumps 122a and the second bumps 130a on the chips 10; in this embodiment, as shown Figure 6A As shown, the second bump 130a needs to be formed at least at a corner position of the chip 10, wherein the width D4 of the first layer 134a of the second bump 130a is greater than the width D1' of the first bump 122a, and the first bumps 122a and the second bumps 130a are a column; in another preferred embodiment, the first bumps 122a and the second bumps 130a can be cylindrical in shape, but are not limited to this; preferably, the second bumps 130a are formed at the four corners of the chip 10.

[0080] In step (f), Figure 5B The encapsulant 200 is ground until the first layer 134a of the second bumps 130a disappears, and the second layer 131a of the second bumps 130a and the first bumps 122a are exposed. Figure 5B The encapsulation body 200 is thinned as shown. Figure 5CIn the present embodiment, the surface 210 of the encapsulation body 200 ', the exposed surfaces 123 'of the first bumps 122a and the exposed surfaces 133 'of the second bumps 130a constitute a plane 220; as shown in FIG. Figure 6B As shown, the width D5 of the second layer 131a of the second bump 130a is substantially the same as the width D1' of the first bump 122a; preferably, the grinding depth is greater than the thickness L1 of the first layer 134a of the second bump 130a, and less than the thickness L1 of the first layer 134a plus the thickness L2 of the second layer 131a, so that a grinding stop line of a grinding device can be set in the second layer 131a of the second bump 130a.

[0081] During the grinding process, the grinding equipment confirms the size of the second bumps 130a exposed from the encapsulation body 200'. Figure 4A When the exposed dimension is D4, the grinding depth is not enough to completely expose the first bumps 122a from the encapsulation body 200'. Therefore, the grinding is continued until the exposed dimension is D5, so that the first bumps 122a can be completely exposed from the encapsulation body 200'. If the exposed dimension is D6, the grinding depth is too deep, and the first bumps 122a are over-ground or even ground to disappear. For cases where the grinding depth is insufficient or too deep, please refer to Figure 7A and Figure 7B .

[0082] like Figure 5D In step (g) shown, a redistribution layer 300 is formed on the plane 220, and the redistribution layer 300 includes a plurality of metal wiring layers 31 and a dielectric layer 320, wherein the metal wiring layers 31 are electrically connected to the first bumps 122a of each chip 10 respectively; in this embodiment, the redistribution layer 300 is a fan-out redistribution layer. In another embodiment, as shown in FIG. Figure 2A As shown, the redistribution layer 300 may also be a fan-in redistribution layer.

[0083] At Figure 5E In step (h), the carrier 70 is removed to expose the back surfaces 14 of the chips 10 and the bottom surface 230 of the encapsulation body 200'. In this embodiment, the back surfaces 14 of the chips 10 and the bottom surface 230 of the encapsulation body 200' are further formed as shown in FIG. Figure 2B A protective layer 50 is shown.

[0084] In step (i), the metal lines 31 of the redistribution layer 300 are formed as follows: Figure 5F A plurality of solder balls 40 are shown.

[0085] like Figure 5F and Figure 5GIn step (j), the redistribution layer 300 and the encapsulation body 200' are cut to form a Figure 1A The semiconductor package structure 1a is shown.

[0086] As can be seen from the above description, the method for manufacturing the semiconductor packaging structure of the present invention forms a plurality of first bumps 122a in the first area 12 of the active surface 11 of the chip areas 61, and forms a plurality of second bumps 130a in the second area 13, each of the second bumps 130a includes the first layer 134a, the second layer 131a and the third layer 132a from top to bottom, wherein the size of the first layer 134a, the size of the second layer 131a and the size of the third layer 132a are all different, so in the grinding process of grinding the encapsulation body 200 to reduce its thickness to the thickness of the encapsulation body 200', it can be judged by the size of the second bumps 130a exposed in the encapsulation body 200' whether the grinding depth is sufficient to fully expose the first bumps 122a and smoothly connect electrically to the redistribution layer 300. At the same time, the encapsulant 200' covers the periphery of the chips 10. After the encapsulant 200' is cut to form a single semiconductor package structure, the encapsulant 20 can protect the chip 10 from being broken during the picking process. Alternatively, the protective layer 50 can be further formed on the back side 14 of the chips 10 and the bottom side 230 of the encapsulant 200' to further strengthen the back side 14 of the chip 10 and prevent the back side 14 of the chip 10 from being scratched. Alternatively, the metal lines 124 can be further formed when forming the first bump 122a, so that the redistribution layer 300 can be electrically connected to the first bump 122a by reducing the circuit design, simplifying the circuit design of the redistribution layer 300, and thereby reducing the number of layers of the redistribution layer 300.

[0087] In summary, the semiconductor packaging structure of the present invention is formed with multiple first bumps and multiple second bumps on the active surface of the chip, wherein the first bumps are formed on the chip pads, and the sizes of the second bumps are different from top to bottom. In this way, the grinding depth can be judged by the size of the second bumps exposed from the encapsulation body to ensure that the first bumps are completely exposed from the encapsulation body and are smoothly electrically connected to the redistribution layer, thereby avoiding insufficient grinding depth or excessive grinding; the encapsulation body can further cover the chip to protect the chip from being broken during the picking process; or the protective layer can be further formed on the back of the chip and the fourth surface of the encapsulation body to strengthen the back of the chip and avoid scratches on the back of the chip; in addition, the metal circuit can be further formed when forming the first bumps, so that the redistribution layer can reduce the circuit design and be electrically connected to the first bumps, thereby simplifying the circuit design of the redistribution layer.

[0088] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: Include: A chip includes an active surface, the active surface including a chip pad area and a non-chip pad area, wherein the non-chip pad area surrounds the chip pad area and a plurality of chip pads are formed in the chip pad area; A plurality of first bumps are respectively formed on the corresponding chip pads in the chip pad area, and each of the first bumps includes a first surface away from the chip pad; A plurality of second bumps are formed in the non-chip pad area, each of the second bumps is stepped and includes a first layer and a second layer from top to bottom; wherein the first layer and the second layer have different sizes, the first layer is away from the chip and includes a second surface; an encapsulation body covering the chip, the first bumps, and the second bumps, wherein the first surface of each first bump and the second surface of each second bump are flush with a third surface of the encapsulation body to form a first plane; and A redistribution layer is formed on the first plane and electrically connected to the first bumps.

2. The semiconductor package structure according to claim 1, wherein: The width of the first layer of each of the second bumps is the same as the width of each of the first bumps.

3. The semiconductor package structure according to claim 1 or 2, wherein: The width of the first layer of each second bump is greater than the width of the second layer.

4. The semiconductor package structure according to claim 3, wherein: The encapsulation body further includes a fourth surface opposite to the third surface, and the fourth surface is flush with the back surface of the chip.

5. The semiconductor package structure according to claim 4, wherein: The redistribution layer is a fan-out redistribution layer or a fan-in redistribution layer.

6. The semiconductor package structure according to claim 4, wherein: A protection layer is further formed on the fourth surface of the encapsulation body and the back surface of the chip.

7. The semiconductor package structure according to claim 4, wherein: A metal circuit is further formed in the chip pad area of ​​the chip and is electrically connected to the corresponding first bump.

8. A method for manufacturing a semiconductor packaging structure, characterized in that: Include: (a) providing a wafer, the wafer comprising a plurality of chip regions, each of the chip regions comprising an active surface, the active surface comprising a chip pad region and a non-chip pad region, wherein a plurality of chip pads are formed in the chip pad region; (b) forming a first bump on each chip pad in the chip pad areas, and forming a plurality of second bumps in each non-chip pad area, wherein each second bump is stepped and includes a first layer, a second layer, and a third layer from top to bottom; (c) cutting adjacent boundaries of the chip regions to form a plurality of chips; (d) providing a carrier board, fixing the chips on the carrier board, wherein the active surfaces of the chips are away from the carrier board; (e) forming a sealing body on the carrier, wherein the sealing body covers the chips, the first bumps and the second bumps on the chips; and (f) grinding the encapsulant until the first layer of the second bumps disappears and the second layer of the second bumps and the first bumps are exposed; at this time, the ground surface of the encapsulant, the exposed surfaces of the first bumps, and the exposed second layer surfaces of the second bumps form a plane.

9. The method for manufacturing a semiconductor package structure according to claim 8, wherein: Further including: (g) forming a redistribution layer on the plane; (h) removing the carrier; (i) forming a plurality of solder balls on the redistribution layer; and (j) cutting the redistribution layer and the encapsulation body to form a plurality of semiconductor package structures.

10. The method for manufacturing a semiconductor package structure according to claim 8 or 9, wherein: The first layer size of the second bump is larger than the second layer size, and the second layer size is larger than the third layer size.

11. The method for manufacturing a semiconductor package structure according to claim 8 or 9, wherein: The second layer size of the second bump is the same as that of the first bump.

12. The method for manufacturing a semiconductor package structure according to claim 8 or 9, wherein: The first layer thickness of the second bump is greater than the second layer thickness, and the second layer thickness is greater than the third layer thickness.

13. The method for manufacturing a semiconductor package structure according to claim 9, wherein: The redistribution layer is a fan-out redistribution layer or a fan-in redistribution layer.

14. The method for manufacturing a semiconductor package structure according to claim 9, wherein: In the above step (h), a protection layer is further formed on the bottom surface of the encapsulation body and the back surfaces of the chips.

15. The method for manufacturing a semiconductor package structure according to claim 9, wherein: In the step (b), a metal circuit is further formed in the chip pad regions to be electrically connected to the corresponding first bumps.

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