Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same, the semiconductor structure comprising: a substrate and a plurality of bit lines arranged on the substrate. According to some embodiments, the plurality of bit lines each comprise a first conductive layer, a second conductive layer and a hard mask layer, wherein the first conductive layer is located on the substrate, the second conductive layer is located on the first conductive layer, and the hard mask layer is located on the second conductive layer. In some embodiments, the semiconductor structure further comprises a plurality of contact windows. The contact windows are located on the substrate and between two adjacent bit lines, wherein the bottom surface of the contact windows contacts the substrate. According to some embodiments, the top surface of the contact window does not exceed the top surface of the adjacent hard mask layer. The present invention can not only significantly reduce process costs, but the resulting semiconductor structure also has related components with complete profiles and excellent electronic properties.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure of a dynamic random access memory and a manufacturing method thereof. Background Art

[0002] With advancements in semiconductor technology, the size of memory cells in dynamic random access memory (DRAM) has shrunk to meet consumer demand for smaller electronic devices, and the integration level of memory cells has also increased. For example, DRAMs with bit lines positioned above a substrate and buried word lines within the substrate are designed to meet this increased integration requirement and speed up device operation. Furthermore, isolation structures, such as trench isolation structures, have been developed within buried word line DRAMs to prevent interference between word lines.

[0003] In conventional dynamic random access memory (DRAM), doped regions are formed in the active region of the substrate. These doped active regions serve as source / drain regions on either side of the wordline, and are connected to the surface of the source / drain regions via contacts. In conventional DRAM, the contacts extend to the top surface of the bitline and form a columnar structure with the contact plugs that subsequently connect to the contacts. As the density of memory devices increases, the spacing between related components such as bitlines, contacts, and contact plugs decreases. Currently, more sophisticated processes such as immersion lithography are required to complete the fabrication of device components, significantly increasing manufacturing costs.

[0004] Therefore, although existing semiconductor structure manufacturing methods, such as the manufacturing methods of buried word line dynamic random access memory, are sufficient to cope with their originally intended uses, they still do not fully meet the requirements in all aspects, and therefore there are still technical problems that need to be overcome. Summary of the Invention

[0005] Some embodiments of the present invention disclose a semiconductor structure comprising: a substrate and a plurality of bit lines disposed on the substrate. According to some embodiments, each bit line comprises a first conductive layer, a second conductive layer, and a hard mask layer, wherein the first conductive layer is located on the substrate, the second conductive layer is located on the first conductive layer, and the hard mask layer is located on the second conductive layer. In some embodiments, the semiconductor structure further comprises a plurality of contact windows. The contact windows are located on the substrate and between the two adjacent bit lines, wherein the bottom surface of the contact windows contacts the substrate. According to some embodiments, the top surface of the contact windows does not exceed the top surface of the adjacent hard mask layer.

[0006] Some embodiments of the present invention disclose a method for fabricating a semiconductor structure, comprising providing a substrate, and forming a plurality of bit lines on the substrate. In some embodiments, a spacer material layer is formed over the sidewalls and top surfaces of each bit line, wherein each bit line comprises a conductive layer and a hard mask layer located on the conductive layer. In some embodiments, the method for fabricating the semiconductor structure also comprises forming a first contact material layer on the substrate and overlying the spacer material layer of the bit lines. In some embodiments, the method for fabricating the semiconductor structure further comprises etching the first contact material layer to remove a portion of the first contact material layer, a portion of the hard mask layer, and a portion of the spacer material layer, thereby recessing the first contact material layer and forming a first recess between the remaining portions of the hard mask layer, with the remaining portion of the first contact material layer forming a bottom contact. In some embodiments, the method for fabricating the semiconductor structure further comprises depositing a first dielectric layer over the bottom contact, with the first dielectric layer conformally covering the sidewalls and bottom surface of the first recess and the remaining top surface of the hard mask layer. In some embodiments, the method for fabricating a semiconductor structure further includes patterning the first dielectric layer to remove a portion of the first dielectric layer and expose the top surface of the bottom contact, and forming spacers of varying thickness on opposite sidewalls of the hard mask layer protruding above the bottom contact, wherein second recesses are formed between adjacent spacers, the second recesses corresponding to the exposed top surfaces of the bottom contacts. In some embodiments, the method for fabricating a semiconductor structure further includes forming a top contact above the bottom contact, wherein the top surface of the top contact does not exceed the top surface of the adjacent hard mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figures 1 to 4 、 Figures 5A to 5C 、 Figure 6A 、 Figure 6B 、 7A to 7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figures 15A to 15C 、 16A to 16C are methods for fabricating semiconductor structures at different intermediate stages according to some embodiments of the present invention, wherein:

[0009] Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C is a schematic diagram of a substrate viewed from above;

[0010] Figure 5A 、 Figure 7A 、 Figure 15A 、 Figure 16A Corresponding respectively Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C a schematic cross-sectional view drawn along the section line AA'; and

[0011] Figure 5B 、 Figure 7B 、 Figure 15B 、 Figure 16B Corresponding respectively Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C The cross-sectional view drawn along the section line BB' in the figure.

[0012] Figure 17 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0013] Figure Number:

[0014] 100: Base

[0015] 102: Trench isolation structure

[0016] 104: buried word line group

[0017] 104A, 104B: word lines

[0018] 105: Insulation layer

[0019] 113: first conductive layer

[0020] 114: second conductive layer

[0021] 115:Hard mask layer

[0022] 115S1: first sidewall of the hard mask layer

[0023] 115S2: second sidewall of the hard mask layer

[0024] 100a,115a,122a,123a,125a,165A-a,165B-a: Top surface

[0025] 116: bit line

[0026] 12-1: First nitride material layer

[0027] 121: first nitride layer

[0028] 12-2: Oxidation material layer

[0029] 122: Oxide layer

[0030] 12-3: Second nitride material layer

[0031] 123: Second nitride layer

[0032] 1250: first contact material layer

[0033] 125: bottom contact portion

[0034] 131: First groove

[0035] 132: first dielectric layer

[0036] 134: Etching barrier layer

[0037] 134D1: First injection part

[0038] 134U1: First uninjected portion

[0039] 134D2: Second injection part

[0040] 134U2: Second uninjected portion

[0041] 132S1, 132S2: sidewall portion of the first dielectric layer

[0042] 132B1, 132B2: bottom portion of the first dielectric layer

[0043] R iT : The first groove of the i-th column

[0044] R (i-1)T : The first groove of the (i-1)th column

[0045] R (i-2)T : The first groove of the (i-2)th column

[0046] R (i-3)T : The first groove of the (i-3)th column

[0047] 141: first photoresist pattern

[0048] 1411,1412: First photoresist strip

[0049] 151: First injection step

[0050] 142: second photoresist pattern

[0051] 1421,1422: Second photoresist strip

[0052] 152: Second injection step

[0053] 160: Protective pattern

[0054] 161A, 161B: Second groove

[0055] 165A, 165B: Top contact part

[0056] R iP : Top contact of column i

[0057] R (i-1)P : Top contact of the (i-1)th column

[0058] R (i-2)P : Top contact of the (i-2)th column

[0059] R (i-3)P : Top contact of column (i-3)

[0060] 167: Second dielectric layer

[0061] 171, 172: Contact plug

[0062] W 141 : Width of the first photoresist stripe

[0063] W 142 : Width of the second photoresist stripe

[0064] W 131 : Width of the first groove

[0065] SP1: first spacer

[0066] SP2: Second spacer

[0067] C A ,C B :Contact window

[0068] D1: First direction

[0069] D2: Second direction

[0070] D3: Third direction

[0071] A-A', B-B': hatching line DETAILED DESCRIPTION

[0072] The present invention will be more fully described with reference to the accompanying drawings illustrating exemplary embodiments of the present invention. However, the present invention may be embodied in various forms and should not be limited to the exemplary embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0073] An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same to form a contact window that does not exceed the top surface of the bit line. Compared to the traditional process in which a contact window (contact) extending to the top surface of the bit line and a contact plug (contact plug) subsequently connected to the contact window are formed into a columnar structure, which requires a complex and expensive process to complete the production, the semiconductor structure and the method for manufacturing the same in this embodiment can significantly reduce the difficulty of the process and save costs. In particular, as the integration of memory devices continues to increase, the spacing between related components such as bit lines, contact windows, and contact plugs continues to shrink. The manufacturing method proposed in the embodiment can also complete the production of the semiconductor structure without the need for expensive processes such as immersion lithography. Therefore, the embodiment can not only significantly reduce the process cost, but the resulting semiconductor structure also has related components with complete profiles and excellent electronic properties.

[0074] The semiconductor structure proposed in the embodiment can be applied to the fabrication of bit lines and contacts in a dynamic random access memory (DRAM) device. To simplify the drawings and description, the accompanying drawings depict three bit lines and two contacts on a substrate in a memory device as an example of a semiconductor structure. However, the present invention is not limited to this. In addition, the substrate may have an isolation structure such as a shallow trench isolation structure to define an active region, as well as other components such as a buried word line (gate). In this embodiment, the components in the substrate are simplified to make the drawings clear and facilitate description.

[0075] Figures 1 to 4 、 Figures 5A to 5C 、 Figure 6A 、 Figure 6B 、 7A to 7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figures 15A to 15C 、 16A to 16C is a method of manufacturing a semiconductor structure at different intermediate stages according to some embodiments of the present invention, wherein Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C is a schematic diagram of a substrate viewed from above;

[0076] Figure 5A 、 Figure 7A 、 Figure 15A 、 Figure 16A Corresponding respectively Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C A schematic cross-sectional view drawn along the section line A-A'; Figure 5B 、 Figure 7B 、 Figure 15B 、 Figure 16B Corresponding respectively Figure 5C 、 Figure 7C 、 Figure 15C 、 Figure 16C Schematic cross-sectional view drawn by the section line BB'.

[0077] Please refer to Figure 1A substrate 100 is provided, and a plurality of bit lines 116 are formed above the substrate. Furthermore, components within the substrate 100, such as an isolation structure extending downward from the surface of the substrate 100 to isolate an active region, a buried word line separated from the bit line 116 above, and an insulating layer within the substrate 100 that separates the bit line from the word line, are omitted from the drawings of this example. In some embodiments, the material of the substrate 100 may include a semiconductor material, such as silicon, gallium arsenide, gallium nitride, silicon germanium, other suitable materials, or combinations thereof. In some embodiments, the substrate 100 is a silicon on insulator (SOI) substrate.

[0078] like Figure 1 As shown, each bit line 116 includes a first conductive layer 113 located on the top surface 100a of the substrate 100, a second conductive layer 114 located on the first conductive layer 113, and a hard mask (HM) layer 115 located on the second conductive layer 114. In some embodiments, the first conductive layer 113 comprises an epitaxial material or polysilicon, the second conductive layer 114 comprises a metal material such as tungsten, and the hard mask layer 115 comprises a nitride material such as silicon nitride, but the present invention is not limited thereto. Furthermore, the bit lines 116 are spaced apart in a first direction D1 and extend along a second direction D2. The first conductive layer 113, the second conductive layer 114, and the hard mask layer 115 are stacked in a third direction D3. The buried word lines within the substrate 100 (not shown) extend along the first direction D1.

[0079] Furthermore, the sidewalls of the bit line 116 are covered with a spacer material to protect the bit line 116. Figure 1 As shown, in some embodiments, a first nitride material layer 12-1 is formed on the sidewalls of each bit line 116, an oxide material layer 12-2 is formed on the outer sidewalls of the first nitride material layer 12-1, and a second nitride material layer 12-3 covers the periphery of the oxide material layer 12-2 and covers the top surface of the first nitride material layer 12-1 and the hard mask layer 115. The first nitride material layer 12-1 extends on the sidewalls of the hard mask layer 115, the second conductive layer 114, and the first conductive layer 113. Furthermore, the first nitride material layer 12-1 and the second nitride material layer 12-3 are, for example, silicon nitride, and the oxide material layer 12-2 is, for example, silicon oxide, but the present application is not limited thereto.

[0080] Furthermore, if Figure 1As shown, in some embodiments, a first contact material layer 1250 is formed on the substrate 100, covering the spacer material layer of the bit lines 116 and filling the gaps between adjacent bit lines 116. In some embodiments, the first contact material layer 1250 covers the top surface and sidewalls of the spacer material layer around all bit lines 116, and covers the surface of the substrate 100 exposed between the bit lines 116. That is, as shown in FIG. Figure 1 As shown, the top surface of the first contact material layer 1250 is higher than the top surface of the bit line 116. In some embodiments, the first contact material layer 1250 is, for example, doped or undoped polysilicon, which can be formed on the substrate 100 using chemical vapor deposition. After patterning in subsequent processes, the first contact material layer 1250 will become a part of a contact window, such as the bottom contact portion hereinafter referred to.

[0081] Next, refer to Figure 2 , a portion of the first contact material layer 1250 is removed, causing the first contact material layer 1250 to be recessed. The remaining portion of the first contact material layer 1250 forms a bottom contact portion 125. In some embodiments, an etch back process may be performed to remove a portion of the first contact material layer 1250. Furthermore, during this etch back process, a portion of the hard mask layer 115 and a portion of the spacer material layer are also removed, wherein the spacer material layer includes the second nitride material layer 12-3, the oxide material layer 12-2, and the first nitride material layer 12-1. Therefore, after this etch back process, the top surface of the remaining spacer material layer is substantially coplanar, and the top surface 125a of the bottom contact portion 125 is lower than the top surface of the remaining spacer material layer.

[0082] Next, refer to Figure 3 , the portion of the spacer material layer on the sidewall of the hard mask layer 115 protruding from the bottom contact portion 125 is removed. According to some embodiments, a suitable wet etching process can be used to remove the second nitride material layer 12-3 and the oxide material layer 12-2 located on the sidewall of the hard mask layer 115 and protruding from the bottom contact portion 125. Furthermore, in some embodiments, performing this wet etching process will also cause a slight loss of the hard mask layer 115 and the bottom contact portion 125. Therefore, if Figure 3 The bottom contact 125 and the hard mask layer 115 are shown to be slightly lower than the heights shown in FIG. Figure 2 The heights of the bottom contact 125 and the hard mask layer 115 are shown.

[0083] According to some embodiments, Figure 3As shown, after forming the bottom contact 125 and removing a portion of the spacer material layer, the remaining hard mask layer 115 partially protrudes beyond the top surface 125a of the bottom contact 125. The formed first nitride layer 121 covers the sidewalls of the hard mask layer 115 and the sidewalls of the second conductive layer 114 and the first conductive layer 113. The top surfaces of the formed oxide layer 122 and the second nitride layer 123 are substantially coplanar with the top surface 125a of the bottom contact 125. According to some embodiments, after forming the bottom contact 125 and removing a portion of the spacer material layer, a first trench 131 is formed between the remaining hard mask layer 115, wherein the first trench 131 exposes the top surface 125a of the bottom contact 125, the top surface 122a of the oxide layer 122, and the top surface 123a of the second nitride layer 123.

[0084] Furthermore, if Figure 3 As shown, the hard mask layer 115 of each bit line 116 has opposing first and second sidewalls 115S1 and 115S2 at the portion protruding above the top surface 125a of the bottom contact 125. At this stage, a first nitride layer 121 of the same thickness is formed on the first and second sidewalls 115S1 and 115S2 of the hard mask layer 115. In subsequent processes, a manufacturing method is proposed for forming spacers of different thicknesses on opposite sidewalls of the hard mask layer protruding above the bottom contacts. This allows the top contacts subsequently formed between the spacers—the contact windows—to contact opposite sides with spacers of different thicknesses. Therefore, according to an embodiment of the present invention, by varying and adjusting the spacer thickness to stagger the positions of the top contacts of adjacent columns, the contact plugs connected above the top contacts can be offset.

[0085] Next, refer to Figure 4 A first dielectric layer 132 is conformally deposited over the bottom contact 125 to cover the sidewalls and bottom surface of the first recess 131. That is, the first dielectric layer 132 conformally covers the top surface 115a, first sidewall 115S1, and second sidewall 115S2 of the remaining hard mask layer 115. The first dielectric layer 132 also covers the top surface 122a of the oxide layer 122, the top surface 123a of the second nitride layer 123, and the top surface 125a of the bottom contact 125 exposed in the first recess 131. According to some embodiments, the thickness of the first dielectric layer 132 needs to at least cover the top surface 122a of the oxide layer 122 and the top surface 123a of the second nitride layer 123 exposed in the first recess 131. In some examples, the thickness of the first dielectric layer 132 is, for example, in a range from about 5 nm to about 7 nm, but the present application is not limited thereto.

[0086] Furthermore, in some embodiments, the first dielectric layer 132 includes a nitride-containing layer, such as a silicon nitride layer, but the present invention is not limited to this material. The material of the first dielectric layer 132 can be one or a combination of multiple dielectric materials. In some embodiments, the first dielectric layer 132 can include the same material as the first nitride layer 121. The first dielectric layer 132 can be formed by a deposition method, such as chemical vapor deposition, or other suitable methods.

[0087] Next, the first dielectric layer 132 is patterned to form dielectric portions of different thicknesses on opposite sidewalls of the hard mask layer protruding from the bottom contacts. Different spacer thicknesses, such as opposite spacer thicknesses, are also formed on opposite sidewalls of the hard mask layer corresponding to adjacent first recesses 131 to stagger the positions of subsequently formed top contacts in adjacent rows, such as adjacent first recesses 131 located in adjacent rows. Figures 5A to 14B A method for patterning the first dielectric layer 132 according to some embodiments of the present invention is provided.

[0088] Next, please refer to Figure 5A 、 Figure 5B 、 Figure 5C . Figure 5C is a schematic diagram of a top view of the substrate. Figure 5A and Figure 5B Corresponding respectively Figure 5C The cross-sectional diagram drawn by the section line A-A' and the section line B-B' in FIG. Figure 4 After the first dielectric layer 132 is formed, an etching barrier layer 134 is conformally deposited on the first dielectric layer 132, and a patterned mask layer is provided on the etching barrier layer 134 to shield a portion of the first groove 131 (see FIG. Figure 3 ), wherein the patterned mask layer can be a patterned photoresist layer. In some embodiments, the etch barrier layer 134 is an undoped polysilicon layer, or other suitable barrier materials.

[0089] In some embodiments, as Figure 5C As shown, the aforementioned first grooves 131 are arranged into multiple rows along the first direction D1, and these rows are arranged at intervals in the second direction D2. To simplify the drawings, in this example, the first grooves 131 arranged in four rows are used for illustration. Figure 5C As shown, the top-down configuration is the i-th column R iT The first groove 131, the (i-1)th row R (i-1)TThe first groove 131, the (i-2)th row R (i-2)T The first groove 131, the (i-3)th row R (i-3)T The first groove 131 is formed by a first groove 131, wherein i is a positive integer.

[0090] like Figure 5A 、 Figure 5C As shown, in some embodiments, in the corresponding i-th column R iT and the (i-2)th column R (i-2)T A first photoresist pattern 141 is formed above the first groove 131. The first photoresist pattern 141 exposes the (i-1)th row R (i-1)T and the (i-3)th column R (i-3)T The etching barrier layer 134 of the first groove 131 is as shown in FIG. Figure 5A 、 Figure 5B shown.

[0091] In some embodiments, the first photoresist pattern 141 includes a plurality of photoresist strips (PR strips), for example, a first photoresist strip 1411 covering the first row of R iT The portion of the etching barrier layer 134 on the first groove 131 and another first photoresist strip 1412 covering the portion corresponding to the (i-2)th column R (i-2)T The portion of the etching barrier layer 134 on the first groove 131 is notable. According to an embodiment of the present invention, the width W of each first photoresist strip 1411 / 1412 in the second direction D2 is 141 It may be greater than the width W of the first groove 131 in the second direction D2 131 , for example, the width W of the first photoresist strip 1411 and the first photoresist strip 1412 141 The width W of the grooves in the same row can be included 131 As well as a portion of the distance to the next row of grooves, a conventional photolithography process can be used in conjunction with the photoresist pattern having the larger width of the first photoresist stripe to perform subsequent photolithography processes. Therefore, whether using a precision photolithography process (such as immersion photolithography) or a conventional photoresist in conjunction with a conventional photolithography process, the manufacturing method of the embodiment and the first photoresist pattern 141 can complete subsequent processes.

[0092] Next, refer to Figure 6A and Figure 6B According to some embodiments, for the portion of the etch barrier layer 134 exposed by the first photoresist pattern 141, for example, corresponding to the (i-1)th row R (i-1)T and the (i-3)th column R (i-3)TAccording to some embodiments, the first implant step 151 is performed on the portion exposed by the etching barrier layer 134 at an angle, for example, doping with a P-type dopant, wherein the P-type dopant is, for example, boron or other suitable materials. Figure 6A As shown, the exposed portion of the etch barrier layer 134 that is implanted corresponds to the second sidewall 115S2 and the top surface 115a of the hard mask layer 115. Figure 6B As shown, the portion of the etch barrier layer 134 covered by the first photoresist pattern 141 will not be implanted with any dopants.

[0093] According to some embodiments, after the first implantation step 151 is completed, the first photoresist pattern 141 is removed. In some embodiments, the first photoresist pattern 141 is removed by an ash process.

[0094] Next, please refer to Figure 7A 、 Figure 7B and Figure 7C In some embodiments, in the corresponding (i-1)th column R (i-1)T and the (i-3)th column R (i-3)T A second photoresist pattern 142 is formed above the first groove 131. Figure 7C As shown. The second photoresist pattern 142 exposes the corresponding i-th column R iT and the (i-2)th column R (i-2)T The etching barrier layer 134 of the first groove 131 is as shown in FIG. Figure 7B shown.

[0095] In some embodiments, the second photoresist pattern 142 includes a plurality of photoresist strips (PR strips), for example, a second photoresist strip 1421 covering the (i-1)th column R (i-1)T The portion of the etching barrier layer 134 on the first groove 131 and another second photoresist strip 1422 covering the portion corresponding to the (i-3)th column R (i-3)T The portion of the etching barrier layer 134 on the first groove 131 is as shown in FIG. Figure 7C As shown, according to some embodiments of the present invention, the width W of each second photoresist strip 1421 / 1422 in the second direction D2 is 142 It may be greater than the width W of the first groove 131 in the second direction D2 131 In some examples, such as Figure 7C As shown, the width W of the second photoresist strip 1421 and the second photoresist strip 1422 is 142 The width W of the grooves in the same row can be included 131As well as a portion of the distance between the grooves of two adjacent rows, the second photoresist pattern 142 can be used to perform subsequent photolithography processes on this photoresist pattern with a relatively large width using a conventional photolithography process. Therefore, whether a precise photolithography process such as immersion photolithography is used or a conventional photoresist is used in conjunction with a conventional photolithography process, subsequent processes can be completed using the second photoresist pattern 142 of the embodiment.

[0096] Next, refer to Figure 8A and Figure 8B For example, the portion of the etching barrier layer 134 exposed by the second photoresist pattern 142 corresponds to the i-th column R iT and the (i-2)th column R (i-2)T The first groove 131 is formed by the etching process, and a second implant step 152 is performed. The implantation angle in the second implant step 152 is different from the implantation angle in the first implant step 151. According to some embodiments, the second implant step 152 is performed on the exposed portion of the etching barrier layer 134 at another tilt angle different from the tilt direction of the first implant step 151, for example, doping with a P-type dopant, wherein the P-type dopant is, for example, boron or other suitable materials. Figure 8A As shown, the portion of the etch barrier layer 134 covered by the second photoresist pattern 142 will not be implanted with any dopants. Figure 8B As shown, the exposed implanted portion of the etch barrier layer 134 corresponds to the first sidewall 115S1 and the top surface 115 a of the hard mask layer 115 .

[0097] Next, refer to Figure 9A and Figure 9B According to some embodiments, after the second implantation step 152 is completed, the second photoresist pattern 142 is removed. In some embodiments, the second photoresist pattern 142 is removed by an ash process.

[0098] like Figure 9A As shown, in the corresponding (i-1) column R (i-1)T and the (i-3)th column R (i-3)T A first implanted portion 134D1 of the etch barrier layer 134 is formed in the first recess 131 and above the first dielectric layer 132 corresponding to the second sidewall 115S2 of the hard mask layer 115 and the top surface 115a of the hard mask layer 115, while the remaining portion of the etch barrier layer 134 is a first non-implanted portion 134U1.

[0099] like Figure 9B As shown, in the corresponding column R iTand the (i-2)th column R (i-2)T Second implanted portions 134D2 of the etch barrier layer 134 are formed in the first recess 131 and above the first dielectric layer 132 corresponding to the first sidewalls 115S1 and the top surface 115a of the hard mask layer 115. The remaining portions of the etch barrier layer 134 are second non-implanted portions 134U2.

[0100] Afterwards, refer to Figure 10A and Figure 10B According to some embodiments, the implanted portion of the etch barrier layer 134 is removed, leaving the unimplanted portion. In some embodiments, the first implanted portion 134D1 and the second implanted portion 134D2 of the etch barrier layer 134 are removed, for example, by wet etching, leaving the first unimplanted portion 134U1 (see Figure 10A ) and the second unimplanted portion 134U2 (see Figure 10B ), wherein the etching barrier layer is, for example, a polysilicon layer.

[0101] In some embodiments, as Figure 10A As shown, the remaining portion of the etching barrier layer corresponding to the first grooves 131 in the (i-1)th and (i-3)th columns, i.e., the first non-implanted portion 134U1), exposes a portion of the first dielectric layer 132 located on the second sidewall 115S2 and the top surface 115a of the hard mask layer 115. Figure 10B As shown, the remaining portion of the etching barrier layer corresponding to the first groove 131 of the i-th column and the (i-2)-th column, that is, the second non-injected portion 134U2, exposes a portion of the first dielectric layer 132 located on the first sidewall 115S1 and the top surface 115a of the hard mask layer 115.

[0102] Next, refer to Figure 11A and Figure 11B According to some embodiments, the portion of the first dielectric layer 132 not covered by the remaining portion of the etch barrier layer 134 is removed. The remaining portion of the etch barrier layer 134 is the first non-implanted portion 134U1 and the second non-implanted portion 134U2. In some embodiments, the portion of the first dielectric layer 132 is removed by, for example, wet etching and / or SiCoNi etching processes or other suitable processes. Figure 11A As shown, in the first grooves 131 of the (i-1)th and (i-3)th columns, the portion of the first dielectric layer 132 located on the second sidewall 115S2 and the top surface 115a of the hard mask layer 115 is removed, leaving the sidewall portion 132S1 of the first dielectric layer. Figure 11BAs shown, in the first grooves 131 in the i-th and (i-2)-th columns, portions of the first dielectric layer 132 located on the first sidewalls 115S1 and the top surface 115a of the hard mask layer 115 are removed, leaving sidewall portions 132S2 of the first dielectric layer.

[0103] Next, refer to Figure 12A and Figure 12B According to some embodiments, all remaining portions of the etch barrier layer 134 are removed. For example, Figure 11A The first unimplanted portion 134U1 in the Figure 11B In some embodiments, the etch barrier layer 134 is a polysilicon layer, and an etching gas having a high selectivity to polysilicon, such as SF6, is used to remove the etch barrier layer 134.

[0104] In some embodiments, as Figure 12A As shown, in the first recesses 131 of the (i-1)th and (i-3)th columns, the sidewall portion 132S1 of the first dielectric layer 132 located on the first sidewall 115S1 of the hard mask layer 115 and the bottom portion 132B1 of the first dielectric layer 132 located on the top surface 125a of the bottom contact portion 125 remain. Figure 12B As shown, in the first grooves 131 of the i-th column and the (i-2)-th column, the sidewall portion 132S2 of the first dielectric layer 132 located on the second sidewall 115S2 of the hard mask layer 115 and the bottom surface portion 132B2 of the first dielectric layer 132 located on the top surface 125a of the bottom contact portion 125 are left.

[0105] Next, according to some embodiments, a portion of the first dielectric layer 132 located at the bottom of the first groove 131 is removed to expose the top surface 125 a of the bottom contact portion 125 . Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B A manufacturing method for removing the first dielectric layer at the bottom of the first groove according to some embodiments of the present invention is provided.

[0106] Please refer to Figure 13A 、 Figure 13B According to some embodiments, a protection pattern 160 is formed on the hard mask layer 115 to expose a portion of the first dielectric layer 132 at the bottom of the first groove 131. In some embodiments, for example, a polymer material layer or other suitable material layer is deposited on the substrate using methane (CH4) as a deposition gas. Figure 12A 、 Figure 12B The structure shown in FIG. 1 is formed by a suitable patterning process. Figure 13A 、 Figure 13BA protection pattern 160 is shown.

[0107] In some embodiments, as Figure 13A As shown, at the first groove 131 corresponding to the (i-1)th column and the (i-3)th column, the protective pattern 160 formed covers the top surface 115a of the hard mask layer 115, the first nitride layer 121 on the second side wall 115S2 of the hard mask layer 115, and the first nitride layer 121 on the first side wall 115S1 of the hard mask layer 115 and the side wall portion 132S1 of the first dielectric layer 132.

[0108] In some embodiments, as Figure 13B As shown, at the first groove 131 corresponding to the i-th column and the (i-2)-th column, the protective pattern 160 formed covers the top surface 115a of the hard mask layer 115, the first nitride layer 121 on the first side wall 115S1 of the hard mask layer 115, and the first nitride layer 121 on the second side wall 115S2 of the hard mask layer 115 and the side wall portion 132S2 of the first dielectric layer 132.

[0109] Next, refer to Figure 14A 、 14B The portion of the first dielectric layer 132 located at the bottom of the first recess 131 is removed to expose the top surface 125a of the bottom contact 125. In some embodiments, the bottom surface portion 132B1 and the bottom surface portion 132B2 of the first dielectric layer 132 are removed, for example, using an etching process having a higher selectivity for the material of the first dielectric layer 132 than for the material of the protection pattern 160.

[0110] In some embodiments, as Figure 14A As shown, the bottom surface portion 132B1 of the first dielectric layer 132 in the first grooves 131 located in the (i-1)th column and the (i-3)th column is removed (see Figure 13A ), thereby exposing the top surface 125a of the bottom contact portion 125. In some embodiments, after removing the bottom portion 132B1 of the first dielectric layer 132, the top surface 122a of the oxide layer 122 and the top surface 123a of the second nitride layer 123 adjacent to the second sidewall 115S2 of the hard mask layer 115 are further exposed. Figure 14B As shown, in the same step, the bottom surface portion 132B2 of the first dielectric layer 132 in the first grooves 131 in the i-th row and the (i-2)-th row can be removed at the same time (see Figure 13B ), thereby exposing the top surface 125a of the bottom contact portion 125. In some embodiments, after removing the bottom portion 132B2 of the first dielectric layer 132, the top surface 122a of the oxide layer 122 and the top surface 123a of the second nitride layer 123 adjacent to the first sidewall 115S1 of the hard mask layer 115 are further exposed.

[0111] Then, according to some embodiments, after exposing the top surface 125a of the bottom contact portion 125, the protection pattern 160 is removed. In some embodiments, the protection pattern 160 is removed by an ash process or other suitable process.

[0112] According to some embodiments of the present invention, by Figures 5A to 14B By using the process, spacers with different thicknesses can be formed on opposite side walls of the hard mask layer 115 protruding from the top surface 125a of the bottom contact portion 125, for example Figure 14A 、 Figure 14B The first spacer SP1 and the second spacer SP2 are shown, and a second groove 161A and a second groove 161B are formed between adjacent spacers. Therefore, when looking down at the bottom contact portions 125 on the substrate 100, the top surface 125a of the bottom contact portion 125 exposed by the second groove 161A and the second groove 161B is offset in the second direction D2. Of course, the present invention is not limited to the above Figures 5A to 14B Other methods for forming spacers with different thicknesses on opposite sidewalls of the hard mask layer 115 are also included in the embodiments of the present invention.

[0113] According to some embodiments, Figure 14A As shown, at the first recess 131 adjacent to the (i-1)th column and the (i-3)th column, the first nitride layer 121 on the first sidewall 115S1 of the hard mask layer 115 and the sidewall portion 132S1 of the first dielectric layer 132 may constitute a first spacer SP1, while the first nitride layer 121 on the second sidewall 115S2 of the hard mask layer 115 may be regarded as a second spacer SP2. Figure 14A In the example shown, the thickness of the first spacer SP1 is greater than the thickness of the second spacer SP2.

[0114] According to some embodiments, Figure 14B As shown, at the first groove 131 adjacent to the i-th column and the (i-2)-th column, the first nitride layer 121 on the first sidewall 115S1 of the hard mask layer 115 can be regarded as a first spacer SP1, and the first nitride layer 121 on the second sidewall 115S2 of the hard mask layer 115 and the sidewall portion 132S1 of the first dielectric layer 132 can constitute a second spacer SP2. Figure 14B In the example shown, the thickness of the first spacer SP1 is smaller than the thickness of the second spacer SP2.

[0115] Next, please refer to Figure 15A 、 Figure 15B 、 Figure 15C . Figure 15C is a schematic diagram of a top view of the substrate. Figure 15A and Figure 15B Corresponding respectively Figure 15C According to some embodiments, when forming the Figure 14A 、 Figure 14B After the structure shown in FIG. 1 is formed, a top contact portion 165A and a top contact portion 165B are formed in the second groove 161A and the second groove 161B, respectively. The top contact portion 165A and the top contact portion 165B are respectively located above the corresponding bottom contact portion 125 and form contact windows (contacts C) together with the bottom contact portion 125. A 、Contact window C B According to some embodiments, Figure 15C As shown, when looking down at the substrate 100, the top contact portions 165A and 165B are arranged in the i-th row R from top to bottom. iP The top contact portion 165B of the (i-1)th column R (i-1)P The top contact portion 165A of the (i-2)th row R (i-2)P The top contact portion 165B of the (i-3)th column R (i-3)P The top contact portions 165A of different columns or the contact windows C are arranged in a row. A , top contact portion 165B or contact window C B The two electrodes are offset in the second direction D2.

[0116] According to some embodiments, the method of forming the top contact portions 165A and 165B includes, for example, forming a second contact material layer above the bottom contact portions 125, wherein the second contact material layer covers the top surface 115a of the hard mask layer 115 and fills the second grooves 161A and 161B (see Figure 14A 、 Figure 14B The second contact material layer may include a metal material, such as tungsten, but the present application is not limited thereto. Next, the portion of the second contact material layer outside second recesses 161A and 161B is removed. The portion of the second contact material layer remaining within second recesses 161A and 161B forms top contacts 165A and 165B.

[0117] It is worth mentioning that, according to some embodiments of the present invention, the top surface 165A-a of the formed top contact portion 165A and the top surface 165B-a of the formed top contact portion 165B do not exceed the top surface 115a of the adjacent hard mask layer 115. That is, the contacts C formed according to some embodiments of the present invention are A 、Contact window C B The hard mask layer 115 is located between the bit lines and does not extend onto the top surface 115a of the hard mask layer 115. In some embodiments, Figure 15A As shown, the top surface 165A-a of the top contact portion 165A is substantially coplanar with the top surface 115a of the hard mask layer 115. Figure 15B As shown, the top surface 165B-a of the top contact 165B is substantially coplanar with the top surface 115a of the hard mask layer 115 .

[0118] Next, please refer to Figure 16A 、 Figure 16B 、 Figure 16C . Figure 16C is a schematic diagram of a top view of the substrate. Figure 16A and Figure 16B Corresponding respectively Figure 16C According to some embodiments, when forming the Figure 15A 、 Figure 15B After the structure shown in FIG. 1 is formed, a second dielectric layer 167 such as a silicon nitride layer is formed to cover the hard mask layer 115, the first spacer SP1, the second spacer SP2 and the contact window C. A 、Contact window C B , and form a plurality of contact plugs 171 and 172 through the second dielectric layer 167 and disposed in the contact window C A 、Contact window C B On the top, contact plugs 171 and 172 are connected to the contact window C A 、Contact window C B Therefore, the top surface 165A-a of the top contact portion 165A and the top surface 165B-a of the top contact portion 165B are the contact surfaces (landing surfaces) of the contact plug 171 and the contact plug 172, respectively. Figure 16C As shown, the contact plugs 171 and 172 in two adjacent rows are offset in the second direction D2 to increase the spacing between them and avoid electrical interference.

[0119] Figure 17 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 17 Same as above Figure 15B The components in the embodiment of the present invention use the same reference numerals, and their materials and manufacturing methods can be referred to above and will not be described in detail here.

[0120] The semiconductor structure of the embodiment is applied to a dynamic random access memory (DRAM) device with buried word lines, wherein a plurality of active regions A are formed in a substrate 100 of the memory device. A , two adjacent active areas A AThe memory device includes a plurality of buried word line groups 104 in the substrate 100, and each buried word line group 104 includes two word lines 104A and 104B. Figure 17 As shown, an active area A in the substrate 100 A The device has a buried word line group 104, which includes two separated word lines 104A and 104B. The bit line formed therein, including a first conductive layer 113, a second conductive layer 114, and a hard mask layer 115, corresponds to the upper part of the two adjacent buried word lines 104A and 104B. The buried word lines 104A and 104B are separated from the upper bit line 116 by an insulating layer 105. The contact window (e.g., Figure 17 The contact window C shown B ) extends downward and contacts the surface of the substrate 100.

[0121] According to some embodiments of the present invention, the semiconductor structure and the manufacturing method thereof are provided, the contact windows (contacts C) formed A 、Contact window C B Located between the hard mask layer 115 of the bit line and the contact window C A The top surface 165A-a of the top contact portion 165A is aligned with the contact window C B The top surface 165B-a of the top contact portion 165B does not exceed the top surface 115a of the hard mask layer 115. That is, the contact window of the embodiment does not extend to the top surface 115a of the hard mask layer 115. Compared with the existing semiconductor structure process, especially the process of small-scale memory devices, which requires complex and expensive processes to complete the contact window extending to the top surface of the bit line and the subsequent columnar structure of the contact plug connected to the contact window, the semiconductor structure and its manufacturing method proposed in the embodiment can be used in conjunction with a general photolithography process, such as the aforementioned Figure 5C 、 Figure 7C The widths of the photoresist pattern strips 1411, 1412, 1421, and 1422 shown are greater than the width of the grooves, allowing the contact windows to be fabricated. This significantly reduces process complexity and saves costs. Furthermore, the resulting semiconductor structure also has related components with complete profiles, such as a contact window of sufficient width and its top surface serving as the contact surface of a contact plug, resulting in excellent electronic properties. Consequently, a memory device utilizing the semiconductor structure of the embodiment has good reliability and stable operating performance.

[0122] Although the present invention has been disclosed above with respect to several preferred embodiments, they are not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: a base; A plurality of bit lines are located on the substrate, each of the plurality of bit lines comprising: a first conductive layer located on the substrate; a second conductive layer located on the first conductive layer; and a hard mask layer located on the second conductive layer; a plurality of contact windows located on the substrate and between two adjacent bit lines, wherein bottom surfaces of the plurality of contact windows contact the substrate, and top surfaces of the plurality of contact windows do not exceed the top surface of the adjacent hard mask layer, wherein each of the plurality of contact windows includes a bottom contact portion located on the substrate and a top contact portion located above the bottom contact portion, and a top surface width of the top contact portion is greater than a top surface width of the bottom contact portion; and A plurality of contact plugs are respectively arranged on the contact windows and partially extend into the contact windows, wherein a bottom portion of each contact plug is arranged in the corresponding contact window, and a side wall of the bottom portion is in direct contact with a side wall of the corresponding contact window.

2. The semiconductor structure according to claim 1, wherein: The top contact portion is located between adjacent hard mask layers, wherein a top surface of the top contact portion is substantially coplanar with a top surface of the adjacent hard mask layer.

3. The semiconductor structure according to claim 2, wherein: Two opposite sidewalls of each top contact portion are respectively adjacent to the spacers on the sidewalls of the two adjacent hard mask layers, and the spacers have different thicknesses.

4. The semiconductor structure according to claim 1, wherein: Each of the hard mask layers has a first sidewall and a second sidewall opposite to each other, and the semiconductor structure further includes: a first spacer located on the first sidewall; and a second spacer, located on the second side wall, The thickness of the first spacer is different from the thickness of the second spacer.

5. The semiconductor structure according to claim 4, wherein: Each of the first spacers includes a first nitride layer, and each of the second spacers includes the first nitride layer and a second nitride layer; Alternatively, each of the first spacers includes the first nitride layer and the second nitride layer, and each of the second spacers includes the first nitride layer. The semiconductor structure according to claim 1 , wherein: A top surface of the top contact portion does not exceed the top surface of the adjacent hard mask layer.

7. The semiconductor structure according to claim 1, wherein: The top contact portion of each of the multiple contact windows is also located above a lower spacer, and the lower spacer is located between a side wall of the bottom contact portion and the adjacent bit line, wherein the bottom surface of the top contact portion covers the top surface of the corresponding bottom contact portion and the top surface of the lower spacer.

8. The semiconductor structure according to claim 1, wherein: Looking down at the contact windows on the substrate, the contact windows are arranged along a first direction to form a plurality of rows, and the contact windows in two adjacent rows are offset in a second direction that is different from the first direction.

9. The semiconductor structure according to claim 8, wherein: The contact plugs in two adjacent columns are offset in the second direction.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and a plurality of bit lines formed on the substrate, and covering the sidewalls and top surfaces of each bit line with a spacer material layer, wherein each of the plurality of bit lines includes a conductive layer and a hard mask layer located on the conductive layer; forming a first contact material layer on the substrate and covering the spacer material layer of the plurality of bit lines; Etching the first contact material layer to remove a portion of the first contact material layer, a portion of the hard mask layer, and a portion of the spacer material layer, thereby recessing the first contact material layer and forming a first groove between the remaining hard mask layers, with the remaining portion of the first contact material layer forming a bottom contact portion; Depositing a first dielectric layer above the bottom contact portion, wherein the first dielectric layer conformally covers the sidewalls and bottom surface of the first groove and the remaining top surface of the hard mask layer; Patterning the first dielectric layer to remove a portion of the first dielectric layer and expose the top surface of the bottom contact, and forming spacers of different thicknesses on opposite side walls of the hard mask layer protruding from the bottom contact, wherein second grooves are formed between adjacent spacers, and the second grooves correspond to the exposed top surface of the bottom contact; forming a top contact over the bottom contact, wherein a top surface of the top contact does not exceed a top surface of the adjacent hard mask layer, and wherein a top surface width of the top contact is greater than a top surface width of the bottom contact; and A plurality of contact plugs are formed on the top contact portions and partially extend into the top contact portions, wherein a bottom portion of each contact plug is disposed in the corresponding top contact portion, and a side wall of the bottom portion is in direct contact with a side wall of the corresponding top contact portion.

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