Test structure

Abstract

The present application discloses a test structure, which is formed on a wafer for integrating semiconductor devices. The test structure is used to monitor the process of the patterns in this layer. The patterns in this layer include at least two types of patterns with different critical dimensions. The test structure is located in the engineering pattern area, which is used to form engineering patterns. Engineering patterns are non-functional patterns. The test structure includes at least two types of test patterns with different critical dimensions. The critical dimension of each test pattern among the test patterns with different critical dimensions corresponds to the critical dimension of the patterns in this layer. By forming a test structure in the engineering pattern area, and the critical dimension of the test patterns of the test structure corresponding to the critical dimension of the patterns in this layer, the present application can monitor the process of the patterns in this layer through the test structure, without the need to discover process problems through WAT after chip manufacturing is completed, thereby improving the product yield to a certain extent.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly relates to a test structure. Background Art

[0002] As the integrated circuit manufacturing process nodes are reduced, the line widths of the active areas (AAs), polysilicon gates (polys), and even metal layers of semiconductor devices need to be reduced as the chip area shrinks. During the reduction of the critical dimension (CD), higher requirements are imposed on the process capabilities and stabilities of device patterns, especially metal layers (e.g., aluminum (Al) metal layers and / or copper (Cu) metal layers).

[0003] The metal layer constructs electrical connections for different devices and structures at different levels. However, due to chip layout issues, the distribution of the metal layer is usually uneven; and it is difficult to monitor different-shaped, different-line-width, and different-direction chips in real time. Therefore, in related technologies, the monitoring of the process of device patterns (especially metal layer patterns) is usually carried out after chip manufacturing is completed through subsequent wafer acceptance tests (WATs) to discover process problems.

[0004] In view of this, there is an urgent need for a monitoring solution that can timely feedback process fluctuations and failures. Summary of the Invention

[0005] This application provides a test structure, which can solve the problem in related technologies that the process cannot be timely monitored by detecting the process through WAT. The test structure is formed on a wafer, and the wafer is used to integrate semiconductor devices. The test structure is used to monitor the process of the patterns on this layer, and the patterns on this layer include at least two patterns with different critical dimensions.

[0006] The test structure is located in the engineering pattern area, and the engineering pattern area is used to form engineering patterns, which are patterns without functions. The test structure includes at least two test patterns with different critical dimensions, and the critical dimension of each test pattern among the test patterns with different critical dimensions corresponds to the critical dimension of the patterns on this layer.

[0007] In some embodiments, there are different spacings between the patterns on this layer, there are different spacings between the test patterns, and the spacings between the test patterns correspond to the spacings between the patterns on this layer.

[0008] In some embodiments, the current layer patterns have different placement directions, the test patterns have different placement directions, and there are patterns with the same critical dimensions between the current layer patterns and the test patterns with the same placement direction.

[0009] In some embodiments, there are patterns with the same spacing between the current layer patterns and the test patterns that are placed in the same direction.

[0010] In some embodiments, there are patterns with the same spacing and critical dimensions between the current layer patterns and the test patterns that are placed in the same direction.

[0011] In some embodiments, the placement direction includes a horizontal direction and a vertical direction, and the horizontal direction and the vertical direction are perpendicular to each other.

[0012] In some embodiments, the pattern of the current layer is a pattern of a metal layer.

[0013] In some embodiments, the metal layer includes aluminum and / or copper.

[0014] The technical solution of this application has at least the following advantages:

[0015] By forming a test structure in the engineering pattern area, the test structure includes at least two test patterns with different critical sizes. The critical size of each test pattern in the test patterns with different critical sizes corresponds to the critical size of the current layer pattern. In this way, the process of the current layer pattern can be monitored through the test structure, without the need to use WAT to discover process problems after chip manufacturing is completed, thereby improving the product yield to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 1 is a top view schematic diagram of a test structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0018] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0020] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0021] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] Reference Figure 1 , which shows a top view schematic diagram of a test structure provided by an exemplary embodiment of the present application. As Figure 1 shown, the test structure is formed on the wafer 100, which is used to monitor the process of the patterns in this layer. It is located in the engineering pattern area 101 ( Figure 1 the area in the dotted line), and the test structure includes:

[0023] At least two test patterns with different critical dimensions, and the critical dimension of each test pattern among the test patterns with different critical dimensions corresponds to the critical dimension of the patterns in this layer.

[0024] Among them, the wafer 100 is used to integrate semiconductor devices, and the engineering pattern area 101 is used to form engineering patterns (dummy patterns) 310. The engineering patterns 310 are patterns without functions (which are usually used as filling patterns in this layer to ensure the stability of the process).

[0025] The patterns in this layer include at least two different patterns in this layer with different critical dimensions. As Figure 1 shown, the critical dimensions of the patterns 211, 213, and 214 in this layer are different (it should be noted that Figure 1Three types of patterns of this layer with different key dimensions are used as examples for illustration. In actual applications, the patterns of this layer may include two types, or more than three types of key dimensions. The key dimensions of the pattern 212 of this layer are the same as those of the pattern 211 of this layer. Optionally, the pattern of this layer is a pattern of a metal layer, and the metal layer includes aluminum and / or copper.

[0026] Correspondingly, for the test patterns, the key dimension of each test pattern corresponds to the key dimension of the pattern of this layer. For example, as Figure 1 shown, the key dimensions of the test patterns 411, 412, and 414 are different, the key dimensions of the test pattern 411 and the test pattern 413 are the same, the key dimension of the test pattern 411 is the same as that of the pattern 211 of this layer, the key dimension of the test pattern 412 is the same as Figure 1 the key dimension of the pattern of this layer not shown in the figure, the key dimension of the test pattern 413 is the same as that of the pattern 212 of this layer, and the key dimension of the test pattern 414 is the same as that of the pattern 214 of this layer.

[0027] Optionally, there are different spacings between the patterns of this layer, there are different spacings between the test patterns, and the spacings between the test patterns correspond to the spacings between the patterns of this layer. Exemplarily, as Figure 1 shown, the spacing between the patterns 211 of this layer is D1, the spacing between the test patterns 411 is d1, D1 = d1, the spacing between the patterns 212 of this layer is D2 ( Figure 1 only one pattern 212 of this layer is shown in the figure, and there are multiple patterns 212 in other areas of the wafer 100 in actuality), the spacing between the test patterns 412 is d2, D2 = d2.

[0028] Optionally, the patterns of this layer have different placement directions, the test patterns have different placement directions, and between the patterns of this layer and the test patterns with the same placement direction, there are patterns with the same key dimensions; between the patterns of this layer and the test patterns with the same placement direction, there are patterns with the same spacings; between the patterns of this layer and the test patterns with the same placement direction, there are patterns with the same spacings and key dimensions. Exemplarily, as Figure 1 shown, the placement directions of the test patterns include horizontal and vertical, the horizontal and vertical are perpendicular to each other, the placement directions of the test patterns 411 and 412 are horizontal, the placement directions of the test patterns 413 and 414 are vertical. Correspondingly, the key dimensions of the pattern 211 of this layer and the test pattern 411 with the same horizontal placement direction are the same, and the spacing between the patterns 211 of this layer and the spacing between the test patterns 411 are the same.

[0029] In summary, in the embodiments of the present application, by forming a test structure in the engineering graphics area, the test structure includes at least two test patterns with different critical dimensions, and the critical dimension of each test pattern among the test patterns with different critical dimensions corresponds to the critical dimension of the graphics of this layer. Therefore, the process of the graphics of this layer can be monitored through the test structure, and it is not necessary to discover process problems through WAT after chip manufacturing is completed, which improves the product yield to a certain extent.

[0030] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A test structure, characterized in that, The test structure is formed on a wafer for integrating semiconductor devices, and the test structure is used to monitor the process of the patterns in this layer, where the patterns in this layer include at least two patterns with different critical dimensions. The test structure is located in the engineering pattern area for forming engineering patterns which are non-functional patterns. The test structure includes at least two test patterns with different critical dimensions, and the critical dimension of each test pattern among the test patterns with different critical dimensions corresponds to the critical dimension of the pattern in this layer.

2. The test structure according to claim 1, characterized in that, There are different spacings between the patterns in this layer, and there are different spacings between the test patterns. The spacings between the test patterns correspond to the spacings between the patterns in this layer.

3. The test structure according to claim 2, wherein The patterns in this layer have different orientations, and the test patterns have different orientations. Between the patterns in this layer and the test patterns with the same orientation, there are patterns with the same critical dimension.

4. The test structure according to claim 3, wherein, Between the patterns in this layer and the test patterns with the same orientation, there are patterns with the same spacing.

5. The test structure according to claim 4, wherein Between the patterns in this layer and the test patterns with the same orientation, there are patterns with the same spacing and the same critical dimension.

6. The test structure according to claim 5, wherein, The orientations include horizontal and vertical, and the horizontal and vertical are perpendicular to each other.

7. The test structure according to any one of claims 1 to 6, characterized in that, The patterns in this layer are patterns of a metal layer.

8. The test structure according to claim 7, wherein The metal layer includes aluminum and / or copper.

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