A semiconductor integrated circuit structure and a manufacturing method thereof, and a scribe lane structure

Abstract

The present disclosure provides a semiconductor integrated circuit structure and a manufacturing method thereof, and a scribe lane structure. The semiconductor integrated circuit structure includes, but is not limited to, a semiconductor substrate, a plurality of layers, a first metal structure, a plurality of voids, and a second metal structure. The plurality of layers are formed on the semiconductor substrate, and the first metal structure is embedded in the plurality of layers. The plurality of voids are arranged above the first metal structure and formed in the plurality of layers. The second metal structure is arranged above the plurality of voids. The second metal structure, the plurality of voids, and the first metal structure together form a crack arrest structure substantially perpendicular to a surface of the semiconductor substrate. The present disclosure can effectively prevent the problem of crack propagation into the chip during wafer cutting, thereby greatly improving the yield and stability of the semiconductor integrated circuit. The overall structure of the semiconductor integrated circuit of the present disclosure is simpler, which not only reduces the cost and improves the reliability, but also significantly reduces the area of the scribe lane part, so that the area for chip manufacturing on the wafer is larger.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuits, and more specifically, this disclosure provides a semiconductor integrated circuit structure and its manufacturing method, as well as a dicing structure. Background Technology

[0002] As semiconductor integrated circuits become smaller and more integrated, their structures become increasingly fragile. In particular, the stress generated during wafer dicing can easily lead to cracks on the chip, resulting in low yield.

[0003] In existing technologies, low-k or ultra-low-k dielectric materials are frequently used to improve the insulation performance of semiconductor integrated circuits. However, structures formed by materials with low dielectric constants tend to be soft and easily permeable. This permeability allows moisture to seep into the chip, and the soft structure facilitates the propagation of cracks during wafer dicing, reducing the yield of semiconductor integrated circuits. To address this issue, crack-stop structures have been proposed. However, conventional crack-stop structures are overly complex, increasing the processing cost of semiconductor integrated circuits and potentially negatively impacting their reliability. Summary of the Invention

[0004] To address the problems of complex structure and high processing cost of existing crack-stopping structures, this disclosure specifically provides a semiconductor integrated circuit structure and its manufacturing method, as well as a dicing structure, to achieve at least one technical objective such as simplifying the crack-stopping structure and reducing processing costs while realizing the crack-stopping function.

[0005] To achieve the above-mentioned technical objectives, this disclosure provides a semiconductor integrated circuit structure. This integrated circuit structure includes, but is not limited to, a semiconductor substrate, a stack, a first metal structure, a gap, and a second metal structure. At least one stack is formed on the semiconductor substrate, and the stack includes a first insulating layer and a second insulating layer. The first metal structure is embedded within the stack. At least one gap is disposed above the first metal structure and formed within the at least one stack. The second metal structure is disposed above the at least one gap, wherein the second metal structure, the at least one gap, and the first metal structure together form a crack-resistant structure substantially perpendicular to the surface of the semiconductor substrate.

[0006] To achieve the above-mentioned technical objectives, this disclosure also specifically provides a dicing structure. This dicing structure may include, but is not limited to, the semiconductor integrated circuit structure in any embodiment of this disclosure.

[0007] To achieve the above-mentioned technical objectives, this disclosure provides a method for manufacturing a semiconductor integrated circuit structure, which may include, but is not limited to, at least one of the following steps: Providing a semiconductor substrate; forming at least one stack on the semiconductor substrate, the stack including a first insulating layer and a second insulating layer; embedding a first metal structure within the stack; then forming at least one void within the at least one stack, the void being disposed above the first metal structure; forming a second metal structure above the at least one void using a damascus embedding method, such that the second metal structure, the at least one void, and the first metal structure together form a crack-resistant structure substantially perpendicular to the surface of the semiconductor substrate.

[0008] The beneficial effects of this disclosure are as follows:

[0009] The technical solution provided in this disclosure can effectively prevent cracks from propagating into integrated circuit chips during wafer dicing, thereby greatly improving the yield and stability of semiconductor integrated circuits. The overall structure of the semiconductor integrated circuit provided in this disclosure is simpler, which not only reduces costs and improves the reliability of semiconductor integrated circuit devices, but also significantly reduces the area of ​​the dicing trace, thereby allowing for a larger area on the wafer used for chip manufacturing and improving wafer utilization.

[0010] Based on the crack-stopping structure formed by the first metal structure, the void, and the second metal structure, this disclosure can effectively prevent stress diffusion during wafer dicing by using the crack-stopping structure on the dicing track, thereby effectively preventing the problem of crack propagation to the chip.

[0011] Furthermore, based on the waterproof and permeable structure obtained during the processing of the dicing structure, this disclosure can also prevent moisture from entering the integrated circuit chip, thus demonstrating that this disclosure has better reliability. Attached Figure Description

[0012] Figure 1 A schematic diagram of the longitudinal cross-sectional structure of a device after a first metal structure is embedded in a stack is shown in one or more embodiments of this disclosure.

[0013] Figure 2 This illustration shows a schematic diagram of the longitudinal cross-sectional structure of a device in one or more embodiments of the present disclosure, in which a patterned photoresist layer is etched to form a through-hole extending into a first metal structure.

[0014] Figure 3 A schematic diagram of the longitudinal cross-sectional structure of the device after deposition of an interlayer dielectric layer in one or more embodiments of this disclosure is shown.

[0015] Figure 4 A schematic diagram of the longitudinal cross-sectional structure of the device after etching the inter-metal dielectric layer is shown in one or more embodiments of this disclosure.

[0016] Figure 5 A schematic diagram of the longitudinal cross-sectional structure of the device after the inter-metal dielectric layer is etched again to form trenches in one or more embodiments of this disclosure is shown.

[0017] Figure 6 A schematic diagram of the longitudinal cross-sectional structure of the device after metal deposition and chemical mechanical planarization is shown in one or more embodiments of this disclosure.

[0018] 100. Semiconductor substrate.

[0019] 101. Photoresist layer.

[0020] 200. Lamination. 201. First insulating layer. 202. Second insulating layer.

[0021] 300. First metal structure.

[0022] 400. Gap.

[0023] 401. First connecting hole.

[0024] 402, Second connecting hole.

[0025] 500. Second metal structure.

[0026] 600. Interlayer dielectric layer between metal layers.

[0027] 601. Trench.

[0028] 700. Tungsten plug for contact hole.

[0029] 800. Shallow trench isolation structure.

[0030] 900, Crack-resistant structure.

[0031] 901. Waterproof and seepage-proof structure.

[0032] 902. Sealing ring structure. Detailed Implementation

[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0036] like Figures 1 to 6 As shown, one or more embodiments of this disclosure can provide a method for manufacturing a semiconductor integrated circuit structure, one technical objective of which is to form a crack-resistant structure. Specifically, the method for manufacturing the integrated circuit structure may include, but is not limited to, at least one of the following steps.

[0037] like Figure 1 As shown, a semiconductor substrate 100 is first provided, and at least one stack 200 is formed on the semiconductor substrate 100. Multiple stacks are formed from bottom to top as shown (five stacks are illustrated), and the stacks 200 include, but are not limited to, a first insulating layer 201 and a second insulating layer 202. For any stack, this disclosure allows for the deposition of a second insulating layer 202 after the deposition of the first insulating layer 201. A next stack can be deposited after the current stack is formed, up to a predetermined number of stacks. This disclosure also embeds a first metal structure 300 within the stacks 200, which can be formed on the bottommost stack, with a tungsten plug for contact holes formed in the stack before the formation of the first metal structure 300.

[0038] Furthermore, this disclosure enables the formation of multiple metal interconnect structures during the lamination process using a Damascus mosaic technique. These multiple metal interconnect structures can be distributed within the dicing structure and the sealing ring structure, as illustrated in the figure. The mosaic process flow will not be described in detail here.

[0039] It is understood that, in one or more embodiments of this disclosure, the first insulating layer 201 is specifically an interlayer dielectric (ILD), which is formed using a low-k or ultra-low-k material. In one or more embodiments of this disclosure, the second insulating layer 202 is a capping layer, which is also formed using a material with a low dielectric constant. As shown in the figures, a tungsten plug with a contact hole and a first metal structure 300 can be sequentially formed within the bottommost first insulating layer 201. Furthermore, in one or more embodiments of this disclosure, a shallow trench isolation structure can also be formed within the semiconductor substrate 100.

[0040] like Figures 2 to 5 As shown, at least one void 400 is formed within at least one stack 200. The void 400 is disposed above the first metal structure 300 and contacts the upper surface of the first metal structure 300. Forming at least one void 400 within at least one stack 200 in one or more embodiments of this disclosure may include: forming at least one first via hole 401 on at least one stack 200 by photolithography and etching, and forming the void 400 within the stack 200 based on the first via hole 401. The formation process of the void 400 is further described below.

[0041] like Figure 2 As shown, after coating all the current stacked layers 200 with a photoresist layer 101, the photoresist layer 101 is patterned to form vias extending into the first metal structure 300. It is understood that after patterning the photoresist layer 101, a pattern corresponding to the underlying first metal structure 300 can be formed at a predetermined position on the photoresist layer 101. Then, using the patterned photoresist layer 101 as a mask, the stacked layers above the first metal structure 300 are etched, thereby forming vias contacting the first metal structure 300 on the stacked layers. The etching method can be, for example, dry etching.

[0042] Specifically, in some embodiments of this disclosure, a gap 400 is formed within the stack 200 based on the first connecting hole 401, including but not limited to... Figures 3 to 5 The steps are shown.

[0043] like Figure 3As shown, after removing the photoresist layer 101, an intermediate metal dielectric (IMD) layer 600 is deposited on top of all the stacked layers 200 to seal one end of the first connecting hole 401. In some embodiments of this disclosure, the material used for the intermediate metal dielectric layer 600 is a tetraethoxysilane (TEOS) series or a fluorosilane (FTEOS) series substance. Due to the poor step coverage of TEOS or FTEOS, the upper end of the first connecting hole 401 can be better sealed when the intermediate metal dielectric layer 600 is deposited. It is worth mentioning that in some embodiments of this disclosure, the thickness of the intermediate metal dielectric layer 600 is close to or the same as the thickness of the multiple stacked layers above the first metal structure 300, which can help to further improve the effect of the crack-arresting structure formed in this disclosure in preventing crack propagation.

[0044] like Figure 4 As shown, photolithography and etching of the intermetallic dielectric layer 600 are performed to form a second via hole 402 that communicates with the first via hole 401. The second via hole 402 is larger than the first via hole 401 and is vertically aligned with the first via hole 401.

[0045] Additionally, in some embodiments of this disclosure, the photolithography and etching of the inter-metal dielectric layer 600 may include simultaneous photolithography and etching of the inter-metal dielectric layer 600 within the crack-stopping structure 900, the waterproofing structure 901, and the sealing ring structure 902 formed on the wafer. Specifically, since the first connecting hole 401 has already been formed in a previous process, there is no capping layer above the first connecting hole 401. Therefore, compared to the connecting holes (extending to the capping layer) above the metal interconnect structures in other regions illustrated, the second connecting hole 402 formed above the first connecting hole 401 will have a greater depth.

[0046] like Figure 5 As shown, the intermetallic dielectric layer 600 is etched again to expand the upper part of the second connecting hole 402 into a trench 601 for filling metal and to form a gap using the first connecting hole below the second connecting hole. Specifically, in some embodiments of this disclosure, re-etching the intermetallic dielectric layer 600 may include increasing the depth and upper width of the second connecting hole 402 by etching the intermetallic dielectric layer 600. While the depth of the second connecting hole 402 increases, the depth of the first connecting hole 401 decreases accordingly. It is evident that this disclosure can form a gap based on the already formed first connecting hole 401, that is, using the first connecting hole 401, whose height is reduced after re-etching, as a gap.

[0047] In some embodiments of this disclosure, re-etching the inter-metal dielectric layer 600 may include forming trenches 601 for filling metal on the inter-metal dielectric layer 600 within the crack-stopping structure 900, the waterproofing structure 901, and the sealing ring structure 902, respectively, by etching. During the re-etching of the inter-metal dielectric layer 600, since there is no cover layer above the first connecting hole 401, the second connecting hole 402 formed above the first connecting hole 401 will have a greater depth compared to the connecting holes (contact metal interconnect structures) above the metal interconnect structures in other regions illustrated, i.e., the height of the first connecting hole 401 is further reduced.

[0048] like Figure 6 As shown, this disclosure enables the formation of a second metal structure 500 above at least one gap 400 using a damascus mosaic method, such that the second metal structure 500, at least one gap 400, and the first metal structure 300 together form a crack-stopping structure 900 substantially perpendicular to the surface of the semiconductor substrate 100. Therefore, in some embodiments of this disclosure, the surface of the semiconductor substrate 100 extends along the x-direction, the crack-stopping structure 900 extends along the y-direction, and the y-direction can be perpendicular to the x-direction. The formation of the second metal structure 500 above at least one gap 400 includes filling the trench 601 and the second connecting hole 402 with metal to form the second metal structure 500. More specifically, this disclosure can fill with barrier metal, utilizing the poor step coverage of the barrier metal to block the upper end of the gap 400. The barrier metal can be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or cobalt (Co). Alternatively, this disclosure may first deposit a barrier metal to block the upper end of the gap 400 before depositing copper to reduce processing costs. In specific implementations, chemical mechanical planarization (CMP) is performed after metal deposition to make the upper surface of the metal flush with the upper surface of the interlayer dielectric layer 600. Furthermore, some embodiments of this disclosure may also deposit a capping layer after forming the second metal structure 500.

[0049] It is understood that the method for manufacturing the semiconductor integrated circuit structure provided in this disclosure can be implemented after the back end of line (BEOL) process. The details of the damascus damascene process involved in forming the second metal structure 500 will not be elaborated in this embodiment.

[0050] The method for manufacturing a semiconductor integrated circuit structure based on some embodiments of this disclosure, but not limited to the method that can form a semiconductor integrated circuit structure, is described in detail below.

[0051] like Figure 6As shown, the semiconductor integrated circuit structure provided in one or more embodiments of this disclosure may include, but is not limited to, a semiconductor substrate 100, a stacked layer 200, a first metal structure 300, a void 400, an inter-metal dielectric layer 600, and a second metal structure 500.

[0052] The semiconductor substrate 100 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG).

[0053] At least one stack 200 is formed on the semiconductor substrate 100, and the stack 200 includes a first insulating layer 201 and a second insulating layer 202. In some embodiments of this disclosure, the first insulating layer 201 is an interlayer dielectric layer and the second insulating layer 202 is a capping layer.

[0054] The interlayer dielectric layer is made of materials such as low-k or ultra-low-k dielectric materials, and the capping layer is made of insulating materials with low dielectric constant.

[0055] The first metal structure 300 is embedded within the stack 200. The metal material constituting the first metal structure 300 may include a barrier metal, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt (Co), or at least an alloy thereof. The metal material constituting the first metal structure 300 may also include copper, aluminum, or tungsten, for example, by depositing a portion of the barrier metal first and then depositing copper during the processing.

[0056] At least one gap 400 is disposed above the first metal structure 300 and formed within the stack 200. The semiconductor integrated circuit structure provided in this disclosure may, for example, include two or more gaps 400 arranged in parallel.

[0057] A second metal structure 500 is disposed above at least one gap 400, wherein the second metal structure 500, at least one gap 400, and the first metal structure 300 together form a crack-stopping structure 900 substantially perpendicular to the surface of the semiconductor substrate 100. Specifically, the second metal structure 500 includes a metal block body and a plurality of extensions extending downward from the metal block body. The first metal structure 300 includes metal support portions corresponding to the extensions. A gap 400 is correspondingly disposed above each metal support portion, and an extension is correspondingly disposed above each gap 400. More specifically, the metal block body is embedded within the inter-metal dielectric layer 600, and the extensions extend from the inter-metal dielectric layer 600 into the stack 200.

[0058] like Figure 6 As shown, in some embodiments of this disclosure, the number of metal support portions is the same as the number of gaps, and also the same as the number of extensions of the second metal structure. As shown, the two gaps 400 correspond to two metal support portions and two extensions, respectively.

[0059] An intermetallic dielectric layer 600 is formed on at least one stack 200. The intermetallic dielectric layer 600 in this disclosure uses a tetraethoxysilane (TEOS) series or a fluorinated silane (FTEOS) series material to better form the voids 400.

[0060] like Figure 6 As shown, the semiconductor integrated circuit structure also includes a contact hole tungsten plug 700 and a shallow trench isolation (STI) structure 800. The shallow trench isolation structure is formed below the first metal structure 300 and can be formed in the upper part of the semiconductor substrate 100.

[0061] At least one contact hole tungsten plug 700 is formed within the stack 200 and is located between the first metal structure 300 and the semiconductor substrate 100, and can be used to prevent metal ions from diffusing into the semiconductor substrate 100.

[0062] It is understood that this disclosure can also provide a scribe lane structure, which may include, but is not limited to, the semiconductor integrated circuit structure in any embodiment of this disclosure. Based on the scribe lane structure provided by this disclosure, when dicing a wafer, cracks will first propagate to the most vulnerable structure in the scribe lane—the voids. It is evident that this disclosure can stop cracks by using a scribe lane structure with voids of 400, thereby protecting the integrated circuit chip portion.

[0063] like Figure 6 As shown, the slicing channel structure also includes a waterproof barrier 901. Therefore, the slicing channel structure provided in this disclosure may include, but is not limited to, a crack stop 900 and a moisture barrier 901.

[0064] Furthermore, the sealing ring structure 902 involved in this disclosure belongs to the semiconductor integrated circuit chip part, and will not be described in detail in this embodiment.

[0065] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0066] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor integrated circuit structure, characterized in that, include: Semiconductor substrate; At least one stack is formed on the semiconductor substrate; the stack includes a first insulating layer and a second insulating layer; A first metal structure is embedded within the stack; At least one gap is disposed above the first metal structure and formed within the stack; A second metal structure is disposed above the at least one gap; The second metal structure, the at least one void, and the first metal structure together form a crack-stopping structure that is substantially perpendicular to the surface of the semiconductor substrate. The second metal structure includes a metal block body and a plurality of extensions extending downward from the metal block body; The first metal structure includes metal support portions that correspond one-to-one with the extension portions; A gap is provided above one of the metal support parts, and an extension is provided above the gap.

2. The semiconductor integrated circuit structure according to claim 1, characterized in that, Also includes: An inter-metal dielectric layer is formed on the at least one stack; The metal block body is embedded in the inter-metal dielectric layer, and the extension extends from the inter-metal dielectric layer into the stack.

3. The semiconductor integrated circuit structure according to claim 1, characterized in that, The first insulating layer is an interlayer dielectric layer; The second insulating layer is a cover layer.

4. The semiconductor integrated circuit structure according to claim 1, characterized in that, Also includes: At least one contact hole tungsten plug is formed within the stack and positioned between the first metal structure and the semiconductor substrate; A shallow trench isolation structure is formed within a semiconductor substrate beneath the first metal structure.

5. A slicing track structure, characterized in that, Includes the semiconductor integrated circuit structure described in any one of claims 1 to 4.

6. The slicing track structure according to claim 5, characterized in that, The paving structure also includes a waterproof and seepage-proof structure.

7. A method for manufacturing a semiconductor integrated circuit structure, characterized in that, For preparing the semiconductor integrated circuit structure according to any one of claims 1 to 4, comprising: Provide semiconductor substrates; At least one stack is formed on the semiconductor substrate; the stack includes a first insulating layer and a second insulating layer; A first metal structure is embedded within the stack; At least one void is formed within the at least one stack, the void being disposed above the first metal structure; A second metal structure is formed above the at least one gap using a damascus inlay method, such that the second metal structure, the at least one gap, and the first metal structure together form a crack-stopping structure that is substantially perpendicular to the surface of the semiconductor substrate. The formation of at least one void within the at least one stack includes: At least one first connecting hole is formed on the at least one stacked layer by photolithography and etching. Based on the first connecting hole, a void is formed in the stack; The formation of a void within the stack based on the first connecting hole includes: A layer of interlayer dielectric metal is deposited on top of all the layers to seal one end of the first connecting via; Photolithography and etching of the intermetallic dielectric layer are used to form a second connecting hole that communicates with the first connecting hole on the first connecting hole; The intermetallic dielectric layer is etched again to expand the upper part of the second connecting hole into a trench for filling the metal and to form a gap using the first connecting hole below the second connecting hole.

8. The method for manufacturing a semiconductor integrated circuit structure according to claim 7, characterized in that, The formation of the second metal structure above the at least one gap includes: Metal is filled into the trench and the second connecting hole to form the second metal structure.

9. The method for manufacturing a semiconductor integrated circuit structure according to claim 7, characterized in that, The re-etching of the intermetallic dielectric layer includes: The depth and upper width of the second via are increased by etching the inter-metal dielectric layer, wherein the depth of the second via increases while the depth of the first via decreases accordingly.

10. The method for manufacturing a semiconductor integrated circuit structure according to claim 7, characterized in that, The photolithography and etching of the intermetallic dielectric layer include: performing simultaneous photolithography and etching on the intermetallic dielectric layer within the crack-stopping structure, waterproofing structure, and sealing ring structure on the wafer. The re-etching of the intermetallic dielectric layer includes: forming grooves for filling metal on the intermetallic dielectric layer within the crack-stopping structure, the waterproofing structure, and the sealing ring structure by etching.

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