Method of manufacturing a flash memory device

Abstract

The present invention provides a method for manufacturing a flash memory device. A gate structure is formed on a substrate, and a tunneling oxide layer and a word line are formed on both sides of the gate structure. The tunneling oxide layer covers the substrate, and the word line covers the sidewalls of the gate structure and a part of the top surface of the tunneling oxide layer; the exposed part of the tunneling oxide layer is thinned; a first sidewall is formed to cover a part of the sidewalls of the word line and a part of the top surface of the tunneling oxide layer, and a recess is formed at the surface of the word line not covered by the first sidewall; a self-aligned silicide blocking layer with an opening is formed to expose at least the gate structure, the word line, and the first sidewall. By thinning the thickness of the tunneling oxide layer, the present invention reduces or avoids damage to the tunneling oxide layer during subsequent etching processes. By controlling the etching process time of the self-aligned silicide blocking layer, the residual oxide in the recess is reduced or avoided, ensuring the formation of a good metal silicide layer in the subsequent process, reducing the contact resistance of the flash memory device, and improving the performance and stability of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly to a method for manufacturing a flash memory device. Background Art

[0002] As a non-volatile memory, a flash memory device has the characteristics of convenience, high storage density, strong reliability, etc., and is widely used. The structure of an existing flash memory device usually includes a split-gate structure, a stacked-gate structure or a combination thereof. Among them, the split-gate flash memory device has the characteristic of high programming efficiency.

[0003] Figure 1 is a schematic structural diagram of a split-gate flash memory device. Referring to Figure 1 , in the process of forming the spacer 20 on the sidewall of the word line 10, it is usually necessary to first deposit a spacer material layer (not shown in the figure), and then form the spacer 20 through a dry etching process. However, the word line 10 is also slightly etched in the dry etching process, resulting in a dimple area 11 on the surface of the word line 10. In the subsequent manufacturing process, oxide residues will be generated in the dimple area 11, resulting in poor quality of the metal silicide layer (such as cobalt silicide) on the surface of the word line 10, thereby affecting the stability of the contact resistance of the flash memory device.

[0004] In view of this, the present invention provides a method to reduce or avoid the problem of unstable contact resistance of a flash memory device caused by poor formation of the metal silicide layer. Summary of the Invention

[0005] One of the purposes of the present invention is to reduce or avoid the occurrence of oxide residues in the dimples on the surface of the word line and ensure the formation of a good metal silicide layer subsequently; another purpose of the present invention is to reduce or avoid damage to the tunneling oxide layer during the etching process of the self-aligned silicide blocking layer, so as to improve the performance and stability of the flash memory device.

[0006] To achieve the above object, the present invention provides a method for manufacturing a flash memory device, including:

[0007] Providing a substrate, on which a gate structure is formed, and a tunneling oxide layer and a word line are formed on both sides of the gate structure. The tunneling oxide layer covers the substrate, and the word line covers the sidewall of the gate structure and a part of the top surface of the tunneling oxide layer;

[0008] Thinning the exposed part of the tunneling oxide layer;

[0009] Forming a first spacer, the first spacer covering a part of the sidewall of the word line and a part of the top surface of the tunneling oxide layer, and forming a dimple at the surface of the word line not covered by the first spacer; and,

[0010] Form a self-aligned silicide blocking layer, and form an opening in the self-aligned silicide blocking layer through an etching process, where the opening exposes at least the gate structure, the word line, and the first sidewall.

[0011] Optionally, the thickness of the thinned tunneling oxide layer is 40% - 70% of the thickness of the tunneling oxide layer before thinning.

[0012] Optionally, a wet etching process is used to form the opening in the self-aligned silicide blocking layer, and the set process time is 280 sec - 350 sec.

[0013] Optionally, the self-aligned silicide blocking layer fills the recess, and the self-aligned silicide blocking layer in the recess is removed when the opening is formed in the self-aligned silicide blocking layer by a wet etching process.

[0014] Optionally, the self-aligned silicide blocking layer and the tunneling oxide layer are made of the same material.

[0015] Optionally, the process of forming the first sidewall and the recess includes:

[0016] Form a first sidewall material layer that covers at least the surface of the word line and a part of the top surface of the tunneling oxide layer;

[0017] Use a dry etching process to etch the first sidewall material layer, and only retain the first sidewall material layer on a part of the sidewall of the word line to form the first sidewall, and at the same time form the recess on the surface of the word line.

[0018] Optionally, after forming the opening, it further includes:

[0019] Form a metal silicide layer that covers the gate structure, the word line, and the first sidewall.

[0020] Optionally, the material of the metal silicide layer includes cobalt silicide.

[0021] Optionally, the gate structure includes an erase gate formed on the substrate and floating gates formed on both sides of the erase gate.

[0022] Optionally, the manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.

[0023] In summary, the present invention provides a method for manufacturing a flash memory device. A gate structure is formed on a substrate, and a tunneling oxide layer and a word line are formed on both sides of the gate structure. The tunneling oxide layer covers the substrate, and the word line covers the sidewalls of the gate structure and a part of the top surface of the tunneling oxide layer; the exposed part of the tunneling oxide layer is thinned; a first sidewall is formed to cover a part of the sidewalls of the word line and a part of the top surface of the tunneling oxide layer, and a depression is formed on the surface of the word line not covered by the first sidewall; a self-aligned silicide blocking layer with an opening is formed, and the opening exposes at least the gate structure, the word line, and the first sidewall. By thinning the thickness of the tunneling oxide layer, the present invention reduces or avoids damage to the tunneling oxide layer during the etching process of the self-aligned silicide blocking layer. By controlling the etching process time of the self-aligned silicide blocking layer, oxide residues in the depression on the surface of the word line are reduced or avoided, ensuring the formation of a good metal silicide layer subsequently, thereby reducing the contact resistance of the flash memory device and improving the performance and stability of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. is a schematic structural diagram of a split-gate flash memory device;

[0025] Figures 2 to 5 FIG. is a schematic structural diagram corresponding to some steps in a method for manufacturing a flash memory device;

[0026] Figure 6 FIG. is a flowchart of a method for manufacturing a flash memory device provided by an embodiment of the present invention;

[0027] Figures 7 to 13 FIG. is a schematic structural diagram corresponding to each step in a method for manufacturing a flash memory device provided by an embodiment of the present invention;

[0028] Among them, the reference numerals are as follows:

[0029] 10 - word line; 11 - depression region; 20 - sidewall;

[0030] 100 - substrate; 110 - gate structure; 111 - erase gate; 112 - floating gate; 120 - tunneling oxide layer; 121 - second depression; 130 - word line; 131 - first depression; 140 - word line sidewall; 150 - self-aligned silicide blocking layer; 151 - opening; 160 - metal silicide layer.

[0031] 200 - substrate; 210 - gate structure; 211 - erase gate; 212 - floating gate; 213 - second sidewall; 214 - third sidewall; 215 - fourth sidewall; 216 - protective layer; 220 - tunneling oxide layer; 230 - word line; 231 - depression; 240 - first sidewall; 241 - first sidewall material layer; 250 - self-aligned silicide blocking layer; 251 - opening; 260 - metal silicide layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The specific embodiments of the present invention will be described in more detail below in conjunction with the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the attached drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0033] Figures 2 - 4 It is a schematic structural diagram corresponding to some steps in the manufacturing method of a flash memory device.

[0034] First, refer to Figure 2 , a substrate 100 is provided. A gate structure 110 is formed on the surface of the substrate 100. A tunneling oxide layer 120 and a word line 130 are formed on both sides of the gate structure 110. The tunneling oxide layer 120 covers the substrate 100, and the word line 130 covers the side walls of the gate structure 110 and a part of the top surface of the tunneling oxide layer 120 close to the gate structure 110. Optionally, the gate structure 110 includes an erase gate 111 and floating gates 112 formed on both sides of the erase gate 111. A first sidewall (not marked in the figure) is further formed on the surface of the floating gate 112. A second sidewall (not marked in the figure) is further formed between the floating gate 112 and the erase gate 111, and the second sidewall covers the side wall of the first sidewall. A third sidewall (not marked in the figure) is further formed between the floating gate 112 and the word line 130, and the third sidewall covers the side wall of the first sidewall. A protective layer (not marked in the figure) is formed on the surface of the erase gate 111. Optionally, the tunneling oxide layer is a silicon oxide layer.

[0035] Next, refer to Figure 3 , a word line sidewall 140 is formed on the exposed part of the tunneling oxide layer, and the word line sidewall 140 covers a part of the side wall of the word line 130. Specifically, the process of forming the word line sidewall 140 includes: forming a word line sidewall material layer (not shown in the figure) that at least covers the word line 130 and the tunneling oxide layer 120, and using a dry etching process to remove the word line sidewall material layer located outside the side wall of the word line 130 to form the word line sidewall 140. Optionally, the word line sidewall 140 is an ONO stacked structure (i.e., a structure formed by sequentially stacking silicon oxide, silicon nitride, and silicon oxide). It should be noted that continuing to refer to Figure 3 , since the word line sidewall 140 only covers a part of the top surface of the word line 130, therefore, the word line 130 will also be slightly damaged in the above dry etching process, and a first depression 131 is formed on the surface of the word line 130 that is not covered by the word line sidewall 130.

[0036] Subsequently, refer to Figure 4, a self-aligned silicide blocking layer 150 covering the substrate 100, the gate structure 110, the word line 130, and the word line sidewall 140 is formed, and an opening 151 is formed in the self-aligned silicide blocking layer by a wet etching process, and the opening 151 exposes at least the gate structure 110, the word line 130, and the word line sidewall 140. Optionally, the self-aligned silicide blocking layer 150 is a silicon oxide layer. It should be noted that the self-aligned silicide blocking layer 150 fills the first recess 131 on the surface of the word line 130, and in the subsequent wet etching process, the self-aligned silicide blocking layer 150 filled in the first recess 131 is completely removed.

[0037] However, continuing to refer to Figure 4 , since the tunneling oxide layer 120 and the self-aligned silicide blocking layer 150 are made of the same material, which is silicon oxide, therefore, in the wet etching process, the tunneling oxide layer 120 is also etched and a second recess 121 is formed. During the subsequent formation of the metal silicide layer 160 (refer to Figure 5 ), voids 122 are likely to occur at the second recess 121, thus affecting the performance of the flash memory device.

[0038] To solve the above problems, the present invention provides a method for manufacturing a flash memory device. By thinning the thickness of the tunneling oxide layer, the tunneling oxide layer is reduced or avoided from being damaged in the etching process of the self-aligned silicide blocking layer. By controlling the etching process time of the self-aligned silicide blocking layer, oxide residues in the recesses on the surface of the word line are reduced or avoided, ensuring the subsequent formation of a good metal silicide layer, thereby reducing the contact resistance of the flash memory device and improving the performance and stability of the flash memory device.

[0039] Figure 6 FIG. is a flowchart of a method for manufacturing a flash memory device provided by an embodiment of the present invention. Refer to Figure 6 , the method for manufacturing the flash memory device described in this embodiment includes:

[0040] Step S01: Provide a substrate, a gate structure is formed on the substrate, tunneling oxide layers and word lines are formed on both sides of the gate structure, the tunneling oxide layer covers the substrate, and the word line covers the sidewalls of the gate structure and a part of the top surface of the tunneling oxide layer;

[0041] Step S02: Thin the exposed part of the tunneling oxide layer;

[0042] Step S03: Form a first sidewall, the first sidewall covers a part of the sidewalls of the word line and a part of the top surface of the tunneling oxide layer, and a recess is formed on the surface of the word line not covered by the first sidewall; and,

[0043] Step S04: Form a self-aligned silicide blocking layer, and form an opening in the self-aligned silicide blocking layer through an etching process, where the opening exposes at least the gate structure, the word line, and the first sidewall.

[0044] Figures 7 - 13 Structural schematic diagrams corresponding to each step in the manufacturing method of the flash memory device described in this embodiment are as follows. The following will be combined with Figures 7 - 13 to detail the manufacturing method of the flash memory device described in this embodiment.

[0045] First, refer to Figure 7 , step S01: Provide a substrate 200, on which a gate structure 210 is formed. Tunneling oxide layers 220 and word lines 230 are formed on both sides of the gate structure 210. The tunneling oxide layer 220 covers the substrate 200, and the word line 230 covers the sidewalls of the gate structure 210 and part of the top surface of the tunneling oxide layer 220. In this embodiment, the gate structure 210 includes an erase gate 211 formed on the substrate 200 and floating gates 212 formed on both sides of the erase gate 211. A second sidewall 213 is formed on the surface of the floating gate 212. A third sidewall 214 is formed between the floating gate 212 and the erase gate 211, and the third sidewall 214 covers the sidewall of the second sidewall 213. A fourth sidewall 215 is formed between the floating gate 212 and the word line 230, and the fourth sidewall 215 covers the sidewall of the second sidewall 213. A protective layer 216 is formed on the surface of the erase gate 211.

[0046] Specifically, the process of forming the tunneling oxide layer 220 and the word line 230 includes: successively forming a floating gate material layer (not shown in the figure) and a hard mask layer (not shown in the figure) on the substrate 200, forming a hard mask layer opening (not shown in the figure) on the hard mask layer to expose the floating gate material layer, and forming a second sidewall 213 on the sidewall of the hard mask layer opening; etching the floating gate material layer using the hard mask layer and the second sidewall 213 as masks, so that the hard mask layer opening exposes the substrate 200; forming a third sidewall 214 on the sidewall and bottom of the hard mask layer opening, and forming an erase gate 211 in the hard mask layer opening; forming a protective layer 216 covering the erase gate 211; removing the hard mask layer and the floating gate material layer under the hard mask layer to form the floating gate 212; forming a fourth sidewall 215 on the sidewall of the floating gate 212 and the second sidewall 213 on the side opposite to the erase gate 211, and forming the tunneling oxide layer 220 on the substrate 200 on the side of the floating gate 212 opposite to the erase gate 211; forming the word line 230 on the sidewall of the fourth sidewall 215 opposite to the floating gate 212. It should be noted that in other embodiments of the present invention, other process flows may also be used to form the tunneling oxide layer 220 and the word line 230, and the present invention does not limit this.

[0047] In this embodiment, the substrate 200 is a silicon substrate, the erase gate 211, the floating gate 212, and the word line 230 are all polysilicon layers, and the materials of the second sidewall 213, the third sidewall 214, the fourth sidewall 215, the protective layer 216, and the tunneling oxide layer 220 all include silicon oxide. In other embodiments of the present invention, the materials and structures of the above-mentioned respective film layers can be adjusted according to actual needs, and the present invention does not limit this.

[0048] Next, refer to Figure 8 , perform step S02 to thin the exposed part of the tunneling oxide layer 220. In this embodiment, a wet etching process is used to thin the tunneling oxide layer 220, and the thickness of the thinned tunneling oxide layer 220 is 40% - 70% of the thickness of the tunneling oxide layer 220 before thinning.

[0049] Subsequently, refer to Figure 9 and Figure 10, perform step S03 to form a first sidewall 240. The first sidewall 240 covers a partial sidewall of the word line 230 and a partial top surface of the tunneling oxide layer 220, and a depression 231 is formed at a surface of the word line 230 not covered by the first sidewall. In this embodiment, the first sidewall 240 is an ONO stacked structure (Oxide-Nitride-Oxide, that is, a stacked structure formed by stacking an oxide, a nitride, and an oxide). Specifically, the process of forming the first sidewall 240 and the depression 231 includes: Refer to Figure 9 , form a first sidewall material layer 241, and the first sidewall material layer 241 covers at least the surface of the word line 230 and a partial top surface of the tunneling oxide layer 220; and, etch the first sidewall material layer 241 by a dry etching process, and only retain the first sidewall material layer 241 on a partial sidewall of the word line 230 to form the first sidewall 240, and at the same time form the depression 231 on the surface of the word line 230.

[0050] Subsequently, refer to Figure 11 and Figure 12 , perform step S04 to form a self-aligned silicide blocking layer 250 (Silicide Alignment Block, SAB), and form an opening 251 in the self-aligned silicide blocking layer 250 through an etching process. The opening 251 exposes at least the gate structure 210, the word line 230, and the first sidewall 240. Optionally, the opening 251 is formed by a wet etching process, and the set process time is 280 sec to 350 sec. It should be noted that the self-aligned silicide blocking layer 250 fills the depression 231, and when the opening 251 is formed in the self-aligned silicide blocking layer 250 by a wet etching process, the self-aligned silicide blocking layer 250 in the depression 231 is removed. By controlling the process time of the wet etching process, it can be ensured that the self-aligned silicide blocking layer 250 filled in the depression 231 is completely removed, so as to avoid the influence of the residual oxide on the normal formation of the subsequent metal silicide layer.

[0051] In this embodiment, the material of the self-aligned silicide blocking layer 250 is the same as that of the tunneling oxide layer 220, and both include silicon oxide. Since the thickness of the tunneling oxide layer 220 is thinned in step S02, therefore, the sidewall of the tunneling oxide layer 220 exposed in the wet etching process of the self-aligned silicide blocking layer 250 is reduced, reducing or avoiding the possibility of damage and depression of the tunneling oxide layer 220 in this wet etching process.

[0052] In addition, refer to Figure 13, after forming the opening 251, the method for manufacturing a flash memory device according to this embodiment further includes: forming a metal silicide layer 260 that covers the gate structure 210, the word line 230, and the first sidewall 240. Optionally, the material of the metal silicide layer 260 includes cobalt silicide.

[0053] In this embodiment, the method for manufacturing a flash memory device is used to manufacture a split-gate flash memory device. In other embodiments of the present invention, the method for manufacturing a flash memory device can be used to manufacture other semiconductor devices with the same or similar structures, and the present invention does not limit this.

[0054] Comparison Figure 1 and Figure 13 It can be seen that the method for manufacturing a flash memory device according to this embodiment ensures that there is no oxide residue in the depression 231 on the surface of the word line 230 by controlling the process time of the wet etching of the self-aligned silicide blocking layer 250, reducing or avoiding the problem of poor quality of the subsequently formed metal silicide layer caused by oxide residue. Comparison Figure 5 and Figure 13 It can be seen that the method for manufacturing a flash memory device according to this embodiment reduces or avoids the possibility of damage to the tunneling oxide layer 220 during the wet etching process of the self-aligned silicide blocking layer 250 by thinning the thickness of the tunneling oxide layer 220, thereby reducing or avoiding the possibility of voids appearing on the sidewalls of the tunneling oxide layer 220 when forming the metal silicide layer 260 subsequently, and improving the performance and stability of the flash memory device.

[0055] In summary, the present invention provides a method for manufacturing a flash memory device, which forms a gate structure on a substrate, with a tunneling oxide layer and a word line formed on both sides of the gate structure. The tunneling oxide layer covers the substrate, and the word line covers the sidewalls of the gate structure and part of the top surface of the tunneling oxide layer; the exposed part of the tunneling oxide layer is thinned; a first sidewall is formed to cover part of the sidewalls of the word line and part of the top surface of the tunneling oxide layer, and a depression is formed on the surface of the word line not covered by the first sidewall; a self-aligned silicide blocking layer with an opening is formed, and the opening exposes at least the gate structure, the word line, and the first sidewall. The present invention thins the thickness of the tunneling oxide layer to reduce or avoid damage to the tunneling oxide layer during the etching process of the self-aligned silicide blocking layer, and controls the etching process time of the self-aligned silicide blocking layer to reduce or avoid oxide residue in the depression on the surface of the word line, ensuring the formation of a good metal silicide layer subsequently, thereby reducing the contact resistance of the flash memory device and improving the performance and stability of the flash memory device.

[0056] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a flash memory device, characterized in that, Including: Providing a substrate, on which a gate structure is formed, a tunneling oxide layer and a word line are formed on both sides of the gate structure, the tunneling oxide layer covers the substrate, and the word line covers the sidewalls of the gate structure and part of the top surface of the tunneling oxide layer; Thinning the exposed part of the tunneling oxide layer, wherein the thickness of the thinned tunneling oxide layer is 40% - 70% of the thickness of the tunneling oxide layer before thinning; Forming a first sidewall, the first sidewall covers part of the sidewalls of the word line and part of the top surface of the tunneling oxide layer, and a recess is formed at the surface of the word line not covered by the first sidewall; and, Forming a self-aligned silicide blocking layer, and forming an opening in the self-aligned silicide blocking layer by a wet etching process, the opening exposes at least the gate structure, the word line and the first sidewall, wherein the etching time of the wet etching process is 280 sec - 350 sec.

2. The manufacturing method of the flash memory device according to claim 1, characterized in that, The self-aligned silicide blocking layer fills the recess, and the self-aligned silicide blocking layer in the recess is removed when the opening is formed in the self-aligned silicide blocking layer by the wet etching process.

3. The manufacturing method of the flash memory device according to claim 1, characterized in that, The self-aligned silicide blocking layer and the tunneling oxide layer are made of the same material.

4. The manufacturing method of the flash memory device according to claim 1, characterized in that, The process of forming the first sidewall and the recess includes: Forming a first sidewall material layer, the first sidewall material layer covers at least the surface of the word line and part of the top surface of the tunneling oxide layer; and, Etching the first sidewall material layer by a dry etching process, only retaining the first sidewall material layer on part of the sidewalls of the word line to form the first sidewall, and at the same time forming the recess on the surface of the word line.

5. The manufacturing method of the flash memory device according to claim 1, characterized in that, After forming the opening, it further includes: Forming a metal silicide layer, the metal silicide layer covers the gate structure, the word line and the first sidewall.

6. The manufacturing method of the flash memory device according to claim 5, characterized in that, The material of the metal silicide layer includes cobalt silicide.

7. The manufacturing method of the flash memory device according to claim 1, characterized in that, The gate structure includes an erase gate formed on the substrate and floating gates formed on both sides of the erase gate.

8. The manufacturing method of the flash memory device as described in claim 1, characterized in that, The manufacturing method of the flash memory device is used to manufacture a split-gate flash memory device.

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