Photoetching alignment mark structure

Abstract

The utility model provides a photoetching alignment mark structure which comprises a substrate, a dielectric substance layer located on the substrate and a photoetching alignment mark located in the dielectric substance layer, and a groove is formed in the photoetching alignment mark. Compared with the prior art in which photoetching alignment marks are formed in dielectric substance layers which are sequentially positioned on the substrate and the self-alignment silicide, the photoetching alignment mark is formed in the dielectric substance layer positioned on the substrate, so that the definition of the photoetching alignment mark can be improved, and the optical alignment precision and the overlay precision are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a photolithography alignment mark structure. Background Art

[0002] During the photolithography process, a critical step in accurately transferring the mask pattern onto the wafer is aligning the mask and wafer. This involves calculating the position of the mask relative to the wafer to ensure overlay accuracy. As feature sizes decrease, the requirements for overlay accuracy, and the resulting alignment accuracy, become increasingly stringent. The complete chip manufacturing process typically involves dozens to twenty photolithography passes. Except for the initial pass, each subsequent pass requires alignment of the pattern on that layer with the pattern left behind by the previous layer before exposure. This alignment process occurs during the reticle placement and wafer exposure phases, aiming to overlay the mask pattern onto the existing wafer pattern with maximum precision. This process primarily involves the mask alignment system and the wafer alignment system.

[0003] There are two main photolithography alignment solutions in the existing technology. One is the through-the-lens (TTL) alignment technology, which uses a laser to illuminate the alignment marks on the mask and image them on the wafer surface through an objective lens. The wafer machine is moved so that the reference marks on the wafer machine scan the image of the alignment marks. At the same time, the intensity of the image is used. The position with the maximum light intensity received by the detector indicates the correct alignment position.

[0004] The other is the OA off-axis alignment technology, which uses an off-axis alignment system to measure multiple alignment marks on the wafer and the reference marks on the reference plate on the wafer machine to achieve alignment between the wafer and the wafer machine. Then, the reference marks on the wafer machine are aligned with the alignment marks on the mask to achieve alignment between the mask and the wafer machine. In this way, the positional relationship between the mask and the wafer can be obtained, and the mask and wafer can be aligned.

[0005] However, in the prior art, during photolithography alignment, the scanning machine often fails to find a strong enough ECG Mark (Enhanced Global Alignment Mark) signal, i.e., the ECG Mark has low recognizability, and an alarm is triggered, causing the process to be unable to continue. Utility Model Content

[0006] The utility model aims to provide a photolithography alignment mark structure, wherein the photolithography alignment mark is clearly visible, thereby improving optical alignment and overlay accuracy.

[0007] To solve the above technical problems, the present invention provides a photolithography alignment mark structure, comprising: a substrate, a dielectric layer located on the substrate, a photolithography alignment mark located in the dielectric layer, and a groove formed in the photolithography alignment mark.

[0008] Optionally, the depth of the groove is greater than or equal to 1 μm and less than or equal to 10 μm.

[0009] Optionally, the bottom of the photolithography alignment mark is lower than or flush with the upper surface of the substrate.

[0010] Optionally, a metal silicide layer is further formed between the dielectric layer and the substrate.

[0011] Optionally, the bottom of the photolithography alignment mark contacts the surface of the metal silicide layer.

[0012] Optionally, the distance between the bottom of the photolithography alignment mark and the upper surface of the substrate is greater than 0 and less than or equal to 100 nm.

[0013] Optionally, the dielectric layer is a single-layer structure or a multi-layer stacked structure.

[0014] Optionally, the dielectric layer is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer or a combination thereof.

[0015] Optionally, the upper surface of the photolithography alignment mark is flush with the upper surface of the dielectric layer.

[0016] Optionally, the photolithography alignment mark is made of a metal material, and portions of the metal material are exposed on both sides of the groove.

[0017] In summary, the present invention provides a photolithography alignment mark structure comprising a substrate, a dielectric layer located on the substrate, and a photolithography alignment mark located within the dielectric layer, wherein a groove is formed within the photolithography alignment mark. Compared to the prior art method of forming photolithography alignment marks in dielectric layers located sequentially on the substrate and salicide, the present invention forms the photolithography alignment mark in the dielectric layer located on the substrate, thereby improving the clarity of the photolithography alignment mark and thereby enhancing optical alignment accuracy and overlay accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0019] Figure 1 It is a schematic diagram of a photolithography alignment mark structure in the prior art.

[0020] Figure 2This is a schematic diagram of a photolithography alignment mark structure provided by an embodiment of the present invention.

[0021] Figure 3 This is a flow chart of a method for manufacturing a photolithography alignment mark structure provided by one embodiment of the present invention.

[0022] Description of reference numerals:

[0023] 10 - substrate; 11 - self-aligned silicide barrier layer; 12 - self-aligned silicide layer; 13 - dielectric layer; 141 - first deep trench; 142 - second deep trench; 143 - third deep trench; 144 - groove; 15 - photolithography alignment mark; 16 - first metal plug; 17 - second metal plug. DETAILED DESCRIPTION

[0024] Figure 1 This is a schematic diagram of the photolithography alignment mark structure in the prior art. Figure 1 As shown, the steps of forming the photolithography alignment mark structure mainly include: forming a salicide blocking layer 11 on a substrate 10, wherein the salicide blocking layer 11 covers an area where salicide does not need to be formed, and forming a salicide layer 12 on the substrate 10 not covered by the salicide blocking layer 11; forming a dielectric layer 13 on the salicide blocking layer 11 and the salicide layer 12, wherein the dielectric layer 13 covers the salicide blocking layer 11 and the salicide layer 12 and has a flat upper surface; forming a third deep trench 143 in the dielectric layer 13 on the salicide blocking layer 11, and filling the third deep trench 143 with a metal material to form a photolithography alignment mark 15, wherein a groove 144 is formed in the photolithography alignment mark 15.

[0025] Simultaneously with the formation of the third deep trench 143, a first deep trench 141 exposing the salicide layer 12 and a second deep trench 142 exposing the salicide barrier layer 11 are also formed in the dielectric layer 13. Simultaneously with the filling of the third deep trench 143 with metal material, both the first deep trench 141 and the second deep trench 142 are filled with metal material. The first deep trench 141 is filled with metal material to form a first metal plug 16 contacting the active area, while the second deep trench 142 is filled with metal material to form a second metal plug 17 contacting the gate, source, or drain. The third deep trench 143 is filled with metal material, and a recess 144 is formed within the metal material to serve as a photolithography alignment mark 15.

[0026] Since the third deep trench 143 is formed on the self-aligned silicide barrier layer 11, the depth of the third deep trench 143 is less than the depth of the first deep trench 141. When the first deep trench 141, the second deep trench 142 and the third deep trench 143 are filled with metal material, when the metal material fills the first deep trench 141 and the second deep trench 142, the metal material has also filled most of the third deep trench 143, so that the depth of the groove 144 not filled with the metal material is relatively small, that is, the height difference between the bottom of the groove 144 and the dielectric layer 13 is relatively small, for example, the height difference is only The groove 144 is too shallow, so that the scanning machine cannot clearly identify the photolithography alignment mark 15, thereby causing the machine to alarm.

[0027] In response to the above problem, the inventors discovered through research that the third deep trench 143 is disposed in the dielectric layer 13 located on the substrate 10, rather than in the dielectric layer 13 located on the self-aligned silicide barrier layer 11 as mentioned above. In this way, the depth of the third deep trench 143 is increased. When the first deep trench 141 is filled, the space in the third deep trench 143 that is not filled by the metal material is relatively large, and the groove 144 formed thereby is relatively deep, so that the photolithography alignment mark is clearly visible, thereby improving the optical alignment and overlay accuracy.

[0028] After further research, the utility model provides a photolithography alignment mark structure, including: a substrate, a dielectric layer located on the substrate, a photolithography alignment mark located in the dielectric layer, and a groove formed in the photolithography alignment mark.

[0029] Compared with the prior art in which the photolithography alignment marks are formed in a dielectric layer sequentially located on a substrate and a self-aligned silicide layer, the present invention forms the photolithography alignment marks in a dielectric layer located on a substrate, which can improve the clarity of the photolithography alignment marks, thereby improving the optical positioning accuracy and overlay accuracy.

[0030] To further clarify the objectives, advantages, and features of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are highly simplified and not drawn to scale, and are intended solely to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often portions of the actual structures. In particular, different drawings may require different emphases and may use different scales.

[0031] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. As used in the present application, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in the present application, the term "plurality" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. As used in the present application, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," are used merely for descriptive purposes and are not necessarily intended to signify relative importance or a quantity of the specified technical features. Thus, features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features.

[0032] Figure 2 is a schematic view of a photoetching alignment mark structure provided by an embodiment of the present application. As shown in Figure 2 , the photoetching alignment mark structure includes a substrate 10, a dielectric layer 13 on the substrate 10, a photoetching alignment mark 15 in the dielectric layer 13, and a groove 144 formed in the photoetching alignment mark 15.

[0033] In an embodiment of the present application, the depth of the groove 144 is greater than or equal to 1 μm and less than or equal to 10 μm. For example, the depth of the groove 144 is 1 μm, 3 μm, 5 μm, 7 μm, or 10 μm, and the depth of the groove 144 is preferably 5 μm.

[0034] In an embodiment of the present application, the bottom of the photoetching alignment mark 15 is lower than or flush with the upper surface of the substrate 10. For example, when the photoetching alignment mark 15 is formed in the dielectric layer 13, the dielectric layer 13 is first etched to form a deep groove (for example, the third deep groove 143 in Figure 2 ), and a material is filled in the third deep groove 143 to form the photoetching alignment mark 15. In this case, the third deep groove 143 exposes the substrate 10, i.e., the bottom of the third deep groove 143 is flush with the upper surface of the substrate 10. Alternatively, the third deep groove 143 can extend to the substrate 10, i.e., the bottom of the third deep groove 143 is lower than the upper surface of the substrate 10.

[0035] In another embodiment of the present application, the bottom of the photoetching alignment mark 15 is higher than the upper surface of the substrate 10, i.e., the bottom of the photoetching alignment mark 15 also has a portion of the thickness of the dielectric layer 13, and the third deep groove 143 does not expose the substrate 10.

[0036] In an embodiment of the present application, a metal silicide layer 12 is further formed between the dielectric layer 13 and the substrate 10, and the thickness of the metal silicide layer 12 is less than or equal to 100 nm, that is, the distance between the bottom of the lithography alignment mark 15 and the upper surface of the substrate 10 is greater than 0 and less than or equal to 100 nm, and of course, it is not limited to this. In this embodiment, the third deep trench 143 exposes the metal silicide layer 12, and the lithography alignment mark 15 is flush with the upper surface of the metal silicide layer 12. In another embodiment, the third deep trench 143 does not expose the metal silicide layer 12, the bottom of the lithography alignment mark 15 is higher than the upper surface of the metal silicide layer 12, and the bottom of the lithography alignment mark 15 also has a partial thickness of the dielectric layer 13.

[0037] In an embodiment of the present application, the dielectric layer 13 is a single-layer structure or a multi-layer laminated structure, and for example, the dielectric layer 13 is one or a combination of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, the dielectric layer 13 is a single-layer structure, and the dielectric layer 13 is a silicon oxide layer; or the dielectric layer 13 is a laminated structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0038] Please refer to Figure 2 In the present application, the lithography alignment mark 15 has two upper surfaces, the first upper surface is flush with the upper surface of the dielectric layer 13, and the second upper surface is lower than the first upper surface, the second upper surface is the bottom surface of the groove 144, and the first upper surface and the second upper surface have a height difference so that the lithography alignment mark 15 is recognized by the scanning machine.

[0039] In an embodiment of the present application, the lithography alignment mark 15 is a metal material, and part of the metal material is exposed on both sides of the groove 144, that is, the groove 144 is completely located in the lithography alignment mark 15, and at the same horizontal height, the cross-sectional size of the groove 144 is smaller than the cross-sectional size of the third deep trench 143.

[0040] Please refer to Figure 2As shown, a salicide blocking layer 11 is also formed on the substrate 10. The salicide blocking layer 11 covers the area of ​​the substrate 10 where salicide is not required to be formed. A salicide layer 12 is formed on the substrate 10 not covered by the salicide blocking layer 11. In the present invention, the photolithography alignment mark 15 is formed above the salicide layer 12, rather than above the salicide blocking layer 11. In other words, the salicide blocking layer 11 is removed from the area where the photolithography alignment mark 15 is to be formed. The dielectric layer 13 covers the salicide blocking layer 11 and the salicide layer 12.

[0041] While forming the third deep trench 143, a first deep trench 141 and a second deep trench 142 are also formed in the dielectric layer 13. The first deep trench 141 is located in the active area and exposes the salicide layer 12. The second deep trench 142 is located in the dielectric layer 13 on the salicide blocking layer 11 and exposes the salicide blocking layer 11. The depth of the third deep trench 143 is equal to the depth of the first deep trench 141 and greater than the depth of the second deep trench 142. The cross-sectional dimensions of the third deep trench 143 are greater than those of the second deep trench 142, and the cross-sectional dimensions of the second deep trench 142 are greater than those of the first deep trench 141. This ensures that when the first deep trench 141 and the second deep trench 142 are subsequently filled, the third deep trench 143 is not fully filled.

[0042] While filling the metal material to form the photolithography alignment mark 15, the first deep trench 141 and the second deep trench 142 are also filled to form a first metal plug 16 and a second metal plug 17. The first metal plug 16 is used to contact the active area, and the second metal plug 17 is used to contact the gate, source, or drain, etc., but the present invention is not limited to these. In this embodiment, the first metal plug 16 and the second metal plug 17 are metal plugs connected to the first metal layer in the interconnect structure.

[0043] Figure 3 This is a flow chart of a method for manufacturing a photolithography alignment mark structure provided by an embodiment of the present invention. Figure 2 and Figure 3 As shown, the method for forming the photolithography alignment mark 15 is briefly introduced.

[0044] In step S1, a substrate 10 is provided, and a salicide blocking layer 11 and a salicide layer 12 are formed on the substrate 10. Exemplarily, a salicide blocking material layer is formed on the substrate 10, and the salicide blocking material layer is patterned to expose the area where salicide is to be formed, thereby forming a salicide blocking layer 11 covering the area where salicide is not to be formed. Then, a salicide layer 12 is formed on the substrate 10 using the salicide blocking layer 11 as a mask. In this embodiment, the salicide layer 12 is located in the active area and also in the area where the photolithography alignment mark 15 is to be formed.

[0045] In step S2, a dielectric layer 13 is formed, which covers the salicide barrier layer 11 and the salicide layer 12. The dielectric layer 13 is a single-layer structure or a multi-layer stacked structure, and is one or more combinations of silicon oxide layers, silicon nitride layers, and silicon oxynitride layers.

[0046] In step S3, the dielectric layer 13 is etched to form a first deep trench 141 and a third deep trench 143 that expose the salicide layer 12, and a second deep trench 142 that exposes the salicide barrier layer 11. The cross-sectional dimensions of the third deep trench 143 are larger than those of the first deep trench 141.

[0047] In step S4, a metal material is filled to form a first metal plug 16, a second metal plug 17, and a photolithography alignment mark 15. The metal material is filled to fill the first deep trench 141 and the second deep trench 142, while covering the sidewalls and bottom of the third deep trench 143, forming a recess 144 in the third deep trench 143. The first metal plug 16 is formed in the first deep trench 141, the second metal plug 17 is formed in the second deep trench 142, and the photolithography alignment mark 15 is formed in the third deep trench 143.

[0048] Since the third deep trench 143 is formed in the dielectric layer 13 located on the substrate 10, the depth of the third deep trench 143 is the same as the depth of the first deep trench 141. When the cross-sectional size of the third deep trench 143 is larger than the cross-sectional size of the first deep trench 141, when the first deep trench 141 is filled, the metal material only covers the sidewalls and bottom of the third deep trench 143, that is, the groove 144 formed in the third deep trench 143 is relatively deep, so that the photolithography alignment mark 15 can be clearly seen, thereby improving the recognition of the photolithography alignment mark 15 by the scanning machine, thereby improving the optical alignment and overlay accuracy.

[0049] In summary, the present invention provides a photolithography alignment mark structure comprising a substrate; a dielectric layer located on the substrate; and a photolithography alignment mark located within the dielectric layer, wherein a groove is formed within the photolithography alignment mark. Compared to the prior art method of forming photolithography alignment marks in dielectric layers located sequentially on the substrate and salicide, the present invention forms the photolithography alignment marks in the dielectric layer located on the substrate, thereby improving the clarity of the photolithography alignment marks and thereby enhancing optical alignment and overlay accuracy.

[0050] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A photolithography alignment mark structure, characterized in that: include: A substrate, a dielectric layer located on the substrate, a third deep trench located in the dielectric layer, and a photolithography alignment mark formed in the third deep trench, wherein the depth of the third deep trench is equal to the depth of a first deep trench in the dielectric layer for forming a first metal plug, and the cross-sectional size of the third deep trench is larger than the cross-sectional size of the first deep trench, and the photolithography alignment mark has two upper surfaces, a first upper surface is flush with the dielectric layer, and a second upper surface is lower than the first upper surface, so that a groove is formed in the photolithography alignment mark.

2. The photolithography alignment mark structure according to claim 1, wherein: The depth of the groove is greater than or equal to 1 μm and less than or equal to 10 μm.

3. The photolithography alignment mark structure according to claim 1, wherein: The bottom of the photolithography alignment mark is lower than or flush with the upper surface of the substrate.

4. The photolithography alignment mark structure according to claim 1, wherein: A metal silicide layer is formed between the dielectric layer and the substrate.

5. The photolithography alignment mark structure according to claim 4, wherein: The bottom of the photolithography alignment mark contacts the surface of the metal silicide layer.

6. The photolithography alignment mark structure according to claim 5, wherein: The distance between the bottom of the photolithography alignment mark and the upper surface of the substrate is greater than 0 and less than or equal to 100 nm.

7. The photolithography alignment mark structure according to claim 1, wherein: The dielectric layer is a single-layer structure or a multi-layer stacked structure.

8. The photolithography alignment mark structure according to claim 7, wherein: The dielectric layer is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

9. The photolithography alignment mark structure according to claim 1, wherein: The photolithography alignment mark is made of metal material, and portions of the metal material are exposed on both sides of the groove.

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