Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: a substrate having a fin and an interlayer dielectric layer covering part of the fin, the interlayer dielectric layer having a gate opening formed therein, the fin partially in the gate opening as a channel fin, and source-drain doping layers formed in the fin on both sides of the gate opening, wherein the source-drain doping layers include a drain doping layer on one side of the gate opening; performing an amorphization treatment on the channel fin and the drain doping layer in a position where the channel fin and the drain doping layer are in contact, to form a transition layer; and performing an annealing treatment on the transition layer, to convert part of the channel fin in the transition layer into a doping extension layer, the doping extension layer having a first ion with a same conductivity type as that of the ions in the source-drain doping layers, and the first ion having a lower ion concentration than the ions in the source-drain doping layers. The doping extension layer slows down the doping concentration gradient of the drain doping layer, and improves the reliability of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to suppress the short-channel effect, the industry usually uses lightly doped drain (LDD) ion implantation on the semiconductor substrates on both sides of the gate stack structure to create an ultrashallow junction to improve the SCE effect. Furthermore, the ion distribution implanted by LDD and other methods is further optimized by pre-amorphization implantation (PAI) and the introduction of stress into the channel to improve device performance.

[0004] However, in practice, it has been found that these methods cannot completely eliminate the short-channel effect and high leakage current problem, and still cannot meet the requirements for further improvement of MOSFET device performance. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the reliability of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, on which fins are formed, and a gate structure spanning the fins is also formed on the substrate, the gate structure covering a portion of the top and sidewalls of the fins, and the portion of the fins covered by the gate structure serving as a channel fin; source / drain doped layers located in the fins on both sides of the gate structure, wherein the source / drain doped layers include a drain doped layer located on one side of the gate structure; and a doped extension layer located in a portion of the channel fin adjacent to the drain doped layer and in contact with the drain doped layer, the doped extension layer having conductive first ions, the first ions having the same conductivity type as the ions in the source / drain doped layers, and the doping concentration of the first ions being less than the doping concentration of the source / drain doped layers.

[0007] Optionally, the semiconductor structure further includes: a sidewall located on the sidewall of the gate structure; the source / drain doped layer extending along the extension direction of the fin to below the adjacent sidewall; and the doped extension layer located in the exposed portion of the channel fin of the sidewall and in contact with the drain doped layer located below the sidewall.

[0008] Optionally, the doping concentration of the source / drain doped layers decreases along the direction away from the gate structure and towards the gate structure.

[0009] Optionally, the doped extension layer may also contain a non-conductive second ion.

[0010] Optionally, the second ion includes silicon ions or germanium ions.

[0011] Optionally, the ion concentration of the second ion is from 1E18 atoms / cm3 to 1E19 atoms / cm3.

[0012] Optionally, the gate structure includes a metal gate structure.

[0013] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a fin is formed on the substrate and an interlayer dielectric layer covering a portion of the fin, a gate opening is formed in the interlayer dielectric layer spanning the fin, the gate opening exposing a portion of the top and a portion of the sidewall of the fin, and a portion of the height of the fin in the gate opening serves as a channel fin, and source / drain doped layers are formed in the fins on both sides of the gate opening, wherein the source / drain doped layers include a drain doped layer located on one side of the gate opening; in the extension direction of the fin, at the position where the drain doped layer and the channel fin contact, performing an amorphization treatment on a portion of the width of the channel fin and a portion of the width of the drain doped layer that are in contact to form a transition layer; annealing the transition layer to convert a portion of the channel fin in the transition layer into a doped extension layer, the doped extension layer having a conductive first ion, the first ion having the same conductivity type as the ions in the source / drain doped layer, and the doping concentration of the first ion being less than the doping concentration of the source / drain doped layer.

[0014] Optionally, the amorphization process can be performed by ion implantation.

[0015] Optionally, in the step of providing the substrate, the sidewall of the gate opening is further formed with a sidewall; the source and drain doped layer extends along the extension direction of the fin to below the adjacent sidewall; in the step of performing the ion implantation process, the portion of the channel fin exposed by the sidewall and the portion of the drain doped layer in contact with the channel fin are subjected to the ion implantation process.

[0016] Optionally, the implanted ions in the ion implantation process are non-conductive second ions.

[0017] Optionally, the second ion includes silicon ions or germanium ions.

[0018] Optionally, the process parameters of the ion implantation process include: the angle between the ion implantation direction and the normal direction of the substrate surface is 5° to 15°.

[0019] Optionally, the process parameters of the ion implantation process include: the angle between the projection of the ion beam on the substrate surface and the extension direction of the fin is 0° to 45°.

[0020] Optionally, the process parameters of the ion implantation process include: the ion implantation energy is 2 KeV to 10 KeV, and the ion implantation dose is 1E13 atms / cm2 to 1E14 atmos / cm2.

[0021] Optionally, the annealing temperature is 700°C to 900°C, and the annealing time is 30 seconds to 30 minutes.

[0022] Optionally, the doping concentration of the source / drain doped layer decreases in the direction away from the gate opening and towards the gate opening.

[0023] Optionally, before forming the gate opening, a dummy gate structure spanning the fin is formed in the interlayer dielectric layer, the dummy gate structure covering a portion of the top and a portion of the sidewalls of the fin, and the top of the dummy gate structure is exposed in the interlayer dielectric layer; the step of forming the gate opening includes: removing the dummy gate structure and forming the gate opening in the interlayer dielectric layer; after forming the doped extension layer, the step further includes: forming a gate structure in the gate opening, the gate structure covering a portion of the top and a portion of the sidewalls of the fin.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] This invention provides a semiconductor structure including source and drain doped layers located in fins on both sides of a gate structure. The source and drain doped layers include a drain doped layer on one side of the gate structure. A doped extension layer is located in a channel fin of a portion width adjacent to the drain doped layer and is in contact with the drain doped layer. The doped extension layer contains conductive first ions, which have the same conductivity type as the ions in the source and drain doped layers, and the concentration of the first ions is lower than the concentration of the ions in the source and drain doped layers. The doped extension layer mitigates the doping concentration gradient of the drain doped layer, thereby reducing the junction leakage current and the electric field near the drain doped layer in the semiconductor structure. Therefore, it improves the hot carrier injection (HCI) effect and increases the breakdown voltage (BV) of the semiconductor structure, thus enhancing the reliability of the semiconductor structure.

[0026] In the formation method provided by this embodiment of the invention, the gate opening exposes a portion of the top and a portion of the sidewall of the fin, and a portion of the fin at the height of the gate opening serves as a channel fin. Source and drain doped layers are formed in the fins on both sides of the gate opening. The source and drain doped layers include a drain doped layer located on one side of the gate opening. At the contact point between the drain doped layer and the channel fin, a portion of the contacting channel fin and a portion of the contacting drain doped layer are amorphized to form a transition layer. The transition layer is annealed to transform a portion of the channel fin in the transition layer into a doped extension layer. The doped extension layer contains conductive first ions, the first ions having the same conductivity type as the ions in the source and drain doped layers, and the concentration of the first ions being less than the concentration of the ions in the source and drain doped layers. In the transition layer formed by the amorphization process, the contacting portion of the channel fin and the portion of the drain doped layer generate interstitial defects due to amorphization, thereby enhancing the junction diffusion of the drain doped layer. If the diffusion capability is improved, the transition layer is then annealed. The interstitial defects in the transition layer recrystallize due to lattice repair. At the same time, ions in the drain doped layer diffuse into the channel fins in the transition layer during the lattice repair process. Therefore, a portion of the channel fins in the transition layer forms a doped extension layer by acquiring the diffused ions. The doped extension layer reduces the doping concentration gradient of the drain doped layer, thereby reducing the junction leakage current of the semiconductor structure and the electric field near the drain doped layer. Thus, the hot electron injection effect is improved, and the breakdown voltage of the semiconductor structure is increased, thereby improving the reliability of the semiconductor structure. Attached Figure Description

[0027] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure;

[0028] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0029] Figures 4 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0030] The reliability of semiconductor structures currently needs improvement. This paper analyzes the reasons why the reliability of a semiconductor structure needs to be improved, using a specific semiconductor structure formation method as an example.

[0031] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1 A substrate 10 is provided, on which fins 20 are formed and an interlayer dielectric layer 40 covering a portion of the fins 20 is formed. A gate opening 52 is formed in the interlayer dielectric layer 40, spanning the fins 20. The gate opening 52 exposes a portion of the top and a portion of the sidewalls of the fins 20. Source and drain doped layers 30 are formed in the fins 20 on both sides of the gate opening 52, wherein the source and drain doped layers 30 include a drain doped layer 31 located on one side of the gate opening 52.

[0033] refer to Figure 2 A gate structure 70 is formed in the gate opening 52, and the gate structure 70 covers part of the top and part of the sidewall of the fin 20.

[0034] Because the device channel length of the semiconductor structure is relatively short, the dopant ion concentration gradient in the source / drain doped layer 30 is still relatively large after its formation. This is especially true for the drain doped layer 31, where the dopant ion concentration is even higher and the steep ion concentration distribution is more pronounced. This results in an excessively large dopant ion concentration gradient in the drain doped layer 31, leading to an excessively strong electric field. Consequently, the drain doped layer 31 is prone to internal electron bombardment of other film layers, which in turn affects the reliability of the semiconductor structure.

[0035] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which fins and an interlayer dielectric layer covering a portion of the fins are formed, a gate opening spanning the fins is formed in the interlayer dielectric layer, the gate opening exposing a portion of the top and a portion of the sidewalls of the fins, and a portion of the height of the fins in the gate opening serving as a channel fin, and source / drain doped layers formed in the fins on both sides of the gate opening, wherein the source / drain doped layers include a drain doped layer located on one side of the gate opening; in the extending direction of the fins, at the location where the drain doped layer and the channel fins contact, performing an amorphization treatment on a portion of the width of the channel fins and a portion of the width of the drain doped layer that are in contact to form a transition layer; annealing the transition layer to convert a portion of the channel fins in the transition layer into a doped extension layer, the doped extension layer having a conductive first ion, the first ion having the same conductivity type as the ions in the source / drain doped layer, and the ion concentration of the first ion being less than the ion concentration of the source / drain doped layer.

[0036] In the formation method provided by this embodiment of the invention, the gate opening exposes a portion of the top and a portion of the sidewall of the fin, and a portion of the fin at the height of the gate opening serves as a channel fin. Source and drain doped layers are formed in the fins on both sides of the gate opening. The source and drain doped layers include a drain doped layer located on one side of the gate opening. At the contact point between the drain doped layer and the channel fin, a portion of the contacting channel fin and a portion of the contacting drain doped layer are amorphized to form a transition layer. The transition layer is annealed to transform a portion of the channel fin in the transition layer into a doped extension layer. The doped extension layer contains conductive first ions, the first ions having the same conductivity type as the ions in the source and drain doped layers, and the concentration of the first ions being less than the concentration of the ions in the source and drain doped layers. In the transition layer formed by the amorphization process, the contacting portion of the channel fin and the portion of the drain doped layer generate interstitial defects due to amorphization, thereby enhancing the junction diffusion of the drain doped layer. If the diffusion capability is improved, the transition layer is then annealed. The interstitial defects in the transition layer recrystallize due to lattice repair. At the same time, ions in the drain doped layer diffuse into the channel fins in the transition layer during the lattice repair process. Therefore, a portion of the channel fins in the transition layer forms a doped extension layer by acquiring the diffused ions. The doped extension layer reduces the doping concentration gradient of the drain doped layer, thereby reducing the junction leakage current of the semiconductor structure and the electric field near the drain doped layer. Thus, the hot electron injection effect is improved, and the breakdown voltage of the semiconductor structure is increased, thereby improving the reliability of the semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0039] The semiconductor structure includes: a substrate 101 on which fins 201 are formed, and a gate structure 701 spanning the fins 201 is also formed on the substrate 101. The gate structure 701 covers a portion of the top and a portion of the sidewalls of the fins 201, and the portion of the height of the fins 201 covered by the gate structure 701 serves as a channel fin 211; a source / drain doped layer 301 located in the fins 201 on both sides of the gate structure 701, wherein the source / drain doped layer 301 includes a drain doped layer 311 located on one side of the gate structure 701; and a doped extension layer 611 located in the channel fin 211 of a portion of its width adjacent to the drain doped layer 311 and in contact with the drain doped layer 311. The doped extension layer 611 has conductive first ions, the first ions having the same conductivity type as the ions in the source / drain doped layer 301, and the doping concentration of the first ions being less than the doping concentration of the source / drain doped layer 301.

[0040] The doped extension layer 611 mitigates the doping concentration gradient of the drain doped layer 311, thereby reducing the junction leakage current of the semiconductor structure and the electric field near the drain doped layer. As a result, the hot carrier injection (HCI) effect is improved, and the breakdown voltage (BV) of the semiconductor structure is increased, thus improving the reliability of the semiconductor structure.

[0041] The substrate 101 provides the basis for the process operation of forming the semiconductor structure.

[0042] The substrate 101 includes a substrate.

[0043] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be a material suitable for process requirements or easy to integrate.

[0044] The fin 201 is used to provide a channel for a fin field-effect transistor, wherein a portion of the height of the fin 201 serves as a channel fin 211, which serves as a channel for the fin field-effect transistor.

[0045] In this embodiment, the fin 201 and the substrate are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0046] In this embodiment, the material of the fin 201 is the same as the material of the substrate, which is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0047] The gate structure 701 is a device gate structure used to control the opening or closing of the channel of the fin field-effect transistor.

[0048] In this embodiment, the gate structure 701 includes a metal gate structure.

[0049] In this embodiment, the metal gate structure includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0050] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0051] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0052] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0053] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0054] In this embodiment, the extending direction of the fin 201 (e.g.) Figure 3 The direction shown in the X direction is perpendicular to the extension direction of the gate structure 521, that is, the gate structure of the device is orthogonal to the fin 201.

[0055] The source / drain doped layer 301 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 301 is the same as the channel conductivity type of the corresponding transistor.

[0056] In this embodiment, the source / drain doped layer 301 includes a drain doped layer 311 located on one side of the gate structure 701, which serves as part of the drain region of the formed fin field-effect transistor.

[0057] In this embodiment, the doping concentration of the source / drain doped layer 301 decreases along the direction away from the gate structure 701 and towards the gate structure 701.

[0058] Specifically, the source / drain doped layer 301 includes a multi-layered stacked first sub-doped layer 321, second sub-doped layer 331, and third sub-doped layer 341. Along the direction from away from the gate structure 701 to near the gate structure 701, the concentration of doped ions in the first sub-doped layer 321, second sub-doped layer 331, and third sub-doped layer 341 decreases. That is, the third sub-doped layer 341, which is closest to the channel fin 211, has the lowest concentration, while the first sub-doped layer 321, located on the outermost surface of the source / drain doped layer 301, has the highest concentration.

[0059] The doping concentration of the source and drain doped layers 301 decreases from the direction away from the gate structure 701 to the direction closer to the gate structure 701. That is, the doped ions inside the drain doped layer 311 have a certain concentration gradient, which is beneficial to reduce the junction leakage current of the semiconductor structure and the electric field near the drain doped layer, thereby improving the reliability of the semiconductor structure.

[0060] Furthermore, a source / drain plug electrically connected to the source / drain doped layer 301 will be formed on top of the source / drain doped layer 301. The first sub-doped layer 321 located on the outermost surface of the source / drain doped layer 301 has the highest concentration, which helps to reduce the contact resistance between the source / drain doped layer 301 and the source / drain plug.

[0061] The doped extension layer 611 and the drain doped layer 311 together serve as the drain region of the formed fin field-effect transistor.

[0062] In this embodiment, the doping concentration of the doped extension layer 611 is less than the doping concentration of the source / drain doped layer 301. Therefore, the doping concentration of the doped extension layer 611 is less than the doping concentration of the drain doped layer 311, which helps to reduce the doping concentration gradient in the drain region.

[0063] In this embodiment, the doped extension layer 611 also contains a non-conductive second ion.

[0064] The formation process of the doped extension layer 611 is as follows: Second ions are implanted into a portion of the channel fin and a portion of the drain doped layer at the contact point between the drain doped layer and the channel fin along the extension direction of the fin, forming a transition layer with gap defects. The transition layer is then annealed. Ions in the drain doped layer 311 undergo lattice repair as the gap defects are repaired. During annealing, ions in the drain doped layer diffuse into the channel fin 211 of the transition layer. The portion of the channel fin 211 receives the diffused ions and forms the doped extension layer 611. By using non-conductive second ions, the influence on the doping concentration of conductive ions in the doped extension layer 611 is reduced, thereby helping to mitigate the doping concentration gradient in the drain region.

[0065] Specifically, the second ion includes silicon ions or germanium ions. Silicon ions and germanium ions are not conductive, and the use of silicon ions or germanium ions facilitates the formation of interstitial defects, which in turn facilitates ion diffusion during the lattice repair process, forming the doped extension layer 611.

[0066] In this embodiment, the concentration of the second ion in the doped extension layer 611 is 1E18 atoms / cm². 3 Up to 1E19 atmos / cm 3 .

[0067] The concentration of the second ion in the doped extension layer 611 cannot be too low or too high. If the concentration of the second ion in the doped extension layer 611 is too low, it means that the concentration of the second ion implanted during the formation of the doped extension layer 611 is too low. This makes it difficult for the contact portion of the channel fin and the portion of the drain doped layer to obtain sufficient gap defects, weakening the effect of lattice repair caused by repairing gap defects during subsequent annealing, and thus making it difficult to improve the reliability of the semiconductor structure. If the concentration of the ion in the doped extension layer 611 is too high, it means that the concentration of the second ion implanted during the formation of the doped extension layer 611 is too high. This can easily cause excessive lateral penetration, leading to a short-channel effect in the device. Simultaneously, an excessively high implanted ion concentration can easily lead to excessive gap defects that are difficult to repair. Therefore, in this embodiment, the concentration of the second ion in the doped extension layer 611 is 1E18 atoms / cm². 3 Up to 1E19 atmos / cm 3 .

[0068] In this embodiment, the semiconductor structure further includes a sidewall 511 located on the sidewall of the gate structure 701.

[0069] The sidewall 511 is used to protect the sidewall of the gate structure 701. At the same time, the sidewall 511 is also used to define the positions of the source / drain doped layer 301 and the doped extension layer 611.

[0070] The sidewall 511 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 511 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 511 is a single-layer structure, and the material of the sidewall 511 is silicon nitride.

[0071] In this embodiment, the source / drain doped layer 301 extends along the extension direction of the fin 201 to below the adjacent sidewall 511.

[0072] The source / drain doped layer 301 extends along the extension direction of the fin 201 to below the adjacent sidewall 511, increasing the area of ​​the source / drain doped layer 301 and correspondingly reducing the doping concentration gradient inside the source / drain doped layer 301.

[0073] Therefore, in this embodiment, the doped extension layer 611 is located in the exposed portion of the channel fin of the sidewall and is in contact with the drain doped layer 311 located below the sidewall 511. Based on the reduction of the doping concentration gradient inside the source and drain doped layer 301, the doping concentration gradient of the source and drain doped layer 301 is further reduced.

[0074] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0075] Figures 4 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0076] Reference Figure 4 and Figure 5 A substrate 100 is provided, on which fins 200 are formed and an interlayer dielectric layer 400 covering a portion of the fins 200. A gate opening 520 is formed in the interlayer dielectric layer 400, spanning the fins 200. The gate opening 520 exposes a portion of the top and a portion of the sidewalls of the fins 200, and a portion of the height of the fins 200 in the gate opening 520 serves as a channel fin 210. Source and drain doped layers 300 are formed in the fins 200 on both sides of the gate opening 520, wherein the source and drain doped layers 300 include a drain doped layer 310 located on one side of the gate opening 520.

[0077] The substrate 100 provides the basis for the process operation of forming the semiconductor structure.

[0078] The substrate 100 includes a substrate.

[0079] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be a material suitable for process requirements or easy to integrate.

[0080] The fin 200 is used to provide a channel for a fin field-effect transistor, wherein a portion of the height of the fin 200 serves as a channel fin 210, which serves as a channel for the fin field-effect transistor.

[0081] In this embodiment, the fin 200 and the substrate are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0082] In this embodiment, the material of the fin 200 is the same as the material of the substrate, which is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0083] The interlayer dielectric layer 400 serves to isolate adjacent devices.

[0084] The material of the interlayer dielectric layer 400 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0085] The gate opening 520 is used to provide space for the subsequent formation of the device gate structure.

[0086] In this embodiment, the extending direction of the fin 200 (e.g., Figure 4 (As shown in the X direction) is perpendicular to the extension direction of the gate opening 520, so that the gate structure of the subsequent device is orthogonal to the fin 200.

[0087] The source / drain doped layer 300 serves as the source or drain region of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor.

[0088] In this embodiment, the source / drain doped layer 300 includes a drain doped layer 310 located on one side of the gate opening 520, which serves as the drain region of the formed fin field-effect transistor.

[0089] In this embodiment, the doping concentration of the source / drain doped layer 300 decreases in the direction away from the gate opening 520 and towards the gate opening 520.

[0090] Specifically, the source / drain doped layer 300 includes a multi-layered stacked first sub-doped layer 320, second sub-doped layer 330, and third sub-doped layer 340. Along the direction from away from the gate opening 520 to near the gate opening 520, the concentration of doped ions in the first sub-doped layer 320, second sub-doped layer 330, and third sub-doped layer 340 decreases in that order. That is, the third sub-doped layer 340, which is closest to the channel fin 210, has the lowest concentration, while the first sub-doped layer 320, located on the outermost surface of the source / drain doped layer 300, has the highest concentration.

[0091] The doping concentration of the source and drain doped layers 300 decreases from the direction away from the gate opening 520 to the direction closer to the gate opening 520. That is, the doped ions inside the drain doped layer 310 have a certain concentration gradient, which is beneficial to reduce the junction leakage current of the semiconductor structure and the electric field near the drain doped layer, thereby improving the reliability of the semiconductor structure.

[0092] Furthermore, a source / drain plug that is electrically connected to the source / drain doped layer 300 will be formed on top of the source / drain doped layer 300. The first sub-doped layer 320 located on the outermost surface of the source / drain doped layer 300 has the highest concentration, which helps to reduce the contact resistance between the source / drain doped layer 300 and the source / drain plug.

[0093] In this embodiment, during the step of providing the substrate 100, a sidewall 510 is also formed on the sidewall of the gate opening 520.

[0094] The sidewall 510 is used to protect the sidewall of the device gate structure. At the same time, the sidewall 510 is also used to define the location of the source and drain doped layer 300 and the subsequent formation of the doped extension layer.

[0095] The sidewall 510 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 510 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 510 is a single-layer structure, and the material of the sidewall 510 is silicon nitride.

[0096] In this embodiment, the source / drain doped layer 300 extends along the extension direction of the fin 200 to below the adjacent sidewall 510.

[0097] The source / drain doped layer 300 extends along the extension direction of the fin 200 to below the adjacent sidewall 510, increasing the area of ​​the source / drain doped layer 300 and correspondingly reducing the doping concentration gradient inside the source / drain doped layer 300.

[0098] Specifically, refer to Figure 4 Before forming the gate opening 520, a pseudo-gate structure 500 is formed in the interlayer dielectric layer 400, spanning the fin 200. The pseudo-gate structure 500 covers part of the top and part of the sidewalls of the fin 200, and the top of the pseudo-gate structure 500 is exposed in the interlayer dielectric layer 400.

[0099] The dummy gate structure 500 is used to occupy space for the subsequent formation of the device gate structure. The interlayer dielectric layer 400 exposes the top of the dummy gate structure 500 to prepare for the formation of the gate opening 520.

[0100] In this embodiment, after forming the pseudo-gate structure 500 and forming the sidewall 510 on the sidewall of the pseudo-gate structure 500, and before forming the interlayer dielectric layer 400, the source / drain doped layer 300 is formed in the fins 200 on both sides of the pseudo-gate structure 500.

[0101] refer to Figure 5 The step of forming the gate opening 520 includes: removing the dummy gate structure 500 and forming the gate opening 520 in the interlayer dielectric layer 400.

[0102] The pseudo-gate structure 500 is removed to provide space for the subsequent formation of the device gate structure.

[0103] refer to Figure 6 In the extending direction of the fin 200 (e.g. Figure 6 In the X direction, at the position where the drain doped layer 310 and the channel fin 210 are in contact, the channel fin 210 and the drain doped layer 310 of a certain width in contact are subjected to amorphization treatment to form a transition layer 600.

[0104] The transition layer 600 formed by the amorphization process has gap defects, which are used to prepare for the lattice repair process caused by repairing gap defects during subsequent annealing, thereby converting part of the channel fin in the transition layer into a doped extension layer through annealing.

[0105] In this embodiment, the amorphization treatment is performed using an ion implantation process. The ion implantation process is used to create gap defects in the transition layer 600.

[0106] The ion implantation process is directional, facilitating amorphization of the channel fins 210 and drain doped layer 310 in the target region, and making it easier to control the formation location of the transition layer 600. Furthermore, the amorphization effect can be controlled by adjusting the parameters of the ion implantation process. At the same time, compared to plasma bombardment, the ion implantation process is more effective at localizing treatment and is easier to control.

[0107] Specifically, the ion implantation process is used to implant ions into the portion of the channel fin 210 exposed by the gate opening 520 and the portion of the drain doped layer 310 in contact with the channel fin 210.

[0108] In this embodiment, during the ion implantation process, ion implantation is performed on the exposed portion of the channel fin 210 of the sidewall 510 and the portion of the drain doped layer 310 in contact with the channel fin 210.

[0109] Since the source / drain doped layer 300 extends along the extension direction of the fin 200 to below the adjacent sidewall 510, and the drain doped layer 310 is blocked by the sidewall 510, it is necessary to perform ion implantation on the portion of the channel fin 210 exposed by the sidewall 510 and the portion of the drain doped layer 310 in contact with the channel fin 210. Therefore, by using an ion implantation process and adjusting the implantation angle, it is easy to implant ions into the drain doped layer 310 below the sidewall 510. Moreover, during the ion implantation process, the sidewall 510 also protects the interlayer dielectric layer 400 of the gate opening 520 sidewall.

[0110] In this embodiment, the implanted ions in the ion implantation process are non-conductive second ions.

[0111] Specifically, the second ion includes silicon ions or germanium ions. Silicon ions and germanium ions are non-conductive, have high process compatibility, and by using silicon ions or germanium ions, it is beneficial to generate gap defects in the formed transition layer 600, and to cause lattice repair process by repairing gap defects during subsequent annealing. Moreover, gap defects generated during silicon ion and germanium ion implantation are also relatively easy to repair.

[0112] In this embodiment, the implanted ions in the ion implantation process are silicon ions. Since the channel fin 210 is made of silicon in this embodiment, implanting silicon ions makes the process more compatible, forming amorphous silicon with gap defects.

[0113] In this embodiment, the process parameters of the ion implantation process include: the ion implantation direction and the normal direction of the surface of the substrate 100 (e.g., ...). Figure 6The included angle α (in the Y direction) is 5° to 15°.

[0114] The angle α between the ion implantation direction and the normal direction of the substrate 100 surface cannot be too large or too small. If the angle α between the ion implantation direction and the normal direction of the substrate 100 surface is too large, the ion implantation direction is too close to being parallel to the substrate 100 surface, and too many ions are implanted onto the sidewall 510 surface, making it difficult to implant into the portion of the channel fin 210 and the portion of the drain doped layer 310 in contact with the channel fin 210. This results in the transition layer 600 area being too small, which in turn adversely affects the formation of subsequent doped extension layers. If the angle α between the ion implantation direction and the normal direction of the substrate 100 surface is too small, the ions are implanted onto the sidewall 510 surface, making it difficult to implant into the portion of the channel fin 210 and the portion of the drain doped layer 310 in contact with the channel fin 210. This results in the transition layer 600 area being too small, which in turn adversely affects the formation of subsequent doped extension layers. If the ion implantation direction is too close to being perpendicular to the surface of the substrate 100, too many ions will be implanted into the channel fin 210, making it difficult to implant into the portion of the drain doped layer 310 that contacts the channel fin 210. This results in the doped ions in the drain doped layer 310 having difficulty diffusing into the transition layer 600 during subsequent annealing and lattice repair, thus hindering the improvement of the semiconductor structure's reliability. Alternatively, the transition layer 600 may excessively occupy a position in the channel fin 210, potentially negatively impacting the channel fin's performance. Therefore, in this embodiment, the process parameters for the ion implantation process include an angle α between the ion implantation direction and the normal direction of the substrate 100 surface of 5° to 15°.

[0115] In this embodiment, the process parameters of the ion implantation process include: the angle between the projection of the ion beam on the surface of the substrate 100 and the extension direction of the fin 200 is 0° to 45°, so that ions can be implanted into the sidewall of the gate opening 520 and the corner of the fin 200.

[0116] The angle between the projection of the ion beam onto the surface of the substrate 100 and the extending direction of the fin 200 cannot be too large. If the angle between the projection of the ion beam onto the surface of the substrate 100 and the extending direction of the fin 200 is too large, most of the ions will be implanted into the end of the gate opening 520 along its extending direction, and it will be difficult to implant them into the portion of the width of the channel fin 210 and the portion of the width of the drain doped layer 310 that contacts the channel fin 210. This will result in the transition layer 600 being too small, which will adversely affect the formation of the subsequent doped extension layer. Therefore, in this embodiment, the process parameters of the ion implantation process include: the angle between the projection of the ion beam onto the surface of the substrate 100 and the extending direction of the fin 200 is 0° to 45°.

[0117] In this embodiment, the process parameters of the ion implantation process include: the ion implantation energy is 2 keV to 10 keV, and the ion implantation dose is 1 E13 atoms / cm. 2 Up to 1E14 atmos / cm 2 .

[0118] The ion implantation energy must be neither too high nor too low. If the ion implantation energy is too high, the ion beam will have excessive penetrating power, easily forming an excessively large transition layer 600, and potentially damaging other film layers. If the ion implantation energy is too low, the ion beam will have insufficient penetrating power, making it difficult to form a sufficiently large transition layer 600, thus affecting the formation quality of the subsequent doped extension layer, consequently impacting the process effect of the doped extension layer, and hindering the improvement of the semiconductor structure's reliability. Therefore, in this embodiment, the ion implantation energy is between 2 KeV and 10 KeV.

[0119] The ion implantation dose must be neither too high nor too low. If the ion implantation dose is too high, excessive lateral punch-through can easily occur, leading to a short-channel effect in the device. Simultaneously, the excessive ion concentration can result in excessive gap defects that are difficult to repair. If the ion implantation dose is too low, the formed transition layer 600 will not have sufficient gap defects, weakening the lattice repair effect caused by gap defect repair during subsequent annealing. It will also be difficult for dopant ions to diffuse from the drain doped layer 310 to the transition layer 600, making it difficult to mitigate the doping concentration gradient of the drain doped layer 310, and consequently, difficult to improve the reliability of the semiconductor structure. Therefore, in this embodiment, the ion implantation dose is 1E13 atoms / cm². 2 Up to 1E14 atmos / cm 2 .

[0120] refer to Figure 7 The transition layer 600 is annealed to convert a portion of the channel fin 210 in the transition layer 600 into a doped extension layer 610. The doped extension layer 610 contains conductive first ions. The first ions have the same conductivity type as the ions in the source / drain doped layer 300, and the ion concentration of the first ions is less than the ion concentration of the source / drain doped layer 300.

[0121] In the transition layer 600 formed by amorphization, interstitial defects are generated in the contact portion of the channel fin 210 and the portion of the drain doped layer 310 due to amorphization, thereby enhancing the junction diffusion capability of the drain doped layer 310. Then, the transition layer 600 is annealed, and the interstitial defects in the transition layer 600 recrystallize due to lattice repair. At the same time, ions in the drain doped layer 310 diffuse into the channel fin 210 in the transition layer 600 during the lattice repair process. Therefore, a portion of the channel fin 210 in the transition layer 600 forms a doped extension layer 610 by acquiring the diffused ions. The doped extension layer 610 reduces the doping concentration gradient of the drain doped layer 310, thereby reducing the junction leakage current of the semiconductor structure and the electric field near the drain doped layer. Therefore, the hot electron injection effect is improved, and the breakdown voltage of the semiconductor structure is increased, thereby improving the reliability of the semiconductor structure.

[0122] The doped extension layer 610 and the drain doped layer 310 together serve as the drain region of the formed fin field-effect transistor.

[0123] In this embodiment, the ion concentration of the first ion in the source / drain doped layer 300 is less than the ion concentration of the source / drain doped layer 300. Therefore, the ion concentration of the first ion is less than the doping concentration of the drain doped layer 310, which helps to reduce the doping concentration gradient in the drain region.

[0124] In this embodiment, the annealing temperature is 700°C to 900°C, and the annealing time is 30 seconds to 30 minutes.

[0125] The annealing temperature must not be too high or too low. If the annealing temperature is too high, excessive lateral punch-through can easily occur, leading to a short-channel effect in the device. Furthermore, excessively high temperatures can increase process costs and cause unnecessary waste. If the annealing temperature is too low, the recrystallization effect of the gap defects in the transition layer 600 due to lattice repair is poor. Simultaneously, it is difficult to achieve the desired diffusion of ions from the drain doped layer 310 into the channel fins 210 of the transition layer 600 during the lattice repair process, making it difficult to mitigate the doping concentration gradient of the drain doped layer 310 and consequently hindering the improvement of the semiconductor structure's reliability. Therefore, in this embodiment, the annealing temperature is between 700°C and 900°C.

[0126] The annealing process must be neither too long nor too short. If the annealing time is too long, excessive lateral penetration can occur, leading to a short-channel effect in the device. Furthermore, an excessively long processing time increases process costs and causes unnecessary waste. If the annealing time is too short, it is difficult to achieve sufficient recrystallization of gap defects in the transition layer 600 due to lattice repair. The diffusion effect of ions from the drain doped layer 310 into the channel fins 210 of the transition layer 600 during lattice repair is reduced, making it difficult to mitigate the doping concentration gradient of the drain doped layer 310, and consequently, to improve the reliability of the semiconductor structure. Therefore, in this embodiment, the annealing time is 30 seconds to 30 minutes.

[0127] It should be noted that when the transition layer 600 is annealed, the interstitial defects in the transition layer 600 recrystallize due to lattice repair. At the same time, the ions in the drain doped layer 310 diffuse into the channel fin portion 210 in the transition layer 600 during the lattice repair process. As a result, a portion of the channel fin portion 210 in the transition layer 600 forms a doped extension layer 610 by acquiring the diffused ions. Therefore, the doping concentration of the doped extension layer 610 decreases from near the drain doped layer 310 to far away from the drain doped layer 310, which is more conducive to mitigating the doping concentration gradient in the drain region where the doped extension layer 610 and the drain doped layer 310 together form the drain region.

[0128] refer to Figure 8 After forming the doped extension layer 610, the method further includes forming a gate structure 700 in the gate opening 520, the gate structure 700 covering a portion of the top and a portion of the sidewalls of the fin 200.

[0129] Correspondingly, the gate structure 700 also covers the doped extension layer 610 in the fin 200.

[0130] The gate structure 700 is a device gate structure used to control the opening or closing of the channel of the fin field-effect transistor.

[0131] In this embodiment, the gate structure 700 includes a metal gate structure.

[0132] In this embodiment, the metal gate structure includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0133] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0134] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0135] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0136] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0137] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate on which a fin is formed, and a gate structure spanning the fin is also formed on the substrate. The gate structure covers a portion of the top and a portion of the sidewalls of the fin, and the portion of the fin covered by the gate structure serves as a channel fin. Source and drain doped layers are located in the fins on both sides of the gate structure, wherein the source and drain doped layers include a drain doped layer located on one side of the gate structure; A doped extension layer is located in a channel fin portion adjacent to and in contact with the drain doped layer. The doped extension layer contains conductive first ions, which have the same conductivity type as the ions in the source and drain doped layers. The doping concentration of the first ions is less than that of the source and drain doped layers. The ions in the doped extension layer diffuse from the ions in the drain doped layer. The doping concentration of the doped extension layer is less than that of the drain doped layer. The doped extension layer and the drain doped layer together constitute the drain region.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a sidewall located on the sidewall of the gate structure; The source / drain doped layer extends along the extension direction of the fin to below the adjacent sidewall; The doped extension layer is located in the exposed portion of the channel fin of the sidewall and is in contact with the drain doped layer located below the sidewall.

3. The semiconductor structure as described in claim 1, characterized in that, The doping concentration of the source and drain doped layers decreases from the direction away from the gate structure to the direction closer to the gate structure.

4. The semiconductor structure as described in claim 1, characterized in that, The doped extended layer also contains a non-conductive second ion.

5. The semiconductor structure as described in claim 4, characterized in that, The second ion includes silicon ions or germanium ions.

6. The semiconductor structure as described in claim 4, characterized in that, The concentration of the second ion is 1E18 atoms / cm³. 3 Up to 1E19 atmos / cm 3 .

7. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a metal gate structure.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which fins are formed and an interlayer dielectric layer covering a portion of the fins are formed. A gate opening is formed in the interlayer dielectric layer that spans the fins. The gate opening exposes a portion of the top and a portion of the sidewalls of the fins. A portion of the height of the fins in the gate opening serves as a channel fin. Source and drain doped layers are formed in the fins on both sides of the gate opening. The source and drain doped layers include a drain doped layer located on one side of the gate opening. In the extending direction of the fin, at the position where the drain doped layer and the channel fin come into contact, the contact portion of the channel fin and the portion of the drain doped layer are subjected to amorphization treatment to form a transition layer. The transition layer is annealed to convert a portion of the channel fin in the transition layer into a doped extension layer. The doped extension layer contains conductive first ions. The first ions have the same conductivity type as the ions in the source / drain doped layer, and the concentration of the first ions is less than the concentration of the ions in the source / drain doped layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The amorphization process is performed by ion implantation.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, the sidewall of the gate opening is further formed with a sidewall; The source / drain doped layer extends along the extension direction of the fin to below the adjacent sidewall; In the ion implantation process, ion implantation is performed on the exposed width of the channel fin and the portion of the drain doped layer that contacts the channel fin.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The implanted ions in the ion implantation process are non-conductive second ions.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The second ion includes silicon ions or germanium ions.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters of the ion implantation process include: the angle between the ion implantation direction and the normal direction of the substrate surface is 5° to 15°.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters of the ion implantation process include: the angle between the projection of the ion beam on the substrate surface and the extension direction of the fin is 0° to 45°.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters for the ion implantation process include: an ion implantation energy of 2 keV to 10 keV, and an ion implantation dose of 1 E13 atoms / cm². 2 Up to 1E14 atmos / cm 2 .

16. The method for forming a semiconductor structure as described in claim 8, characterized in that, The annealing temperature is 700°C to 900°C, and the annealing time is 30 seconds to 30 minutes.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The doping concentration of the source and drain doped layers decreases from the direction away from the gate opening to the direction closer to the gate opening.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, Before forming the gate opening, a pseudo-gate structure is formed in the interlayer dielectric layer that spans the fin, the pseudo-gate structure covering part of the top and part of the sidewalls of the fin, and the top of the pseudo-gate structure is exposed in the interlayer dielectric layer. The step of forming the gate opening includes: removing the dummy gate structure and forming the gate opening in the interlayer dielectric layer; After forming the doped extension layer, the method further includes: forming a gate structure in the gate opening, the gate structure covering a portion of the top and a portion of the sidewalls of the fin.

Images