Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device. For a semiconductor device having a structure in which a buried electrode is provided under a gate trench electrode, hysteresis of gate leakage is reduced. A semiconductor device (100) has an active trench gate (11) formed in a trench reaching a drift layer (1) in contact with an emitter layer (13), a base layer (15), and a carrier accumulation layer (2). The active trench gate (11) has a gate trench insulating film (11b) formed on an inner wall of the trench, and a gate trench electrode (11a) and a buried electrode (11c) formed on the gate trench insulating film (11b) in the trench, insulated from each other, the buried electrode (11c) being disposed under the gate trench electrode (11a). The buried electrode (11c) has a lower phosphorus concentration than the gate trench electrode (11a).

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] From an energy-saving perspective, IGBTs (Insulated Gate Bipolar Transistors) and diodes are used in power modules for variable speed control of three-phase motors in fields such as general-purpose inverters and AC servos. To reduce inverter losses, these power modules require low switching losses and low on-state voltage in their IGBTs and diodes.

[0003] Trench-gate IGBTs with a gate electrode (gate trench electrode) formed within a trench are devices with low switching losses. In particular, IGBTs with a structure in which a buried electrode is provided below the gate trench electrode are known as devices with low gate capacitance (e.g., Patent Document 1 below). In IGBTs with both a gate trench electrode and a buried electrode, the gate trench electrode is connected to the gate potential, and the buried electrode is connected to the emitter potential. Thus, the gate trench electrode is shielded by the buried electrode, achieving low gate capacitance.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2020-077727

[0005] For IGBTs with gate trench electrodes and buried electrodes, phosphorus-doped polysilicon is typically used as the material for the gate trench electrodes and buried electrodes. However, if phosphorus segregates at the interface between the gate trench electrodes and buried electrodes and the insulating film (gate trench insulating film) disposed on their surfaces, the gate leakage hysteresis of the IGBT increases.

[0006] For example, when a positive bias is applied to the gate, electrons are easily captured by phosphorus segregations formed at the interface between the buried electrode and the gate trench insulating film, which increases the hysteresis of gate leakage (positive-side gate leakage). Conversely, when a negative bias is applied to the gate, electrons are easily captured by phosphorus segregations formed at the interface between the gate trench electrode and the gate trench insulating film, which also increases the hysteresis of gate leakage (negative-side gate leakage).

[0007] One of the reasons for phosphorus segregation at the interface between the buried electrode and the gate trench insulating film is that during the IGBT manufacturing process, the gate trench insulating film is formed after the buried electrode is formed, and therefore a large amount of heat treatment is applied to the buried electrode. Summary of the Invention

[0008] The present invention was proposed to solve the above-mentioned problems, and its purpose is to reduce the hysteresis of gate leakage in semiconductor devices with a structure having a buried electrode below the gate trench electrode.

[0009] The semiconductor device of the present invention comprises: a semiconductor substrate having a first main surface, a second main surface, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed on the semiconductor substrate at a location closer to the first main surface than the drift layer, and having a higher peak concentration of impurities compared to the drift layer; a base layer of a second conductivity type formed on the semiconductor substrate at a location closer to the first main surface than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type, which are formed on the semiconductor substrate and connected to the first main surface. The first main surface is contacted with the ground; and an active trench gate is formed in a trench that contacts the emitter layer, the base layer and the carrier accumulation layer to reach the drift layer. The active trench gate has: a gate trench insulating film formed on the inner wall of the trench; and a gate trench electrode and a buried electrode formed in the trench on the gate trench insulating film and insulated from each other. The buried electrode is disposed closer to the second main surface than the gate trench electrode, and the phosphorus concentration of the buried electrode is lower than that of the gate trench electrode.

[0010] The effects of the invention

[0011] According to the present invention, for a semiconductor device having a structure in which a buried electrode is provided below the gate trench electrode, the hysteresis of gate leakage can be reduced. Attached Figure Description

[0012] Figure 1 This is a top view of the semiconductor device involved in Embodiment 1.

[0013] Figure 2 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0014] Figure 3 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0015] Figure 4 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0016] Figure 5 This is a flowchart illustrating the manufacturing method of the semiconductor device according to Embodiments 1 to 5. Detailed Implementation

[0017] <Implementation Method 1>

[0018] Figure 1 This is a top view of the semiconductor device 100 according to Embodiment 1. Figure 2 This is a cross-sectional view of the semiconductor device 100. Figure 2 Show along Figure 1 A cross-section of line AA is shown. In this embodiment, an IGBT is shown as a component structure of the semiconductor device 100. However, the application of the technology involved in this invention is not limited to IGBTs, and can be widely used in power devices such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and RC-IGBTs (Reverse-Conducting IGBTs).

[0019] Furthermore, there are no particular limitations on the voltage rating of the semiconductor device 100 or the type of semiconductor substrate used in the semiconductor substrate 10 (e.g., FZ (Floating Zone) substrate, MCZ (Magnetic Field Applied Czochralski) substrate, epitaxial substrate, etc.). Besides silicon (Si), wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond can also be used as the material for the semiconductor substrate 10. High voltage withstand capability, low loss, and high heat resistance can be achieved by using wide-bandgap semiconductors.

[0020] The following explanation will use n-type and p-type as the first conductivity type and p-type as the second conductivity type for semiconductors. However, it is also possible to use p-type and n-type as the first conductivity type and p-type as the second conductivity type.

[0021] The semiconductor device 100 is formed using a semiconductor substrate 10 having a drift layer 1 of a first conductivity type (n-type). Here, [the following will be described]. Figure 1 The upper surface of the semiconductor substrate 10 is defined as the "first main surface", and the lower surface is defined as the "second main surface".

[0022] On the semiconductor substrate 10, a carrier accumulation layer 2 of a first conductivity type with a higher peak impurity concentration than the drift layer 1 is formed on the side closer to the first main surface than the drift layer 1. Furthermore, a base layer 15 of a second conductivity type (p-type) is formed on the side closer to the first main surface than the carrier accumulation layer 2. And, on the side closer to the first main surface than the base layer 15, an emitter layer 13 of the first conductivity type and a contact layer 14 of the second conductivity type with a higher peak impurity concentration than the base layer 15 are each formed to contact the first main surface.

[0023] Furthermore, a trench is formed on the first main surface of the semiconductor substrate 10, penetrating the emitter layer 13, the base layer 15, and the carrier accumulation layer 2 to reach the drift layer 1. Thus, the trench contacts the emitter layer 13, the base layer 15, and the carrier accumulation layer 2, and its bottom is located further along the second main surface than the boundary between the drift layer 1 and the carrier accumulation layer 2. An active trench gate 11 or a dumb trench gate 12 is formed within each trench.

[0024] The active trench gate 11 has a gate trench insulating film 11b formed on the inner wall of the trench, a gate trench electrode 11a formed on the gate trench insulating film 11b, and a buried electrode 11c. The buried electrode 11c is disposed further along the second main surface than the gate trench electrode 11a, and the gate trench insulating film 11b exists between the gate trench electrode 11a and the buried electrode 11c. That is, the gate trench electrode 11a and the buried electrode 11c are insulated from each other. Furthermore, the bottom of the gate trench electrode 11a is located further along the second main surface than the boundary between the base layer 15 and the carrier accumulation layer 2.

[0025] The dumb trench gate 12 is composed of a dumb trench insulating film 12b formed on the inner wall of the trench and a dumb trench electrode 12a formed on the dumb trench insulating film 12b. That is, the dumb trench gate 12 does not have a buried electrode. Furthermore, the semiconductor device 100 only needs to have at least one of the active trench gate 11 and the dumb trench gate 12, and the dumb trench gate 12 can be omitted.

[0026] An interlayer insulating film 4 covering the gate trench electrode 11a and the dumb trench electrode 12a is formed on the first main surface of the semiconductor substrate 10. An emitter electrode 6 is formed on the interlayer insulating film 4. The emitter electrode 6 is connected to the emitter layer 13 and the contact layer 14 through contact holes formed in the interlayer insulating film 4. In addition, the buried electrode 11c of the active trench gate 11 is connected to the emitter electrode 6 in a region not shown. Thus, the emitter electrode 6 is electrically connected to the active trench gate 11.

[0027] In this embodiment, the emitter electrode 6 has a blocking metal 5 disposed on its lower surface. The emitter electrode 6 can be made of metals such as Al or AlSi. The blocking metal 5 can be made of metals such as Ti, TiN, or TiSi. Alternatively, the emitter electrode 6 may also include a plug made of W or the like within the contact hole.

[0028] On the other hand, in the semiconductor substrate 10, a buffer layer 3 with a higher peak impurity concentration than the drift layer 1 is formed on the side closer to the second main surface than the drift layer 1. Furthermore, a collector layer 16 of the second conductivity type is formed to contact the second main surface on the side closer to the second main surface than the buffer layer 3. Additionally, a collector electrode 7 connected to the collector layer 16 is formed on the second main surface of the semiconductor substrate 10.

[0029] In Embodiment 1, the gate trench electrode 11a and the buried electrode 11c are formed of phosphorus-doped polysilicon. However, the phosphorus concentration in the buried electrode 11c is set to be lower than that in the gate trench electrode 11a. This reduces the phosphorus concentration in the buried electrode 11c, thereby reducing phosphorus segregation between the buried electrode 11c and the gate trench insulating film 11b, and decreasing the hysteresis of positive-side gate leakage. Furthermore, the phosphorus concentration in the dumb trench electrode 12a can be the same as that in the buried electrode 11c.

[0030] <Implementation Method 2>

[0031] The structure of the semiconductor device 100 according to Embodiment 2 is basically the same as... Figure 1 and Figure 2 The same applies. However, in Embodiment 2, a phosphorus-free material is used for the buried electrode 11c. Examples of materials for such a buried electrode 11c include undoped polysilicon, metals, and nitrogen-doped polysilicon. Compared to Embodiment 1, which uses phosphorus-doped polysilicon as the material for the buried electrode 11c, the resistance of the buried electrode 11c is higher when using undoped polysilicon, but the resistance of the buried electrode 11c can be reduced when using metals or nitrogen-doped polysilicon.

[0032] According to Embodiment 2, since the buried electrode 11c does not contain phosphorus, phosphorus segregation at the interface between the buried electrode 11c and the gate trench insulating film 11b can be prevented, thereby reducing the hysteresis of positive gate leakage. Furthermore, the dumb trench electrode 12a can also be made of the same material as the buried electrode 11c.

[0033] <Implementation Method 3>

[0034] Figure 3 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 3, and... Figure 2 Similarly, it shows along Figure 1 The cross section of line AA.

[0035] In embodiment 3, the surface portion of the buried electrode 11c, i.e., the portion in contact with the gate trench insulating film 11b, is formed of undoped polysilicon, while the inner portion is formed of phosphorus-doped polysilicon. That is, as... Figure 3 As shown, the buried electrode 11c is composed of a doped polysilicon layer 11c1 with phosphorus added at the center of the buried electrode 11c and an undoped polysilicon layer 11c2 located outside the doped polysilicon layer 11c1.

[0036] According to Embodiment 3, since the buried electrode 11c has an undoped polysilicon layer 11c2 on its surface, phosphorus segregation at the interface between the buried electrode 11c and the gate trench insulating film 11b can be prevented, thereby reducing the hysteresis of positive gate leakage. Furthermore, since the interior of the buried electrode 11c is a doped polysilicon layer 11c1, high resistance in the buried electrode 11c is prevented.

[0037] Furthermore, the structure of the dumb trench electrode 12a can also be the same as that of the buried electrode 11c, i.e., the portion in contact with the gate trench insulating film 11b is formed of undoped polysilicon, and the inner portion is formed of phosphorus-doped polysilicon. That is, it can also be as follows: Figure 3 As shown, the dumb trench electrode 12a is composed of a doped polysilicon layer 12a1 with phosphorus added at the center of the dumb trench electrode 12a and an undoped polysilicon layer 12a2 located outside the doped polysilicon layer 12a1.

[0038] <Implementation Method 4>

[0039] The structure of the semiconductor device 100 according to embodiment 4 is basically the same as... Figure 1 and Figure 2 The same applies. However, in Embodiment 4, a phosphorus-free material is used for the gate trench electrode 11a (of course, unlike Embodiment 1, the phosphorus concentration in the buried electrode 11c can also be higher than the phosphorus concentration in the gate trench electrode 11a). Examples of materials for such a gate trench electrode 11a include undoped polysilicon, metal, and nitrogen-doped polysilicon. Compared to Embodiment 1, which uses phosphorus-doped polysilicon as the material for the gate trench electrode 11a, the resistance of the gate trench electrode 11a increases when using undoped polysilicon, but the resistance of the gate trench electrode 11a can be reduced when using metal or nitrogen-doped polysilicon.

[0040] According to embodiment 4, since the gate trench electrode 11a does not contain phosphorus, phosphorus segregation at the interface between the gate trench electrode 11a and the gate trench insulating film 11b can be prevented, thereby reducing the hysteresis of negative gate leakage.

[0041] <Implementation Method 5>

[0042] Figure 4 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 5, and... Figure 2 Similarly, it shows along Figure 1 The cross section of line AA.

[0043] In embodiment 5, the surface portion of the gate trench electrode 11a, i.e., the portion in contact with the gate trench insulating film 11b, is formed of undoped polysilicon, while the inner portion is formed of phosphorus-doped polysilicon. That is, as... Figure 4 As shown, the gate trench electrode 11a is composed of a doped polysilicon layer 11a1 with phosphorus added to the center of the gate trench electrode 11a and an undoped polysilicon layer 11a2 located outside the doped polysilicon layer 11a1.

[0044] According to Embodiment 5, since the gate trench electrode 11a has an undoped polysilicon layer 11a2 on its surface, phosphorus segregation at the interface between the gate trench electrode 11a and the gate trench insulating film 11b can be prevented, thereby reducing the hysteresis of negative-side gate leakage. Furthermore, since the interior of the gate trench electrode 11a is a doped polysilicon layer 11a1, high resistance of the gate trench electrode 11a is prevented.

[0045] <Implementation Method 6>

[0046] In Embodiment 6, the manufacturing method of the semiconductor device 100 according to Embodiments 1 to 5 will be described. Figure 5 This is a flowchart illustrating the manufacturing method.

[0047] First, a semiconductor substrate 10 of the first conductivity type is prepared (step S101), and an end structure (e.g., a guard ring, FLR (Field Limiting Ring) or the like) for maintaining voltage resistance is formed in the end region outside the element formation region of the IGBT or the like (step S102).

[0048] Next, by repeatedly performing a process of forming a mask using photolithography (mask processing) and selective ion implantation using the mask on the first main surface of the semiconductor substrate 10, a carrier accumulation layer 2 and a base layer 15 are formed on the semiconductor substrate 10 (step S103). At this time, the region of the first conductivity type remaining under the carrier accumulation layer 2 becomes the drift layer 1.

[0049] Next, a trench for the active trench gate 11 is formed by selectively etching the first main surface of the semiconductor substrate 10 (step S104). Then, a first insulating film that becomes part of the gate trench insulating film 11b is formed on the inner surface of the trench (step S105), and a buried electrode 11c is formed on the first insulating film in the trench (step S106).

[0050] Next, the portion of the first insulating film formed on the sidewall of the base layer 15 in the trench is removed by etching using the buried electrode 11c as a mask (step S107). Then, a second insulating film, which becomes part of the gate trench insulating film 11b, is formed on the buried electrode 11c in the trench and on the sidewall of the base layer 15 by oxidation, CVD (Chemical Vapor Deposition), or a combination thereof (step S108). Then, the gate trench electrode 11a is formed on the second insulating film in the trench (step S109), thereby completing the active trench gate 11.

[0051] For example, if the buried electrode 11c is polysilicon, and the second insulating film is formed solely by oxidation, the thickness of the second insulating film formed on the buried electrode 11c tends to become uneven. Furthermore, if the buried electrode 11c is metal, if the second insulating film is formed solely by oxidation, an oxide film cannot be formed on the buried electrode 11c. Therefore, particularly when the buried electrode 11c is polysilicon or metal, forming the second insulating film using a method including CVD improves the insulation between the buried electrode 11c and the gate trench electrode 11a.

[0052] Furthermore, when a dumb trench gate 12 is formed from a portion of the trench formed in step S104, the dumb trench insulating film 12b can be formed in step S105 (forming the first insulating film) or step S108 (forming the second insulating film), and the dumb trench electrode 12a can be formed in step S106 (forming the buried electrode 11c) or step S109 (forming the gate trench electrode 11a). Thus, the dumb trench gate 12 can be introduced without increasing the number of manufacturing steps.

[0053] After the active trench gate 11 is completed, the emitter layer 13 and the contact layer 14 are formed by repeatedly performing masking and ion implantation (step S110).

[0054] Then, an interlayer insulating film 4 is formed on the first main surface of the semiconductor substrate 10 (step S111). Then, after a contact hole is formed on the interlayer insulating film 4 (step S112), an emitter electrode 6 is formed on the interlayer insulating film 4 (step S113).

[0055] Finally, a back-side structure including a buffer layer 3, a collector layer 16 and a collector electrode 7 is formed on the second main surface side of the semiconductor substrate 10 (step S114), thereby completing the semiconductor device 100.

[0056] The heat treatment used to activate the impurities to be ion-implanted can be performed after each individual ion implantation step, or it can be performed together after multiple ion implantation steps. In addition, the order of the steps can be appropriately changed.

[0057] Furthermore, it is possible to freely combine the various implementation methods, or to appropriately modify or omit the various implementation methods.

[0058] Explanation of the label

[0059] 100 Semiconductor device, 1 Drift layer, 2 Carrier accumulation layer, 3 Buffer layer, 4 Interlayer insulating film, 5 Barrier metal, 6 Emitter electrode, 7 Collector electrode, 10 Semiconductor substrate, 11 Active trench gate, 11a Gate trench electrode, 11b Gate trench insulating film, 11c Buried electrode, 12 Dumb trench gate, 12a Dumb trench electrode, 12b Dumb trench insulating film, 13 Emitter layer, 14 Contact layer, 15 Base layer, 16 Collector layer, 11a1, 11c1, 12a1 Doped polysilicon layers, 11a2, 11c2, 12a2 Undoped polysilicon layers.

Claims

1. A semiconductor device, comprising: a semiconductor substrate having a first main surface, a second main surface, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the drift layer, the peak concentration of impurities in the carrier accumulation layer being higher than that in the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed in the semiconductor substrate so as to be in contact with the first main surface; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate having: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a fill-in electrode formed on the gate trench insulating film in the trench so as to be insulated from each other, the fill-in electrode being disposed at a position closer to the second main surface than the gate trench electrode, both the gate trench electrode and the fill-in electrode containing phosphorus, the phosphorus concentration of the fill-in electrode being lower than that of the gate trench electrode.

2. A semiconductor device, comprising: a semiconductor substrate having a first main surface, a second main surface, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the drift layer, the peak concentration of impurities in the carrier accumulation layer being higher than that in the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed in the semiconductor substrate so as to be in contact with the first main surface; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate having: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a fill-in electrode formed on the gate trench insulating film in the trench so as to be insulated from each other, the fill-in electrode being disposed at a position closer to the second main surface than the gate trench electrode, the phosphorus concentration of the fill-in electrode being lower than that of the gate trench electrode, the fill-in electrode being formed of doped polysilicon to which nitrogen is added and which does not contain phosphorus.

3. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein the process of forming the active trench gate includes the following processes: process (a) of forming the trench in the first main surface of the semiconductor substrate; process (b) of forming a first insulating film on the inner surface of the trench; process (c) of forming the fill-in electrode on the first insulating film in the trench; and process (d) of removing the first insulating film from the side wall of the base layer in the trench after the process (c). ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ (e) forming a second insulating film on the buried electrode and the side wall of the base layer in the trench by a method including a CVD method after the step (d), wherein CVD means chemical vapor deposition; and (f) forming the gate trench electrode on the second insulating film in the trench.

4. A semiconductor device comprising: a semiconductor substrate having a first main surface, a second main surface, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the drift layer, the carrier accumulation layer having a higher peak concentration of impurities than the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed in the semiconductor substrate so as to be in contact with the first main surface; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate having: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a buried electrode formed on the gate trench insulating film in the trench so as to be insulated from each other, the buried electrode being disposed at a position closer to the second main surface than the gate trench electrode, a surface layer portion of the buried electrode being formed of undoped polysilicon, and a portion of the buried electrode closer to an inner side than the surface layer portion being formed of doped polysilicon to which phosphorus is added.

5. A method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the active trench gate includes the following steps: (a) forming the trench in the first main surface of the semiconductor substrate; (b) forming a first insulating film on an inner surface of the trench; (c) forming the buried electrode on the first insulating film in the trench; (d) removing the first insulating film from the side wall of the base layer in the trench after the step (c); (e) forming a second insulating film on the buried electrode and the side wall of the base layer in the trench by a method including a CVD method after the step (d), wherein CVD means chemical vapor deposition; and (f) forming the gate trench electrode on the second insulating film in the trench.

6. A semiconductor device comprising: a semiconductor substrate having a first main surface, a second main surface, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the drift layer, the carrier accumulation layer having a higher peak concentration of impurities than the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main surface than the carrier accumulation layer; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ an emitter layer of the first conductivity type and a contact layer of the second conductivity type, which are formed in contact with the first main face at the semiconductor substrate; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate has: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a fill-in electrode formed on the gate trench insulating film in the trench in insulation from each other, the fill-in electrode being disposed at a position closer to the second main face side than the gate trench electrode, the gate trench electrode is formed of undoped polysilicon.

7. A semiconductor device having: a semiconductor substrate having a first main face, a second main face, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main face side than the drift layer, the peak concentration of impurities being higher than that of the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main face side than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type, which are formed in contact with the first main face at the semiconductor substrate; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate has: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a fill-in electrode formed on the gate trench insulating film in the trench in insulation from each other, the fill-in electrode being disposed at a position closer to the second main face side than the gate trench electrode, the gate trench electrode is formed of doped polysilicon to which nitrogen is added, at least a surface layer portion of the gate trench electrode does not contain phosphorus.

8. A semiconductor device having: a semiconductor substrate having a first main face, a second main face, and a drift layer of a first conductivity type; a carrier accumulation layer of the first conductivity type formed in the semiconductor substrate at a position closer to the first main face side than the drift layer, the peak concentration of impurities being higher than that of the drift layer; a base layer of a second conductivity type formed in the semiconductor substrate at a position closer to the first main face side than the carrier accumulation layer; an emitter layer of the first conductivity type and a contact layer of the second conductivity type, which are formed in contact with the first main face at the semiconductor substrate; and an active trench gate formed in a trench reaching the drift layer in contact with the emitter layer, the base layer, and the carrier accumulation layer, the active trench gate has: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode and a fill-in electrode formed on the gate trench insulating film in the trench in insulation from each other, the fill-in electrode being disposed at a position closer to the second main face side than the gate trench electrode, The surface layer portion of the gate trench electrode is formed of undoped polysilicon, and the portion of the gate trench electrode which is further inward than the surface layer portion is formed of doped polysilicon to which phosphorus is added.

9. A method of manufacturing a semiconductor device, the method of manufacturing a semiconductor device according to any one of claims 6 to 8, The process of forming the active trench gate includes the following processes: Process (a) of forming the trench on the first main surface of the semiconductor substrate; Process (b) of forming a first insulating film on the inner surface of the trench; Process (c) of forming the fill-in electrode on the first insulating film in the trench; Process (d) of removing the first insulating film of the side wall of the base layer in the trench after the process (c); Process (e) of forming a second insulating film on the fill-in electrode in the trench and the side wall of the base layer by a method including a CVD method after the process (d), wherein CVD means chemical vapor deposition; and Process (f) of forming the gate trench electrode on the second insulating film in the trench.

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