A multi-loop control circuit for charging chip

Abstract

The present invention belongs to the field of analog circuit technology, and more specifically, it relates to a multi-loop control circuit for a charging chip. The main problem with the traditional method is that when the multi-loop is switched, the originally saturated loop needs to reduce the output voltage of the operational amplifier from the saturated power supply voltage to an intermediate value close to VC3. A delay will occur during the reduction process, resulting in an overcharge of the output voltage or current. The present invention clamps the output of the saturated operational amplifier to a value slightly larger than VC3 by adding an additional follower circuit. In this way, during the loop switching process, the output of the saturated operational amplifier will quickly decrease and work to reduce the overcharge of the output voltage or current.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuits, and in particular relates to a multi-loop control circuit for a charging chip. Background Art

[0002] Figure 1 This is a simplified functional block diagram of a charging chip. It includes a power supply VIN, which provides power to the system end VSYS. When charging, VSYS supplies power to the battery through a MOS tube, or when the power supply VIN is not available, the battery will in turn supply power to the system VSYS through a MOS tube. The control from the power supply VIN to the system VSYS generally includes multiple control loops, typically the voltage loop and the maximum output current constant current loop as shown in the figure. The voltage loop detects the voltage of VSYS and feeds it back to VFB to the op amp CV of the constant voltage loop, and outputs VC2 after error amplification. The current loop detects the output current IOUT to obtain the detection current ISNS, which is given to the constant current op amp CC, and outputs VC1 after error amplification. VC1 and VC2 are passed through an analog low selection circuit, which automatically selects the smaller value of VC1 and VC2 as the output, namely VC3. VC3 will control the output control circuit of the lower level to adjust the size of the output current IOUT, thereby achieving the purpose of constant output voltage VSYS or constant maximum output current.

[0003] In normal steady-state operation, generally only one loop is in a normal amplification state, while the other one or more loops are in a saturation state. For example, when the VSYS output voltage is constant, the voltage loop works, and the VFB voltage is equal to the reference voltage VREF. The output VC2 of the op amp CV is at an intermediate value. At this time, since the output current of the constant current loop has not reached the maximum current limit, ISNS is lower than the reference current source, the output of the op amp CC is in a saturation state, and VC1 is pulled to the supply voltage of the op amp. As a result, the voltage of VC1 is much higher than VC2. Once the load conditions change, such as suddenly loading a large load current on VSYS, exceeding the maximum output constant current, the constant current loop needs to respond quickly to keep the output current constant at the maximum output current point. However, since the op amp CC was previously in a saturated state, the output VC1 was pulled to the supply voltage of the op amp. Even if the large output current causes ISNS to exceed IREF, since VC1 needs to be discharged from a high point, there will be a time delay and it cannot be reduced in time, resulting in a large overcharge of the output current. Therefore, switching from the voltage loop to the current loop will cause an overcharge of current at the output VSYS.

[0004] For similar reasons, when the charging loop operates at the maximum constant current output, the op amp CC1 operates in the normal amplification state, ISNS is equal to IREF, and the output VC1 of the op amp CC is at an intermediate value. In the maximum constant current state, the large load will pull the system output VSYS to a value lower than the normal value, making VFB less than the reference voltage VREF, the op amp CV is in a saturated state, and the output VC2 is pulled to the power supply voltage of the op amp. The value of VC2 is much larger than VC1. When the VSYS load changes and becomes smaller, the VSYS voltage will increase, but until VFB is higher than VREF, since VC2 needs to be discharged from the high point, there will be a time delay, and the output current cannot be reduced in time, causing VSYS to be rushed up and causing voltage overcharge. Therefore, switching from the current loop to the voltage loop will cause voltage overcharge at the output VSYS. Summary of the invention

[0005] In view of the above problems, the present invention proposes a multi-loop control circuit for a charging chip. The main problem of the above traditional method is that when the multi-loop is switched, the originally saturated loop needs to reduce the output voltage of the operational amplifier from the saturated power supply voltage to an intermediate value close to VC3. Delays will occur during the reduction process, resulting in overcharge of the output voltage or current. The present invention clamps the output of the saturated operational amplifier to a value slightly larger than VC3 by adding an additional follower circuit. In this way, during the loop switching process, the output of the saturated operational amplifier will quickly decrease and work to reduce the overcharge of the output voltage or current.

[0006] In view of the above problems, the technical solution of the present invention is:

[0007] A multi-loop control circuit for a charging chip, comprising a first error amplifier, a second error amplifier, an analog low selection circuit, and an output control circuit; the non-inverting input of the first error amplifier is connected to a reference voltage, and the inverting input of the first error amplifier is connected to an output feedback voltage; the non-inverting input of the second error amplifier is connected to a reference current, and the inverting input of the second error amplifier is connected to an output detection current; the output of the first error amplifier and the output of the second error amplifier are both connected to the input of the analog low selection circuit, the analog low selection circuit selects a smaller value from the outputs of the first error amplifier and the second error amplifier as the input of the output control circuit, and the output control circuit adjusts the output current according to the input to achieve the purpose of constant output voltage or constant maximum output current; it is characterized in that it also includes a follower circuit, the input of the follower circuit is the output of the analog low selection circuit, and the output of the follower circuit is used to feedback and adjust the output of the first error amplifier and the second error amplifier;

[0008] The follower circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a resistor, and a bias current source; the input of the bias current source is connected to a power supply VDD, the output is connected to the source of the first PMOS tube after passing through the resistor, the gate of the first PMOS tube is connected to the output of the analog low selection circuit, and the source of the second PMOS tube is connected to the output of the bias current source;

[0009] The drain of the first NMOS tube is connected to the drain of the first PMOS tube, the gate of the first NMOS tube is connected to the drain of the second PMOS tube, and the source of the first NMOS tube is grounded; the drain and gate of the second NMOS tube are connected to the drain of the second PMOS tube, and the source of the second NMOS tube is grounded;

[0010] The drain and gate of the third NMOS tube are connected to the drain of the first PMOS tube, the source of the third NMOS tube is grounded, the gate of the fourth NMOS tube is connected to the drain of the first PMOS tube, and the source of the fourth NMOS tube is grounded;

[0011] The gate of the second PMOS tube and the drain of the fourth NMOS tube are connected as the output of the follower circuit, connected to the output of the first error amplifier and / or the output of the second error amplifier (two follower circuits are used to adjust two error amplifiers simultaneously).

[0012] The beneficial effects of the present invention are as follows: by adding a follower circuit, the outputs of the operational amplifiers of the multiple loops are clamped at a minimum value slightly higher than the outputs of all the operational amplifiers, thereby reducing the delay during loop switching, thereby reducing the overcharge of the output voltage or current during loop switching; at the same time, the specific implemented circuit is simple and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Provide multi-loop control for charging chips;

[0014] Figure 2 It is a schematic diagram of a multi-loop control circuit of the present invention;

[0015] Figure 3 It is a schematic diagram of the circuit structure of the follower circuit in the present invention. DETAILED DESCRIPTION

[0016] The present invention is described in detail below in conjunction with the accompanying drawings.

[0017] The present invention adds an additional circuit, such as Figure 2 As shown, the output VC1 or VC2 of the saturated op amp closely follows the smaller one VC3. When loop switching occurs, the output of the op amp does not need to drop from the supply voltage, which greatly reduces the delay and quickly takes over the loop.

[0018] The specific circuit is as follows Figure 3 As shown: The circuit is composed of transistors M1-M6, resistor ROS and bias current IBIAS. Resistor ROS is used to generate a small offset voltage VOS at the input terminals M1 and M2, VOS = ROS*IBIAS / 2.

[0019] When VC1 or VC2 is higher than VC3+VOS, the current flowing through M1 is greater than the current of M2, while the currents of M3 and M4 are equal, so the current of M1 over M2 will flow to M5, and be mirrored to M6 through M5. The current of M6 pulls down the voltage of VC1 or VC2. Through this negative feedback, the value of VC1 or VC2 is clamped at VC3+VOS. By adjusting the value of ROS, the value of VOS can be adjusted, thereby clamping VC1 or VC2 to a value slightly higher than VC3. In this way, when the loop switches, VC1 or VC2 can be quickly reduced to the value of VC3, which greatly reduces the delay and effectively reduces the overcharge of the output voltage or current.

Claims

1. A multi-loop control circuit for a charging chip, comprising a first error amplifier, a second error amplifier, an analog low selection circuit, and an output control circuit; the non-inverting input of the first error amplifier is connected to a reference voltage, and the inverting input of the first error amplifier is connected to an output feedback voltage; the non-inverting input of the second error amplifier is connected to a reference current, and the inverting input of the second error amplifier is connected to an output detection current; the output of the first error amplifier and the output of the second error amplifier are both connected to the input of the analog low selection circuit, and the analog low selection circuit selects a smaller value from the outputs of the first error amplifier and the second error amplifier as the input of the output control circuit, and the output control circuit adjusts the output current according to the input to achieve the purpose of constant output voltage or constant maximum output current; it is characterized in that It also includes a follower circuit, the input of the follower circuit is the output of the analog low selection circuit, and the output of the follower circuit is used for feedback adjustment of the outputs of the first error amplifier and the second error amplifier; The follower circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a resistor, and a bias current source; the input of the bias current source is connected to a power supply VDD, the output is connected to the source of the first PMOS tube after passing through the resistor, the gate of the first PMOS tube is connected to the output of the analog low selection circuit, and the source of the second PMOS tube is connected to the output of the bias current source; The drain of the first NMOS tube is connected to the drain of the first PMOS tube, the gate of the first NMOS tube is connected to the drain of the second PMOS tube, and the source of the first NMOS tube is grounded; the drain and gate of the second NMOS tube are connected to the drain of the second PMOS tube, and the source of the second NMOS tube is grounded; The drain and gate of the third NMOS tube are connected to the drain of the first PMOS tube, the source of the third NMOS tube is grounded, the gate of the fourth NMOS tube is connected to the drain of the first PMOS tube, and the source of the fourth NMOS tube is grounded; The gate of the second PMOS tube and the drain of the fourth NMOS tube are connected as the output of the follower circuit, and are connected to the output of the first error amplifier or the output of the second error amplifier.

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