Preemptive upgrade for full span degradation

Abstract

A method for improving degraded performance to a RAID array is disclosed. The method periodically scans a cache for first spans that are ready to be degraded to a RAID array. In scanning the cache, the method identifies second spans that are not currently ready to be degraded to the RAID array but will likely be ready to be degraded during a subsequent scan of the cache. The method initiates a pre-emptive promotion of any missing data for the second spans from the RAID array to the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method degrades the second spans from the cache to the RAID array from the cache.

Description

Technical Field

[0001] This invention relates to systems and methods for improving the destage performance of RAID arrays. Background Technology

[0002] RAID (Redundant Array of Independent Disks) is a storage technology that provides increased storage functionality and reliability through redundancy. RAID is created by combining multiple storage drive components (e.g., disk drives and / or solid-state drives) into a logical unit. Data is then distributed across the drives using various techniques, known as “RAID levels.” The current standard RAID levels, including RAID levels 1 through 6, are a basic set of RAID configurations that employ striping, mirroring, and / or parity to provide data redundancy. Each configuration offers a balance between two key objectives: (1) increased data reliability and (2) increased I / O performance.

[0003] Disks configured in a RAID array can provide accelerated read performance because data can be accessed from multiple drives simultaneously. However, when performing writes to RAID arrays such as RAID-5 or RAID-6, there can be increased overhead. This is primarily due to parity calculations. For example, to write a subset of the data's stride (i.e., a stripe) to a RAID-5 array, the stripe of the stride may need to be staged from the RAID-5 array to recalculate the parity value associated with the stride. Once the parity value has been recalculated, the entire stride can be degraded back to the RAID-5 array. Therefore, a write to a RAID-5 array less than the full stride can incur significant overhead to stage the data from the RAID array, recalculate the parity value, and degrade the data and the recalculated parity value back to the RAID array. On the other hand, a single operation can degrade the entire span of data, along with the calculated parity value, to the RAID-5 array. This is because it is not necessary to load any missing data values ​​or parity values ​​from the disk drive before writing the span to the RAID array. Summary of the Invention

[0004] The present invention has been developed in response to the level of existing technology, and specifically, in response to problems and needs that are not fully solved by currently available systems and methods in the art. Therefore, the present invention has been developed to improve the degraded performance of RAID arrays. The features and advantages of the invention will become more apparent from the following description and the appended claims, or may be learned by practicing the invention as described below.

[0005] Consistent with the foregoing, a method for improving degradation performance to a RAID array is disclosed. In one embodiment, this method periodically scans a first span in a cache that is ready to be degraded to the RAID array. While scanning the cache, the method identifies a second span that is not currently ready to be degraded to the RAID array but may be ready to be degraded during a subsequent scan of the cache. The method initiates a preemptive upgrade of any missing data in the second span from the RAID array to the cache in preparation for a subsequent scan. When a subsequent scan occurs, the method downgrades the second span from the cache to the RAID array.

[0006] This document also discloses and claims protection for a corresponding computer program product and system. Attached Figure Description

[0007] To make the advantages of the invention readily apparent, a more detailed description of the invention, which has been briefly described above, will be presented by reference to specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of the invention and are therefore not intended to limit its scope. The invention will be described and explained with additional features and details using the drawings, in which:

[0008] Figure 1 This is a high-level block diagram illustrating an example of a network environment in which the systems and methods according to the present invention can be implemented;

[0009] Figure 2 It is shown in Figure 1 A high-level block diagram of an example storage system used in a network environment;

[0010] Figure 3A This is a high-level block diagram showing the span in a RAID array;

[0011] Figure 3B It is shown as Figure 3A A table of parity values ​​calculated for each span in a RAID array;

[0012] Figure 4 This is a high-level block diagram showing the read cache and write cache within the cache;

[0013] Figure 5 This is a high-level block diagram illustrating a cache degradation module that degrades data from the cache to a RAID array;

[0014] Figure 6 This is a flowchart illustrating one embodiment of a method for scanning the span in the cache to be downgraded to a RAID array; and

[0015] Figure 7This is a flowchart illustrating one embodiment of a method for adjusting the number of spans that are preemptively upgraded to the cache. Detailed Implementation

[0016] It will be readily understood that the components of the invention, as generally described and illustrated in the accompanying drawings, can be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of embodiments of the invention as illustrated in the drawings is not intended to limit the scope of the claimed invention, but merely to illustrate certain examples of currently contemplated implementations according to the invention. The embodiments currently described will be best understood by reference to the accompanying drawings, and throughout the text, the same parts are always represented by the same numbers.

[0017] This invention can be embodied as a system, method, and / or computer program product. The computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0018] Computer-readable storage media can be tangible devices capable of retaining and storing instructions used by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or protrusions in slots) having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0019] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0020] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages).

[0021] Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0022] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0023] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that, when executed via the processor of the computer or other programmable data processing apparatus, these instructions create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of writing containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0024] These computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, thereby causing the instructions to be executed on the computer, other programmable apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0025] refer to Figure 1 An example of a network environment 100 is shown. Network environment 100 is presented to illustrate an example of an environment in which embodiments of the invention may operate. Network environment 100 is presented by way of example only and not as a limitation. In fact, the systems and methods disclosed herein are applicable to a wide variety of different network environments besides the network environment 100 shown.

[0026] As shown in the figure, network environment 100 includes one or more computers 102, 106 interconnected via network 104. Network 104 may include, for example, a local area network (LAN) 104, a wide area network (WAN) 104, the Internet 104, an intranet 104, etc. In some embodiments, computers 102, 106 may include both a client computer 102 and a server computer 106 (also referred to herein as a “host” 106 or “host system” 106). Typically, client computer 102 initiates a communication session, while server computer 106 waits for and responds to requests from client computer 102. In some embodiments, computer 102 and / or server 106 may be connected to one or more internal or external directly attached storage systems 112 (e.g., arrays of hard disk drives, solid-state drives, tape drives, etc.). These computers 102, 106 and directly attached storage systems 112 may communicate using protocols such as ATA, SATA, SCSI, SAS, Fibre Channel, etc.

[0027] In some embodiments, network environment 100 may include a storage network 108, such as a storage area network (SAN) 108 or a LAN 108, located behind server 106 (e.g., when using network-attached storage devices). This network 108 can connect server 106 to one or more storage systems 110, such as an array 110a of hard disk drives or solid-state drives, a tape library 110b, individual hard disk drives 110c or solid-state drives 110c, tape drives 110d, CD-ROM libraries, etc. To access storage system 110, host system 106 can communicate via physical connections from one or more ports on host system 106 to one or more ports on storage system 110. Connections can be via switches, infrastructure, direct connections, etc. In some embodiments, server 106 and storage system 110 may communicate using networking standards such as Fibre Channel (FC) or iSCSI.

[0028] refer to Figure 2 An embodiment of a storage system 110a comprising an array of storage drives 204 (e.g., hard disk drives and / or solid-state drives) is illustrated. As shown, the storage system 110a includes a storage controller 200, one or more switches 202, and one or more storage drives 204, such as hard disk drives and / or solid-state drives (e.g., flash-based drives). The storage controller 200 enables one or more hosts 106 (e.g., open systems and / or mainframe servers 106) to access data in one or more storage drives 204. In some embodiments, the storage drives 204 may be configured in RAID arrays of different RAID levels to provide a desired level of I / O performance and / or data redundancy.

[0029] In the selected embodiment, storage controller 200 includes one or more servers 206. Storage controller 200 may also include a host adapter 208 and a device adapter 210 to connect storage controller 200 to host device 106 and storage drive 204, respectively. During normal operation (when both servers 206 are operational), servers 206 can manage I / O for different logical subsystems (LSS) within enterprise storage system 110a. For example, in some configurations, a first server 206a may handle I / O to even-numbered LSSs, while a second server 206b may handle I / O to odd-numbered LSSs. These servers 206a, 206b can provide redundancy to ensure data is always available for the connected host 106. Therefore, when one server 206a fails, another server 206b can take over the I / O load of the failed server 206a to ensure I / O can continue between host 106 and storage drive 204. This process can be referred to as "failover".

[0030] In selected embodiments, each server 206 includes one or more processors 212 and memory 214. Memory 214 may include volatile memory (e.g., RAM) and non-volatile memory (e.g., ROM, EPROM, EEPROM, flash memory, local disk drive, local solid-state drive, etc.). In some embodiments, the volatile and non-volatile memory may be stored in software modules running on the processor(s) 212 and used to access data in the storage drive 204. These software modules manage all read and write requests for logical volume 302 in the storage drive 204.

[0031] In the selected embodiment, memory 214 includes cache 218, such as DRAM cache 218. Whenever host 106 performs a read operation (e.g., open system or mainframe server 106), the server 206 performing the read can retrieve the data from storage drive 204 and store the data in its cache 218 if needed again. If host 106 requests data again, server 206 can retrieve the data from cache 218 instead of from storage drive 204, thus saving time and resources. Similarly, when host 106 performs a write operation, server 106 receiving the write request can store the write in its cache 218 and later degrade the write to storage drive 204. While the write is stored in cache 218, the write can also be stored in non-volatile storage (NVS) 220 of peer server 206, so that the write can be recovered by peer server 206 in the event of failure of the first server 206.

[0032] With Figure 2 An example of a storage system 110a with a similar architecture to the one shown is from IBM. Enterprise storage systems. It provides high-performance, high-capacity storage controllers designed to support continuous operation of disks and solid-state storage. However, the systems and methods disclosed herein are not limited to IBM. Enterprise storage systems, rather than being implemented in any comparable or similar storage system or group of storage systems, regardless of the manufacturer, product name, or component or component name associated with the system. Any storage system that can benefit from one or more embodiments of the invention is considered to fall within the scope of the invention. Therefore, IBM Presented only as examples and not intended to be restrictive.

[0033] refer to Figure 3AIn the selected embodiment, the disk drives 204 of the storage system 110a can be configured in a RAID array 302 (i.e., a redundant array of low-cost disks). For example, in a "RAID 5" array 302, logically sequential data can be segmented across multiple disk drives 204a-204d. For example, in the case where disk drives 204a-204d comprise four disks, logically sequential data "A" can be divided into segments "A1", "A2", and "A3" (collectively referred to as "span A") and stored on three separate disks 204a-204c. In the selected embodiment, each segment includes one or more tracks 300, but other divisions are also possible. Parity data "Ap" can be calculated by performing an XOR operation on A1, A2, and A3. This parity data can be stored on a fourth disk 204d. Figure 3B The example data and parity values ​​are shown (parity values ​​are shaded). In the event of a failure in one of disks 204a-204c, the remaining data and parity values ​​can be used to reconstruct the data on the failed disk. For example, if disk 204b containing A2 is missing, the values ​​A1, A3, and A... p It can be used to refactor A2.

[0034] The disks configured in RAID array 302 can provide accelerated read performance because data can be accessed simultaneously from multiple drives 204a-204c. However, when performing writes to the array, there is typically increased overhead. This is primarily due to parity calculations. For example, to write A1, it may be necessary to load (i.e., upgrade) values ​​A2, A3, and A4 from disk drive 204. p The value A1 needs to be modified on the disk drive, and the parity value A needs to be recalculated (using values ​​A1, A2, and A3). p And it is downgraded to disk drive 204. These operations require a total of four disk operations. On the other hand, the full span of data (i.e., A1, A2, and A3) can be combined with the parity value A using a single disk operation. p Both are downgraded to disk drive 204. This is because when writing a span to disk drive 204, it is not necessary to load data values ​​or parity values ​​from disk drive 204. For this reason, a full span downgrade is preferred when downgrading data from cache 218 to storage drive 204.

[0035] See Figure 4In some embodiments, cache 218 may be divided into read cache 218a and write cache 218b. Read cache 218a may store unmodified data (e.g., unmodified track 400). Write cache 218b may store modified data (e.g., modified track 400). Modified data may eventually be degraded to backend storage drive 204.

[0036] In some embodiments, an ordered list (e.g., b-tree) of modified data elements (e.g., tracks) may be maintained for each rank (i.e., RAID array 302) in storage system 110a. This ordered list can be used to determine which modified data elements should be downgraded from write cache 218b to RAID array 302, and the commands used to perform the downgrade. In some embodiments, the ordered list is sorted based on the physical location of each data element within RAID array 302.

[0037] like Figure 4 As shown, in some embodiments, one or more clock bits 402 may be maintained for each modified data element 400 written to cache 218b. For example, in some embodiments, four clock bits 402 may be maintained for each data element 400, thereby achieving values ​​from zero to fifteen. (As will be combined with...) Figure 6 To explain in more detail, these clock bits 402 can store a count used to determine when to degrade a data element. The count of data elements can be decremented each time the ordered list is scanned. The count associated with data element 400 can be incremented whenever data element 400 is written. This counting ensures that frequently written data element 400 is not prematurely degraded from cache 218 to storage drive 204.

[0038] refer to Figure 5 In some embodiments, a cache degradation module 500 may be provided to degrade data element 400 from write cache 218b to storage drive 204. The cache degradation module 500 may include different submodules to provide different features and functionalities. The cache degradation module 500 and associated submodules may be implemented in hardware, software, firmware, or a combination thereof. The cache degradation module 500 and associated submodules are presented as examples and not as limitations. In different embodiments, more or fewer submodules may be provided. For example, the functionality of some submodules may be combined into a single or fewer submodules, or the functionality of a single submodule may be distributed across several submodules.

[0039] As shown in the figure, the cache degradation module 500 includes one or more of the following: a cache scan module 502, a count decrement module 504, a count determination module 506, a threshold module 508, an upgrade module 510, a degradation module 512, a preemptive upgrade module 514, and a limit module 516. The cache scan module 502 can be configured to periodically scan an ordered list to determine which data elements 400 are ready to be degraded from the write cache 218b to the RAID array 302. Each time the data element 400 in the ordered list is scanned, the count decrement module 504 can decrement the count in the clock bit 402 associated with the data element 400.

[0040] While scanning data element 400 in the ordered list, the counting determination module 506 can determine the count associated with data element 400 by reading clock bit 402. After making this determination, the threshold module 508 can determine whether all counts associated with data element 400 from the same span are less than or equal to a first threshold (e.g., zero). If the counts are less than or equal to the first threshold, data element 400 can be considered "ready" to be downgraded from cache 218 to RAID array 302. If necessary, the upgrade module 510 can upgrade any missing data element 400 from RAID array 302 to cache 218, such that data elements 400 in cache 218 constitute the full span. Then, if necessary, the downgrade module 512 can recalculate the parity value associated with the span and downgrade the span from cache 218 to RAID array 302.

[0041] If the count of data elements 400 associated with the span is not less than or equal to a first threshold, the threshold module 508 can determine whether the count is less than or equal to a second threshold (e.g., a third). If so, the data elements 400 associated with the span may not currently be “ready” to be downgraded to RAID array 302 (because their count is not less than or equal to the first threshold), but may be ready during a subsequent scan of cache 218 (since their count will decrease, they may be less than or equal to the first threshold during a subsequent scan, unless any event, such as a write, could increase the count beyond the first threshold). In this case, the preemptive upgrade module 514 can preemptively upgrade any missing data elements 400 from RAID array 302 to cache 218, so that the full span exists in cache 218 for the next traversal of cache scan module 502. If, during the next scan of cache 218, all counts associated with the data elements 400 of the span are below the first threshold, the data elements 400 associated with the span will be considered “ready” to be downgraded. Upgrading the missing data element 400 in this way can eliminate or reduce the need to upgrade the missing data element 400 from the RAID array 302 to the cache 218 during downgrade, thereby improving efficiency.

[0042] Limiting module 516 can be configured to limit the number of spans during a preemptive upgrade process from RAID array 302. In some embodiments, limiting module 516 can limit the number of spans to a selected threshold (e.g., fifty). If the number of spans being preemptively upgraded is equal to or exceeds this amount, limiting module 516 can queue any additional requests for preemptive upgrades. When the number of spans being preemptively upgraded drops below the threshold (or even a lower threshold), limiting module 516 can resume processing requests for preemptive upgrade spans, starting with those requests in the order they were placed in the queue. Figure 7 The discussion covers embodiments of method 700 that can be used by the restriction module 516.

[0043] refer to Figure 6 This provides one embodiment of a method 600 for scanning cache 218. This method 600 can be performed by the cache degradation module 500 discussed earlier. As shown, method 600 initially determines 602 whether it is time to scan cache 218. In some embodiments, the scan can occur when a previous scan has completed or at a specified interval. In some embodiments, the time required to perform the scan can correspond to the amount of time required to traverse the previously discussed ordered list.

[0044] As shown in the figure, when a new scan is initiated, method 600 checks the data elements 400 in cache 218 associated with the first span in the ordered list. If the count (i.e., clock bit 402) of all data elements 400 associated with the span in step 606 is equal to or less than a first threshold (e.g., zero), the span is ready to be downgraded to RAID array 302. If, in step 608, there is a data gap for performing a full span downgrade (assuming a full span downgrade and / or downgrading data in the most efficient way), method 600 upgrades the missing data elements 400 from RAID array 302 to 610, so that the full span exists in cache 218. Using the full span of data, method 600 recalculates parity value 612 and downgrades the span 612 to RAID array 302. On the other hand, if, in step 608, data is not missing from the span, method 600 simply recalculates parity value 612 and downgrades the span 612. There is no need to upgrade the missing data element 400 from RAID array 302. Method 600 then determines whether the ordered list 614 contains more spans, and if so, checks the next span in the ordered list 604.

[0045] If, in step 606, the count of all data elements 400 associated with the span (i.e., clock bits 402) is not equal to or below a first threshold, then method 600 determines 616 whether the count of all data elements 400 associated with the span is equal to or below a second threshold (e.g., three). If not, then method 600 determines 614 whether the ordered list contains more spans, and if so, checks 604 the next span in the ordered list. If all data elements 400 associated with the span are equal to or below the second threshold, the span may not currently be ready to be degraded to RAID array 302, but may be ready for degrade during a subsequent scan of cache 218 (assuming no further writes to data elements 400). In step 616, if all data elements 400 associated with the span are equal to or below the second threshold, then method 600 determines 618 whether any missing data is needed to complete the span, assuming a full span degrade and / or maximum efficiency is required. If data is missing, method 600 preemptively upgrades the missing data from RAID array 302 to cache 218, thereby ensuring that the full span is present in cache 218 for the next scan. Alternatively, if no data is missing from the span in step 618, no preemptive upgrade is needed. Method 600 then determines whether the ordered list 614 contains more spans, and if so, checks the next span in the ordered list 604.

[0046] Once all spans in the ordered list 604 have been checked, method 600 terminates and waits for 602 for the next scan to begin. In some embodiments, the next scan begins immediately. In other embodiments, the next scan begins after a previous scan has ended and a certain amount of time has elapsed. In other embodiments, scans occur at regular intervals, and the next scan begins at the start of the next regular interval.

[0047] refer to Figure 7 This illustrates an embodiment of a method 700 for adjusting the number of spans preemptively upgraded from RAID array 302. As shown, method 700 determines 702 whether a span in cache 218 needs to be preemptively upgraded. If so, method 700 determines 704 whether the number of spans currently being preemptively upgraded is higher than a high threshold (e.g., fifty). If so, method 700 queues the spans 706. If at step 704, the number of spans currently being preemptively upgraded is lower than the high threshold, method 700 increments 708 the number of spans currently being preemptively upgraded and initiates 708 a preemptive upgrade of the span.

[0048] If a span has already been preemptively upgraded in step 710, method 700 decrements the number of spans currently being preemptively upgraded by step 712. Method 700 then determines whether the number of spans currently being preemptively upgraded is below a low threshold (e.g., forty). If so, method 700 determines whether any spans are currently in the queue. If so, method 700 increments the number of spans currently being preemptively upgraded by step 708 and initiates a preemptive upgrade for the next span in the queue by step 708. If there are no spans in the queue, method 700 returns to the top to determine whether another span needs to be preemptively upgraded by step 702, or whether a span has already been preemptively upgraded by step 710.

[0049] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer-usable media according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, comprising one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than shown in the figures. For example, depending on the function involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A method for improving destage performance to a RAID array, the method comprising: maintaining a count for each data element of each extent stored in a cache; periodically scanning the cache for a first extent that is ready to be destaged to the RAID array, wherein identifying the first extent comprises identifying an extent whose count for each data element is less than or equal to a first specified threshold; identifying, while scanning the cache, a second extent that is not currently ready to be destaged to the RAID array but will likely be ready to be destaged during a subsequent scan of the cache, wherein identifying the second extent comprises identifying an extent whose count for each data element is less than or equal to a second specified threshold that is different from the first specified threshold; initiating a pre-emptive promotion of any missing data elements of the second extent from the RAID array to the cache in preparation for the subsequent scan; and destaging the second extent from the cache to the RAID array when the subsequent scan occurs.

2. The method of claim 1, wherein the count is incremented each time the data element corresponding thereto is written.

3. The method of claim 2, wherein the count is decremented each time the data element corresponding thereto is scanned.

4. The method of claim 3, wherein the first specified threshold is zero.

5. The method of claim 2, wherein the count comprises four clock bits.

6. The method of claim 2, wherein the data element is a track.

7. The method of claim 1, wherein initiating a pre-emptive promotion comprises initiating a pre-emptive promotion of a plurality of second extents that reach the specified threshold.

8. A computer program product for improving destage performance to a RAID array, the computer program product comprising a non-transitory computer-readable storage medium having computer usable program code embodied therein, the computer usable program code configured such that, when executed by at least one processor, performs the following: maintaining a count for each data element of each extent stored in a cache; periodically scanning the cache for a first extent that is ready to be destaged to the RAID array, wherein identifying the first extent comprises identifying an extent whose count for each data element is less than or equal to a first specified threshold; identifying, while scanning the cache, a second extent that is not currently ready to be destaged to the RAID array but will likely be ready to be destaged during a subsequent scan of the cache, wherein identifying the second extent comprises identifying an extent whose count for each data element is less than or equal to a second specified threshold that is different from the first specified threshold; initiating a pre-emptive promotion of any missing data elements of the second extent from the RAID array to the cache in preparation for the subsequent scan; and destaging the second extent from the cache to the RAID array when the subsequent scan occurs. ​ ​ 9. The computer program product of claim 8, wherein the count is incremented each time the data element to which it corresponds is written.

10. The computer program product of claim 9, wherein the count is decremented each time the data element to which it corresponds is scanned.

11. The computer program product of claim 10, wherein the first specified threshold is zero.

12. The computer program product of claim 9, wherein the count comprises four clock bits.

13. The computer program product of claim 9, wherein the data element is a track.

14. The computer program product of claim 8, wherein initiating a pre-emptive promotion comprises initiating a pre-emptive promotion for a plurality of second spans that reach a specified threshold.

15. A system for improving degradation performance to a RAID array, the system comprising: at least one processor; at least one memory device operably coupled to the at least one processor and storing instructions for execution on the at least one processor, the instructions causing the at least one processor to: maintain a count for each data element of each span stored in a cache; periodically scan the cache for first spans ready to be degraded to a RAID array, wherein identifying the first spans comprises identifying spans for which the count for each data element is less than or equal to a first specified threshold; identify, while scanning the cache, second spans that are not currently ready to be degraded to a RAID array but will likely be ready to be degraded during a subsequent scan of the cache, wherein identifying the second spans comprises identifying spans for which the count for each data element is less than or equal to a second specified threshold that is different from the first specified threshold; initiate a pre-emptive promotion of any missing data elements of the second spans from the RAID array to the cache in preparation for the subsequent scan; and degrade the second spans from the cache to the RAID array upon occurrence of the subsequent scan.

16. The system of claim 15, wherein the count is incremented each time the data element to which it corresponds is written.

17. The system of claim 16, wherein the count is decremented each time the data element to which it corresponds is scanned.

18. The system of claim 16, wherein the count comprises four clock bits.

19. The system of claim 16, wherein the data element is a track.

20. The system of claim 15, wherein initiating a pre-emptive promotion comprises initiating a pre-emptive promotion for a plurality of second spans that reach a specified threshold. ​

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