Solid-state imaging device and imaging device

Abstract

The solid-state imaging device (100) includes: a photoelectric conversion element (120) formed on a semiconductor substrate (150) that accumulates signal charges generated by photoelectric conversion; a first diffusion layer (FD1) that holds the signal charges transferred from the photoelectric conversion element (120); a capacitor element (126) that holds the signal charges overflowing from the photoelectric conversion element (120); an amplification transistor (124) that outputs a signal corresponding to the amount of signal charges in the first diffusion layer (FD1); a contact (c1) connected to the first diffusion layer (FD1), a contact (c2) connected to the gate of the amplification transistor (124), and a first wiring (w1) that connects the contact (c1) and the contact (c2). The shortest distance between the semiconductor substrate (150) and the first wiring (w1) is smaller than the shortest distance between the semiconductor substrate (150) and the capacitor element (126).

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and an imaging device. Background Art

[0002] Conventionally, in order to expand the dynamic range, for example, a solid-state imaging device shown in Patent Document 1 has been proposed. The solid-state imaging device of Patent Document 1 includes: an overflow gate that transfers charges overflowing from a photodiode; and a capacitor element that accumulates the charges transferred through the overflow gate during an accumulation operation. The solid-state imaging device expands the dynamic range by synthesizing a low illuminance signal and a high illuminance signal.

[0003] (Prior Art Document)

[0004] (Patent Document)

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-217410

[0006] However, in this Patent Document 1, there is a problem that the SN ratio deteriorates as the dynamic range expands. Summary of the Invention

[0007] Therefore, the present disclosure provides a solid-state imaging device, an imaging device, and an imaging method that suppress deterioration of the SN ratio caused by expansion of the dynamic range.

[0008] In order to solve the above problems, a solid-state imaging device according to one aspect of the present disclosure includes: a photoelectric conversion element formed on a semiconductor substrate that generates signal charges through photoelectric conversion; a first diffusion layer that holds the signal charges transferred from the photoelectric conversion element; a capacitor element that holds signal charges overflowing from the photoelectric conversion element; an amplification transistor that outputs a signal corresponding to the signal charges in the first diffusion layer; a first contact connected to the first diffusion layer; a second contact connected to the gate of the amplification transistor; and a first wiring that connects the first contact and the second contact. The shortest distance between the semiconductor substrate and the first wiring is smaller than the shortest distance between the semiconductor substrate and the capacitor element.

[0009] Moreover, an imaging device according to one aspect of the present disclosure includes: the solid-state imaging device that captures an object, an imaging optical system that guides incident light from the object to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0010] With the solid-state imaging device and the imaging device of the present disclosure, it is possible to suppress deterioration of the SN ratio caused by expansion of the dynamic range. Brief Description of the Drawings

[0011] Figure 1 This is a block diagram schematically showing a configuration example of the solid-state imaging device in the first embodiment.

[0012] Figure 2 A configuration example of pixels constituting the solid-state imaging device in the first embodiment is shown.

[0013] Figure 3A It is a cross-sectional view schematically showing a first configuration example of a pixel unit constituting the solid-state imaging device in the first embodiment.

[0014] Figure 3B It is a cross-sectional view schematically showing a second configuration example of a pixel unit constituting the solid-state imaging device in the first embodiment.

[0015] Figure 3C It is a cross-sectional view schematically showing a third configuration example of the pixel unit constituting the solid-state imaging device in the first embodiment.

[0016] Figure 4 The potentials of pixels constituting the solid-state imaging device in the first embodiment within the semiconductor substrate are shown.

[0017] Figure 5 This is a timing chart for explaining a first example of the operation of the pixels constituting the solid-state imaging device in the first embodiment.

[0018] Figure 6 This is a graph showing the relationship between the subject illumination of the pixels constituting the solid-state imaging device and the signal output of the pixels in the first embodiment.

[0019] Figure 7 This is a graph showing the relationship between the subject illumination of the pixels constituting the solid-state imaging device in the first embodiment and the SN (signal-to-noise ratio) of the pixels.

[0020] Figure 8 A configuration example of an imaging device to which a solid-state imaging device is applied in the second embodiment is shown. DETAILED DESCRIPTION

[0021] The embodiments to be described below are all specific examples. The values, shapes, materials, components, configuration positions of components, connection methods, steps, and order of steps shown in the following embodiments are all examples, and their purpose is not to limit the present invention. In addition, the components of the following embodiments that are not recorded in the independent technical solutions showing the highest concept are described as arbitrary components.

[0022] (First embodiment)

[0023] The solid-state imaging device according to the first embodiment will be described below with reference to the accompanying drawings.

[0024] [1 Configuration example of solid-state imaging device 100]

[0025] Figure 1 It is a configuration diagram of the solid-state imaging device 100 according to the first embodiment.

[0026] As Figure 1 shown, the solid-state imaging device 100 according to the present embodiment includes: a pixel array unit 102, a vertical scanning circuit 103, a constant current source circuit 104, a column processing circuit 105, a horizontal scanning circuit 106, a signal processing circuit 107, an output circuit 108, a timing generation circuit 109, and a vertical signal line PIXOUT.

[0027] The pixel array unit 102 is formed by arranging a plurality of pixel units (unit cells) 101 that perform photoelectric conversion in a matrix.

[0028] The vertical signal line PIXOUT connects the constant current source circuit 104 and the column processing circuit 105, and transmits the signals of the pixel units 101 for each column of the pixel units 101.

[0029] The vertical scanning circuit 103 drives the pixel array unit 102.

[0030] The constant current source circuit 104 includes constant current sources corresponding to each column of the pixel units 101.

[0031] The column processing circuit 105 includes: a CDS (correlated double sampling) circuit that receives the pixel signals of each column and serves as a noise eliminator; and an analog-to-digital conversion circuit (ADC) that receives the pixel signals from the CDS circuit.

[0032] The horizontal scanning circuit 106 selects the data that has been analog-to-digital converted for each column, and sequentially outputs the data to the signal processing circuit 107.

[0033] The signal processing circuit 107 performs signal processing on the data output from the column processing circuit 105.

[0034] The output circuit 108 is a buffer circuit that outputs the data signal-processed by the signal processing circuit 107 to the outside of the solid-state imaging device 100.

[0035] The timing generation circuit 109 generates timing signals for operating each part of the solid-state imaging device 100.

[0036] Further, the CDS circuit included in the column processing circuit 105 is connected to each pixel unit 101 according to each column of the pixel units 101 arranged in a matrix in the pixel array unit 102. Further, the CDS circuit performs CDS processing on the signal output from the pixel units 101 of the row selected by the vertical scanning circuit 103 via the vertical signal line PIXOUT. The CDS processing is a signal processing for eliminating the reset noise generated in the pixel unit 101 and the specific pattern noise unique to the pixel caused by the threshold deviation of the transistor. Further, the column processing circuit 105 temporarily holds the pixel signal after the signal processing.

[0037] The analog-digital conversion circuit (ADC) has an AGC (Auto Gain Control) function and an analog-digital conversion function, and converts the analog signal, i.e., the pixel signal, held by the CDS circuit into a digital signal through the ADC.

[0038] [1.1 Circuit example of pixel unit 101]

[0039] Figure 2 The configuration example of the pixel constituting the solid-state imaging device 100 in the first embodiment is shown.

[0040] As Figure 2 shown, the pixel unit 101 includes: a photoelectric conversion element 120 that accumulates signal charges generated through photoelectric conversion; a first transfer transistor 121 that transfers the signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1; a capacitive element 126 as a holding unit that holds the signal charges overflowing from the photoelectric conversion element 120; and a second transfer transistor 128 that transfers the signal charges held in the capacitive element 126 to the second diffusion layer FD2.

[0041] More specifically, the pixel unit 101 has: a photoelectric conversion element 120, a first transfer transistor 121, a switching transistor 122, a reset transistor 123, an amplifying transistor 124, and a selection transistor 125. Further, the pixel unit 101 has, for example, a capacitive element 126 as a holding unit, an overflow transistor 127, and a second transfer transistor 128.

[0042] As each of the transistors 121 to 125 and 127 to 128, for example, an N-channel MOS transistor can be used. Further, regarding the state of the N-channel MOS transistor (Nch transistor), it is turned on when the gate potential is at the "High" level and turned off when at the "Low" level. Further, regarding the state of the P-channel MOS transistor (Pch transistor), it is turned on when the gate potential is at the "Low" level and turned off when at the "High" level.

[0043] The first transfer transistor 121 is connected between the cathode electrode of the photoelectric conversion element 120 and the first diffusion layer FD1. A transfer control line TG is connected to the gate electrode of the first transfer transistor 121. When the gate electrode of the first transfer transistor 121 is applied with a "High" level by a transfer pulse of the transfer control line TG the first transfer transistor 121 becomes conductive, and the signal charge (specifically, electrons) that is photoelectrically converted by the photoelectric conversion element 120 and accumulated in the photoelectric conversion element 120 is transferred to the first diffusion layer FD1.

[0044] The overflow transistor 127 is connected between the cathode electrode of the photoelectric conversion element 120 and the capacitor element 126. An overflow control line OF is connected to the gate electrode of the overflow transistor 127. When a DC bias voltage from the overflow control line OF is applied to the gate electrode of the overflow transistor 127, by controlling the potential of the channel portion of the overflow transistor 127, when the generation of the signal charge in the photoelectric conversion element 120 exceeds the saturation capacity of the photoelectric conversion element 120, it is transferred to the capacitor element 126 via the overflow transistor 127. In addition, when the potential of the overflow transistor 127 is different due to temperature or inter-chip deviation, a correction circuit may be mounted to correct the deviation by changing the DC bias voltage value of the overflow control line OF. And although here the overflow transistor 127 is used to control the charge transfer from the photoelectric conversion element 120 to the capacitor element 126, it is also possible to achieve the same function as the overflow transistor 127 without the overflow transistor 127, but by controlling the impurity distribution in the semiconductor substrate 150.

[0045] The second transfer transistor 128 is connected between the capacitor element 126 and the second diffusion layer FD2, and the second diffusion layer FD2 is located between the switching transistor 122 and the reset transistor 123. A transfer control line TGC is connected to the gate electrode of the second transfer transistor 128. When the gate electrode of the second transfer transistor 128 is applied with a "High" level by a transfer pulse from the transfer control line TGC the second transfer transistor 128 becomes conductive, and the signal charge (specifically, electrons) accumulated in the capacitor element 126 is transferred to the second diffusion layer FD2. In this transfer, the signal charge of the capacitor element 126 is charge-distributed to the second diffusion layer FD2.

[0046] A capacitance control line PVDD is connected to the electrode on the other side of the capacitance element 126. A DC bias value can also be supplied to the capacitance control line PVDD. For example, if the DC bias value is set to 1 / 2 of the power supply voltage VDDC, since the voltage at the time of reset of the capacitance element 126 is the power supply voltage VDDC, the voltage between the capacitance elements 126 becomes 1 / 2 of the power supply voltage VDDC. And, when high-intensity light is irradiated, since a large amount of signal charges are transmitted and the potential drops, the potential of the capacitance element 126 rises to around 0V. The voltage between the capacitance elements 126 at this time is 1 / 2 of VDDC. That is, from the time of reset to the time of signal accumulation, the absolute value of the voltage between the capacitance elements 126 is the largest and becomes 1 / 2 of the power supply voltage VDDC. In addition, when the DC bias supplied to the capacitance control line PVDD is set to VDDC, from the time of reset to the time of signal accumulation, the absolute value of the voltage between the capacitance elements 126 is the largest and becomes the power supply voltage VDDC. Accordingly, from the viewpoint of ensuring reliability, in order to reduce the absolute value of the voltage between the capacitance elements 126, supplying a voltage of 1 / 2 of the power supply voltage VDDC as the DC bias supplied to the capacitance control line PVDD is effective.

[0047] Moreover, the capacitance control line PVDD is not limited by the DC bias value, and a bias value can also be provided as a pulse.

[0048] Regarding the switching transistor 122, its gate is connected to the switch control line SW, its drain electrode is connected to the second diffusion layer FD2, and its source electrode is connected to the first diffusion layer FD1.

[0049] And, regarding the reset transistor 123, its gate is connected to the reset control line RS, its drain electrode is connected to the power supply voltage VDDC, and its source electrode is connected to the second diffusion layer FD2. Before transferring the signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1, when a reset pulse transmitted through the reset control line RS is applied at a "High" level to the gate electrode of the reset transistor 123, the reset transistor 123 becomes conductive, and when a switch pulse transmitted through the reset control line SW1 is applied at a "High" level to the gate electrode of the switching transistor 122, the switching transistor 122 also becomes conductive, and the potentials of the first diffusion layer FD1 and the second diffusion layer FD2 are reset to the power supply voltage VDDC.

[0050] Regarding the amplification transistor 124, its gate electrode is connected to the first diffusion layer FD1, its drain electrode is connected to the power supply voltage VDDC, and its source electrode is connected to the drain electrode of the selection transistor 125.

[0051] Regarding the selection transistor 125, its gate electrode is connected to the selection control line SEL, its drain electrode is connected to the source electrode of the amplification transistor 124, and its source electrode is connected to the vertical signal line PIXOUT. When a row to be read is selected, a selection pulse transmitted through the selection control line SEL is applied at a "High" level, the selection transistor 125 becomes conductive, and the source electrode of the amplification transistor 124 is connected to the vertical signal line PIXOUT.

[0052] The amplification transistor 124 outputs the potential of the first diffusion layer FD1 after reset as a reset level to the vertical signal line PIXOUT through the selection transistor 125 in a conductive state, the switch transistor 122, and the reset transistor 123, and outputs the potential of the first diffusion layer FD1 after the signal charge is transferred by the first transfer transistor 121 as a signal level to the vertical signal line PIXOUT. Regarding the combination of the reset level and the signal level, there are three types by switching the switch transistor 122 and the second transfer transistor 128. These three types correspond to, for example, low illuminance use, medium illuminance use, and high illuminance use.

[0053] Here, if the elementary charge is set as q and the capacitance value of the floating diffusion portion is set as C, the conversion efficiency η from the signal charge to voltage is expressed by η = q / C. Since the conversion efficiency η is determined by the capacitance value C, at the gate portion of the amplification transistor 124 when the switch transistor 122 is conductive, since the first diffusion layer FD1 and the second diffusion layer FD2 are in a connected state, compared with the state where only the first diffusion layer FD1 is connected to the gate portion of the amplification transistor 124 when the switch transistor 122 is cutoff, it has the characteristic that the conversion efficiency η decreases.

[0054] Here, when the conversion efficiency η is higher, the signal charge can be converted into voltage more efficiently, so that the voltage value of the output signal can be increased. Accordingly, the ratio S / N of the pixel signal S to the noise component N generated in the column processing circuit 105 connected to the vertical signal line PIXOUT can be increased, and thus a high-quality image can be obtained.

[0055] Also, regarding the reading of the capacitor element 126, since the second transfer transistor 128 is turned on, when transferring to the first diffusion layer FD1, it is not a complete transfer. Instead, through charge distribution, the capacitor element 126 moves the signal charge to the second diffusion layer FD2 and the first diffusion layer FD1. The potential of the first diffusion layer FD1 after the second transfer transistor 128 is turned on is output as the signal level of the capacitor element 126 to the vertical signal line PIXOUT. After that, through the reset transistor 123, the first diffusion layer FD1 is reset to the power supply voltage VDDC. kTC noise occurs when the reset transistor 123 is turned off. The potential of the reset first diffusion layer FD1 is output as the reset level to the vertical signal line PIXOUT. Based on the difference between the signal level and the reset level, the output signal of the signal charge accumulated in the capacitor element 126 is read out, so it becomes an output signal containing kTC noise. Here, since the output signal of the photoelectric conversion element 120 is used for image generation in low illuminance areas, and the output signal of the capacitor element 126 is used for image generation in high illuminance areas, a large dynamic range is achieved. For this reason, since the output signal of the capacitor element 126 accumulates a certain amount of signal charge, the influence of the kTC noise generated here on the image quality is slight.

[0056] Through Figure 2 The pixel unit 101 shown can achieve a large dynamic range by using the output signal of the photoelectric conversion element 120 for image generation corresponding to low illuminance and using the output signal of the capacitor element 126 for image generation corresponding to high illuminance. Also, due to the presence of the capacitor element 126, the photoelectric conversion element 120 is suitable for long-term exposure (for example, constant exposure). Therefore, flicker can be easily suppressed.

[0057] Suppression of flicker will be described herein. In recent years, LED light sources (light-emitting diode light sources) or LD light sources (laser diode light sources) have been increasingly popularized. Most of these light sources are driven dynamically, which means that the lighting and extinguishing are repeated at a speed that is hardly perceptible to the human eye. In other words, flicker at a speed that cannot be felt by the human eye is generated. For example, LED light sources are used not only for lighting fixtures but also for signal lights, vehicle headlights, brake lights, etc. During dynamic lighting, although the human eye sees the light source as being constantly lit, the flicker affects the solid-state imaging device. When the solid-state imaging device captures such a light source or the lighting environment using such a light source, there are the following two cases: one is the case of obtaining an image when the light source is lit (or obtaining a bright image), and the other is the case of obtaining an image when the light source is extinguished (or obtaining a dark image). That is, the phenomenon of flicker occurs in the captured image itself. In the latter case, that is, when obtaining an image when the light source is extinguished (or obtaining a dark image), it can be said that the imaging is defective. Suppressing the imaging defect caused by such flicker is called flicker suppression.

[0058] In addition, although the selection transistor 125 is described herein, a configuration without the selection transistor 125 is also possible. As a method for selecting rows of the pixel unit 101, by increasing the potential of the first diffusion layer FD1 of the pixel unit 101 in the selected row and decreasing the potential of the first diffusion layer FD1 of the non-selected row, the amplification transistor 124 in the selected row can be made effective, and thus output can be made to the vertical signal line PIXOUT.

[0059] [1.2 Cross-sectional configuration example of the pixel unit 101]

[0060] Next is a cross-sectional view schematically showing the first to third configuration examples of the pixel unit 101 in the solid-state imaging device 100 according to the first embodiment.

[0061] Figure 3A It is a cross-sectional view schematically showing the first configuration example of the pixel unit constituting the solid-state imaging device 100 in the first embodiment. In Figure 3AA schematic cross-sectional view of a surface-irradiation type pixel unit 101 is shown. The pixel unit 101 includes, within a semiconductor substrate 150: a well region 140 containing p-type impurities, a photoelectric conversion element 120 containing n-type impurities different from the p-type, a diffusion layer of n-type impurities, an overflow transistor gate 127g, a first transfer transistor gate 121g, a second transfer transistor gate 128g, a switching transistor gate 122g, a reset transistor gate 123g, an amplification transistor gate 124g, and a selection transistor gate 125g. In addition, the pixel unit 101 in this figure has wiring layers L1 to L6 capable of forming wirings. Moreover, the pixel unit 101 has: a first wiring w1 made of polysilicon, a contact c1 made of polysilicon that connects the first wiring w1 and the first diffusion layer FD1, and a contact c2 made of polysilicon that connects the first wiring w1 and the amplification transistor gate 124g. The wiring layers L4 and L5 include wirings made of copper, for example. For example, the contact 145 is made of a copper material. The photoelectric conversion element 120 is formed as a buried diode.

[0062] In addition, as an example of the material of the first wiring w1, although it is a polysilicon material, it is not limited thereto, and a copper material can also be used to form it. And, as an example of the material of the contacts c1 and c2, although it is a polysilicon material, it is not limited thereto, and a copper material can also be used to form it.

[0063] Here, the capacitive element 126 has a concavo-convex pattern. That is, the opposing electrodes of the capacitive element 126 are composed of an electrode formed as a planar wiring pattern with concavo-convexities in the wiring layer L2 and an electrode formed as a planar wiring pattern with concavo-convexities in the wiring layer L3. This is an example of a configuration that can easily increase the capacitance value by increasing the opposing surface area of the electrodes. In addition, the concavo-convexities of the capacitive element 126 may not be provided in the direction parallel to the Figure 3A cross-section, but may be provided in the direction perpendicular to the cross-section.

[0064] Here, as the wiring connecting the first diffusion layer FD1 and the amplification transistor gate 125g, the first wiring w1 is used. The first wiring w1 is formed in the wiring layer L1 on the semiconductor substrate 150 side compared to the capacitive element 126, and the contact length can be made shorter compared to the case of being formed in any of the wiring layers L2 to L6. That is, by shortening the contact lengths of the contacts c1 and c2, the parasitic capacitance between the wirings can be reduced, and the conversion efficiency η can be increased. Accordingly, by increasing the S / N, a high image quality can be obtained.

[0065] Also, as the wiring for connecting the capacitor element 126 to the capacitor element node C1, the wiring w2 within the wiring layer L1 is employed. Accordingly, since the layout flexibility of the contact c4 is increased, the layout flexibility of the capacitor element 126 is increased. In this way, a layout can be achieved in which the area of the capacitor element 126 is configured to the maximum extent, thereby increasing the capacitance value of the capacitor element 126 and realizing an expansion of the dynamic range.

[0066] Also, here, as the first wiring w1 for connecting the first diffusion layer FD1 to the gate 125g of the amplification transistor, by using a polysilicon material, metal contamination of the first diffusion layer FD1 can be suppressed, and leakage current can be reduced.

[0067] Also, as the material of the wiring w2 for connecting the capacitor element 126 to the capacitor element node C1, by using a polysilicon material, metal contamination of the capacitor element node C1 can be suppressed. Accordingly, the leakage current occurring at the capacitor element node C1 can be reduced.

[0068] Also, a part of the first wiring w1 is formed to cover the gate 121g of the first transfer transistor. When a "High" level is applied through a transfer pulse the first transfer transistor 121 becomes conductive. When the photoelectric conversion element 120 is photoelectrically converted and the signal charge (specifically, electrons) accumulated in the photoelectric conversion element 120 is transferred to the first diffusion layer FD1, the potential of the first diffusion layer FD1 rises due to the coupling of the parasitic capacitance. Accordingly, the transfer efficiency of the signal charge (specifically, electrons) from the photoelectric conversion element 120 to the first diffusion layer FD1 is improved, and the occurrence of afterimages can be suppressed.

[0069] Figure 3B It is a cross-sectional view showing a second configuration example of the pixel unit constituting the solid-state imaging device 100 in the first embodiment in a schematic manner. Figure 3B A schematic cross-sectional view of the back-illuminated pixel unit 101 is shown. Figure 3B And Figure 3A The difference from Figure 3B is that light is incident from below the semiconductor substrate 150, and the capacitor element 126 is arranged so as to cover a part of the photoelectric conversion element 120. Hereinafter, the differences from Figure 3A will be mainly described.

[0070] In the plan view of the semiconductor substrate 150, the capacitor element 126 has a portion overlapping with the photoelectric conversion element 120. That is, at least a part of the capacitor element 126 overlaps with at least a part of the photoelectric conversion element 120. Accordingly, in the back-illuminated pixel unit 101 as compared with the surface-illuminated pixel unit, since the capacitor element 126 can be configured to cover the photoelectric conversion element 120, a larger capacitance value can be obtained. Accordingly, an expansion of the dynamic range can be achieved.

[0071] Figure 3C FIG. is a schematic cross-sectional view showing a third configuration example of the pixel unit constituting the solid-state imaging device 100 in the first embodiment in terms of mode. In Figure 3C A schematic cross-sectional view of the back-illuminated pixel unit 101 is shown. Figure 3C Differences from Figure 3B are that the wiring belonging to the wiring layer L1 is formed of a copper material, and a wiring 147 serving as a reflector is formed above the photoelectric conversion element 120, and the wiring 147 serving as the reflector is located in the same wiring layer L1 as the first wiring w1. Hereinafter, the differences from Figure 3C in Figure 3B will be mainly described.

[0072] The wiring 147 serving as a reflector is formed in the same wiring layer L1 as the first wiring w1 and is located at a position overlapping with at least a part of the photoelectric conversion element 120 in the plan view of the semiconductor substrate 150. In the example of this figure, the wiring 147 serving as a reflector overlaps with the entire photoelectric conversion element 120. And the wiring 147 serving as a reflector is formed of a copper material having a higher reflectivity than polysilicon. Accordingly, when the light irradiated from below the semiconductor substrate 150 passes through the photoelectric conversion element 120, it is reflected to the photoelectric conversion element 120 side by the wiring 147 serving as a reflector, so that the photoelectric conversion efficiency of the photoelectric conversion element 120 can be improved. In this way, a reduction in the photoelectric conversion efficiency due to the shape or material of the capacitor element 126 can be prevented.

[0073] [1.3 Potentials of each part of the pixel unit 101]

[0074] Figure 4 FIG. shows the potentials of the pixels constituting the solid-state imaging device 100 in the first embodiment in the semiconductor substrate 150. The horizontal direction of this figure shows the relative position in the semiconductor substrate 150. The vertical direction of this figure shows that the potential becomes higher as it goes downward.

[0075] "FD2" in this figure represents the potential of the second diffusion layer FD2. "TGC" represents the potential of the semiconductor substrate 150 under the second transfer transistor gate 128g. "C1" represents the potential of the capacitor element node C1. "OF" represents the potential of the semiconductor substrate 150 under the overflow transistor gate 127g. "PD" represents the potential of the photoelectric conversion element 120. "TG" represents the potential of the semiconductor substrate 150 under the first transfer transistor gate 121g. "FD1" represents the potential of the first diffusion layer FD1. "SW" represents the potential of the semiconductor substrate 150 under the switch transistor gate 122g. "FD2" represents the potential of the second diffusion layer FD2. "RS" represents the potential of the semiconductor substrate 150 under the reset transistor gate 123g. "VDDC" represents the potential in the power supply voltage VDDC.

[0076] First, Figure 4 (a) shown in represents that during the reset operation, at the reset transistor gate 123g, a "High" level is applied from the reset control line RS as a reset pulse At the switch transistor gate 122g, a "High" level is applied from the switch control line SW as a switch pulse At the first transfer transistor gate 121g, a "High" level is applied from the first transfer control line TG as a reset pulse At the second transfer transistor gate 128g, a "High" level is applied from the second transfer control line TGC as a reset pulse Accordingly, the first diffusion layer FD1, the second diffusion layer FD2, and the capacitor element node (C1) are reset to the power supply voltage VDDC. All signal charges are transferred from the photoelectric conversion element 120, and thus the photoelectric conversion element 120 is reset.

[0077] Figure 4 (b1) shown in shows the potential at the start of exposure during the accumulation control period. At the reset transistor gate 123g, a "Low" level is applied from the reset control line RS as a reset pulse At the switch transistor gate 122g, a "Low" level is applied from the switch control line SW as a switch pulse At the first transfer transistor gate 121g, a "Low" level is applied from the transfer control line TG as a transfer pulse At the second transfer transistor gate 128g, a "Low" level is applied from the transfer control line TGC as a transfer pulse Accordingly, the photoelectric conversion element 120 and the capacitor element 126 become in a state capable of accumulating signal charges.

[0078] Figure 4(b2) shows the potential when storing signal charges during the storage control period. The photoelectric conversion element 120 performs photoelectric conversion according to the irradiated light and stores signal charges. The barrier in the semiconductor substrate 150 under the overflow transistor gate 127g adjacent to the photoelectric conversion element 120 is controlled by the DC bias supplied through the overflow control line OF to be lower than the barrier in the semiconductor substrate 150 under the first transfer transistor gate 121g adjacent to the same photoelectric conversion element 120. Accordingly, when the generation of the signal charges stored in the photoelectric conversion element 120 exceeds the saturation capacity of the photoelectric conversion element 120, the signal charges are transferred to the capacitor element 126 through the semiconductor substrate 150 under the overflow transistor gate 127g, and the signal charges are stored in the capacitor element 126.

[0079] Figure 4 (c1) shows the potential when transferring the signal charges stored in the photoelectric conversion element 120 to the first diffusion layer FD1 during the storage control period. At the first transfer transistor gate 121g, a transfer pulse is applied at the "High" level. Accordingly, all the signal charges stored in the photoelectric conversion element 120 are transferred from the photoelectric conversion element 120 to the first diffusion layer FD1.

[0080] Figure 4 (c2) shows the potential when transferring the signal charges of the capacitor element 126 to the first diffusion layer FD1 and the second diffusion layer FD2. At the second transfer transistor gate 128g, a transfer pulse is applied at the "High" level. Accordingly, the signal charges stored in the capacitor element 126 are transferred from the capacitor element 126 to the second diffusion layer FD2. At the switch transistor gate 122g, a switch pulse is applied at the "High" level. Accordingly, the second diffusion layer FD2 is connected to the first diffusion layer FD1, and the signal charges stored at the capacitor element node C1 are transferred to the first diffusion layer FD1 and the second diffusion layer FD2.

[0081] [2. Operating example of the solid-state imaging device 100]

[0082] Next, Figure 5 shows an example of a timing chart for explaining the operation of the Figure 2 shown pixel.

[0083] First, at time t1, and become at the "High" level, and the second diffusion layer FD2 and the first diffusion layer FD1 are applied with the power supply voltage VDDC. And, Becomes a "High" level, and the signal charges of the photoelectric conversion element 120 are discharged. Also, Becomes a "High" level, and the power supply voltage VDDC is applied to the capacitor element 126.

[0084] At time t2, and Become "Low" levels. At this time, under normal circumstances, due to the noise generated by the on and off of the reset transistor 123 and the switch transistor 122, the potential of the first diffusion layer FD1 has a step. Also, and Become "Low" levels, and the photoelectric conversion element 120 and the capacitor element 126 become states capable of storing signal charges.

[0085] At time t3, Becomes a "Low" level, whereby the potential of the capacitor element node C1 decreases. As shown here Figure 3A , the capacitor element node C1 is connected to the diffusion layer of n-type impurities surrounded by the well region 140 including p-type impurities in the semiconductor substrate 150. Here, as an example, the well region 140 including p-type impurities is applied with the GND potential, and by reducing the potential of the capacitor element node C1, the potential difference between the diffusion layer of n-type impurities and the well region 140 including p-type impurities is reduced, thereby reducing the leakage current.

[0086] At time t4, and Become "High" levels, and the power supply voltage VDDC is applied to the second diffusion layer FD2 and the first diffusion layer FD1. Also, Becomes a "High" level, the selection transistor 125 becomes conductive, and the source electrode of the amplification transistor 124 is electrically connected to the vertical signal line PIXOUT. A certain current flows through the amplification transistor 124 to form a source follower. At the gate electrode of the selection transistor 125 of other pixels connected to the same vertical signal line PIXOUT, as is applied with a "Low" level, the selection transistor 125 is cut off.

[0087] At time t5, Becomes a "Low" level. At this time, due to the coupling of the parasitic capacitance generated by the on and off of the switch transistor 122, the potential of the first diffusion layer FD1 decreases.

[0088] At time t6, Becomes a "Low" level. At this time, due to the noise generated by the on and off of the reset transistor 123, the potential of the second diffusion layer FD2 has a step.

[0089] At time t7, It becomes a "High" level. At this time, due to the coupling of the parasitic capacitance generated by the on / off of the switching transistor 122 and the gate capacitance of the switching transistor 122, the potentials of the first diffusion layer FD1 and the second diffusion layer FD2 rise.

[0090] Accordingly, the transfer efficiency of signal charges (specifically electrons) from the photoelectric conversion element 120 to the first diffusion layer FD1 is improved, thereby suppressing the occurrence of afterimages. And at the time t7a when the potential is stable, the signal level (CL2) is sampled.

[0091] A series of operations from time t4 to time t7 here are operations related to the reset operation of the first diffusion layer FD1 and the second diffusion layer FD2. If the reset operation is performed with this drive, then at At the time t7a when it becomes a "High" level, the potentials of the first diffusion layer FD1 and the second diffusion layer FD2 can become a higher state. The reason is that the reset of the second diffusion layer FD2 at time t6 is performed in a state where is a "Low" level. Therefore, at time t7, when becomes a "High" level, the first diffusion layer FD1 and the second diffusion layer FD2 become floating states because is a "Low" level. When becomes a "High" level, they are coupled due to the parasitic capacitance of the switching transistor 122 and the first diffusion layer FD1 and the second diffusion layer FD2, and thus the potential is raised. By making the potentials of the first diffusion layer FD1 and the second diffusion layer FD2 a higher state, the transfer of signal charges from the photoelectric conversion element 120 becomes easier, and accordingly, the residual of signal charges can be suppressed.

[0092] At time t8, It becomes a "Low" level. At this time, at the time t8a when the potential of the first diffusion layer FD1 is stable, the signal level (CL1) is sampled.

[0093] At time t9, It becomes a "High" level. At this time, signal charges are transferred from the photoelectric conversion element 120 to the first diffusion layer FD1, and the potential of the first diffusion layer FD1 decreases.

[0094] At time t10, It becomes a "Low" level, and the transfer of signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1 ends.

[0095] At time t10a, the potential of the first diffusion layer FD1 stabilizes, and the signal level (SH1) is sampled. Then, in the column processing circuit 105, based on the difference between the signal level (CL1) at time 8a and the signal level (SH1) at time 10a, the output signal Sig1 of the photoelectric conversion element 120 is extracted.

[0096] At time t11, it becomes a "High" level. At this time, in addition to the first diffusion layer FD1, since the capacitance equivalent to the parasitic capacitance of the switching transistor 122 and the second diffusion layer FD2 increases, the conversion efficiency η decreases compared to time t10, and the potential of the first diffusion layer FD1 rises.

[0097] At time t12, it becomes a "High" level. At this time, if there is residual signal charge in the photoelectric conversion element 120, the signal charge is transferred to the first diffusion layer FD1 and the second diffusion layer (FD2), and the potential of the first diffusion layer FD1 decreases.

[0098] At time t13, it becomes a "Low" level, and the transfer of signal charge from the photoelectric conversion element 120 to the first diffusion layer FD1 and the second diffusion layer FD2 ends.

[0099] At the moment t13a when the potential of the first diffusion layer FD1 stabilizes, the signal level (SH2) is sampled. Then, in the column processing circuit 105, based on the difference between the signal level (CL2) at time t7a and the signal level (SH2) at time t13a, the output signal Sig2 of the photoelectric conversion element 120 is extracted.

[0100] At time t14, it becomes a "High" level, and the potential of the capacitor element node C1 rises. And, it becomes a "High" level. At this time, in addition to the capacitances of the first diffusion layer FD1, the switching transistor 122, and the second diffusion layer FD2, the capacitances of the second transfer transistor 128 and the capacitor element 126 also increase. Therefore, compared to time t13, the conversion efficiency η decreases. At the moment t14a when the potential of the first diffusion layer FD1 stabilizes, the signal level (SH3) is sampled.

[0101] At time t15, it becomes a "High" level, and the first diffusion layer FD1, the second diffusion layer FD2, and the capacitor element node C1 are applied with the power supply voltage VDDC.

[0102] At time t16, Becomes the "Low" level. At this time, due to the noise generated by the conduction and cutoff of the reset transistor 123, the potentials of the first diffusion layer FD1, the second diffusion layer FD2, and the capacitor element node C1 have steps. At the moment t16a when the potential of the first diffusion layer FD1 stabilizes, the signal level (CL3) is sampled.

[0103] Then, in the column processing circuit 105, based on the difference between the signal level (SH3) at time 14a and the signal level (CL3) at time 16a, the output signal Sig3 of the photoelectric conversion element 120 is extracted.

[0104] At time t17, and Become the "Low" level. And, Becomes the "Low" level, the selection transistor 125 is cut off, and the connection between the source electrode of the amplification transistor 124 and the vertical signal line PIXOUT is electrically disconnected.

[0105] According to the above timing chart, a total of three output signals Sig1 to Sig3 in different states can be obtained. The output signal Sig1 is a signal that converts signal charges in the photoelectric conversion element 120 into voltage with a higher conversion efficiency with the switching transistor 122 in the cutoff state. The output signal Sig2 is a signal that converts signal charges in the photoelectric conversion element 120 into voltage with the switching transistor 122 in the conducting state. The output signal Sig3 is a signal that converts the signal charges in the photoelectric conversion element 120 and the signal charges stored in the capacitor element 126 that stores the signal charges overflowing from the photoelectric conversion element 120 into voltage with the switching transistor 122 in the conducting state and the second transfer transistor 128 in the conducting state.

[0106] [2.1 Subject Illuminance and Signal Output]

[0107] Figure 6It is a graph showing the relationship between the subject illuminance of the pixels constituting the solid-state imaging device 100 in the first embodiment and the signal output of the pixels. The horizontal axis represents the subject illuminance, and the vertical axis represents the output. In this figure, it shows that the signal charge of the photoelectric conversion element 120, with the switching transistor 122 in the cut-off state, converts the signal charge into an output signal Sig1 of voltage with a higher conversion efficiency; with the switching transistor 122 turned on, converts the signal charge into an output signal Sig2 of voltage; and converts the signal charge of the photoelectric conversion element 120 and the signal charge stored in the capacitor element 126 that has stored the signal charge overflowing from the photoelectric conversion element 120 into voltage and performs arithmetic processing to obtain an output signal Sig3. The slope of the graph depends on the conversion efficiency, the gain setting during AD conversion, the accumulation period, and the exposure period. In the output signal Sig1 that can correspond to a low-illuminance subject, since the conversion efficiency is high and the gain setting during AD conversion is also higher than others, the slope of the graph is steep. And since the output represents the output after AD conversion, the maximum value depends on the number of bits (bit number) during AD conversion.

[0108] When the subject illuminance becomes L01, the output value after AD conversion of Sig1 reaches the maximum value, thus becoming a fixed output independent of the subject illuminance.

[0109] When the subject illuminance becomes L02, the output value after AD conversion of Sig2 reaches the maximum value, thus becoming a fixed output independent of the subject illuminance. Since the conversion efficiency of the first diffusion layer FD1 is lower and the gain setting during AD conversion is also lower compared to Sig1, the output at the subject illuminance L02 on the higher illuminance side becomes the maximum value.

[0110] When the subject illuminance becomes L03, the output value after AD conversion of Sig3 reaches the maximum value, thus becoming a fixed output independent of the subject illuminance.

[0111] Compared with Sig2, the range of subject illuminance that Sig3 can capture is relatively large, being 0 to L3. Therefore, even when the subject illuminance is relatively high, a signal charge corresponding to the subject illuminance can be obtained. This is because the signal charge overflowing from the photoelectric conversion element 120 can be stored in the capacitor element 126.

[0112] In this way, the output signals Sig1, Sig2, and Sig3 are for low illuminance, medium illuminance, and high illuminance.

[0113] Here, in order to suppress the flicker generated by the LED light source, the solid-state imaging device 100 needs to perform an exposure operation frequently. Regarding the output signals Sig1 and Sig2, since they are the signal charges of the photoelectric conversion element 120 and are the signal charges obtained during the frequent exposure operation, the flicker is suppressed. And regarding Sig3, by using the capacitor element 126 to increase the accumulated charge amount of the signal charge, an image with the flicker of the LED light source suppressed can be obtained in a state where a high-luminance subject can be photographed.

[0114] [2.2 Subject Illuminance and SN Ratio]

[0115] Figure 7 It is a graph showing the relationship between the subject illuminance of the pixels constituting the solid-state imaging device 100 in the first embodiment and the SN (signal-to-noise ratio) of the pixels. The horizontal axis represents the subject illuminance, and the vertical axis represents the SN. In this figure, from low illuminance to high illuminance, the output signals of Sig1, Sig2, and Sig3 are connected to show the SN of the image with respect to the subject illuminance. By synthesizing each output signal, a high SN can be maintained and a large dynamic range can be obtained.

[0116] Moreover, if the capacitor element 126 is used, kTC noise is included in the output signal, resulting in serious noise. If an image with a large dynamic range is obtained only with Sig3, the influence of kTC noise becomes significant in the low-illuminance region, and the image quality (S / N) deteriorates. In particular, the image quality of low illuminance that emphasizes SN is unacceptable. However, in the first embodiment, since the image quality of low illuminance is from the output signals Sig1 and Sig2 of the photoelectric conversion element 120, there is no problem of deterioration in the S / N of the low-illuminance image quality.

[0117] For example, the output signal of the photoelectric conversion element 120 can be used for image generation corresponding to low illuminance to maintain a high SN. And a large dynamic range can be achieved by using the output signal of the capacitor element 126 for image generation corresponding to high illuminance. And because there is the capacitor element 126, the photoelectric conversion element 120 is suitable for long-term exposure (such as frequent exposure). Therefore, flicker can be easily suppressed.

[0118] As described above, the solid-state imaging device 100 in Embodiment 1 includes: a photoelectric conversion element 120 formed on a semiconductor substrate 150, which accumulates signal charges generated by photoelectric conversion; a first diffusion layer FD1 that holds the signal charges transferred from the photoelectric conversion element 120; a capacitor element 126 that holds the signal charges overflowing from the photoelectric conversion element 120; an amplification transistor 124 that outputs a signal corresponding to the amount of signal charges in the first diffusion layer FD1; a first contact c1 connected to the first diffusion layer FD1; a second contact c2 connected to the gate of the amplification transistor 124; and a first wiring w1 that connects the first contact c1 and the second contact c2. The first wiring w1 is disposed between the semiconductor substrate 150 and the capacitor element 126 in the normal direction of the semiconductor substrate 150. In other words, the shortest distance between the semiconductor substrate 150 and the first wiring w1 is smaller than the shortest distance between the semiconductor substrate 150 and the capacitor element 126.

[0119] Accordingly, it is possible to suppress the deterioration of the SN ratio due to the expansion of the dynamic range. Specifically, it is possible to reduce the parasitic capacitance of the first wiring and increase the conversion efficiency of the amplification transistor 124 that converts the potential of the first diffusion layer into a voltage. Accordingly, it is possible to suppress the deterioration of the SN ratio and obtain high image quality.

[0120] Here, it may also be that the solid-state imaging device 100 includes a plurality of wiring layers, and the first wiring w1 includes a wiring layer L1 closest to the semiconductor substrate 150 among the plurality of wiring layers.

[0121] Accordingly, it is possible to further reduce the parasitic capacitance of the first wiring.

[0122] Here, it may also be that the closest wiring layer is a wiring layer that does not include the gate of the amplification transistor 124.

[0123] Accordingly, for example, when there is no wiring in the layer that does not include the gate, the closest wiring layer becomes a wiring layer that does not include the gate. In this case, it is possible to effectively reduce the parasitic capacitance of the first wiring.

[0124] Here, it may also be that the closest wiring layer is a wiring layer that includes the gate of the amplification transistor 124.

[0125] Accordingly, for example, when the gate and the wiring connecting the gate are located in the same wiring layer, this wiring layer becomes the closest wiring layer. In this case, it is possible to effectively reduce the parasitic capacitance of the first wiring.

[0126] Here, the solid-state imaging device 100 may further include a first transfer transistor 121 that transfers signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1. In the plan view of the semiconductor substrate 150, a first wiring w1 overlaps with a part of the gate electrode of the first transfer transistor 121.

[0127] Accordingly, when the signal charges are transferred from the photoelectric conversion element 120 to the first diffusion layer FD1, due to the coupling of the parasitic capacitance between the first wiring and the gate electrode 121g of the first transfer transistor 121, the potential of the first diffusion layer FD1 rises. Accordingly, the transfer efficiency of the signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1 can be improved, and the occurrence of afterimages can be suppressed.

[0128] Here, the solid-state imaging device 100 may further include: a third contact c3 connected to a capacitance element node C1 formed on the semiconductor substrate 150; a fourth contact c4 connected to the capacitance element 126; and a second wiring w2 connecting the third contact and the fourth contact. The second wiring w2 is included in the same wiring layer L1 as the first wiring w1.

[0129] Accordingly, the layout flexibility of the capacitance element 126 can be improved. For example, a layout that maximally configures the area of the capacitance element 126 can be achieved, the capacitance value of the capacitance element 126 can be increased, and the dynamic range can be expanded.

[0130] Here, the first wiring w1 may include polysilicon.

[0131] Accordingly, metal contamination of the first diffusion layer FD1 can be suppressed, and leakage current can be reduced.

[0132] Here, the solid-state imaging device 100 may be a back-illuminated structure.

[0133] Accordingly, the photoelectric conversion efficiency of the photoelectric conversion element 120 can be improved.

[0134] Here, in the plan view of the semiconductor substrate 150, the capacitance element 126 may overlap at least a part of the photoelectric conversion element 120.

[0135] Accordingly, the capacitance element 126 can obtain a larger capacitance value. Accordingly, the dynamic range can be easily expanded.

[0136] Here, the solid-state imaging device 100 may further include a wiring 147 as a reflector. The wiring 147 as the reflector is located in the same wiring layer L1 as the first wiring w1 and overlaps at least a part of the photoelectric conversion element 120 in the plan view of the semiconductor substrate 150.

[0137] Accordingly, the photoelectric conversion efficiency of the photoelectric conversion element 120 can be improved. For example, without the reflector, the photoelectric conversion efficiency of the reflected light depends on the shape and / or material of the capacitor element 126 and decreases. The reflector can prevent the decrease in the photoelectric conversion efficiency.

[0138] Here, the solid-state imaging device 100 may further include: a first transfer transistor 121 that transfers signal charges from the photoelectric conversion element 120 to the first diffusion layer FD1; a second diffusion layer FD2 that holds the signal charges transferred from the capacitor element 126; a switch transistor 122 that connects the first diffusion layer FD1 and the second diffusion layer FD2; a second transfer transistor 128 that transfers signal charges from the capacitor element 126 to the second diffusion layer FD2; and a reset transistor 123 that resets the first diffusion layer FD1.

[0139] Accordingly, the transfer of signal charges from the capacitor element 126 to the second diffusion layer FD2 can be controlled.

[0140] Here, the solid-state imaging device 100 starts the reset operation of the first diffusion layer FD1 and the second diffusion layer FD2 by turning on the reset transistor 123 and the switch transistor 122.

[0141] Accordingly, the second diffusion layer FD2 and the first diffusion layer FD1 can be reset simultaneously.

[0142] Here, the solid-state imaging device 100 releases the reset operation of the first diffusion layer FD1 by turning off the switch transistor 122 after the start of the reset operation of the first diffusion layer FD1 and the second diffusion layer FD2.

[0143] Accordingly, the reset operation of the first diffusion layer FD1 can be released while continuing the reset operation of the second diffusion layer FD2.

[0144] Here, the solid-state imaging device 100 releases the reset operation of the second diffusion layer FD2 by turning off the reset transistor 123 after releasing the reset operation of the first diffusion layer FD1.

[0145] Here, the solid-state imaging device 100 outputs the reset level from the amplification transistor 124 in a state where the switch transistor 122 is turned on after the reset of the second diffusion layer FD2 is released.

[0146] Accordingly, the reset level in a state where the second diffusion layer FD2 and the first diffusion layer FD1 are connected can be output.

[0147] Here, it is also possible that after the solid-state imaging device 100 reads out at the reset level, the switching transistor 122 is turned off, and other reset levels are output from the amplification transistor 124.

[0148] Accordingly, even in a state where the second diffusion layer FD2 and the first diffusion layer FD1 are not connected, the reset level of the first diffusion layer FD1 can be output.

[0149] Here, it is also possible that in the solid-state imaging device 100, the amplification transistor 124 outputs a first reset level and a second reset level. The second reset level is output from the amplification transistor 124 in a state where the reset of the second diffusion layer FD2 is released and the switching transistor 122 is turned on. The first reset level is output from the amplification transistor 124 in a state where the second reset level is output and the switching transistor 122 is turned off.

[0150] Here, it is also possible that the amplification transistor 124 outputs a first signal level and a second signal level. The first signal level is output from the amplification transistor 124 in a state where the first reset level is output, the first transfer transistor 121 is turned on and then off, and the switching transistor 122 is turned off. The second signal level is output from the amplification transistor 124 in a state where the first signal level is output, the first transfer transistor 121 is turned on and then off, and the switching transistor 122 is turned on. The first reset level and the first signal level are the processing objects of CDS (correlated double sampling). The second reset level and the second signal level are the processing objects of CDS.

[0151] Accordingly, it is possible to easily achieve a large dynamic range. For example, based on the first reset level and the first signal level, a pixel signal for low illuminance can be obtained with high sensitivity. And based on the second reset level and the second signal level, a pixel signal for higher high illuminance can be obtained with lower sensitivity.

[0152] Here, it is also possible that the amplification transistor 124 outputs a third signal level and a third reset level. The third signal level is output from the amplification transistor 124 in a state where the second signal level is output, the second transfer transistor is turned on, and the switching transistor 122 is turned on. The third reset level is output from the amplification transistor 124 in a state where the third signal level is output and the reset transistor 123 is turned on and then off.

[0153] Accordingly, the dynamic range can be easily expanded. For example, pixel signals for low illuminance can be obtained with high sensitivity from the first reset level and the first signal level. Pixel signals for medium illuminance can be obtained with medium sensitivity from the second reset level and the second signal level. Pixel signals for high illuminance can be obtained with low sensitivity from the third reset level and the third signal level. Moreover, the dynamic range can be expanded by synthesizing at least two of the pixel signals for low illuminance, medium illuminance, and high illuminance.

[0154] (Second Embodiment)

[0155] Figure 8 FIG. 7 is a diagram showing a configuration example of an imaging device 200 to which the solid-state imaging device 100 in the second embodiment is applied. The imaging device in this figure is a camera system and includes: a solid-state imaging device 100, an imaging optical system 202 including a lens, a signal processing unit 203, a driving circuit 204, and a system control unit 205.

[0156] In Figure 8 the imaging device 200 shown, the solid-state imaging device 100 of the first embodiment (including each modification) is used.

[0157] Moreover, the driving circuit 204 receives a control signal corresponding to the driving mode from the system control unit 205 and provides a driving mode signal to the solid-state imaging device 100. In the solid-state imaging device 100 to which the driving mode signal is provided, the timing generation circuit 109 generates driving pulses corresponding to the driving mode signal and provides them to each functional block in the solid-state imaging device 100.

[0158] Furthermore, the signal processing unit 203 receives the image signal output from the solid-state imaging device 100 and performs various signal processes on the image signal.

[0159] In this way, the imaging device in the present embodiment includes: the above-described solid-state imaging device 100, an imaging optical system 202 that guides incident light from a subject to the solid-state imaging device 100, and a signal processing unit 203 that processes the output signal from the solid-state imaging device 100.

[0160] The present disclosure relates to a solid-state imaging device and an imaging device that uses the solid-state imaging device as an imaging apparatus, and is most suitable for, for example, cameras, digital cameras, and the like.

[0161] Reference Signs

[0162] 100 Solid-state imaging device

[0163] 101 Pixel unit

[0164] 102 Pixel array unit

[0165] 103 Vertical scanning circuit

[0166] 104 Constant current source circuit

[0167] 105 Column processing circuit

[0168] 106 Horizontal scanning circuit

[0169] 107 Signal processing circuit

[0170] 108 Output circuit

[0171] 109 Timing generation circuit

[0172] 120 Photoelectric conversion element

[0173] 121 First transfer transistor

[0174] 122 Switching transistor

[0175] 123 Reset transistor

[0176] 124 Amplifying transistor

[0177] 125 Selecting transistor

[0178] 126 Capacitor element

[0179] 127 Overflow transistor

[0180] 128 Second transfer transistor

[0181] 129 Charge discharging transistor

[0182] 140 Well region

[0183] 147 Wiring

[0184] 150 Semiconductor substrate

[0185] 200 Imaging device

[0186] 202 Imaging optical system

[0187] 203 Signal processing section

[0188] FD1 First diffusion layer

[0189] FD2 Second diffusion layer

[0190] C1 Capacitor element node

[0191] c1 to c5 Contacts

[0192] L1 to L6 Wiring layers

[0193] w1 First wiring

[0194] w2 Second wiring

Claims

1. A solid-state imaging device, The solid-state imaging device includes: A photoelectric conversion element formed on a semiconductor substrate that generates signal charges through photoelectric conversion; A first diffusion layer that holds the signal charges transferred from the photoelectric conversion element; A capacitor element that holds signal charges overflowing from the photoelectric conversion element; An amplifying transistor that outputs a signal corresponding to the signal charge of the first diffusion layer; A first contact connected to the first diffusion layer; A second contact connected to the gate of the amplifying transistor; A first wiring connecting the first contact and the second contact; A first transfer transistor that transfers signal charge from the photoelectric conversion element to the first diffusion layer; A second diffusion layer that holds the signal charge transferred from the capacitor element; A switching transistor that connects the first diffusion layer and the second diffusion layer; A second transfer transistor that transfers signal charge from the capacitor element to the second diffusion layer; And A reset transistor that resets the first diffusion layer, The shortest distance between the semiconductor substrate and the first wiring is smaller than the shortest distance between the semiconductor substrate and the capacitor element.

2. The solid-state imaging device according to claim 1, The solid-state imaging device includes a plurality of wiring layers, The first wiring is included in the wiring layer closest to the semiconductor substrate among the plurality of wiring layers.

3. The solid-state imaging device according to claim 2, The closest wiring layer is a wiring layer that does not include the gate of the amplifying transistor.

4. The solid-state imaging device according to claim 2, The closest wiring layer is a wiring layer that includes the gate of the amplifying transistor.

5. The solid-state imaging device according to claim 2, In a plan view of the semiconductor substrate, the first wiring overlaps a part of the gate electrode of the first transfer transistor.

6. The solid-state imaging device according to any one of claims 1 to 5, The solid-state imaging device further includes: A third contact connected to the capacitor element; A fourth contact connected to a capacitor element node formed on the semiconductor substrate; and A second wiring that connects the third contact and the fourth contact, The second wiring is included in the same wiring layer as the first wiring.

7. The solid-state imaging device according to any one of claims 1 to 5, wherein the first wiring includes polysilicon.

8. The solid-state imaging device according to any one of claims 1 to 5, wherein the solid-state imaging device has a back-illuminated structure.

9. The solid-state imaging device according to claim 8, wherein in a plan view of the semiconductor substrate, the capacitor element overlaps at least a part of the photoelectric conversion element.

10. The solid-state imaging device according to claim 8, wherein the solid-state imaging device further includes wiring serving as a reflector, the wiring serving as a reflector is located on the same wiring layer as the first wiring, and in a plan view of the semiconductor substrate, overlaps at least a part of the photoelectric conversion element.

11. The solid-state imaging device according to any one of claims 1 to 5, wherein the reset operation of the first diffusion layer and the second diffusion layer is started by turning on the reset transistor and the switch transistor.

12. The solid-state imaging device according to claim 11, wherein after the reset operation of the first diffusion layer and the second diffusion layer is started, the reset operation of the first diffusion layer is cancelled by turning off the switch transistor.

13. The solid-state imaging device according to claim 12, wherein after the reset operation of the first diffusion layer is cancelled, the reset operation of the second diffusion layer is cancelled by turning off the reset transistor.

14. The solid-state imaging device according to claim 13, wherein after the reset operation of the second diffusion layer is cancelled, a reset level is output from the amplifier transistor with the switch transistor turned on.

15. The solid-state imaging device according to claim 14, wherein after the reset level is read out, another reset level is output from the amplifier transistor with the switch transistor turned off.

16. The solid-state imaging device according to claim 13, wherein the amplifier transistor outputs a first reset level and a second reset level, the second reset level is output from the amplifier transistor with the switch transistor turned on after the reset operation of the second diffusion layer is cancelled, and the first reset level is output from the amplifier transistor with the switch transistor turned off after the second reset level is output.

17. The solid-state imaging device according to claim 16, wherein the amplifying transistor outputs a first signal level and a second signal level, wherein the first signal level is output from the amplifying transistor in a state where the first transfer transistor is turned on and then off and the switching transistor is turned off after the first reset level is output, wherein the second signal level is output from the amplifying transistor in a state where the first transfer transistor is turned on and then off and the switching transistor is turned on after the first signal level is output, wherein the first reset level and the first signal level are objects of correlated double sampling processing, and wherein the second reset level and the second signal level are objects of correlated double sampling processing.

18. The solid-state imaging device according to claim 17, further, wherein the amplifying transistor outputs a third signal level and a third reset level, wherein the third signal level is output from the amplifying transistor in a state where the second transfer transistor is turned on and the switching transistor is turned on after the second signal level is output, and wherein the third reset level is output from the amplifying transistor in a state where the reset transistor is turned on and then off after the third signal level is output.

19. The solid-state imaging device according to any one of claims 1 to 5, wherein in a plan view of the semiconductor substrate, the first wiring does not overlap with the capacitor element.

20. An imaging device, comprising: the solid-state imaging device according to any one of claims 1 to 19 that captures an object; an imaging optical system that guides incident light from the object to the solid-state imaging device; and a signal processing unit that processes an output signal from the solid-state imaging device.

Images