Error correction encoding apparatus, error correction encoding method, error correction apparatus, error correction method, communication method, optical communication system, and communication system employing soft decision error correction frame data structure

Abstract

An error correction coding device (100) includes an encoding section (120) that generates soft decision error correction frame information composed of an m-row by N-column bit array by combining first bit string group information and second bit string group information based on input information, the first bit string group information being composed of an m-row by N1-column bit array and capable of being pulse amplitude modulated into modulation symbols by combining bit values of each column of the first bit string group information using a first symbol mapping rule, the second bit string group information being composed of an m-row by N2-column bit array and capable of being pulse amplitude modulated into modulation symbols by combining bit values of each column of the second bit string group information using a second symbol mapping rule.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an error correction encoding apparatus, an error correction encoding method, an error correction apparatus, an error correction method, a communication method, an optical communication system, and a soft-decision error correction frame data structure. BACKGROUND

[0002] There is a communication system in which a transmission apparatus performs error correction encoding on input information input to the transmission apparatus, transmits a signal based on the information subjected to the error correction encoding to a reception apparatus, and the reception apparatus receives the signal transmitted from the transmission apparatus, performs error correction on information based on the signal, and thereby outputs output information corresponding to the input information.

[0003] For example, in Non-Patent Literature 1, a communication method using information generated by combining a probability distribution shaping encoding process and a multi-level encoding process in the field of an optical communication system is disclosed. The information has a prescribed data structure in which a combination of a plurality of bits can be multi-value modulated by separately using two symbol mappings of a first symbol mapping and a second symbol mapping.

[0004] Specifically, a transmission apparatus (hereinafter referred to as a "conventional transmission apparatus") described in Non-Patent Literature 1 generates information having the above-described data structure based on input information. More specifically, the conventional transmission apparatus performs a soft-decision error correction encoding process using a bit located at the lowest bit and a plurality of bits located at the middle bit as an object of a Golay encoding process, and configures a soft-decision parity check bit obtained by the soft-decision error correction encoding process to a bit located at the highest bit, thereby generating information having the above-described data structure. Further, the conventional transmission apparatus divides a first symbol group in which the bit located at the highest bit is the soft-decision parity check bit and a second symbol group in which the bit located at the highest bit is not the soft-decision parity check bit. The conventional transmission apparatus performs a first symbol mapping based on a Golay code on a symbol belonging to the first symbol group, and performs a second symbol mapping different from the first symbol mapping on a symbol belonging to the second symbol group.

[0005] Further, a reception device described in Non-Patent Literature 1 (hereinafter referred to as "conventional reception device") receives a signal generated by the conventional transmission device based on information having the above-described data structure, performs multi-level decoding processing on information based on the signal, and thereby acquires output information corresponding to input information. More specifically, the conventional reception device performs soft-decision error correction processing using soft-decision parity check bits, and thereby performs error correction on bits located at the lowest level and a plurality of bits located at the middle level that are the object of the Gray encoding processing. Further, the conventional reception device performs hard-decision processing on a plurality of bits located at the middle level and a bit located at the highest level with respect to a symbol of the highest level that is not a soft-decision parity check bit, i.e., a symbol corresponding to a symbol belonging to the 1st symbol group in the conventional transmission device, using a bit value after the above-described soft-decision error correction processing of a bit located at the lowest level of the symbol.

[0006] Prior Art Documents

[0007] Non-Patent Literature

[0008] Non-Patent Literature 1: K. Sugitani et al., "Partial multilevel coding with probabilistic shaping for low-power optical transmission", Proc. OECC / PSC 2019, Paper TuB1-5. SUMMARY

[0009] Problems to be Solved by the Invention

[0010] Generally, in soft-decision error correction encoding processing, the more the number of bits that become the object of protection by soft-decision error correction increases, the more the amount of calculation required increases. Therefore, it is desirable for soft-decision error correction encoding processing to reduce the number of bits that become the object of protection by soft-decision error correction.

[0011] The soft-decision error correction encoding processing described in Non-Patent Literature 1 (hereinafter referred to as "conventional soft-decision error correction encoding processing") uses bits located at the lowest level and a plurality of bits located at the middle level that are the object of the Gray encoding processing. Therefore, in the conventional soft-decision error correction encoding processing, there is a problem in that all bits except for bits located at the highest level are set as the object of protection by soft-decision error correction.

[0012] The present disclosure is used to solve the above-described problem, and aims to provide an error correction encoding device that can reduce the number of bits that become the object of protection by soft-decision error correction compared to the conventional soft-decision error correction encoding processing.

[0013] Means for Solving the Problems

[0014] The error correction coding apparatus of the present disclosure is configured to include:

[0015] an input information acquisition section that acquires input information;

[0016] an encoding section that generates soft decision error correction frame information composed of an m-row by N-column bit array in which a first bit string group information composed of an m-row by N1-column bit array and a second bit string group information composed of an m-row by N2-column bit array are combined, based on the input information acquired by the input information acquisition section, the first bit string group information being able to be pulse amplitude modulated into modulation symbols by using a first symbol mapping rule that is decided in advance, the second bit string group information being able to be pulse amplitude modulated into modulation symbols by using a second symbol mapping rule that is decided in advance, where m is a natural number of 2 or more, N1 is a natural number of 2 or more, N2 is a natural number of 1 or more, and N is a number obtained by adding N1 and N2;

[0017] a modulation symbol conversion section that pulse amplitude modulates the combination of the bit values of each column of the soft decision error correction frame information generated by the encoding section into modulation symbols according to each column of the soft decision error correction frame information by using the first symbol mapping rule or the second symbol mapping rule, thereby generating modulation symbol group information composed of N modulation symbols; and

[0018] a transmission waveform shaping section that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion section, and outputs the generated digital baseband modulation signal,

[0019] the encoding section generates the soft decision error correction frame information by the following processing:

[0020] generates first input bit array information composed of an m-1-row by N-column bit array and second input bit array information composed of a 1-row by N3-column bit array based on the input information acquired by the input information acquisition section, where N3 is a natural number of 1 or more and smaller than N1,

[0021] stores the generated second input bit array information as a part of the first MSB information composed of a 1-row by N1-column bit array in a decided region of the first row of the first bit string group information,

[0022] generates shaped bit array information composed of an m-1-row by N-column bit array by performing a probability distribution shaping coding process on the generated first input bit array information,

[0023] By separating the generated shaped bit array information, a first set of bit array information consisting of a combination of N1 predetermined columns and a second set of bit array information consisting of a combination of N2 predetermined columns are generated.

[0024] The first LSB information consisting of a 1-row N1-column bit array is generated by extracting the bit array of the m-1th row in the first group of bit array information from the generated first group of bit array information, and the inverted first LSB information consisting of a 1-row N1-column bit array is generated by calculating the exclusive OR of the bit values ​​of each column in the generated 1 LSB information and the bit values ​​of each column in the information of the first row in the first bit string group information after storing the second input bit array information, thereby generating the inverted first LSB information consisting of a 1-row N1-column bit array, and storing the generated inverted first LSB information in the mth row in the first bit string group information.

[0025] The second LSB information consisting of a 1-row N2-column bit array is generated by extracting the m-1-th row bit array from the generated second group of bit array information, and the generated second LSB information is stored in the m-th row of the second bit string group information.

[0026] Soft decision parity bits are generated by performing a systematic soft decision error correction coding process using the generated inverted first LSB information and the generated second LSB information. The generated soft decision parity bits are stored in the first row of the second bit string group information as the second MSB information consisting of a 1-row N2-column bit array.

[0027] When m is greater than or equal to 3, the first to m-2th rows of the first group of bit array information are extracted from the generated first group of bit array information, thereby generating the first SSB information consisting of the m-2 rows and N1 columns of the bit array, and storing the generated first SSB information in the second to m-1th rows of the first bit string group information.

[0028] When m is greater than 3, the 1st to m-2th rows in the second group of bit array information are extracted from the generated second group of bit array information, thereby generating the second SSB information consisting of a bit array of m-2 rows and N2 columns, and the generated second SSB information is stored in the 2nd to m-1th rows in the second bit string group information.

[0029] Effects of the Invention

[0030] According to the present disclosure, the number of bits to be protected by soft decision error correction can be reduced compared to conventional soft decision error correction coding processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1This is a structural diagram showing an example of the structure of the main part of the communication system according to the first embodiment.

[0032] Figure 2 This is a structural diagram showing an example of the structure of the main part of the error correction coding device according to the first embodiment.

[0033] Figure 3 This is a structural diagram showing an example of the structure of the main part of the encoding unit according to embodiment 1.

[0034] Figure 4A This is an explanatory diagram for explaining an example of the first symbol mapping rule according to the first embodiment. Figure 4B This is an explanatory diagram for explaining an example of the second symbol mapping rule according to the first embodiment.

[0035] Figure 5A and Figure 5B This is a diagram showing an example of the hardware configuration of the error correction coding device according to the first embodiment.

[0036] Figure 6A This is a part of a flowchart showing an example of processing by the error correction encoding device according to the first embodiment.

[0037] Figure 6B This is another part of the flowchart showing an example of processing by the error correction encoding device according to the first embodiment.

[0038] Figure 6C This is the remaining portion of the flowchart showing an example of processing by the error correction encoding device according to the first embodiment.

[0039] Figure 7 This is a structural diagram showing an example of the structure of the main part of the error correction device according to the first embodiment.

[0040] Figure 8 This is a structural diagram showing an example of the structure of the main part of the decoding unit according to the first embodiment.

[0041] Figure 9A and Figure 9B This is a diagram showing an example of the hardware configuration of the error correction device according to the first embodiment.

[0042] Figure 10A This is a part of a flowchart showing an example of processing of the error correction device according to the first embodiment.

[0043] Figure 10B This is another part of the flowchart showing an example of the processing of the error correction device according to the first embodiment.

[0044] Figure 10C This is the remaining portion of the flowchart showing an example of processing by the error correction device according to the first embodiment.

[0045] Figure 11 is a structural diagram showing an example of the structure of a main part of the communication system of Embodiment 2.

[0046] Figure 12 is a structural diagram showing an example of the structure of a main part of the error correction encoding device of Embodiment 2.

[0047] Figure 13 is a structural diagram showing an example of the structure of a main part of the encoding section of Embodiment 2.

[0048] Figure 14A is a part of a flowchart showing an example of the processing of the error correction encoding device of Embodiment 2.

[0049] Figure 14B is another part of a flowchart showing an example of the processing of the error correction encoding device of Embodiment 2.

[0050] Figure 14C is a remaining part of a flowchart showing an example of the processing of the error correction encoding device of Embodiment 2.

[0051] Figure 15 is a structural diagram showing an example of the structure of a main part of the error correction device of Embodiment 2.

[0052] Figure 16 is a structural diagram showing an example of the structure of a main part of the decoding section of Embodiment 2.

[0053] Figure 17A is a part of a flowchart showing an example of the processing of the error correction device of Embodiment 2.

[0054] Figure 17B is another part of a flowchart showing an example of the processing of the error correction device of Embodiment 2.

[0055] Figure 17C is a remaining part of a flowchart showing an example of the processing of the error correction device of Embodiment 2.

[0056] Figure 18 is a structural diagram showing an example of the structure of a main part of the communication system of Embodiment 3.

[0057] Figure 19 is a structural diagram showing an example of the structure of a main part of the error correction encoding device of Embodiment 3.

[0058] Figure 20 is a structural diagram showing an example of the structure of a main part of the encoding section of Embodiment 3.

[0059] Figure 21A is a part of a flowchart showing an example of the processing of the error correction encoding device of Embodiment 3.

[0060] Figure 21B FIG. 6 is another portion of a flowchart showing an example of the processing of the error correction encoding device of Embodiment 3.

[0061] Figure 21C FIG. 7 is the remaining portion of the flowchart showing an example of the processing of the error correction encoding device of Embodiment 3.

[0062] Figure 22 FIG. 8 is a configuration diagram showing an example of the configuration of the main portion of the error correction device of Embodiment 3.

[0063] Figure 23 FIG. 9 is a configuration diagram showing an example of the configuration of the main portion of the decoding section of Embodiment 3.

[0064] Figure 24A FIG. 10 is a portion of a flowchart showing an example of the processing of the error correction device of Embodiment 3.

[0065] Figure 24B FIG. 11 is another portion of a flowchart showing an example of the processing of the error correction device of Embodiment 3.

[0066] Figure 24C FIG. 12 is the remaining portion of the flowchart showing an example of the processing of the error correction device of Embodiment 3.

[0067] Figure 25A FIG. 13 is an explanatory diagram showing an example of the bit array space in which the soft decision error correction frame information before the exchange by the interleaving section of Embodiment 3 is stored. Figure 25B FIG. 14 is an explanatory diagram showing an example of the bit array space in which the soft decision error correction frame information after the exchange by the interleaving section of Embodiment 3 is stored.

[0068] Figure 26A FIG. 15 is an explanatory diagram showing an example of the modulation symbol group information in the case where the error correction encoding device of Embodiment 3 does not have an interleaving section. Figure 26B FIG. 16 is an explanatory diagram showing an example of the modulation symbol group information in the case where the error correction encoding device of Embodiment 3 has an interleaving section.

[0069] Figure 27A FIG. 17 is an explanatory diagram showing an example of the bit array space in which the soft decision error correction frame information before the exchange by the LSB interleaving section of Embodiment 3 is stored. Figure 27B FIG. 18 is an explanatory diagram showing an example of the bit array space in which the soft decision error correction frame information after the exchange by the LSB interleaving section of Embodiment 3 is stored.

[0070] Figure 28 FIG. 19 is a configuration diagram showing an example of the configuration of the main portion of the communication system of the modified example of Embodiment 1.

[0071] Figure 29 is a structural diagram showing an example of the structure of a main part of the error correction encoding device of the modification example of Embodiment 1.

[0072] Figure 30 is a structural diagram showing an example of the structure of a main part of the encoding section of the modification example of Embodiment 1.

[0073] Figure 31A is a part of a flowchart showing an example of the processing of the error correction encoding device of the modification example of Embodiment 1.

[0074] Figure 31B is another part of the flowchart showing an example of the processing of the error correction encoding device of the modification example of Embodiment 1.

[0075] Figure 31C is a remaining part of the flowchart showing an example of the processing of the error correction encoding device of the modification example of Embodiment 1.

[0076] Figure 32 is a structural diagram showing an example of the structure of a main part of the error correction device of the modification example of Embodiment 1.

[0077] Figure 33 is a structural diagram showing an example of the structure of a main part of the decoding section of the modification example of Embodiment 1.

[0078] Figure 34A is a part of a flowchart showing an example of the processing of the error correction device of the modification example of Embodiment 1.

[0079] Figure 34B is another part of the flowchart showing an example of the processing of the error correction device of the modification example of Embodiment 1.

[0080] Figure 34C is a remaining part of the flowchart showing an example of the processing of the error correction device of the modification example of Embodiment 1.

[0081] Figure 35 is a structural diagram showing an example of the structure of a main part of the communication system of the modification example of Embodiment 2.

[0082] Figure 36 is a structural diagram showing an example of the structure of a main part of the error correction encoding device of the modification example of Embodiment 2.

[0083] Figure 37 is a structural diagram showing an example of the structure of a main part of the encoding section of the modification example of Embodiment 2.

[0084] Figure 38A is a part of a flowchart showing an example of the processing of the error correction encoding device of the modification example of Embodiment 2.

[0085] Figure 38B FIG. 6 is another part of a flowchart showing an example of the process of the error correction encoding device of the modification example of Embodiment 2.

[0086] Figure 38C FIG. 7 is the remaining part of the flowchart showing an example of the process of the error correction encoding device of the modification example of Embodiment 2.

[0087] Figure 39 FIG. 8 is a configuration diagram showing an example of the configuration of the main part of the error correction device of the modification example of Embodiment 2.

[0088] Figure 40 FIG. 9 is a configuration diagram showing an example of the configuration of the main part of the decoding section of the modification example of Embodiment 2.

[0089] Figure 41A FIG. 5 is a part of a flowchart showing an example of the process of the error correction device of the modification example of Embodiment 2.

[0090] Figure 41B FIG. 6 is another part of a flowchart showing an example of the process of the error correction encoding device of the modification example of Embodiment 2.

[0091] Figure 41C FIG. 7 is the remaining part of the flowchart showing an example of the process of the error correction encoding device of the modification example of Embodiment 2. DETAILED DESCRIPTION

[0092] Hereinafter, in order to describe the present disclosure in more detail, a mode for carrying out the present disclosure will be described with reference to the accompanying drawings.

[0093] Embodiment 1.

[0094] Reference Figure 1 The configuration of the main part of the communication system 1 of Embodiment 1 will be described.

[0095] Figure 1 FIG. 4 is a configuration diagram showing an example of the configuration of the main part of the communication system 1 of Embodiment 1.

[0096] In Embodiment 1, as an example, the case where the communication system 1 is an optical communication system will be described, but the optical communication system is only an example, and the communication system 1 is not limited to the optical communication system. For example, the communication system 1 can also be a communication system based on wireless communication or metal communication, or the like.

[0097] The communication system 1 is provided with a transmission device 10, a transmission path 30, and a reception device 20.

[0098] The transmission device 10 acquires input information and outputs a signal based on the acquired input information. Since Figure 1 The communication system 1 shown in FIG. 1 is an optical communication system, and therefore,Figure 1 The transmission device 10 shown is an optical transmission device that outputs an optical signal.

[0099] The transmission path 30 transmits the signal output by the transmission device 10 to the reception device 20. Since Figure 1 The communication system 1 shown is an optical communication system, and thus Figure 1 The transmission path 30 shown is an optical transmission path that can transmit the optical signal output by the transmission device 10 to the reception device 20. The transmission path 30 is constituted by, for example, an optical cross-connect device, a transmission optical fiber, and an optical amplifier, none of which is shown. The optical cross-connect device is constituted by a wavelength-selective switch, a wavelength multiplexing device, a wavelength separation device, or an optical coupler, or the like. The transmission optical fiber is constituted by a single-core single-mode optical fiber or a space-multiplexed optical fiber, or the like. The optical amplifier is constituted by an erbium-doped optical amplifier or a Raman optical amplifier, or the like.

[0100] The reception device 20 receives the signal output by the transmission device 10 via the transmission path 30, generates output information corresponding to the input information on the basis of the signal, and outputs the generated output information. Since Figure 1 The communication system 1 shown is an optical communication system, and thus Figure 1 The reception device 20 shown is an optical reception device that receives an optical signal.

[0101] The transmission device 10 is provided with an error correction encoding device 100, a D / A converter 11, a transmission light source 12, and an optical modulator 13. The transmission section is constituted by the D / A converter 11, the transmission light source 12, and the optical modulator 13.

[0102] The error correction encoding device 100 acquires input information input from the outside, and generates a digital baseband modulation signal on the basis of the acquired input information. The error correction encoding device 100 outputs the generated digital baseband modulation signal to the D / A converter 11.

[0103] The D / A converter 11 receives the digital baseband modulation signal output by the error correction encoding device 100, converts the digital baseband modulation signal into a transmission electric signal that is an analog baseband modulation signal, and outputs the converted transmission electric signal. The D / A converter 11 can also convert the digital baseband modulation signal into an analog baseband modulation signal and electrically amplify the analog baseband modulation signal, and output the amplified analog baseband modulation signal as the transmission electric signal.

[0104] The transmission light source 12 outputs unmodulated light of a single wavelength. The transmission light source 12 is constituted by an external resonator type wavelength variable light source, or the like. The transmission light source 12, for example, generates unmodulated light having a center wavelength of 1550 nanometers (hereinafter referred to as "nm") and outputs the generated unmodulated light to the optical modulator 13.

[0105] The optical modulator 13 receives the transmission electric signal output by the D / A converter 11 and the unmodulated light output by the transmission light source 12, generates modulated light by modulating the unmodulated light with the transmission electric signal, and outputs the generated modulated light as a modulated light signal to the transmission path 30. The optical modulator 13 is constituted by a polarization multiplexed quadrature phase modulator or the like.

[0106] The reception apparatus 20 is provided with a reception light source 22, an optical receiver 21, an A / D converter 23, and an error correction apparatus 200. The reception section is constituted by the reception light source 22, the optical receiver 21, and the A / D converter 23.

[0107] The reception light source 22 outputs unmodulated light of a single wavelength corresponding to the center wavelength of the modulated light signal, that is, the modulated light, output to the transmission path 30 by the transmission apparatus 10. The reception light source 22 is constituted by an external resonator type wavelength variable light source or the like, for example, generates unmodulated light of a center wavelength of 1550 nm, and outputs the generated unmodulated light to the optical receiver 21.

[0108] The optical receiver 21 receives the modulated light signal output to the transmission path 30 by the transmission apparatus 10 and the unmodulated light output by the reception light source 22. The optical receiver 21 performs coherent detection using the modulated light as the modulated light signal and the unmodulated light, thereby generating a reception electric signal as a reception analog baseband modulation signal, and outputs the generated reception electric signal to the A / D converter 23.

[0109] The A / D converter 23 receives the reception electric signal output by the optical receiver 21, converts the reception electric signal into a reception digital baseband modulation signal, and outputs the converted reception digital baseband modulation signal. Specifically, the A / D converter 23 samples and converts the reception analog baseband modulation signal as the reception electric signal into a digital baseband modulation signal, and outputs the same to the error correction apparatus 200. The A / D converter 23 can also amplify the reception electric signal, and convert the amplified reception electric signal into a reception digital baseband modulation signal.

[0110] The error correction apparatus 200 receives the reception digital baseband modulation signal output by the A / D converter 23, generates output information corresponding to the input information on the basis of the reception digital baseband modulation signal, and outputs the generated output information.

[0111] Reference Figure 2 The structure of the main part of the error correction encoding apparatus 100 of Embodiment 1 will be described.

[0112] Figure 2 is a structural diagram showing an example of the structure of the main part of the error correction encoding apparatus 100 of Embodiment 1.

[0113] The error correction coding device 100 includes an input information acquisition section 110, an encoding section 120, a modulation symbol conversion section 130, and a transmission waveform shaping section 140.

[0114] The input information acquisition section 110 acquires input information.

[0115] The encoding section 120 generates soft decision error correction frame information in which first bit string group information and second bit string group information are combined, based on the input information acquired by the input information acquisition section 110.

[0116] The first bit string group information is information composed of a bit array of m (m is a natural number of 2 or more) rows and Nl (Nl is a natural number of 2 or more) columns, and is information in which a combination of bit values of each column of the first bit string group information can be pulse amplitude modulated into a modulation symbol using a first symbol mapping rule decided in advance.

[0117] The second bit string group information is information composed of a bit array of m rows and N2 (N2 is a natural number of 1 or more) columns, and is information in which a combination of bit values of each column of the second bit string group information can be pulse amplitude modulated into a modulation symbol using a second symbol mapping rule decided in advance.

[0118] The soft decision error correction frame information is information in which the first bit string group information and the second bit string group information are combined, and is information composed of a bit array of m rows and N (N is a number obtained by adding Nl and N2) columns.

[0119] The encoding section 120 will be described in detail later.

[0120] In the following description, a case in which the soft decision error correction frame information is stored in "D" which is a bit array space of m rows and N columns will be described.

[0121] Further, a bit array space of m rows and Nl columns in D which is a bit array space and in which the first bit string group information is stored will be denoted as "Dd[1]", and a bit array space of m rows and N2 columns in which the second bit string group information is stored will be denoted as "Dd[2]".

[0122] Further, in the following description, q-p+l elements from p (p is a natural number of 1 or more) to q (q is a natural number of p or more) will be denoted as "p:q".

[0123] Further, a bit array space of 1 row and N columns in Dd[l:m] which is a bit array space and in which the most significant bit (MSB) is stored will be denoted as "Dv[l][l:2]". In the following description, information stored in Dv[l][l] will be referred to as first MSB information, and information stored in Dv[l][2] will be referred to as second MSB information.

[0124] Further, a bit array space of 1 row and N columns in Dd[l:m] that stores the LSB (Least Significant Bit) in Dd[l:m] as a bit array space is denoted as "Dv[m][l:2]". In the following description, information stored in Dv[m][l] is referred to as first LSB information, and information stored in Dv[m][2] is referred to as second LSB information.

[0125] Further, an m-2 row and N column bit array space in Dd[l:m] that stores middle bits other than the MSB and the LSB in Dd[l:m] as a bit array space is denoted as "Dv[2:m-l][l:2]". In the following description, information stored in Dv[2:m-l][l] is referred to as first SSB information, and information stored in Dv[2:m-l][2] is referred to as second SSB information.

[0126] Further, in the case where m is 2, the first bit string group information is composed of only the first MSB information and the first LSB information, and the second bit string group information is composed of only the second MSB information and the second LSB information. Therefore, in the case where m is 2, the first SSB information and the second SSB information do not exist, and thus Dv[2:m-l][l:2] is omitted.

[0127] Further, a bit space of the k-th (k is a natural number of 1 or more and Nl or less in Dd[l], and a natural number of 1 or more and N2 or less in Dd[2]) column in Dd[l:m] as a bit array space is denoted as "D[l:m][l:2][k]".

[0128] Further, a bit value of the soft-decision error correction frame information stored in D[l:m][l:2][k] as a bit space is denoted as "B[l:m][l:2][k]".

[0129] The modulation symbol conversion section 130 pulse-amplitude-modulates the combination of the bit values of each column of the soft-decision error correction frame information generated by the encoding section 120 into a modulation symbol in accordance with the first symbol mapping rule or the second symbol mapping rule, per column of the soft-decision error correction frame information. The modulation symbol conversion section 130 generates modulation symbol group information composed of N modulation symbols by performing pulse-amplitude-modulation per column of the soft-decision error correction frame information.

[0130] Specifically, for example, the modulation symbol conversion section 130 is provided with a first symbol mapping section 131 and a second symbol mapping section 132.

[0131] The first symbol mapping section 131 pulse-amplitude-modulates the combination of the bit values of each column of the first bit string group information in the soft-decision error correction frame information generated by the encoding section 120 into a modulation symbol using a first symbol mapping rule decided in advance, for each column of the first bit string group information. The first symbol mapping section 131 generates first modulation symbol group information composed of Nl modulation symbols by performing pulse-amplitude-modulation for each column of the first bit string group information.

[0132] The second symbol mapping section 132 pulse-amplitude-modulates the combination of the bit values of each column of the second bit string group information in the soft-decision error correction frame information generated by the encoding section 120 into a modulation symbol using a second symbol mapping rule decided in advance, for each column of the second bit string group information. The second symbol mapping section 132 generates second modulation symbol group information composed of N2 modulation symbols by performing pulse-amplitude-modulation for each column of the second bit string group information.

[0133] In the following description, the modulation symbol after pulse-amplitude-modulation is referred to as a PAM (Pulse-Amplitude Modulation) symbol.

[0134] Further, the modulation symbol group information generated by the modulation symbol conversion section 130 is denoted as [X], the first modulation symbol group information is denoted as "Xv[l]", and the second modulation symbol group information is denoted as "Xv[2]".

[0135] Further, the PAM symbol corresponding to the combination of the bit values of the k-th column of the first bit string group information, i.e., B[l:m][l][k], among the PAM symbols belonging to Xv[l] as the first modulation symbol group information is denoted as "X[l][k]".

[0136] Further, the PAM symbol corresponding to the combination of the bit values of the k-th column of the second bit string group information, i.e., B[l:m][2][k], among the PAM symbols belonging to Xv[2] as the second modulation symbol group information is denoted as "X[2][k]".

[0137] That is, the first symbol mapping section 131 converts the combination of the bit values of the k-th column of the first bit string group information, i.e., B[l:m][l][k], into X[l][k] using the first symbol mapping rule, and the second symbol mapping section 132 converts the combination of the bit values of the k-th column of the second bit string group information, i.e., B[l:m][2][k], into X[2][k] using the second symbol mapping rule, whereby the modulation symbol conversion section 130 generates modulation symbol group information composed of N PAM symbols.

[0138] The first symbol mapping rule and the second symbol mapping rule will be described in detail later.

[0139] The transmission waveform shaping section 140 generates a digital baseband modulation signal based on the modulation symbol group information composed of N PAM symbols generated by the modulation symbol conversion section 130, and outputs the generated digital baseband modulation signal to the D / A converter 11.

[0140] Specifically, for example, the transmission waveform shaping section 140 is provided with a polarization multiplexing section 141 and a transmission digital signal generation section 142.

[0141] The polarization multiplexing section 141 generates polarization multiplexed modulation symbols (hereinafter referred to as "QAM (Quadrature Amplitude Modulation) symbols") based on the modulation symbol group information generated by the modulation symbol conversion section 130.

[0142] Specifically, for example, the polarization multiplexing section 141 performs quadrature phase amplitude modulation on X[1][1:N1] as the first modulation symbol group information and X[2][1:N2] as the second modulation symbol group information based on the modulation symbol group information generated by the modulation symbol conversion section 130, thereby generating QAM symbols.

[0143] In addition, the method of quadrature phase amplitude modulation processing is known, and thus detailed description related to the method is omitted.

[0144] The transmission digital signal generation section 142 generates a digital baseband modulation signal based on the polarization multiplexed modulation symbols generated by the polarization multiplexing section 141. The transmission digital signal generation section 142 outputs the generated digital baseband modulation signal.

[0145] In addition, the method of generating a digital baseband modulation signal based on QAM symbols is known, and thus detailed description related to the method is omitted.

[0146] Specifically, the transmission digital signal generation section 142 outputs the digital baseband modulation signal generated based on the QAM symbols to the D / A converter 11.

[0147] The transmission digital signal generation section 142 can also perform upsampling such as 2x upsampling or processing such as root-raised cosine low-pass filtering when generating the digital baseband modulation signal. Furthermore, the transmission digital signal generation section 142 can also perform bandwidth compensation, differential delay compensation, or amplitude adjustment of the optical modulator 13, the transmission path 30, or the optical receiver 21, or the like when generating the digital baseband modulation signal.

[0148] In addition, the method of performing upsampling, root-raised cosine low-pass filtering, bandwidth compensation, differential delay compensation, or amplitude adjustment, or the like when generating a digital baseband modulation signal based on QAM symbols is known, and thus detailed description related to the processing method is omitted.

[0149] For example, in a case where the transmission path 30 has a noise characteristic of additive white Gaussian noise (hereinafter referred to as "AWGN (Additive White Gaussian Noise)"). and the like, a signal such as a modulated optical signal transmitted via the transmission path 30 needs to have a signal-to-noise ratio (hereinafter referred to as "SNR (Signal-to-Noise Ratio)") required to obtain a desired communication quality. The digital signal for transmission generation section 142 adjusts the values of the QAM symbols in such a manner that the absolute values of the QAM symbols become a distribution close to a distribution decided in advance such as a discrete Gaussian distribution, when generating the digital baseband modulation signal, and shapes the QAM symbols.

[0150] Note that the discrete Gaussian distribution is only an example, and the digital signal for transmission generation section 142 adjusts the values of the QAM symbols in such a manner that the values become a distribution suitable for the noise characteristic possessed by the transmission path 30 when generating the digital baseband modulation signal, and the method by which the digital signal for transmission generation section 142 adjusts the values of the QAM symbols is not limited to adjusting in such a manner that the values become a distribution close to the discrete Gaussian distribution.

[0151] As described above, the error correction encoding device 100 acquires input information input from the outside, and generates soft decision error correction frame information based on the acquired input information. Further, the error correction encoding device 100 generates a digital baseband modulation signal based on the generated soft decision error correction frame information, and outputs the generated digital baseband modulation signal to the D / A converter 11.

[0152] Further, the transmission device 10 converts the digital baseband modulation signal generated based on the soft decision error correction frame information based on the input information into a modulated light as a modulated optical signal via the D / A converter 11 and the optical modulator 13, and outputs the modulated light to the reception device 20.

[0153] Reference Signs Figure 3 The structure of the main part of the encoding section 120 of Embodiment 1 will be described.

[0154] Figure 3 is a structural diagram showing an example of the structure of the main part of the encoding section 120 of Embodiment 1.

[0155] The encoding section 120 includes an input bit array information generation section 121, a probability distribution shaping encoding section 122, a bit inversion section 123, and a soft decision error correction encoding section 124.

[0156] The input bit array information generating section 121 generates first input bit array information composed of an m-1 row by N column bit array and second input bit array information composed of a 1 row by N3 (N3 is a natural number of 1 or more and smaller than N1) column bit array, based on the input information acquired by the input information acquiring section 110.

[0157] In a case where the input information is information including the first input bit array information composed of an m-1 row by N column bit array and the second input bit array information composed of a 1 row by N3 column bit array, the input bit array information generating section 121 extracts the first input bit array information and the second input bit array information from the input information, respectively, or separates the input information into the first input bit array information and the second input bit array information, thereby generating the first input bit array information and the second input bit array information.

[0158] In a case where the input information includes information equivalent to the first input bit array information and the information does not satisfy the number of bits of (m-1) x N, the input bit array information generating section 121 extracts the information from the input information, and shapes the extracted information into an m-1 row by N column bit array, thereby generating the first input bit array information. For example, the input bit array information generating section 121 sets a part of bit values in the m-1 row by N column bit array to the information, and sets bit values of the remaining part to a predetermined value (e.g., "0"), when shaping the information into the m-1 row by N column bit array, thereby generating the first input bit array information.

[0159] In a case where the input information includes information equivalent to the second input bit array information and the information does not satisfy the number of bits of N3, the input bit array information generating section 121 extracts the information from the input information, and shapes the extracted information into a 1 row by N3 column bit array, thereby generating the second input bit array information. For example, the input bit array information generating section 121 sets a part of bit values in the 1 row by N3 column bit array to the information, and sets bit values of the remaining part to a predetermined value (e.g., "0"), when shaping the information into the 1 row by N3 column bit array, thereby generating the second input bit array information.

[0160] In a case where the input information does not include information equivalent to the first input bit array information or the second input bit array information, the input bit array information generating section 121 sets bit values of all of the first input bit array information or the second input bit array information not included in the input information to a predetermined value (e.g., "0"), thereby generating the first input bit array information or the second input bit array information not included in the input information.

[0161] In the case where the input information includes information corresponding to the first input bit array information and the information is information of a bit number larger than (m-1) x N, the input bit array information generating section 121 divides the information into a plurality of first input bit array information having a bit number of (m-1) x N or less. For example, the error correction coding device 100 generates a plurality of soft decision error correction frame information corresponding to the divided plurality of first input bit array information, respectively, generates a plurality of digital baseband modulation signals corresponding to the plurality of soft decision error correction frame information, respectively, and sequentially outputs the generated plurality of digital baseband modulation signals.

[0162] In the case where the input information includes information corresponding to the second input bit array information and the information is information of a bit number larger than N3, the input bit array information generating section 121 divides the information into a plurality of second input bit array information having a bit number of N3 or less. For example, the error correction coding device 100 generates a plurality of soft decision error correction frame information corresponding to the divided plurality of second input bit array information, respectively, generates a plurality of digital baseband modulation signals corresponding to the plurality of soft decision error correction frame information, respectively, and sequentially outputs the generated plurality of digital baseband modulation signals.

[0163] By being configured as described above, the error correction coding device 100 can generate soft decision error correction frame information for input information having an arbitrary bit number, and output a digital baseband modulation signal based on the generated soft decision error correction frame information.

[0164] The input bit array information generating section 121 sets the generated second input bit array information as a part of the first MSB information composed of a bit array of one row and N1 columns, and stores the second input bit array information in a predetermined region (hereinafter referred to as a "second input bit region") in the first row in the first bit string group information.

[0165] Specifically, the input bit array information generating section 121 stores the second input bit array information in the second input bit region in Dv[1][1] which is a bit array space in which the first MSB is stored. Hereinafter, a case where the second input bit region is D[1][1][1:N3] will be described.

[0166] The probability distribution shaping coding section 122 performs a probability distribution shaping coding process on the generated first input bit array information, and thereby generates shaping bit array information composed of (m-1) rows and N columns of bit arrays.

[0167] The probability distribution shaping coding section 122 can perform a probability distribution shaping coding process on the first input bit array information as a whole, or can divide the first input bit array information into a plurality of information and perform a probability distribution shaping coding process on each of the divided information.

[0168] The probability distribution shaping encoding section 122 performs the probability distribution shaping encoding process, for example, using the method shown in "Hierarchical Distribution Matching for Probabilistically Shaped Coded Modulation" by T. Yoshida et al., Journal of Lightwave Technology, vol. 37, no. 6, pp. 1579-1589, March 2019.

[0169] The probability distribution shaping encoding section 122 stores the generated shaping bit array information in Dv[2:m][1:2] as a bit array space.

[0170] Specifically, for example, the probability distribution shaping encoding section 122 generates the 1st LSB information, the 2nd LSB information, the 1st SSB information, and the 2nd SSB information by the process shown below. The probability distribution shaping encoding section 122 stores the generated 1st LSB information, 2nd LSB information, 1st SSB information, and 2nd SSB information in the regions corresponding to the 1st LSB information, 2nd LSB information, 1st SSB information, and 2nd SSB information, respectively, in Dv[2:m][1:2], thereby storing the shaping bit array information in Dv[2:m][1:2].

[0171] First, the probability distribution shaping encoding section 122 generates the 1st group bit array information composed of a combination of N1 number of predetermined columns and the 2nd group bit array information composed of a combination of N2 number of predetermined columns by separating the generated shaping bit array information.

[0172] Further, the probability distribution shaping encoding section 122 generates the 1st LSB information composed of a bit array of 1 row and N1 columns by extracting the information of the m-1th row in the 1st group bit array information from the generated 1st group bit array information, and stores it in the mth row in the 1st bit string group information.

[0173] Specifically, the probability distribution shaping encoding section 122 stores the generated 1st LSB information in Dv[m][1] as a bit array space.

[0174] Further, the probability distribution shaping encoding section 122 generates the 2nd LSB information composed of a bit array of 1 row and N2 columns by extracting the information of the m-1th row in the 2nd group bit array information from the generated 2nd group bit array information, and stores the generated 2nd LSB information in the mth row in the 2nd bit string group information.

[0175] Specifically, the probability distribution shaping coding section 122 stores the generated 2nd LSB information in Dv[m][2] as a bit array space.

[0176] Further, the probability distribution shaping coding section 122, in the case where m is 3 or more, extracts information of the 1st to (m-2)th rows in the 1st group of bit array information from the generated 1st group of bit array information, thereby generates 1st SSB information composed of an (m-2)th row by Nl columns of bit array, and stores the generated 1st SSB information in the 2nd to (m-l)th rows in the 1st bit string group information.

[0177] Specifically, the probability distribution shaping coding section 122 stores the generated 1st SSB information in Dv[2:m-l][l] as a bit array space.

[0178] Further, the probability distribution shaping coding section 122, in the case where m is 3 or more, extracts information of the 1st to (m-2)th rows in the 2nd group of bit array information from the generated 2nd group of bit array information, thereby generates 2nd SSB information composed of an (m-2)th row by N2 columns of bit array, and stores the generated 2nd SSB information in the 2nd to (m-l)th rows in the 2nd bit string group information.

[0179] Specifically, the probability distribution shaping coding section 122 stores the generated 2nd SSB information in Dv[2:m-l][2] as a bit array space.

[0180] The bit inversion section 123 generates post-inversion 1st LSB information composed of a 1st row by Nl columns of bit array by operating XOR of bit values of each column in the 1st LSB information and bit values of each column in the 1st MSB information corresponding to each column in the 1st LSB information.

[0181] Specifically, the bit inversion section 123 operates XOR of bit values of each column in Dv[m][l] in which the 1st LSB information is stored, i.e., B[m][l][k], and bit values of each column in Dv[l][l] in which the 2nd input bit array information is stored, i.e., B[l][l][k]. The bit inversion section 123 stores the post-inversion 1st LSB information which is a result of the operation of the XOR of all columns from the 1st column to the Nlth column in the 1st bit string group information in the mth row. Specifically, the bit inversion section 123 stores the post-inversion 1st LSB information which is a result of the operation of the XOR in Dv[m][l] in which the 1st LSB information is stored, and overwrites B[m][l][l:Nl] with the post-inversion 1st LSB information.

[0182] The soft-decision error correction encoding section 124 performs a soft-decision error correction encoding process using the inverted first LSB information generated by the bit inversion section 123 and the second LSB information generated by the probability distribution shaping encoding section 122, thereby generating soft-decision parity bits. The soft-decision error correction encoding section 124 stores the generated soft-decision parity bits as the second MSB information constituted by a bit array of 1 row and N2 columns in the first row of the second bit string group information.

[0183] Specifically, the soft-decision error correction encoding section 124 performs a soft-decision error correction encoding process using the bit values of each column in Dv[m][1] in which the inverted first LSB information is stored, i.e., B[m][1][1:N1], and the bit values of each column in Dv[m][2] in which the second LSB information is stored, i.e., B[m][2][1:N2], thereby generating soft-decision parity bits. The soft-decision error correction encoding section 124 stores the generated soft-decision parity bits as the second MSB information in Dv[1][2] as a bit array space.

[0184] As the soft-decision error correction encoding process, a turbo product code, a parity check code, or a polar code, or the like is used.

[0185] By being configured as described above, the encoding section 120 generates soft-decision error correction frame information by storing the soft-decision error correction frame information in Dv[1:m][1:2] as a bit array space.

[0186] As described above, the encoding section 120 performs a soft-decision error correction encoding process using the bit values of each column in Dv[m][1] and the bit values of each column in Dv[m][2]. Therefore, the bits that become the target of protection by the soft-decision error correction encoding process are only the least significant bits of each column in Dd[1:2] in the soft-decision error correction frame information.

[0187] Therefore, the encoding section 120 can reduce the number of bits that become the target of protection by the soft-decision error correction encoding process compared to the conventional soft-decision error correction encoding process.

[0188] Reference Signs Figure 4A and Figure 4B The first symbol mapping rule and the second symbol mapping rule of Embodiment 1 will be described.

[0189] Figure 4A is a diagram for explaining an example of the first symbol mapping rule of Embodiment 1. Specifically, Figure 4Ais a diagram showing a correspondence relation between a combination of bit values of D[1:m][1][k] as a bit array space, i.e., B[1:m][1][k], and X[1][k] as a PAM symbol. Hereinafter, the correspondence relation between the combination of B[1:m][1][k] and X[1][k] as a PAM symbol will be explained as a first symbol mapping rule.

[0190] Figure 4B is an explanatory diagram for explaining an example of a second symbol mapping rule of Embodiment 1. Specifically, Figure 4B is a diagram showing a correspondence relation between a combination of bit values of D[1:m][2][k] as a bit array space, i.e., B[1:m][2][k], and X[2][k] as a PAM symbol. Hereinafter, the correspondence relation between the combination of B[1:m][2][k] and X[2][k] as a PAM symbol will be explained as a second symbol mapping rule.

[0191] In Fig. 4, as an example, a case where the modulation symbol conversion section 130 performs 16-value pulse amplitude modulation (hereinafter referred to as "16-PAM") processing using a combination of four bit values is shown in the case where m is 4.

[0192] As an example of the symbol mapping rule, the modulation symbol conversion section 130 uses the first symbol mapping rule or the second symbol mapping rule shown in Fig. 4 to one-dimensionally pulse amplitude modulate the combination of bit values of each column of the soft-decision error correction frame information generated by the encoding section 120 into a modulation symbol in accordance with each column of the soft-decision error correction frame information.

[0193] In the following explanation, as an example, a case where the modulation symbol conversion section 130 performs 16-PAM processing using a combination of four bit values is explained, but the modulation symbol conversion section 130 is not limited to this. That is, m can be 2 or more, and the modulation symbol conversion section 130 can perform 2 m value pulse amplitude modulation processing.

[0194] In Figure 4A the first symbol mapping rule shown in Fig. 4, the relation of B[1:m-1][1][k] and X[1][k] is equivalent to a binary reflected Gray code (hereinafter referred to as "BRGC"). Further, the relation of B[m][1][k] and X[1][k] is such that the values of B[m][1][k] corresponding to two X[1][k] adjacent to each other respectively become values different from each other.

[0195] On the other hand, in Figure 4BIn the illustrated second symbol mapping rule, the relationship between B[l:m-l][2][k] and X[2][k] is equivalent to BRGC. Furthermore, the relationship between B[m][2][k] and X[2][k] is that B[m][2][k] corresponding to X[2][k] of a positive value and B[m][l][k] corresponding to X[l][k] of a value identical to that of X[2][k] are the same value, and B[m][2][k] corresponding to X[2][k] of a negative value becomes a value obtained by inverting the value of B[m][l][k] corresponding to X[l][k] of a value identical to that of X[2][k].

[0196] In addition, the first symbol mapping rule and the second symbol mapping rule illustrated in Fig. 4 are merely examples, and the first symbol mapping rule and the second symbol mapping rule are not limited to the examples illustrated in Fig. 4. As for the combination of the m-bit values in the first symbol mapping rule and the second symbol mapping rule, as long as the first symbol mapping rule and the second symbol mapping rule are the above-described symbol mapping rules to each other and the value of the PAM symbol is uniquely determined by the combination of the m-bit values, the combination of the m-bit values is arbitrary.

[0197] Furthermore, as illustrated in Fig. 4, in a case where the maximum value of the number of PAM symbols is 16, the number of PAM symbols can be set to 8 or 4. In other words, 16-PAM can be used as 8-PAM or 4-PAM.

[0198] For example, in a case where m is 3 or more, when the number of effective bits in the combination of m-bit values is me (me is a natural number of 2 or more and m or less), the modulation symbol conversion section 130 performs 2 me value pulse amplitude modulation processing.

[0199] Specifically, for example, in a case where m is 4 and me is 3, by setting the value of B[2][l:2][k] in B[l:m][l:2][k] illustrated in Fig. 4 to "0", the modulation symbol conversion section 130 can perform 2 3 value pulse amplitude modulation processing, that is, 8-value pulse amplitude modulation processing.

[0200] Furthermore, for example, in a case where m is 4 and me is 2, by setting the value of B[2:3][l:2][k] in B[l:m][l:2][k] illustrated in Fig. 4 to "0", the modulation symbol conversion section 130 can perform 2 2 value pulse amplitude modulation processing, that is, 4-value pulse amplitude modulation processing.

[0201] Further, in a case where there is a non-valid bit in the combination of bit values, for example, in a case where the value of B[2][1:2][k] or the value of B[2:3][1:2][k] shown in the above-described example is set to "0", the probability distribution shaping coding section 122 provided in the error correction coding device 100 can also set the information in the 1st input bit array information corresponding to the row in which all the values are set to "0" as an object of probability distribution shaping coding.

[0202] With respect to X[2][k], according to the 1st symbol mapping rule and the 2nd symbol mapping rule shown in Fig. 4, if the absolute values of the amplitude values of X[2][k] are the same, the combination of the bit values of B[2:m][2][k] is the same, and B[1][2][k] shows the polarity of the positive or negative of X[2][k].

[0203] Therefore, the error correction coding device 100 can control the appearance probability of the combination of the bit values of B[2:m][2][k], i.e., the appearance probability of the absolute value of X[2][k], by the probability distribution shaping coding section 122 performing probability distribution shaping coding on the information in the 1st input bit array information corresponding to B[2:m][2][k].

[0204] On the other hand, with respect to X[1][k], according to the 1st symbol mapping rule and the 2nd symbol mapping rule shown in Fig. 4, in a case where X[1][k] is a positive value, the combination of the bit values of B[1:m][1][k] corresponding to the value of X[1][k] and the combination of the bit values of B[1:m][2][k] corresponding to X[2][k] having the same value as X[1][k] are the same. Further, in a case where X[1][k] is a negative value, with respect to X[1][k], the combination of the bit values of B[2:m][1][k] corresponding to the value of X[1][k] and the combination of the bit values of B[2:m][2][k] corresponding to X[2][k] having the same value as X[1][k] are the same, and the bit value of B[1][1][k] corresponding to X[1][k] is the value obtained by inverting the bit value of B[1][2][k] corresponding to X[2][k] having the same value as X[1][k].

[0205] Therefore, the error correction coding device 100 can control the appearance probability of the combination of the bit values of B[2:m][1][k], i.e., the appearance probability of the absolute value of X[1][k], by the probability distribution shaping coding section 122 performing probability distribution shaping coding on the information in the 1st input bit array information corresponding to B[2:m][1][k], and the bit inversion section 123 setting the value obtained by taking the exclusive OR of B[1][1][k] and the probability distribution shaped B[m][1][k] as B[2:m][1][k].

[0206] Referring to Figure 5A and Figure 5B A hardware structure of the main part of the error correction encoding device 100 of Embodiment 1 will be described.

[0207] Figure 5A and Figure 5B is a diagram showing an example of the hardware structure of the error correction encoding device 100 of Embodiment 1.

[0208] As shown in Figure 5A , the error correction encoding device 100 is constituted by a computer having a processor 501 and a memory 502. In the memory 502, a program for causing the computer to function as the input information acquisition section 110, the encoding section 120, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 is stored. The functions of the input information acquisition section 110, the encoding section 120, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 are realized by the processor 501 reading out and executing the program stored in the memory 502.

[0209] Further, as shown in Figure 5B , the error correction encoding device 100 can also be constituted by a processing circuit 503. In this case, the functions of the input information acquisition section 110, the encoding section 120, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 can also be realized by the processing circuit 503.

[0210] Further, the error correction encoding device 100 can also be constituted by the processor 501, the memory 502, and the processing circuit 503 (not shown). In this case, it can also be that part of the functions of the input information acquisition section 110, the encoding section 120, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 are realized by the processor 501 and the memory 502, and the remaining functions are realized by the processing circuit 503.

[0211] The processor 501 uses, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a microprocessor, a microcontroller, or a DSP (Digital Signal Processor).

[0212] The storage 502 uses, for example, a semiconductor memory or a magnetic disk. More specifically, the storage 502 uses, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a SSD (Solid State Drive), or a HDD (Hard Disk Drive).

[0213] The processing circuit 503 uses, for example, an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), a FPGA (Field-Programmable Gate Array), a SoC (System-on-a-Chip), or a system LSI (Large-Scale Integration).

[0214] The operation of the error correction encoding device 100 of Embodiment 1 will be described with reference to Figure 6A , Figure 6B and Figure 6C .

[0215] Figure 6A is a part of a flowchart showing an example of the processing of the error correction encoding device 100 of Embodiment 1.

[0216] Figure 6B is another part of a flowchart showing an example of the processing of the error correction encoding device 100 of Embodiment 1.

[0217] Figure 6C is a remaining part of a flowchart showing an example of the processing of the error correction encoding device 100 of Embodiment 1.

[0218] Hereinafter, the Figure 6A , Figure 6B and Figure 6C are collectively referred to as FIG. 6.

[0219] The error correction encoding device 100 repeatedly performs the processing of the flowchart shown in FIG. 6.

[0220] First, in step ST601, the input information acquiring section 110 acquires input information.

[0221] Next, in step ST610, the encoding section 120 generates soft-decision error correction frame information.

[0222] Specifically, the encoding section 120 performs the processing of steps ST611 to ST618 in the following processing A, thereby performing the processing of step ST610.

[0223] First, in step ST611, the input bit array information generating section 121 possessed by the encoding section 120 generates first input bit array information and second input bit array information.

[0224] Next, in step ST612, the input bit array information generating section 121 possessed by the encoding section 120 stores the second input bit array information in the second input bit region in Dv[l][l].

[0225] Next, in step ST613, the probability distribution shaping encoding section 122 possessed by the encoding section 120 generates shaping bit array information.

[0226] Next, in step ST614, the probability distribution shaping encoding section 122 possessed by the encoding section 120 stores the shaping bit array information in Dv[2:m][l:2].

[0227] Next, in step ST615, the bit inverting section 123 possessed by the encoding section 120 operates XOR of the bit values of each column in Dv[m][l] and the bit values of each column in Dv[l][l].

[0228] Next, in step ST616, the bit inverting section 123 possessed by the encoding section 120 rewrites the bit values of each column in Dv[m][l] with the operation result of XOR, thereby storing the operation result of XOR in Dv[m][l].

[0229] Next, in step ST617, the soft-decision error correction encoding section 124 possessed by the encoding section 120 performs systematic soft-decision error correction encoding processing using the bit values of each column in Dv[m][l] and the bit values of each column in Dv[m][2], thereby generating soft-decision parity bits.

[0230] Next, in step ST618, the soft-decision error correction encoding section 124 possessed by the encoding section 120 stores the soft-decision parity bits in Dv[l][2].

[0231] After step ST618, the encoding section 120 ends the processing A. That is, after step ST618, the encoding section 120 ends the processing of step ST610.

[0232] After the step ST610, in a step ST620, the modulation symbol conversion section 130 generates modulation symbol group information composed of N PAM symbols.

[0233] Specifically, the modulation symbol conversion section 130 performs the processing of the step ST620 by performing the processing of the steps ST621 to ST622 in the following processing B.

[0234] In the step ST621, the 1st symbol mapping section 131 possessed by the modulation symbol conversion section 130 generates 1st modulation symbol group information composed of N1 PAM symbols.

[0235] Next, in the step ST622, the 2nd symbol mapping section 132 possessed by the modulation symbol conversion section 130 generates 2nd modulation symbol group information composed of N2 PAM symbols.

[0236] After the step ST622, the modulation symbol conversion section 130 ends the processing B. That is, after the step ST622, the modulation symbol conversion section 130 ends the processing of the step ST620.

[0237] In addition, the order of the processing of the step ST621 and the step ST622 is arbitrary.

[0238] After the step ST620, in a step ST630, the transmission waveform shaping section 140 outputs the digital baseband modulation signal.

[0239] Specifically, the transmission waveform shaping section 140 performs the processing of the step ST630 by performing the processing of the steps ST631 to ST633 in the following processing C.

[0240] In the step ST631, the polarization multiplexing section 141 possessed by the transmission waveform shaping section 140 generates the QAM symbol.

[0241] Next, in the step ST632, the digital signal for transmission generating section 142 possessed by the transmission waveform shaping section 140 generates the digital baseband modulation signal.

[0242] Next, in the step ST633, the digital signal for transmission generating section 142 possessed by the transmission waveform shaping section 140 outputs the digital baseband modulation signal.

[0243] After the step ST633, the transmission waveform shaping section 140 ends the processing C. That is, after the step ST633, the transmission waveform shaping section 140 ends the processing of the step ST630.

[0244] After the step ST630, the error correction encoding device 100 ends the processing of the flowchart shown in Fig. 6, and returns to the processing of the step ST601 to repeat the processing of the flowchart shown in Fig. 6.

[0245] Referring to Figure 7 The configuration of the main part of the error correction device 200 of Embodiment 1 will be described.

[0246] Figure 7 is a configuration diagram showing an example of the configuration of the main part of the error correction device 200 of Embodiment 1.

[0247] The error correction device 200 includes a reception modulation symbol group information generation section 210, a hard decision candidate generation section 220, a soft decision information generation section 230, a decoding section 240, and an information output section 290.

[0248] The reception modulation symbol group information generation section 210 receives a digital baseband modulation signal output by the A / D converter 23, that is, a reception digital baseband modulation signal. The reception modulation symbol group information generation section 210 generates modulation symbol group information composed of N modulation symbols, that is, reception modulation symbol group information composed of N reception modulation symbols (hereinafter referred to as "reception PAM symbols") based on the reception digital baseband modulation signal.

[0249] The reception digital baseband modulation signal received by the reception modulation symbol group information generation section 210 is a signal corresponding to the digital baseband modulation signal output by the transmission waveform shaping section 140 included in the error correction encoding device 100.

[0250] Further, the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210 is information corresponding to the modulation symbol group information composed of N modulation symbols generated by the modulation symbol conversion section 130 included in the error correction encoding device 100.

[0251] That is, the reception modulation symbol group information generation section 210 restores the reception modulation symbol group information corresponding to the modulation symbol group information generated by the modulation symbol conversion section 130 based on the reception digital baseband modulation signal.

[0252] The reception modulation symbol group information generation section 210 outputs the generated reception modulation symbol group information to the hard decision candidate generation section 220 and the soft decision information generation section 230.

[0253] Specifically, for example, the reception modulation symbol group information generation section 210 includes a reception polarization multiplexed symbol generation section 211 and a reception modulation symbol generation section 212.

[0254] The reception polarization multiplexed symbol generation section 211 receives the reception digital baseband modulation signal outputted from the A / D converter 23, and generates a reception polarization multiplexed modulation symbol (hereinafter referred to as "reception QAM symbol") as a polarization multiplexed modulation symbol, based on the reception digital baseband modulation signal.

[0255] The reception QAM symbol generated by the reception polarization multiplexed symbol generation section 211 corresponds to the QAM symbol generated by the polarization multiplexed section 141 provided to the transmission waveform shaping section 140 in the error correction coding apparatus 100.

[0256] That is, the reception polarization multiplexed symbol generation section 211 restores the reception PAM symbol corresponding to the QAM symbol generated by the polarization multiplexed section 141, based on the reception digital baseband modulation signal.

[0257] In addition, the method of generating the QAM symbol based on the digital baseband modulation signal is well known, and thus detailed description thereof is omitted.

[0258] The reception modulation symbol generation section 212 generates reception modulation symbol group information composed of N reception PAM symbols, based on the reception QAM symbol restored by the reception polarization multiplexed symbol generation section 211.

[0259] Specifically, the reception modulation symbol generation section 212 generates first reception modulation symbol group information composed of N1 reception PAM symbols and second reception modulation symbol group information composed of N2 reception PAM symbols.

[0260] The first reception modulation symbol group information generated by the reception modulation symbol generation section 212 is information corresponding to the first modulation symbol group information generated by the first symbol mapping section 131 provided to the modulation symbol conversion section 130.

[0261] Further, the second reception modulation symbol group information generated by the reception modulation symbol generation section 212 is information corresponding to the second modulation symbol group information generated by the second symbol mapping section 132 provided to the modulation symbol conversion section 130.

[0262] In the following description, the reception modulation symbol group information generated by the reception modulation symbol generation section 212 is denoted as "Y", the first reception modulation symbol group information is denoted as "Yv[1]", and the second reception modulation symbol group information is denoted as "Yv[2]".

[0263] Further, the reception PAM symbol corresponding to X[1][k] among the reception PAM symbols belonging to the first reception modulation symbol group information, i.e., Yv[1], is denoted as "Y[1][k]", and the X[1][k] is a PAM symbol belonging to the first modulation symbol group information generated by the first symbol mapping section 131.

[0264] Further, a received PAM symbol corresponding to X[2][k] belonging to the 2nd modulation symbol group information generated by the 2nd symbol mapping section 132 is denoted as "Y[2][k]" from among the received PAM symbols belonging to the 2nd received modulation symbol group information, Yv[2].

[0265] The received modulation symbol group information generating section 212 outputs the generated 1st received modulation symbol group information and 2nd received modulation symbol group information to the hard decision candidate generating section 220 and the soft decision information generating section 230.

[0266] Further, a method of generating a PAM symbol from a QAM symbol is known, and thus detailed description related to this method is omitted.

[0267] The hard decision candidate generating section 220 generates 1st, 2nd, and 3rd hard decision candidate bit array information using the received modulation symbol group information generated by the received modulation symbol group information generating section 210 based on the 1st symbol mapping rule or the 2nd symbol mapping rule.

[0268] Specifically, for example, the hard decision candidate generating section 220 includes a 1st hard decision candidate generating section 221 that generates 1st hard decision candidate bit array information, a 2nd hard decision candidate generating section 222 that generates 2nd hard decision candidate bit array information, and a 3rd hard decision candidate generating section 223 that generates 3rd hard decision candidate bit array information.

[0269] The 1st hard decision candidate generating section 221 generates HIOv[1][1] and HIlv[1][1] using Y[1][1:Nl] as the 1st received modulation symbol group information based on the 1st symbol mapping rule, the HIOv[1][1] and HIlv[1][1] being 1st hard decision candidate bit array information each composed of a 1-row Nl-column bit array.

[0270] The bit value of the kth column of HIOv[1][1] is a hard decision value obtained by hard decision of the value of Y[1][k] in a case where the bit value of B[m][1][k] as an LSB in B[1:m][1][k] is "0", the B[1:m][1][k] being a combination of bit values corresponding to X[1][k] corresponding to Y[1][k].

[0271] Specifically, for example, the 1st hard decision candidate generating section 221 decides the bit value of the kth column of HIOv[1][1] based on the 1st symbol mapping rule shown in FIG. 8. Figure 4A

[0272] ​More specifically, when the bit value of B[m][1][k] is "0", when referring to Figure 4A When the first symbol mapping rule is used, X[1][k] can take any of the eight values ​​of -15, -11, -7, -3, 1, 5, 9, and 13. The first hard decision candidate generator 221 compares the eight values ​​with the value of Y[1][k] and determines that the value of X[1][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[1][k]. The first hard decision candidate generator 221 sets B[m][1][k], which is the LSB of B[1:m][1][k], corresponding to the combination of bit values ​​corresponding to the value of X[1][k] for which the posterior probability is maximized, as the bit value of the k-th column of HI0v[1][1], thereby generating HI0v[1][1].

[0273] Similarly, the bit value of the kth column of HI1v[1][1] is a hard decision value obtained by making a hard decision on the value of Y[1][k] when the bit value of B[m][1][k] as the LSB in B[1:m][1][k] is "1", where B[1:m][1][k] is a combination of the bit values ​​corresponding to X[1][k] corresponding to Y[1][k].

[0274] Specifically, for example, the first hard decision candidate generation unit 221 generates a Figure 4A The first symbol mapping rule shown determines the bit value of the kth column of HI1v[1][1].

[0275] More specifically, when the bit value of B[m][1][k] is "1", when referring to Figure 4A When the first symbol mapping rule is used, X[1][k] can take any of the eight values ​​of -13, -9, -5, -1, 3, 7, 11, and 15. The first hard decision candidate generator 221 compares the eight values ​​with the value of Y[1][k] and determines that the value of X[1][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[1][k]. The first hard decision candidate generator 221 sets B[m][1][k], which is the LSB of B[1:m][1][k], corresponding to the combination of bit values ​​corresponding to the value of X[1][k] for which the posterior probability is maximized, as the bit value of the k-th column of HI1v[1][1], thereby generating HI1v[1][1].

[0276] When m is greater than 3, the second hard decision candidate generation unit 222 uses Y[1][1:N1] as the first received modulation symbol group information based on the first symbol mapping rule to generate HI0v[2:m-1][1] and HI1v[2:m-1][1], both of which are hard decision candidate bit array information of m-2 rows and N1 columns.

[0277] The bit value of the kth column of HI0v[2:m-1][1] is a hard decision value obtained by making a hard decision on the value of Y[1][k] when the bit value of B[m][1][k] as the LSB in B[1:m][1][k] is "0", where B[1:m][1][k] is a combination of the bit values ​​corresponding to X[1][k] corresponding to Y[1][k].

[0278] Specifically, for example, the second hard decision candidate generation unit 222 generates a Figure 4A The first symbol mapping rule shown determines the bit value of the k-th column of HI0v[2:m-1][1].

[0279] More specifically, when the bit value of B[m][1][k] is "0", when referring to Figure 4A When the first symbol mapping rule is used, X[1][k] can take any of the eight values ​​of -15, -11, -7, -3, 1, 5, 9, and 13. The second hard decision candidate generator 222 compares the eight values ​​with the value of Y[1][k] and determines that the value of X[1][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[1][k]. The second hard decision candidate generator 222 sets B[2:m-1][1][k] in B[1:m][1][k], which is the combination of bit values ​​corresponding to the value of X[1][k] for which the posterior probability is maximized, as the bit value of the kth column of HI0v[2:m-1][1], thereby generating HI0v[2:m-1][1].

[0280] Similarly, the bit value of the kth column of HI1v[2:m-1][1] is a hard decision value obtained by making a hard decision on the value of Y[1][k] when the bit value of B[m][1][k] as the LSB in B[1:m][1][k] is "1", where B[1:m][1][k] is a combination of the bit values ​​corresponding to X[1][k] corresponding to Y[1][k].

[0281] Specifically, for example, the second hard decision candidate generation unit 222 generates a Figure 4A The first symbol mapping rule shown determines the bit value of the k-th column of HI1v[2:m-1][1].

[0282] More specifically, when the bit value of B[m][1][k] is "1", when referring to Figure 4A When the first symbol mapping rule is used, X[1][k] can take any of the eight values ​​of -13, -9, -5, -1, 3, 7, 11, and 15. The second hard decision candidate generator 222 compares the eight values ​​with the value of Y[1][k] and determines that the value of X[1][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[1][k]. The second hard decision candidate generator 222 sets B[2:m-1][1][k] in B[1:m][1][k], which is the combination of bit values ​​corresponding to the value of X[1][k] for which the posterior probability is maximized, as the bit value of the kth column of HI1v[2:m-1][1], thereby generating HI1v[2:m-1][1].

[0283] When m is greater than 3, the third hard decision candidate generation unit 223 uses Y[2] as the second received modulation symbol group information based on the second symbol mapping rule to generate HI0v[2:m-1][2] and HI1v[2:m-1][2], both of which are hard decision candidate bit array information of m-2 rows and N2 columns.

[0284] The bit value of the kth column of HI0v[2:m-1][2] is a hard decision value obtained by making a hard decision on the value of Y[2][k] when the bit value of B[m][2][k] as the LSB in B[1:m][2][k] is "0", where B[1:m][2][k] is a combination of the bit values ​​corresponding to X[2][k] corresponding to Y[2][k].

[0285] Specifically, for example, the third hard decision candidate generation unit 223 generates a Figure 4B The second symbol mapping rule shown determines the bit value of the k-th column of HI0v[2:m-1][2].

[0286] More specifically, when the bit value of B[m][2][k] is "0", when referring to Figure 4BWhen the second symbol mapping rule is used, X[2][k] can take any of the eight values ​​of -13, -9, -5, -1, 1, 5, 9, and 13. The third hard decision candidate generator 223 compares the eight values ​​with the value of Y[2][k] and determines that the value of X[2][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[2][k]. The third hard decision candidate generator 223 sets B[2:m-1][2][k], which is the combination of bit values ​​corresponding to the value of X[2][k] for which the posterior probability is maximized, as the bit value of the kth column of HI0v[2:m-1][2], thereby generating HI0v[2:m-1][2].

[0287] Similarly, the bit value of the kth column of HI1v[2:m-1][2] is a hard decision value obtained by making a hard decision on the value of Y[2][k] when the bit value of B[m][2][k] as the LSB in B[1:m][2][k] is "1", where B[1:m][2][k] is a combination of the bit values ​​corresponding to X[2][k] corresponding to Y[2][k].

[0288] Specifically, for example, the third hard decision candidate generation unit 223 generates a Figure 4B The second symbol mapping rule shown determines the bit value of the k-th column of HI1v[2:m-1][2].

[0289] More specifically, when the bit value of B[m][2][k] is "1", when referring to Figure 4B When the second symbol mapping rule is used, X[2][k] can take any of the eight values: -15, -11, -7, -5, 3, 7, 11, and 15. The third hard decision candidate generator 223 compares the eight values ​​with the value of Y[2][k] and determines that the value of X[2][k] for which the posterior probability is maximized among the eight values ​​is the value of Y[2][k]. The third hard decision candidate generator 223 sets the bit value B[2:m-1][2][k], which is the LSB in B[1:m][2][k] and corresponds to the combination of bit values ​​corresponding to the value of X[2][k] for which the posterior probability is maximized, as the bit value of the kth column of HI1v[2:m-1][2], thereby generating HI1v[2:m-1][2].

[0290] The soft decision information generation unit 230 generates a posterior L value sequence, i.e., a first posterior L value sequence, a second posterior L value sequence, and a third posterior L value sequence, by arranging the posterior L values ​​based on the received modulation symbol group information generated by the received modulation symbol group information generation unit 210.

[0291] Specifically, for example, the soft decision information generating section 230 has a first soft decision information generating section 231 that generates a first posterior L value sequence, a second soft decision information generating section 232 that generates a second posterior L value sequence, and a third soft decision information generating section 233 that generates a third posterior L value sequence.

[0292] The posterior L value is a posterior log probability ratio, and is a value calculated on the basis of a value indicated by Y[1:2][k] that is a received PAM symbol.

[0293] Specifically, the posterior L value is a value in which a ratio of a posterior probability that a bit value that becomes an object in B[1:m][1][k] or B[1:m][2][k] is "0" to a posterior probability that the bit value is "1" is set to a log, that is, a soft decision value, where the B[1:m][1][k] or B[1:m][2][k] is a combination of bit values corresponding to X[1][k] or X[1][k] corresponding to Y[1][k] or Y[2][k]. The posterior L value is expressed by a combination of a plurality of bit values of 3 bits to 6 bits.

[0294] For example, in a case where the posterior L value is a positive value, a hard decision value of a bit that becomes an object becomes "0", and in a case where the posterior L value is a negative value, the hard decision value of the bit that becomes an object becomes "1".

[0295] A magnitude of an absolute value of the posterior L value indicates a reliability at the time of performing a hard decision of a bit that becomes an object.

[0296] The soft decision information generating section 230 calculates the posterior L value corresponding to a bit that becomes an object for each received PAM symbol, thereby generating a posterior L value sequence.

[0297] The first soft decision information generating section 231 calculates the posterior L value for each received PAM symbol on the basis of a value indicated by a received PAM symbol belonging to the second received modulation symbol group information, thereby generating a first posterior L value sequence in which N2 posterior L values are arranged.

[0298] Specifically, the posterior L value of the k-th column in the first posterior L value sequence generated by the first soft decision information generating section 231 corresponds to B[1][2][k] that is an MSB in B[1:m][2][k] that is a combination of bit values corresponding to X[2][k] corresponding to Y[2][k].

[0299] Hereinafter, the first posterior L value sequence is expressed as Lv[1][2], and the k-th posterior L value of Lv[1][2] that is the first posterior L value sequence is expressed as L[1][2][k].

[0300] That is, the kth posterior L value of the Lv[m][l] as the 2nd posterior L value sequence, that is, L[m][l][k] corresponds to B[m][l][k] in B[l:m][l][k], which is a combination of bit values corresponding to X[l][k] corresponding to Y[l][k].

[0301] The 2nd soft decision information generating section 232 calculates a posterior L value for each received PAM symbol based on the value indicated by the received PAM symbol belonging to the 1st received modulation symbol group information, thereby generating a 2nd posterior L value sequence in which Nl posterior L values are arranged.

[0302] Specifically, the kth column of the posterior L value in the 2nd posterior L value sequence generated by the 2nd soft decision information generating section 232 corresponds to B[m][l][k] as the LSB in B[l:m][l][k], which is a combination of bit values corresponding to X[l][k] corresponding to Y[l][k].

[0303] Hereinafter, the 2nd posterior L value sequence is expressed as Lv[m][l], and the kth posterior L value of the Lv[m][l] as the 2nd posterior L value sequence is expressed as L[m][l][k].

[0304] That is, the kth posterior L value of the Lv[m][l] as the 2nd posterior L value sequence, that is, L[m][l][k] corresponds to B[m][l][k] in B[l:m][l][k], which is a combination of bit values corresponding to X[l][k] corresponding to Y[l][k].

[0305] The 3rd soft decision information generating section 233 calculates a posterior L value for each received PAM symbol based on the value indicated by the received PAM symbol belonging to the 2nd received modulation symbol group information, thereby generating a 3rd posterior L value sequence in which N2 posterior L values are arranged.

[0306] Specifically, the kth column of the posterior L value in the 3rd posterior L value sequence generated by the 3rd soft decision information generating section 233 corresponds to B[m][l][k] as the LSB in B[l:m][l][k], which is a combination of bit values corresponding to X[l][k] corresponding to Y[l][k].

[0307] Hereinafter, the 3rd posterior L value sequence is expressed as Lv[m][2], and the kth posterior L value of the Lv[m][2] as the 3rd posterior L value sequence is expressed as L[m][2][k].

[0308] That is, the kth posterior L value of the Lv[m][2] as the 3rd posterior L value sequence, that is, L[m][2][k] corresponds to B[m][2][k] in B[1:m][2][k], where the B[1:m][2][k] is a combination of bit values corresponding to the X[2][k] corresponding to the Y[2][k].

[0309] The decoding section 240 performs a multi-stage error correction process based on the 1st hard decision candidate bit array information, the 2nd hard decision candidate bit array information, and the 3rd hard decision candidate bit array information generated by the hard decision candidate generation section 220, and the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence generated by the soft decision information generation section 230, thereby generating output information.

[0310] The decoding section 240 will be described in detail later.

[0311] The information output section 290 outputs the output information generated by the decoding section 240.

[0312] Reference Figure 8 The structure of the main part of the decoding section 240 of Embodiment 1 will be described.

[0313] Figure 8 is a structural diagram showing an example of the structure of the main part of the decoding section 240 of Embodiment 1.

[0314] The decoding section 240 includes a soft decision error correction decoding section 241, a selection section 242, a reception side bit inversion section 243, a probability distribution shaping decoding section 244, a 2nd output bit array generation section 245, and an output information generation section 246.

[0315] The soft decision error correction decoding section 241 performs a 1st decoding process in the multi-stage error correction process.

[0316] Specifically, the soft decision error correction decoding section 241 performs a soft decision error correction process using the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence.

[0317] The soft decision error correction decoding section 241 generates, by performing the soft decision error correction process, the 1st reception LSB information after inversion composed of a bit array of 1 row and N1 columns, which corresponds to the 1st LSB information after inversion generated by the bit inversion section 123.

[0318] Further, the soft decision error correction decoding section 241 generates, by performing the soft decision error correction process, the 2nd reception LSB information composed of a bit array of 1 row and N2 columns, which corresponds to the 2nd LSB information generated by the probability distribution shaping encoding section 122.

[0319] A method of performing soft decision error correction processing using a sequence of L values after the fact is known, and therefore detailed description related to this method is omitted.

[0320] The selection section 242 performs a second decoding process in the multi-stage error correction processing.

[0321] Specifically, for example, the selection section 242 includes a first selection section 2421, a second selection section 2422, and a third selection section 2423.

[0322] The first selection section 2421 generates first received MSB information corresponding to the first MSB information, which is constituted by a bit array of one row and N1 columns, based on the first hard decision candidate bit array information and the inverted first received LSB information.

[0323] Specifically, the first selection section 2421 selects HI0v[1][1] among HI0v[1][1] and HI1v[1][1] as the first hard decision candidate bit array information generated by the first hard decision candidate generation section 221, in a case where the bit value of the kth column in the inverted first received LSB information generated by the soft decision error correction decoding section 241 is "0". The first selection section 2421 substitutes the bit value of the kth column of HI0v[1][1] into the bit of the kth column of the first received MSB information.

[0324] Further, the first selection section 2421 selects HI1v[1][1] among HI0v[1][1] and HI1v[1][1] as the first hard decision candidate bit array information generated by the first hard decision candidate generation section 221, in a case where the bit value of the kth column in the inverted first received LSB information generated by the soft decision error correction decoding section 241 is "1". Further, the first selection section 2421 substitutes the bit value of the kth column of HI1v[1][1] into the bit of the kth column of the first received MSB information.

[0325] The first selection section 2421 substitutes the bit value of the column of HI0v[1][1] or HI1v[1][1] corresponding to the column of the first received MSB information, for each column of the first received MSB information, thereby generating the first received MSB information.

[0326] The second selection section 2422 generates first received SSB information corresponding to the first SSB information, which is constituted by a bit array of m-2 rows and N1 columns, based on the second hard decision candidate bit array information and the inverted first received LSB information, in a case where m is three or more.

[0327] Specifically, the 2nd selection section 2422 selects, in a case where the bit value of the kth column in the inverted 1st received LSB information generated by the soft-decision error correction decoding section 241 is "0", the HI0v[2:m-l][l] out of the HI0v[2:m-l][l] and the HI1v[2:m-l][l] as the 2nd hard-decision candidate bit array information generated by the 2nd hard-decision candidate generating section 222. The 2nd selection section 2422 substitutes the m-2 bit values of the kth column of the HI0v[2:m-l][l] into the m-2 bits of the kth column of the 1st received SSB information.

[0328] Further, the 2nd selection section 2422 selects, in a case where the bit value of the kth column in the inverted 1st received LSB information generated by the soft-decision error correction decoding section 241 is "1", the HI1v[2:m-l][l] out of the HI0v[2:m-l][l] and the HI1v[2:m-l][l] as the 2nd hard-decision candidate bit array information generated by the 2nd hard-decision candidate generating section 222. The 2nd selection section 2422 substitutes the m-2 bit values of the kth column of the HI1v[2:m-l][l] into the m-2 bits of the kth column of the 1st received SSB information.

[0329] The 2nd selection section 2422 substitutes, for each column of the 1st received SSB information, the bit value of the column of the HI0v[2:m-l][l] or the HI1v[2:m-l][l] corresponding to the column of the 1st received SSB information, thereby generating the 1st received SSB information.

[0330] The 3rd selection section 2423 generates, in a case where m is 3 or more, the 2nd received SSB information corresponding to the 2nd SSB information, which is composed of a bit array of m-2 rows and N2 columns, on the basis of the 3rd hard-decision candidate bit array information and the 2nd received LSB information.

[0331] Specifically, the 3rd selection section 2423 selects, in a case where the bit value of the kth column in the 2nd received LSB information generated by the soft-decision error correction decoding section 241 is "0", the HI0v[2:m-l][2] out of the HI0v[2:m-l][2] and the HI1v[2:m-l][2] as the 3rd hard-decision candidate bit array information generated by the 3rd hard-decision candidate generating section 223. The 3rd selection section 2423 substitutes the m-2 bit values of the kth column of the HI0v[2:m-l][2] into the m-2 bits of the kth column of the 2nd received SSB information.

[0332] Further, the 3rd selection section 2423 selects, in a case where the bit value of the kth column in the 2nd received LSB information generated by the soft decision error correction decoding section 241 is "1", HI1v[2:m-l][2] out of HI0v[2:m-l][2] and HI1v[2:m-l][2] generated by the 3rd hard decision candidate generating section 223 as the 3rd hard decision candidate bit array information. The 3rd selection section 2423 substitutes the m-2 bit values of the kth column of HI1v[2:m-l][2] into the m-2 bits of the kth column of the 2nd received SSB information.

[0333] The 3rd selection section 2423 substitutes the bit values of the columns of HI0v[2:m-l][2] or HI1v[2:m-l][2] corresponding to the columns of the 2nd received SSB information for each column of the 2nd received SSB information, thereby generating the 2nd received SSB information.

[0334] As described above, HI0v[l][l] and HI0v[l][l], HI0v[2:m-l][l] and HI0v[2:m-l][l], and HI0v[2:m-l][2] and HI0v[2:m-l][2] are generated by the hard decision candidate generating section 220 by dividing the cases into a case where the bit value of B[m][l:2][k] is "0" and a case where the bit value is "1".

[0335] For example, in a case where the 1st symbol mapping rule and the 2nd symbol mapping rule are the 1st symbol mapping rule and the 2nd symbol mapping rule shown in Fig. 4 as an example of the 1st symbol mapping rule and the 2nd symbol mapping rule, in the same symbol mapping rule, the minimum Euclidean distance between two PAM symbols adjacent to each other is "2", and in contrast, the minimum Euclidean distance in a case where the above-described case division is performed becomes twice, i.e., "4". The SNR is improved by 4 times as 2 times, i.e., 4 times as 2 times. 2

[0336] Therefore, by performing the above-described case division, the accuracy of the determination of the bit values selected by the selection section 242 when substituting the bit values of the 1st received MSB information, the 1st received SSB information, or the 2nd received SSB information is improved by 4 times as compared with a case where the case division is not performed.

[0337] The reception side bit inversion section 243 performs the 3rd decoding processing in the multi-stage error correction processing.

[0338] ​Specifically, the reception-side bit inversion section 243 generates the first reception LSB information corresponding to the first input bit array information by performing exclusive-OR operation on the bit values of each column in the inverted first reception LSB information generated by the soft-decision error correction decoding section 241 and the bit values of each column in the first reception MSB information corresponding to each column in the inverted first reception LSB information, which is generated by the first selection section 2421.

[0339] The probability distribution shaping decoding section 244 performs the fourth decoding process in the multi-stage error correction processing.

[0340] Specifically, the probability distribution shaping decoding section 244 performs the probability distribution shaping decoding process on the first reception SSB information generated by the second selection section 2422, the second reception SSB information generated by the third selection section 2423, the first reception LSB information generated by the reception-side bit inversion section 243, and the second reception LSB information generated by the soft-decision error correction decoding section 241, thereby generating the first output bit array information corresponding to the first input bit array information, which is constituted by an m-1 row by N column bit array.

[0341] Specifically, for example, the probability distribution shaping decoding section 244 prepares an m-1 row by N column bit array space DRv[1:m-1][1:2] constituted by an m-1 row by N1 column bit array space DRv[1:m-1][1] and an m-1 row by N2 column bit array space DRv[1:m-1][2].

[0342] In the following description, the bit value of the kth column of DRv[1:m-1][1] is denoted as "BR[1:m-1][1][k]", and the bit value of the kth column of DRv[1:m-1][2] is denoted as "BR[1:m-1][2][k]".

[0343] The probability distribution shaping decoding section 244 stores the first reception SSB information in DRv[1:m-2][1], the second reception SSB information in DRv[1:m-2][2], the first reception LSB information in DRv[m-1][1], and the second reception LSB information in DRv[m-1][2].

[0344] The probability distribution shaping decoding section 244 performs the probability distribution shaping decoding process on BR[1:m-1][1:2][k].

[0345] The probability distribution shaping decoding section 244 rewrites BR[1:m-1][1:2][k] using the processing result of the probability distribution shaping decoding process.

[0346] The BR[l:m-l][l:2][k] after the rewriting of the BR[l:m-l][l:2][k] by the processing result of the probability distribution shaping decoding process by the probability distribution shaping decoding section 244 is the 1st output bit array information.

[0347] In addition, the probability distribution shaping decoding process is a process paired with the probability distribution shaping encoding process, and the method of the probability distribution shaping decoding process is known, and thus detailed description related to the method is omitted.

[0348] The 2nd output bit array generating section 245 performs the 5th decoding process in the multi-stage error correction process.

[0349] Specifically, the 2nd output bit array generating section 245 extracts information of a region in the 1st received MSB information corresponding to the 2nd input bit region in the 1st MSB information, and thereby generates the 2nd output bit array information composed of a bit array of 1 row and N3 columns corresponding to the 2nd input bit array information.

[0350] The output information generating section 246 performs the 6th decoding process in the multi-stage error correction process.

[0351] Specifically, the output information generating section 246 generates output information corresponding to the input information based on the 1st output bit array information and the 2nd output bit array information.

[0352] Referring to Figure 9A and Figure 9B , the hardware structure of the main part of the error correction device 200 of Embodiment 1 is described.

[0353] Figure 9A and Figure 9B are diagrams showing an example of the hardware structure of the error correction device 200 of Embodiment 1.

[0354] As shown in Figure 9A , the error correction device 200 is composed of a computer having a processor 901 and a memory 902. In the memory 902, a program for causing the computer to function as the reception modulation symbol group information generating section 210, the hard decision candidate generating section 220, the soft decision information generating section 230, the decoding section 240, and the information output section 290 is stored. The functions of the reception modulation symbol group information generating section 210, the hard decision candidate generating section 220, the soft decision information generating section 230, the decoding section 240, and the information output section 290 are realized by the processor 901 reading out and executing the program stored in the memory 902.

[0355] Further, as shown in Figure 9BAs shown, the error correction device 200 can also be constituted by the processing circuitry 903. In this case, the functions of the reception modulation symbol group information generating section 210, the hard decision candidate generating section 220, the soft decision information generating section 230, the decoding section 240, and the information output section 290 can also be implemented by the processing circuitry 903.

[0356] Further, the error correction device 200 can also be constituted by the processor 901, the memory 902, and the processing circuitry 903 (not shown). In this case, it can also be that part of the functions of the reception modulation symbol group information generating section 210, the hard decision candidate generating section 220, the soft decision information generating section 230, the decoding section 240, and the information output section 290 are implemented by the processor 901 and the memory 902, and the remaining functions are implemented by the processing circuitry 903.

[0357] In addition, the processor 901, the memory 902, and the processing circuitry 903 are the same as the processor 501, the memory 502, and the processing circuitry 503 shown in FIG. 5, and thus the description is omitted.

[0358] Referring to Figure 10A , Figure 10B and Figure 10C , the operation of the error correction device 200 of Embodiment 1 will be described.

[0359] Figure 10A is a part of a flowchart showing an example of the processing of the error correction device 200 of Embodiment 1.

[0360] Figure 10B is another part of a flowchart showing an example of the processing of the error correction device 200 of Embodiment 1.

[0361] Figure 10C is the remaining part of a flowchart showing an example of the processing of the error correction device 200 of Embodiment 1.

[0362] Hereinafter, Figure 10A , Figure 10B and Figure 10C are collectively referred to as FIG. 10.

[0363] The error correction device 200 repeatedly performs the processing of the flowchart shown in FIG. 10.

[0364] First, in step ST1000, the reception modulation symbol group information generating section 210 generates reception modulation symbol group information.

[0365] Specifically, the reception modulation symbol group information generating section 210 performs the processing of step ST1000 by performing the processing of steps ST1001 to ST1002 in the following processing D.

[0366] The reception polarization multiplexed symbol generating section 211 included in the reception modulation symbol group information generating section 210 generates the reception QAM symbol in step ST1001.

[0367] Next, the reception modulation symbol generating section 212 included in the reception modulation symbol group information generating section 210 generates the reception modulation symbol group information in step ST1002.

[0368] After step ST1002, the reception modulation symbol group information generating section 210 ends the process D. That is, after step ST1002, the reception modulation symbol group information generating section 210 ends the process of step ST1000.

[0369] After step ST1000, the hard decision candidate generating section 220 generates the 1st hard decision candidate bit array information, the 2nd hard decision candidate bit array information, and the 3rd hard decision candidate bit array information in step ST1010.

[0370] Specifically, the hard decision candidate generating section 220 performs the process of step ST1010 by performing the processes of steps ST1011 to ST1013 in the following process E.

[0371] The 1st hard decision candidate generating section 221 included in the hard decision candidate generating section 220 generates the 1st hard decision candidate bit array information in step ST1011.

[0372] Next, the 2nd hard decision candidate generating section 222 included in the hard decision candidate generating section 220 generates the 2nd hard decision candidate bit array information in step ST1012.

[0373] Next, the 3rd hard decision candidate generating section 223 included in the hard decision candidate generating section 220 generates the 3rd hard decision candidate bit array information in step ST1013.

[0374] In addition, the order of the processes of steps ST1011 to ST1013 is arbitrary.

[0375] After step ST1013, the hard decision candidate generating section 220 ends the process E. That is, after step ST1013, the hard decision candidate generating section 220 ends the process of step ST1010.

[0376] After step ST1010, the soft decision information generating section 230 generates the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence in step ST1020.

[0377] Specifically, the soft decision information generating section 230 performs the processing of step ST1020 by performing the processing of steps ST1021 to ST1023 in the following processing F.

[0378] In step ST1021, the 1st soft decision information generating section 231 possessed by the soft decision information generating section 230 generates the 1st posterior L value sequence.

[0379] Next, in step ST1022, the 2nd soft decision information generating section 232 possessed by the soft decision information generating section 230 generates the 2nd posterior L value sequence.

[0380] Next, in step ST1023, the 3rd soft decision information generating section 233 possessed by the soft decision information generating section 230 generates the 3rd posterior L value sequence.

[0381] After step ST1023, the soft decision information generating section 230 ends the processing F. That is, after step ST1023, the soft decision information generating section 230 ends the processing of step ST1020.

[0382] In addition, the processing order of steps ST1021 to ST1023 is arbitrary.

[0383] Further, the processing order of the processing of step ST1010 and the processing of step ST1020 is arbitrary.

[0384] After step ST1020, in step ST1030, the decoding section 240 generates output information by performing a multi-stage error correction processing.

[0385] Specifically, the decoding section 240 performs the processing of step ST1030 by performing the processing of steps ST1031 to ST1036 in the following processing G.

[0386] In step ST1031, the soft decision error correction decoding section 241 possessed by the decoding section 240 generates the inverted 1st received LSB information and the 2nd received LSB information by performing a soft decision error correction processing.

[0387] Next, in step ST1032, the selection section 242 possessed by the decoding section 240 generates the 1st received MSB information, the 1st received SSB information, and the 2nd received SSB information.

[0388] Specifically, the selection section 242 performs the processing of step ST1032 by performing the processing of steps ST1041 to ST1043 in the following processing H.

[0389] In step ST1041, the 1st selection section 2421 possessed by the selection section 242 generates the 1st received MSB information.

[0390] Next, in step ST1042, the 2nd selection section 2422 included in the selection section 242 generates the 1st received SSB information.

[0391] Next, in step ST1043, the 3rd selection section 2423 included in the selection section 242 generates the 2nd received SSB information.

[0392] After step ST1043, the selection section 242 included in the decoding section 240 ends the process H. That is, after step ST1043, the selection section 242 included in the decoding section 240 ends the process of step ST1032.

[0393] In addition, the order of the processes of step ST1041 to step ST1043 is arbitrary.

[0394] After step ST1032, in step ST1033, the 2nd output bit array generating section 245 included in the decoding section 240 generates the 1st received LSB information.

[0395] Next, in step ST1034, the probability distribution shaping decoding section 244 included in the decoding section 240 generates the 1st output bit array information.

[0396] Next, in step ST1035, the 2nd output bit array generating section 245 included in the decoding section 240 generates the 2nd output bit array information.

[0397] Next, in step ST1036, the output information generating section 246 included in the decoding section 240 generates the output information.

[0398] After step ST1036, the decoding section 240 ends the process G. That is, after step ST1036, the decoding section 240 ends the process of step ST1030.

[0399] After step ST1030, in step ST1050, the information output section 290 outputs the output information.

[0400] After step ST1050, the error correction device 200 ends the process of the flowchart illustrated in Fig. 10, and the error correction device 200 returns to the process of step ST1000, and repeatedly executes the process of the flowchart illustrated in Fig. 10.

[0401] As above, the error correction coding device 100 is configured to include: an input information acquisition section 110 that acquires input information; a coding section 120 that generates soft decision error correction frame information composed of an m-row by N-column bit array in which a first bit string group information composed of an m-row by Nl-column bit array and a second bit string group information composed of an m-row by N2-column bit array are combined, based on the input information acquired by the input information acquisition section 110, the first bit string group information being able to be pulse amplitude modulated into modulation symbols by combining bit values of each column of the first bit string group information using a first symbol mapping rule decided in advance, the second bit string group information being able to be pulse amplitude modulated into modulation symbols by combining bit values of each column of the second bit string group information using a second symbol mapping rule decided in advance; a modulation symbol conversion section 130 that pulse amplitude modulates combinations of bit values of each column of the soft decision error correction frame information generated by the coding section 120 into modulation symbols according to each column of the soft decision error correction frame information using the first symbol mapping rule or the second symbol mapping rule, thereby generating modulation symbol group information composed of N modulation symbols; and a transmission waveform shaping section 140 that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion section 130, and outputs the generated digital baseband modulation signal,

[0402] The coding section 120 generates the soft decision error correction frame information by the following processes:

[0403] generates first input bit array information composed of m-1 rows by N columns and second input bit array information composed of 1 row by N3 columns, based on the input information acquired by the input information acquisition section 110,

[0404] stores the generated second input bit array information as a part of the first MSB information composed of 1 row by Nl columns in a predetermined region of the first row of the first bit string group information,

[0405] generates shaped bit array information composed of m-1 rows by N columns by performing a probability distribution shaping coding process on the generated first input bit array information,

[0406] generates first group bit array information composed of a combination of Nl predetermined columns and second group bit array information composed of a combination of N2 predetermined columns by separating the generated shaped bit array information,

[0407] The first LSB information constituted by one row of N1 columns of bit arrays is generated by extracting the bit arrays of the m-1th row in the first group of bit array information from the generated first group of bit array information, and the inverted first LSB information is generated by operating the exclusive OR of the bit values of each column in the generated first LSB information and the bit values of each column in the information of the first row in the first bit string group information after storing the second input bit array information. The generated inverted first LSB information is stored in the mth row in the first bit string group information,

[0408] The second LSB information constituted by one row of N2 columns of bit arrays is generated by extracting the bit arrays of the m-1th row in the second group of bit array information from the generated second group of bit array information, and the generated second LSB information is stored in the mth row in the second bit string group information.

[0409] The soft decision parity bits are generated by performing the soft decision error correction encoding process of the system using the generated inverted first LSB information and the generated second LSB information, and the generated soft decision parity bits are stored in the first row in the second bit string group information as the second MSB information constituted by one row of N2 columns of bit arrays.

[0410] In the case where m is 3 or more, the first SSB information constituted by m-2 rows of N1 columns of bit arrays is generated by extracting the first to m-2th rows in the first group of bit array information from the generated first group of bit array information, and the generated first SSB information is stored in the second to m-1th rows in the first bit string group information.

[0411] In the case where m is 3 or more, the second SSB information constituted by m-2 rows of N2 columns of bit arrays is generated by extracting the first to m-2th rows in the second group of bit array information from the generated second group of bit array information, and the generated second SSB information is stored in the second to m-1th rows in the second bit string group information.

[0412] By being configured as such, in the error correction encoding device 100, the number of bits to be protected by the soft decision error correction can be reduced compared to the conventional soft decision error correction encoding process. Therefore, in the error correction encoding device 100, the amount of calculation of the soft decision error correction encoding process can be reduced compared to the conventional soft decision error correction encoding process.

[0413] Further, by being configured as such, in the error correction coding device 100, even if the number of bits of the pulse amplitude modulation changes, the number of bits that become the object of protection by the soft decision error correction can be fixed. Therefore, the error correction coding device 100 can fix the amount of calculation of the soft decision error correction coding processing in the pulse amplitude modulation of an arbitrary number of bits. Therefore, the error correction coding device 100 does not need to change the program or processing circuit for performing the soft decision error correction coding processing in accordance with each number of bits of the pulse amplitude modulation in the pulse amplitude modulation of a plurality of numbers of bits.

[0414] Further, as above, the error correction coding device 100 is configured to use the following symbol mapping rules on the basis of the above-described structure: a first symbol mapping rule is a symbol mapping rule in which one bit value combination corresponding to one modulation symbol after one-dimensional pulse amplitude modulation is constituted of an m-row and 1-column bit array, wherein the combination of bit values of the first row to the m-1th row in the m-row and 1-column bit array is a combination corresponding to a binary reflected Gray code, and the bit value of the mth row is a value different from each other in modulation symbols in which the amplitude values of the modulation symbols are adjacent to each other, and a second symbol mapping rule is a symbol mapping rule in which one bit value combination corresponding to one modulation symbol after one-dimensional pulse amplitude modulation is constituted of an m-row and 1-column bit array, wherein the combination of bit values of the first row to the m-1th row in the m-row and 1-column bit array is a combination corresponding to a binary reflected Gray code, the bit value of the mth row is a value different from each other in modulation symbols in which the amplitude values of the modulation symbols are adjacent to each other and have the same sign, and the bit value of the mth row is the same value in modulation symbols in which the absolute value of the amplitude value of the modulation symbol is the smallest in modulation symbols in which the amplitude value of the modulation symbol is positive and in modulation symbols in which the absolute value of the amplitude value of the modulation symbol is the smallest in modulation symbols in which the amplitude value of the modulation symbol is negative.

[0415] By being configured as such, the error correction coding device 100 can improve the SNR. Therefore, the error correction coding device 100 can improve the accuracy of the determination of the bit value in the error correction device 200.

[0416] Further, as above, the error correction coding device 100 is configured to, on the basis of the above-described structure, generate the first input bit array information and the second input bit array information when the encoding section 120 generates the first input bit array information and the second input bit array information on the basis of the input information acquired by the input information acquisition section 110, set the bit values of bits other than the bits corresponding to the input information to 0 in the first input bit array information or the second input bit array information, and thereby generate the first input bit array information and the second input bit array information.

[0417] By being configured as such, the error correction coding device 100 can generate the soft decision error correction frame information with respect to input information having an arbitrary number of bits.

[0418] In addition, the error correction coding device 100 can also cause the soft decision error correction coding section 124 to generate soft decision parity check bits generated by performing soft decision error correction coding processing of the system so as not to be included in soft decision error correction frame information including the inverted first LSB information and the second LSB information used to generate the soft decision parity check bits, but to be included in other soft decision error correction frame information different from the soft decision error correction frame information. For example, the other soft decision error correction frame information is soft decision error correction frame information generated by the error correction coding device 100 immediately after the soft decision error correction frame information including the inverted first LSB information and the second LSB information used by the error correction coding device 100 to generate the soft decision parity check bits.

[0419] By being configured as described above, the error correction coding device 100 can disperse burst errors generated in the transmission path 30. The burst errors referred to herein are errors that are concentrated in a specific portion of a signal due to variations in the transmission path 30 when the signal is transmitted via the transmission path 30. The error correction coding device 100 can reduce degradation of the information after error correction by dispersing the burst errors.

[0420] As described above, the error correction device 200 is configured to include: a reception modulation symbol group information generation section 210 that receives a signal based on the soft decision error correction frame information generated by the error correction coding device 100, i.e., a reception digital baseband modulation signal, and generates reception modulation symbol group information composed of N reception modulation symbols based on the reception digital baseband modulation signal;

[0421] a hard decision candidate generation section 220 that generates, based on the first symbol mapping rule or the second symbol mapping rule, first hard decision candidate bit array information composed of a bit array of one row and N1 columns, second hard decision candidate bit array information composed of a bit array of m-2 rows and N1 columns in the case where m is three or more, and third hard decision candidate bit array information composed of a bit array of m-2 rows and N2 columns in the case where m is three or more, using the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210;

[0422] a soft decision information generation section 230 that generates a first posterior L value sequence composed of N2 posterior L values corresponding to each column of the first row of the second bit string group information, a second posterior L value sequence composed of N1 posterior L values corresponding to each column of the m-th row of the first bit string group information, and a third posterior L value sequence composed of N2 posterior L values corresponding to each column of the m-th row of the second bit string group information, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210;

[0423] a decoding section 240 that performs multistage error correction processing based on the first hard-decision candidate bit array information, the second hard-decision candidate bit array information, and the third hard-decision candidate bit array information generated by the hard-decision candidate generation section 220, and the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence generated by the soft-decision information generation section 230; and

[0424] an information output section 290 that outputs information generated by the decoding section 240 as output information,

[0425] In the first decoding processing of the multistage error correction processing, the decoding section 240 performs soft-decision error correction processing based on the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence, thereby generating the inverted first received LSB information corresponding to the inverted first LSB information, which is constituted by a bit array of 1 row and N1 columns, and the second received LSB information corresponding to the second LSB information, which is constituted by a bit array of 1 row and N2 columns,

[0426] In the second decoding processing of the multistage error correction processing, the decoding section 240 generates the first received MSB information corresponding to the first MSB information, which is constituted by a bit array of 1 row and N1 columns, based on the first hard-decision candidate bit array information and the inverted first received LSB information, and in the case where m is 3 or more, generates the first received SSB information corresponding to the first SSB information, which is constituted by a bit array of m-2 rows and N1 columns, based on the second hard-decision candidate bit array information and the inverted first received LSB information, and in the case where m is 3 or more, generates the second received SSB information corresponding to the second SSB information, which is constituted by a bit array of m-2 rows and N2 columns, based on the third hard-decision candidate bit array information and the second received LSB information,

[0427] In the third decoding processing of the multistage error correction processing, the decoding section 240 generates the first received LSB information corresponding to the first LSB information by operating the bit values of each column in the inverted first received LSB information with the exclusive OR of the bit values of each column in the first received MSB information corresponding to each column in the inverted first received LSB information,

[0428] In the fourth decoding processing of the multistage error correction processing, the decoding section 240 performs probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information, thereby generating the first output bit array information corresponding to the first input bit array information, which is constituted by a bit array of m-1 rows and N columns,

[0429] In the 5th decoding process of the multi-stage error correction processing, the decoding section 240 generates 2nd output bit array information corresponding to the 2nd input bit array information by extracting information of a predetermined region in the 1st received MSB information,

[0430] In the 6th decoding process of the multi-stage error correction processing, the decoding section 240 generates output information corresponding to the input information based on the 1st output bit array information and the 2nd output bit array information, and the information output section 290 outputs the output information generated by the decoding section 240.

[0431] By being thus configured, in the error correction device 200, the number of bits that become the object of protection by soft decision error correction can be reduced compared to the conventional soft decision error correction encoding processing. Therefore, in the error correction device 200, the amount of calculation of the soft decision error correction decoding processing can be reduced compared to the conventional soft decision error correction decoding processing.

[0432] Further, by being thus configured, in the error correction device 200, the number of bits that become the object of protection by soft decision error correction can be fixed even if the number of bits of the pulse amplitude modulation changes. Therefore, in the error correction device 200, the amount of calculation of the soft decision error correction decoding processing can be fixed in the pulse amplitude modulation of an arbitrary number of bits. Therefore, in the error correction device 200, it is not necessary to change the program or processing circuit for performing the soft decision error correction decoding processing in accordance with each number of bits of the pulse amplitude modulation in the pulse amplitude modulation of a plurality of numbers of bits.

[0433] Further, as described above, the error correction device 200 is configured to use the following symbol mapping rules on the basis of the above-described structure: the 1st symbol mapping rule is a symbol mapping rule in which one bit value combination of an m-row-by-1-column bit array corresponds to one modulation symbol after one-dimensional pulse amplitude modulation, where the combination of bit values of the 1st to (m-1)th rows in the m-row-by-1-column bit array is a combination corresponding to a binary reflected Gray code, and the bit value of the mth row is a value different from each other in modulation symbols in which the amplitude values of the modulation symbols are adjacent to each other, and the 2nd symbol mapping rule is a symbol mapping rule in which one bit value combination of an m-row-by-1-column bit array corresponds to one modulation symbol after one-dimensional pulse amplitude modulation, where the combination of bit values of the 1st to (m-1)th rows in the m-row-by-1-column bit array is a combination corresponding to a binary reflected Gray code, the bit value of the mth row is a value different from each other in modulation symbols in which the amplitude values of the modulation symbols are of the same sign and adjacent to each other, and the bit value of the mth row is the same value in a modulation symbol in which the absolute value of the amplitude value of the modulation symbol is the smallest among the modulation symbols in which the amplitude values of the modulation symbols are positive, and a modulation symbol in which the absolute value of the amplitude value of the modulation symbol is the smallest among the modulation symbols in which the amplitude values of the modulation symbols are negative.

[0434] By being configured like this, the error correction device 200 can improve the SNR. Therefore, the error correction device 200 can improve the accuracy of the determination of the bit values.

[0435] As above, the soft-decision error correction frame data structure that the soft-decision error correction frame information generated by the error correction encoding device 100 has is a soft-decision error correction frame data structure for a communication system in which the transmission device 10 transmits a signal based on input information input to the transmission device 10 to the reception device 20, and the reception device 20 receives the signal transmitted by the transmission device 10 and generates output information corresponding to the input information based on the signal, and the soft-decision error correction frame data structure is constituted by a bit array of m rows and N columns in which first bit string group information and second bit string group information are combined, the first bit string group information is constituted by a bit array of m rows and N1 columns, and the combination of the bit values of each column of the first bit string group information can be pulse amplitude modulated into a modulation symbol based on a first symbol mapping rule decided in advance, the second bit string group information is constituted by a bit array of m rows and N2 columns, and the combination of the bit values of each column of the second bit string group information can be pulse amplitude modulated into a modulation symbol based on a second symbol mapping rule decided in advance, and a soft-decision parity check bit is stored in the first row in the second bit string group information, the soft-decision parity check bit being generated by performing systematic soft-decision error correction encoding processing using the bit values of each column of the mth row in the first bit string group information and the bit values of each column of the mth row in the second bit string group information.

[0436] With such a soft-decision error correction frame data structure, in the error correction encoding device 100, the number of bits that become the object of protection by soft-decision error correction can be reduced compared to the conventional soft-decision error correction encoding processing. Therefore, in the error correction encoding device 100, the amount of computation of the soft-decision error correction encoding processing can be reduced compared to the conventional soft-decision error correction encoding processing.

[0437] Further, with such a soft-decision error correction frame data structure, in the error correction encoding device 100, the number of bits that become the object of protection by soft-decision error correction can be fixed even if the number of bits of pulse amplitude modulation changes. Therefore, in the error correction encoding device 100, the amount of computation of the soft-decision error correction encoding processing can be fixed in pulse amplitude modulation of any number of bits. Therefore, in the error correction encoding device 100, it is not necessary to change the program or processing circuit for performing the soft-decision error correction encoding processing in accordance with each number of bits of pulse amplitude modulation in pulse amplitude modulation of a plurality of numbers of bits.

[0438] Further, with such a soft-decision error correction frame data structure, in the error correction device 200, the number of bits that are to be protected by soft-decision error correction can be reduced compared to the conventional soft-decision error correction encoding process. Therefore, in the error correction device 200, the amount of computation of the soft-decision error correction decoding process can be reduced compared to the conventional soft-decision error correction decoding process.

[0439] Further, with such a soft-decision error correction frame data structure, in the error correction device 200, even if the number of bits of the pulse amplitude modulation changes, the number of bits that are to be protected by soft-decision error correction can be fixed. Therefore, in the error correction device 200, the amount of computation of the soft-decision error correction decoding process can be fixed in the pulse amplitude modulation of any number of bits. Therefore, in the error correction device 200, in the pulse amplitude modulation of a plurality of numbers of bits, it is not necessary to change the program or the processing circuit for performing the soft-decision error correction decoding process according to each number of bits of the pulse amplitude modulation.

[0440] Further, with respect to the soft-decision error correction frame data structure that the error correction encoding device 100 generates, based on the reception digital baseband modulation signal that is generated from the signal based on the soft-decision error correction frame information having the soft-decision error correction frame data structure,

[0441] Based on the generated reception modulation symbol group information, using the 1st symbol mapping rule or the 2nd symbol mapping rule, a 1st hard-decision candidate bit array information constituted of a bit array of 1 row and N1 columns, a 2nd hard-decision candidate bit array information constituted of a bit array of m-2 rows and N1 columns in the case where m is 3 or more, and a 3rd hard-decision candidate bit array information constituted of a bit array of m-2 rows and N2 columns in the case where m is 3 or more are generated,

[0442] Based on the generated reception modulation symbol group information, a 1st posterior L value sequence constituted of N2 posterior L values corresponding to each column of the 1st row of the 2nd bit string group information, a 2nd posterior L value sequence constituted of N1 posterior L values corresponding to each column of the mth row of the 1st bit string group information, and a 3rd posterior L value sequence constituted of N2 posterior L values corresponding to each column of the mth row of the 2nd bit string group information are generated,

[0443] Based on the generated 1st hard-decision candidate bit array information, the 2nd hard-decision candidate bit array information, the 3rd hard-decision candidate bit array information, the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence, a multi-stage error correction process is performed, whereby error correction can be performed.

[0444] Further, regarding the soft-decision error correction frame data structure of the soft-decision error correction frame information generated by the error correction coding device 100, in the first decoding process of the multi-stage error correction processing, soft-decision error correction processing is performed based on the first, second, and third posterior L value sequences, whereby the inverted first received LSB information constituted by a 1-row N1-column bit array and the second received LSB information constituted by a 1-row N2-column bit array are generated,

[0445] In the second decoding process of the multi-stage error correction processing, the first received MSB information constituted by a 1-row N1-column bit array is generated based on the first hard-decision candidate bit array information and the inverted first received LSB information, in the case where m is 3 or more, the first received SSB information constituted by an m-2-row N1-column bit array is generated based on the second hard-decision candidate bit array information and the inverted first received LSB information, in the case where m is 3 or more, the second received SSB information constituted by an m-2-row N2-column bit array is generated based on the third hard-decision candidate bit array information and the second received LSB information,

[0446] In the third decoding process of the multi-stage error correction processing, the first received LSB information is generated by operating the exclusive OR of the bit values of each column in the inverted first received LSB information and the bit values of each column in the first received MSB information corresponding to each column in the inverted first received LSB information,

[0447] In the fourth decoding process of the multi-stage error correction processing, the first output bit array information constituted by an m-1-row N-column bit array is generated by performing probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information,

[0448] In the fifth decoding process of the multi-stage error correction processing, the second output bit array information constituted by a 1-row N3-column bit array is generated by extracting the information of a predetermined region in the first received MSB information,

[0449] In the sixth decoding process of the multi-stage error correction processing, output information corresponding to the input information can be generated based on the first output bit array information and the second output bit array information.

[0450] Variation of Embodiment 1

[0451] Reference Figure 28 The structure of the main part of the communication system 1c of the variation of Embodiment 1 will be described.

[0452] Figure 28 is a structure diagram showing an example of the structure of the main part of the communication system 1c of the variation of Embodiment 1.

[0453] In the modification of Embodiment 1, the case where the communication system 1c is an optical communication system is described as an example, but the optical communication system is only an example, and the communication system 1c is not limited to the optical communication system. For example, the communication system 1c can also be a communication system based on wireless communication or metal communication, or the like.

[0454] The communication system 1c includes the transmission device 10c, the transmission path 30, and the reception device 20c.

[0455] The communication system 1c is obtained by changing the transmission device 10 and the reception device 20 of Embodiment 1 to the transmission device 10c and the reception device 20c.

[0456] In Figure 28 , the same reference numerals are labeled to the same blocks as those shown in Figure 1 , and the description is omitted.

[0457] The transmission device 10c acquires input information and outputs a signal based on the acquired input information. Since Figure 28 the communication system 1c shown in Figure 28 is an optical communication system, the transmission device 10c is an optical transmission device that outputs an optical signal.

[0458] The transmission device 10c includes the error correction encoding device 100c, the D / A converter 11, the light source 12 for transmission, and the optical modulator 13.

[0459] The transmission device 10c is obtained by changing the error correction encoding device 100 of Embodiment 1 to the error correction encoding device 100c.

[0460] The error correction encoding device 100c acquires input information input from the outside and generates a digital baseband modulation signal based on the acquired input information. The error correction encoding device 100c outputs the generated digital baseband modulation signal to the D / A converter 11.

[0461] The reception device 20c receives a signal output by the transmission device 10c via the transmission path 30, generates output information corresponding to the input information based on the signal, and outputs the generated output information. Since Figure 28 the communication system 1c shown in Figure 28 is an optical communication system, the reception device 20c is an optical reception device that receives an optical signal.

[0462] The reception device 20c includes the light source 22 for reception, the optical receiver 21, the A / D converter 23, and the error correction device 200c.

[0463] The reception device 20c is obtained by changing the error correction device 200 of Embodiment 1 to the error correction device 200c.

[0464] The error correction device 200c receives the reception digital baseband modulation signal output by the A / D converter 23, generates output information corresponding to the input information on the basis of the reception digital baseband modulation signal, and outputs the generated output information.

[0465] Referring to Figure 29 The structure of the main part of the error correction encoding device 100c of the modification of Embodiment 1 will be described.

[0466] Figure 29 is a structural diagram showing an example of the structure of the main part of the error correction encoding device 100c of the modification of Embodiment 1.

[0467] The error correction encoding device 100c includes an input information acquisition section 110, an encoding section 120c, a modulation symbol conversion section 130, and a transmission waveform shaping section 140.

[0468] The error correction encoding device 100c is obtained by changing the encoding section 120 of Embodiment 1 to the encoding section 120c.

[0469] In Figure 29 , the same reference numerals are labeled to the same blocks as those shown in Figure 2 , and the description is omitted.

[0470] The encoding section 120c generates soft-decision error correction frame information in which the first bit string group information and the second bit string group information are combined, on the basis of the input information acquired by the input information acquisition section 110.

[0471] Referring to Figure 30 , the structure of the main part of the encoding section 120c of the modification of Embodiment 1 will be described.

[0472] Figure 30 is a structural diagram showing an example of the structure of the main part of the encoding section 120c of the modification of Embodiment 1.

[0473] The encoding section 120c includes an input bit array information generation section 121c, a probability distribution shaping encoding section 122, a bit inversion section 123, and a soft-decision error correction encoding section 124c.

[0474] The encoding section 120c is obtained by changing the input bit array information generation section 121 and the soft-decision error correction encoding section 124 included in the encoding section 120 of Embodiment 1 to the input bit array information generation section 121c and the soft-decision error correction encoding section 124c.

[0475] The input bit array information generating section 121 of Embodiment 1 generates, based on the input information, the 1st input bit array information composed of an m-1 row by N column bit array and the 2nd input bit array information composed of a 1 row by N3 column bit array.

[0476] In contrast, the input bit array information generating section 121c generates, based on the input information, the 3rd input bit array information composed of a 1 row by N4 column (N4 is a natural number of 1 or more and smaller than N2) bit array in addition to the 1st input bit array information and the 2nd input bit array information.

[0477] The input bit array information generating section 121c generates the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information composed of a 1 row by N4 column bit array based on the input information obtained by the input information obtaining section 110.

[0478] In the case where the input information includes the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information, the input bit array information generating section 121c extracts the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information from the input information, respectively, or separates the input information into the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information, thereby generating the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information.

[0479] The input bit array information generating section 121c, like the input bit array information generating section 121 of Embodiment 1, stores the generated 2nd input bit array information as a part of the 1st MSB information composed of a 1 row by N1 column bit array in the 2nd input bit area in the 1st bit string group information.

[0480] Further, the input bit array information generating section 121c stores the generated 3rd input bit array information as a part of the 2nd MSB information composed of a 1 row by N2 column bit array in a predetermined area (hereinafter referred to as "3rd input bit area") of the 1st row in the 2nd bit string group information.

[0481] Specifically, the input bit array information generating section 121c stores the 3rd input bit array information in the 3rd input bit area in Dv[1][2] which is a bit array space in which the 2nd MSB is stored. Hereinafter, the case where the 3rd input bit area is D[1][2][1:N4] will be described.

[0482] The probability distribution shaping coding section 122 performs a probability distribution shaping coding process on the first input bit array information generated by the input bit array information generating section 121c, thereby generating shaped bit array information composed of m-1 rows and N columns of bits.

[0483] The soft decision error correction coding section 124c performs a systematic soft decision error correction coding process using the third input bit array information of the third input bit region stored in the second MSB by the input bit array information generating section 121c, in addition to the inverted first LSB information generated by the bit inversion section 123 and the second LSB information generated by the probability distribution shaping coding section 122, thereby generating soft decision parity bits. The soft decision error correction coding section 124c stores the generated soft decision parity bits in a predetermined region (hereinafter referred to as a "soft decision parity region") in the second MSB information that is different from the third input bit region.

[0484] Specifically, the soft decision error correction coding section 124c performs a systematic soft decision error correction coding process using the bit values of each column in Dv[m][l] in which the inverted first LSB information is stored, i.e., B[m][l][l:Nl], the bit values of each column in Dv[m][2] in which the second LSB information is stored, i.e., B[m][2][l:N2], and the bit values of each column in D[l][2][l:N4] in which the third input bit array information is stored, i.e., B[l][2][l:N4], thereby generating soft decision parity bits. The soft decision error correction coding section 124c stores the generated soft decision parity bits in the soft decision parity region in Dv[l][2] that is the bit array space storing the second MSB. Hereinafter, a case where the soft decision parity region is D[l][2][N4+l:N2] will be described.

[0485] By being configured as described above, the coding section 120c generates soft decision error correction frame information by storing the soft decision error correction frame information in Dv[l:m][l:2] that is the bit array space.

[0486] As described above, the coding section 120c performs a systematic soft decision error correction coding process using the bit values of each column in Dv[m][l] and the bit values of each column in Dv[m][2]. Therefore, the bits that become the target of protection by the soft decision error correction coding process are only the least significant bits of each column in Dd[l:2] in the soft decision error correction frame information and D[l][2][l:N4] that stores the third input bit array information.

[0487] Therefore, in the coding section 120c, the number of bits that become the target of protection by the soft decision error correction coding process can be reduced compared to the conventional soft decision error correction coding process.

[0488] In addition, each function of the input information acquisition section 110, the encoding section 120c, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 included in the error correction encoding device 100c according to the modification example of Embodiment 1 can be implemented by the processor 501 and the memory 502 in the hardware structure shown in FIG. 31, or can be implemented by the processing circuit 503. Figure 5A and Figure 5B The processor 501 and the memory 502 in the hardware structure shown in FIG. 31 implement, for example, or the processing circuit 503 can implement.

[0489] Referring to Figure 31A , Figure 31B and Figure 31C , the operation of the error correction encoding device 100c according to the modification example of Embodiment 1 will be described.

[0490] Figure 31A is a part of a flowchart showing an example of the processing of the error correction encoding device 100c according to the modification example of Embodiment 1.

[0491] Figure 31B is another part of the flowchart showing an example of the processing of the error correction encoding device 100c according to the modification example of Embodiment 1.

[0492] Figure 31C is the remaining part of the flowchart showing an example of the processing of the error correction encoding device 100c according to the modification example of Embodiment 1.

[0493] Hereinafter, the steps ST3101, Figure 31A , Figure 31B and Figure 31C are collectively referred to as FIG. 31.

[0494] The error correction encoding device 100c repeatedly performs the processing of the flowchart shown in FIG. 31.

[0495] In addition, the flowchart shown in FIG. 31 is obtained by changing the step ST610 in the flowchart shown in FIG. 6 to the step ST3110.

[0496] In FIG. 31, the same reference numerals are attached to the same processing as the processing of the flowchart shown in FIG. 6, and the description is omitted.

[0497] First, the error correction encoding device 100c performs the processing of the step ST601.

[0498] Next, in the step ST3110, the encoding section 120c generates soft-decision error correction frame information.

[0499] Specifically, the encoding section 120c performs the processing of step ST3110 by performing the processing of steps ST3111 to ST3112, the processing of steps ST612 to ST616, and the processing of steps ST3117 to ST3118 in the following processing M.

[0500] First, in step ST3111, the input bit array information generating section 121c included in the encoding section 120c generates the 1st input bit array information, the 2nd input bit array information, and the 3rd input bit array information.

[0501] Next, in step ST3112, the input bit array information generating section 121c included in the encoding section 120c stores the 3rd input bit array information in the 3rd input bit region in Dv[l][2].

[0502] After step ST3112, the encoding section 120c performs the processing of steps ST612 to ST616.

[0503] After step ST616, in step ST3117, the soft-decision error correction encoding section 124c included in the encoding section 120c performs soft-decision error correction encoding processing using the bit values of each column in Dv[m][l], the bit values of each column in Dv[m][2], and the bit values of each column in D[l][2][l:N4] which is the 3rd input bit region, and thereby generates soft-decision parity bits.

[0504] After step ST3117, in step ST3118, the soft-decision error correction encoding section 124c included in the encoding section 120c stores the soft-decision parity bits in Dv[l][2][N4+l] which is a soft-decision parity region.

[0505] After step ST3118, the encoding section 120c ends the processing M. That is, after step ST3118, the encoding section 120c ends the processing of step ST3110.

[0506] After step ST3110, the error correction encoding apparatus 100c performs the processing of steps ST620 to ST630.

[0507] After step ST630, the error correction encoding apparatus 100c ends the processing of the flowchart illustrated in FIG. 31, and returns to the processing of step ST601 to repeatedly perform the processing of the flowchart illustrated in FIG. 31.

[0508] Referring to Figure 32 The configuration of the main part of the error correction apparatus 200c according to the modification example of Embodiment 1 will be described.

[0509] Figure 32 Fig. 18 is a configuration diagram showing an example of the configuration of a main part of an error correction device 200c that is a modification example of the error correction device 200 of Embodiment 1.

[0510] The error correction device 200c includes a reception modulation symbol group information generating section 210, a hard decision candidate generating section 220, a soft decision information generating section 230, a decoding section 240c, and an information output section 290.

[0511] The error correction device 200c is obtained by changing the decoding section 240 of Embodiment 1 to the decoding section 240c.

[0512] In Figure 32 , the same reference numerals are labeled to the same blocks as those shown in Figure 7 , and the description is omitted.

[0513] The decoding section 240c performs a multi-stage error correction process based on the 1st hard decision candidate bit array information, the 2nd hard decision candidate bit array information, and the 3rd hard decision candidate bit array information generated by the hard decision candidate generating section 220, and the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence generated by the soft decision information generating section 230, thereby generating output information.

[0514] Referring to Figure 33 , the configuration of a main part of the decoding section 240c of the modification example of Embodiment 1 is described.

[0515] Figure 33 Fig. 19 is a configuration diagram showing an example of the configuration of a main part of the decoding section 240c of Embodiment 1.

[0516] The decoding section 240c includes a soft decision error correction decoding section 241c, a selection section 242, a reception side bit inversion section 243, a probability distribution shaping decoding section 244, a 2nd output bit array generating section 245, an output information generating section 246c, and a 3rd output bit array generating section 260.

[0517] The decoding section 240c is obtained by additionally providing the 3rd output bit array generating section 260 to the configuration of the decoding section 240 of Embodiment 1, and changing the soft decision error correction decoding section 241 and the output information generating section 246 of Embodiment 1 to the soft decision error correction decoding section 241c and the output information generating section 246c.

[0518] In Figure 33 , the same reference numerals are labeled to the same blocks as those shown in Figure 8 , and the description is omitted.

[0519] The soft decision error correction decoding section 241c performs a 1st decoding process in the multi-stage error correction process.

[0520] Specifically, the soft-decision error correction decoding section 241c performs soft-decision error correction processing using the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence.

[0521] More specifically, the soft-decision error correction decoding section 241c performs soft-decision error correction processing using the posterior L value sequence corresponding to B[1][2][1:N4] as the 3rd input bit array information in the 2nd received MSB information, i.e., L[1][2][1:N4], the posterior L value sequence corresponding to B[1][2][N4+1:N2] as the soft-decision parity bit in the 2nd received MSB information, i.e., L[1][2][N4+1:N2], the 2nd posterior L value sequence, i.e., Lv[m][1], and the 3rd posterior L value sequence, i.e., Lv[m][2].

[0522] The soft-decision error correction decoding section 241c generates the 2nd received MSB information composed of a bit array of 1 row and N2 columns corresponding to the 2nd MSB information including the 3rd input bit array information generated by the input bit array information generating section 121c by performing soft-decision error correction processing.

[0523] Further, the soft-decision error correction decoding section 241c generates the 2nd received LSB information composed of a bit array of 1 row and N2 columns corresponding to the 2nd LSB information generated by the probability distribution shaping encoding section 122 by performing soft-decision error correction processing.

[0524] Further, the soft-decision error correction decoding section 241c generates the 2nd received MSB information composed of a bit array of 1 row and N2 columns corresponding to the 2nd MSB information including the 3rd input bit array information generated by the input bit array information generating section 121c by performing soft-decision error correction processing.

[0525] The 2nd to 5th decoding processes in the multi-stage error correction processing are the same as those in Embodiment 1, and thus the description thereof is omitted.

[0526] The 3rd output bit array generating section 260 performs the 8th decoding process in the multi-stage error correction processing.

[0527] Specifically, the 3rd output bit array generating section 260 generates the 3rd output bit array information composed of a bit array of 1 row and N4 columns corresponding to the 3rd input bit array information by extracting information of a region in the 2nd received MSB information corresponding to the 3rd input bit region in the 2nd MSB information.

[0528] More specifically, for example, the 3rd output bit array generating section 260 generates the 3rd output bit array information by extracting bit values of the 1st column to the N4th column in the 2nd received MSB information.

[0529] The output information generating section 246c performs a 6th decoding process in the multistage error correction processing.

[0530] Specifically, the output information generating section 246c generates the output information corresponding to the input information based on the 3rd output bit array information in addition to the 1st output bit array information and the 2nd output bit array information.

[0531] In addition, each function of the reception modulation symbol group information generating section 210, the hard decision candidate generating section 220, the soft decision information generating section 230, the decoding section 240c, and the information output section 290 included in the error correction device 200c of the modification example of Embodiment 1 can be implemented by the processing circuit 903 in Embodiment 1. Figure 9A and Figure 9B The processor 901 and the memory 902 in the example hardware structure are shown to be implemented, or can also be implemented by the processing circuit 903.

[0532] Referring to Figure 34A , Figure 34B and Figure 34C , the operation of the error correction device 200c of the modification example of Embodiment 1 will be described.

[0533] Figure 34A is a part of a flowchart showing an example of the processing of the error correction device 200c of the modification example of Embodiment 1.

[0534] Figure 34B is another part of the flowchart showing an example of the processing of the error correction device 200c of the modification example of Embodiment 1.

[0535] Figure 34C is the remaining part of the flowchart showing an example of the processing of the error correction device 200c of the modification example of Embodiment 1.

[0536] Hereinafter, Figure 34A , Figure 34B and Figure 34C are collectively referred to as FIG. 34.

[0537] The error correction device 200c repeatedly performs the processing of the flowchart shown in FIG. 34.

[0538] In addition, the flowchart shown in FIG. 34 is obtained by changing the step ST1030 in the flowchart shown in FIG. 10 to the step ST3430.

[0539] In FIG. 34, the same reference numerals are annotated for the same processing as the processing of the flowchart shown in FIG. 10 and the description is omitted.

[0540] First, the error correction device 200c performs the processing of the steps ST1000 to ST1020.

[0541] After the step ST1020, in a step ST3430, the decoding section 240c generates the output information by performing the multi-stage error correction processing.

[0542] Specifically, the decoding section 240c performs the processing of the step ST3430 by performing the processing of the step ST3431, the processing of the steps ST1032 to ST1036, and the processing of the steps ST3436 to ST3437 in the following processing N.

[0543] First, in the step ST3431, the soft decision error correction decoding section 241c provided to the decoding section 240c generates the inverted first received LSB information, the second received LSB information, and the second received MSB information by performing the soft decision error correction processing.

[0544] After the step ST3431, the decoding section 240c performs the processing of the steps ST1032 to ST1035.

[0545] After the step ST1035, in a step ST3436, the third output bit array generating section 260 provided to the decoding section 240c generates the third output bit array information.

[0546] After the step ST3436, in a step ST3437, the output information generating section 246c provided to the decoding section 240c generates the output information.

[0547] After the step ST3437, the decoding section 240c ends the processing N. That is, after the step ST3437, the decoding section 240c ends the processing of the step ST3430.

[0548] After the step ST3430, the error correction device 200c performs the processing of a step ST1050.

[0549] After the step ST1050, the error correction device 200c ends the processing of the flowchart illustrated in FIG. 34, and the error correction device 200c returns to the processing of the step ST1000 to repeatedly perform the processing of the flowchart illustrated in FIG. 34.

[0550] As described above, the error correction encoding device 100c is configured to include: an input information obtaining section 110 that obtains input information;

[0551] a coding section 120c that generates soft decision error correction frame information composed of a bit array of m rows and N columns by combining first bit string group information composed of a bit array of m rows and Nl columns and second bit string group information composed of a bit array of m rows and N2 columns, and that pulse-amplitude-modulates a combination of bit values of each column of the first bit string group information into a modulation symbol using a first symbol mapping rule decided in advance and pulse-amplitude-modulates a combination of bit values of each column of the second bit string group information into a modulation symbol using a second symbol mapping rule decided in advance;

[0552] a modulation symbol conversion section 130 that pulse-amplitude-modulates a combination of bit values of each column of the soft decision error correction frame information generated by the coding section 120c into a modulation symbol using the first symbol mapping rule or the second symbol mapping rule for each column of the soft decision error correction frame information, and thereby generates modulation symbol group information composed of N modulation symbols; and

[0553] a transmission waveform shaping section 140 that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion section 130, and outputs the generated digital baseband modulation signal,

[0554] The coding section 120c generates the soft decision error correction frame information by the following processing:

[0555] generates first input bit array information composed of a bit array of m-1 rows and N columns and second input bit array information composed of a bit array of 1 row and N3 columns based on the input information acquired by the input information acquisition section 110,

[0556] stores the generated second input bit array information as a part of first MSB information composed of a bit array of 1 row and Nl columns in a predetermined region of the first row in the first bit string group information,

[0557] generates shaped bit array information composed of a bit array of m-1 rows and N columns by performing a probability distribution shaping coding process on the generated first input bit array information,

[0558] generates first group bit array information composed of a combination of Nl predetermined columns and second group bit array information composed of a combination of N2 predetermined columns by separating the generated shaped bit array information,

[0559] generates first LSB information composed of a bit array of 1 row and Nl columns by extracting a bit array of the m-1th row in the first group bit array information from the generated first group bit array information,

[0560] The 1st LSB information generated by the operation is inverted by performing XOR between the bit values of each column in the 1st LSB information and the bit values of each column corresponding to each column in the 1st row of the 1st bit string group information after storing the 2nd input bit array information, thereby generating inverted 1st LSB information composed of a bit array of 1 row and N1 columns, and the generated inverted 1st LSB information is stored in the mth row of the 1st bit string group information,

[0561] The 2nd LSB information composed of a bit array of 1 row and N2 columns is generated by extracting the bit array of the m-1th row of the 2nd group of bit array information from the generated 2nd group of bit array information, and the generated 2nd LSB information is stored in the mth row of the 2nd bit string group information,

[0562] The soft decision parity bits are generated by performing soft decision error correction encoding processing using the generated inverted 1st LSB information and the generated 2nd LSB information, and the generated soft decision parity bits are stored as the 2nd MSB information composed of a bit array of 1 row and N2 columns in the 1st row of the 2nd bit string group information,

[0563] In the case where m is 3 or more, the 1st SSB information composed of a bit array of m-2 rows and N1 columns is generated by extracting the 1st to m-2nd rows of the 1st group of bit array information from the generated 1st group of bit array information, and the generated 1st SSB information is stored in the 2nd to m-1th rows of the 1st bit string group information,

[0564] In the case where m is 3 or more, the 2nd SSB information composed of a bit array of m-2 rows and N2 columns is generated by extracting the 1st to m-2nd rows of the 2nd group of bit array information from the generated 2nd group of bit array information, and the generated 2nd SSB information is stored in the 2nd to m-1th rows of the 2nd bit string group information.

[0565] Further, the error correction encoding device 100c is configured to generate soft decision error correction frame information by the following processing on the basis of the above-described structure:

[0566] The 3rd input bit array information composed of a bit array of 1 row and N4 columns is generated on the basis of the input information acquired by the input information acquisition section 110, in addition to the 1st input bit array information and the 2nd input bit array information,

[0567] The generated 3rd input bit array information is stored as a part of the 2nd MSB information composed of a bit array of 1 row and N2 columns in a predetermined region of the 1st row of the 2nd bit string group information,

[0568] In addition to using the generated inverted first LSB information and the generated second LSB information, the third input bit array information stored as a part of the second MSB information is used to perform the soft decision error correction encoding processing of the system, whereby the soft decision parity bits are generated, and the generated soft decision parity bits are stored in a predetermined region of the first row of the second bit string group information, which is different from the region in which the second bit string group information is stored.

[0569] By being thus configured, in the error correction encoding device 100c, the number of bits that are to be protected by the soft decision error correction can be reduced compared to the conventional soft decision error correction encoding processing. Therefore, in the error correction encoding device 100c, the amount of computation of the soft decision error correction encoding processing can be reduced compared to the conventional soft decision error correction encoding processing.

[0570] Further, by being thus configured, in the error correction encoding device 100c, the number of bits that are to be protected by the soft decision error correction can be fixed even if the number of bits of the pulse amplitude modulation changes. Therefore, in the error correction encoding device 100c, the amount of computation of the soft decision error correction encoding processing can be fixed in the pulse amplitude modulation of an arbitrary number of bits. Therefore, in the error correction encoding device 100c, it is not necessary to change the program or the processing circuit for performing the soft decision error correction encoding processing in accordance with each number of bits of the pulse amplitude modulation in the pulse amplitude modulation of a plurality of numbers of bits.

[0571] Further, by being thus configured, in the error correction encoding device 100c, the third input bit array information can be transmitted to the error correction device 200c in addition to the first input bit array information and the second input bit array information being transmitted to the error correction device 200c, and therefore, compared to the error correction encoding device 100 of Embodiment 1, the effective information in the soft decision error correction frame information can be increased by one. Therefore, the error correction encoding device 100c can efficiently transmit information to the error correction device 200c compared to the error correction encoding device 100 of Embodiment 1.

[0572] Further, as described above, the error correction device 200c is configured to include:

[0573] a reception modulation symbol group information generation section 210 that receives a signal based on the soft decision error correction frame information generated by the error correction encoding device 100c, that is, a reception digital baseband modulation signal, and generates reception modulation symbol group information composed of N reception modulation symbols based on the reception digital baseband modulation signal;

[0574] a hard decision candidate generation section 220 that generates first hard decision candidate bit array information composed of a bit array of 1 row and Nl columns, second hard decision candidate bit array information composed of a bit array of m-2 rows and Nl columns in a case where m is 3 or more, and third hard decision candidate bit array information composed of a bit array of m-2 rows and N2 columns in a case where m is 3 or more, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210, using the first symbol mapping rule or the second symbol mapping rule;

[0575] a soft decision information generation section 230 that generates first posterior L value sequence composed of N2 posterior L values corresponding to each column of the first row of the second bit string group information, second posterior L value sequence composed of Nl posterior L values corresponding to each column of the m-th row of the first bit string group information, and third posterior L value sequence composed of N2 posterior L values corresponding to each column of the m-th row of the second bit string group information, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210;

[0576] a decoding section 240c that performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation section 220, and the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence generated by the soft decision information generation section 230; and

[0577] an information output section 290 that outputs information generated by the decoding section 240c as output information,

[0578] In the first decoding processing of the multi-stage error correction processing, the decoding section 240c performs soft decision error correction processing based on the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence, thereby generating post-inversion first reception LSB information composed of a bit array of 1 row and Nl columns corresponding to post-inversion first LSB information, and second reception LSB information composed of a bit array of 1 row and N2 columns corresponding to the second LSB information,

[0579] In the second decoding process of the multi-stage error correction processing, the decoding section 240c generates first received MSB information corresponding to the first MSB information, which is constituted by a bit array of 1 row and Nl columns, based on the first hard-decision candidate bit array information and the inverted first received LSB information, and generates first received SSB information corresponding to the first SSB information, which is constituted by a bit array of m-2 rows and Nl columns, based on the second hard-decision candidate bit array information and the inverted first received LSB information in the case where m is 3 or more, and generates second received SSB information corresponding to the second SSB information, which is constituted by a bit array of m-2 rows and N2 columns, based on the third hard-decision candidate bit array information and the second received LSB information in the case where m is 3 or more,

[0580] In the third decoding process of the multi-stage error correction processing, the decoding section 240c generates first received LSB information corresponding to the first LSB information by operating exclusive OR of the bit values of each column in the inverted first received LSB information and the bit values of each column in the first received MSB information corresponding to each column in the inverted first received LSB information,

[0581] In the fourth decoding process of the multi-stage error correction processing, the decoding section 240c generates first output bit array information corresponding to the first input bit array information, which is constituted by a bit array of m-l rows and N columns, by performing a probability distribution shaping decoding process on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information,

[0582] In the fifth decoding process of the multi-stage error correction processing, the decoding section 240c generates second output bit array information corresponding to the second input bit array information, which is constituted by a bit array of 1 row and N3 columns, by extracting information of a predetermined region in the first received MSB information,

[0583] In the sixth decoding process of the multi-stage error correction processing, the decoding section 240c generates output information corresponding to the input information based on the first output bit array information and the second output bit array information, and the information output section 290 outputs the output information generated by the decoding section 240c.

[0584] Further, the error correction device 200c is configured, based on the above-described structure, such that the decoding section 240c generates, in the first decoding process of the multi-stage error correction processing, second received MSB information corresponding to the second MSB information, which is constituted by a bit array of 1 row and N2 columns, by performing a soft-decision error correction process based on the first a posteriori L value sequence, the second a posteriori L value sequence, and the third a posteriori L value sequence, in addition to generating the inverted first received LSB information corresponding to the inverted first LSB information, which is constituted by a bit array of 1 row and Nl columns, and the second received LSB information corresponding to the second LSB information, which is constituted by a bit array of 1 row and N2 columns.

[0585] In the 8th decoding process of the multi-stage error correction processing, information of a predetermined region in the 2nd received MSB information is extracted, and a 3rd output bit array information corresponding to the 3rd input bit array information is generated as a bit array of 1 row and N4 columns,

[0586] In the 6th decoding process of the multi-stage error correction processing, the 3rd output bit array information is used in addition to the 1st output bit array information and the 2nd output bit array information, and output information corresponding to the input information is generated.

[0587] By being configured as such, in the error correction device 200c, the number of bits to be protected by the soft decision error correction can be reduced compared to the conventional soft decision error correction encoding processing. Therefore, in the error correction device 200c, the amount of calculation of the soft decision error correction decoding processing can be reduced compared to the conventional soft decision error correction decoding processing.

[0588] Further, by being configured as such, in the error correction device 200c, the number of bits to be protected by the soft decision error correction can be fixed even if the number of bits of the pulse amplitude modulation changes. Therefore, in the error correction device 200c, the amount of calculation of the soft decision error correction decoding processing can be fixed in the pulse amplitude modulation of any number of bits. Therefore, in the error correction device 200c, it is not necessary to change the program or the processing circuit for performing the soft decision error correction decoding processing for each number of bits of the pulse amplitude modulation in the pulse amplitude modulation of a plurality of numbers of bits.

[0589] Further, by being configured as such, in the error correction device 200c, the 3rd output bit array information corresponding to the 3rd input bit array information can be recovered in addition to the 1st output bit array information and the 2nd output bit array information corresponding to the 1st input bit array information and the 2nd input bit array information by the multi-stage error correction processing.

[0590] Therefore, in the error correction device 200c, the effective information recovered from the signal based on one soft decision error correction frame information, that is, the received digital baseband modulation signal can be increased compared to the error correction device 200 of Embodiment 1. Therefore, in the error correction device 200c, information can be efficiently received compared to the error correction device 200 of Embodiment 1.

[0591] Embodiment 2

[0592] Reference Figure 11 The structure of the main part of the communication system 1a of Embodiment 2 will be described.

[0593] Figure 11 is a structural diagram illustrating an example of the structure of the main part of the communication system 1a of Embodiment 2.

[0594] In Embodiment 2, as an example, a case where the communication system la is an optical communication system is described, but the optical communication system is only an example, and the communication system la is not limited to the optical communication system. For example, the communication system la can also be a communication system based on wireless communication or metal communication, or the like.

[0595] The communication system la includes the transmission device 10a, the transmission path 30, and the reception device 20a.

[0596] The communication system la is obtained by changing the transmission device 10 and the reception device 20 of Embodiment 1 to the transmission device 10a and the reception device 20a.

[0597] In Figure 11 , the same reference numerals are labeled to the same blocks as those illustrated in Figure 1 , and the description is omitted.

[0598] The transmission device 10a acquires input information and outputs a signal based on the acquired input information. Since Figure 11 the communication system la illustrated in Figure 11 is an optical communication system, the transmission device 10a is an optical transmission device that outputs an optical signal.

[0599] The transmission device 10a includes the error correction encoding device 100a, the D / A converter 11, the light source 12 for transmission, and the optical modulator 13.

[0600] The transmission device 10a is obtained by changing the error correction encoding device 100 of Embodiment 1 to the error correction encoding device 100a.

[0601] The error correction encoding device 100a acquires input information input from the outside, and generates a digital baseband modulation signal based on the acquired input information. The error correction encoding device 100a outputs the generated digital baseband modulation signal to the D / A converter 11.

[0602] The reception device 20a receives a signal output by the transmission device 10a via the transmission path 30, generates output information corresponding to the input information based on the signal, and outputs the generated output information. Since Figure 11 the communication system la illustrated in Figure 11 is an optical communication system, the reception device 20a is an optical reception device that receives an optical signal.

[0603] The reception device 20a includes the light source 22 for reception, the optical receiver 21, the A / D converter 23, and the error correction device 200a.

[0604] The reception device 20a is obtained by changing the error correction device 200 of Embodiment 1 to the error correction device 200a.

[0605] The error correction device 200a receives the reception digital baseband modulation signal output by the A / D converter 23, generates output information corresponding to the input information on the basis of the reception digital baseband modulation signal, and outputs the generated output information.

[0606] Referring to Figure 12 , the structure of the main part of the error correction encoding device 100a of Embodiment 2 will be described.

[0607] Figure 12 is a structural diagram showing an example of the structure of the main part of the error correction encoding device 100a of Embodiment 2.

[0608] The error correction encoding device 100a includes an input information acquisition section 110, an encoding section 120a, a modulation symbol conversion section 130, and a transmission waveform shaping section 140.

[0609] The error correction encoding device 100a is obtained by changing the encoding section 120 of Embodiment 1 to the encoding section 120a.

[0610] In Figure 12 , the same reference numerals are labeled to the same blocks as those shown in Figure 2 , and the description is omitted.

[0611] The encoding section 120a generates soft-decision error correction frame information in which the first bit string group information and the second bit string group information are combined, on the basis of the input information acquired by the input information acquisition section 110.

[0612] Referring to Figure 13 , the structure of the main part of the encoding section 120a of Embodiment 2 will be described.

[0613] Figure 13 is a structural diagram showing an example of the structure of the main part of the encoding section 120a of Embodiment 2.

[0614] The encoding section 120a includes an input bit array information generation section 121, a probability distribution shaping encoding section 122, a bit inversion section 123, a soft-decision error correction encoding section 124, and a hard-decision error correction encoding section 125.

[0615] The encoding section 120a is obtained by additionally providing the hard-decision error correction encoding section 125 to the structure of the encoding section 120 of Embodiment 1.

[0616] In Figure 13 , the same reference numerals are labeled to the same blocks as those shown in Figure 3 , and the description is omitted.

[0617] The hard-decision error correction coding section 125 performs a system hard-decision error correction coding process using the first input bit array information generated by the input bit array information generating section 121 and the second input bit array information generated by the input bit array information generating section 121.

[0618] The hard-decision error correction coding section 125 can also perform a system hard-decision error correction coding process using the first input bit array information generated by the input bit array information generating section 121, the first SSB information generated by the probability distribution shaping coding section 122, the second SSB information, the second LSB information, and the first LSB information.

[0619] Further, the hard-decision error correction coding section 125 can also perform a system hard-decision error correction coding process using the first input bit array information generated by the input bit array information generating section 121, the first SSB information generated by the probability distribution shaping coding section 122, the second SSB information, the second LSB information, and the first LSB information.

[0620] Figure 13 is a diagram showing a case where the hard-decision error correction coding section 125 performs a system hard-decision error correction coding process using the first input bit array information generated by the input bit array information generating section 121, the first SSB information generated by the probability distribution shaping coding section 122, the second SSB information, the second LSB information, and the first LSB information.

[0621] The hard-decision error correction coding section 125 generates hard-decision parity bits by performing a system hard-decision error correction coding process, and stores the generated hard-decision parity bits as a part of the first MSB information in a predetermined region (hereinafter referred to as a "hard-decision parity region") of the first row in the first bit string group information other than the second input bit region.

[0622] Specifically, the hard-decision error correction coding section 125 stores the generated hard-decision parity bits in the hard-decision parity region in Dv[1][1] which is a bit array space in which the first MSB is stored. Hereinafter, a case where the hard-decision parity region is D[1][1][N3+1:N1] will be described.

[0623] As the system hard-decision error correction coding process, a BCH code or a Reed Solomon code or the like is used.

[0624] In addition, each function of the input information acquiring section 110, the coding section 120a, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 included in the error correction coding apparatus 100a of Embodiment 2 can be implemented by the input information acquiring section 110, the coding section 120, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 included in the error correction coding apparatus 100 of Embodiment 1. Figure 5A and Figure 5BThe processor 501 and the memory 502 in the example hardware structure are implemented, or can also be implemented by the processing circuit 503.

[0625] Referring to Figure 14A , Figure 14B and Figure 14C , the operation of the error correction encoding device 100a of Embodiment 2 will be described.

[0626] Figure 14A is a part of a flowchart showing an example of the process of the error correction encoding device 100a of Embodiment 2.

[0627] Figure 14B is another part of the flowchart showing an example of the process of the error correction encoding device 100a of Embodiment 2.

[0628] Figure 14C is the remaining part of the flowchart showing an example of the process of the error correction encoding device 100a of Embodiment 2.

[0629] Hereinafter, Figure 14A , Figure 14B and Figure 14C will be collectively referred to as FIG. 14.

[0630] The error correction encoding device 100a repeatedly performs the process of the flowchart shown in FIG. 14.

[0631] In addition, the flowchart shown in FIG. 14 is obtained by changing the step ST610 in the flowchart shown in FIG. 6 to the step ST1410.

[0632] Further, as an example, the flowchart shown in FIG. 14 shows the operation in the case where the hard decision error correction encoding section 125 performs the system hard decision error correction encoding process using the 1st input bit array information generated by the input bit array information generation section 121, the 1st SSB information generated by the probability distribution shaping encoding section 122, the 2nd SSB information, the 2nd LSB information, and the 1st LSB information.

[0633] In FIG. 14, the same reference numerals are annotated for the same processes as those of the flowchart shown in FIG. 6, and the description is omitted.

[0634] First, the error correction encoding device 100a performs the process of the step ST601.

[0635] Next, in the step ST1410, the encoding section 120a generates soft decision error correction frame information.

[0636] Specifically, the encoding section 120a performs the processing of step ST1410 by performing the processing of steps ST611 to ST618 and the processing of steps ST1411 to ST1412 in the following processing I.

[0637] First, the encoding section 120a performs the processing of steps ST611 to ST614.

[0638] After step ST614, in step ST1411, the hard-decision error correction encoding section 125 possessed by the encoding section 120a performs system hard-decision error correction encoding processing using the 1st input bit array information, the 1st SSB information, the 2nd SSB information, the 2nd LSB information, and the 1st LSB information.

[0639] Next, in step ST1412, the hard-decision error correction encoding section 125 possessed by the encoding section 120a stores hard-decision parity bits in the hard-decision parity check region in Dv[1][1].

[0640] After step ST1412, the encoding section 120a performs the processing of steps ST615 to ST618.

[0641] After step ST618, the encoding section 120a ends the processing I. That is, after step ST618, the encoding section 120a ends the processing of step ST1410.

[0642] After step ST1410, the error correction encoding apparatus 100a performs the processing of steps ST620 to ST630.

[0643] After step ST630, the error correction encoding apparatus 100a ends the processing of the flowchart illustrated in Fig. 14, and the error correction encoding apparatus 100a returns to the processing of step ST601 to repeatedly perform the processing of the flowchart illustrated in Fig. 14.

[0644] Reference Signs Figure 15 The structure of the main part of the error correction apparatus 200a of Embodiment 2 will be described.

[0645] Figure 15 is a structural diagram illustrating an example of the structure of the main part of the error correction apparatus 200a of Embodiment 2.

[0646] The error correction apparatus 200a includes a reception modulation symbol group information generating section 210, a hard-decision candidate generating section 220, a soft-decision information generating section 230, a decoding section 240a, and an information output section 290.

[0647] The error correction apparatus 200a is obtained by changing the decoding section 240 of Embodiment 1 to the decoding section 240a.

[0648] In Figure 15 , the same reference numerals are labeled to the same blocks shown in Figure 7 , and the explanation is omitted.

[0649] The decoding section 240a generates output information by performing multi-stage error correction processing based on the 1st hard decision candidate bit array information, the 2nd hard decision candidate bit array information, and the 3rd hard decision candidate bit array information generated by the hard decision candidate generation section 220, and the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence generated by the soft decision information generation section 230.

[0650] Referring to Figure 16 , the structure of the main part of the decoding section 240a of Embodiment 2 is explained.

[0651] Figure 16 is a structural diagram showing an example of the structure of the main part of the decoding section 240a of Embodiment 2.

[0652] The decoding section 240a includes a soft decision error correction decoding section 241, a selection section 242, a reception side bit inversion section 243, a probability distribution shaping decoding section 244, a 2nd output bit array generation section 245, an output information generation section 246, and a hard decision error correction decoding section 247.

[0653] The decoding section 240a is obtained by adding the hard decision error correction decoding section 247 to the structure of the decoding section 240 of Embodiment 1.

[0654] In Figure 16 , the same reference numerals are labeled to the same blocks shown in Figure 8 , and the explanation is omitted.

[0655] The hard decision error correction decoding section 247 performs a 7th decoding process in the multi-stage error correction processing.

[0656] The hard decision error correction decoding section 247 performs hard decision error correction processing on the information corresponding to the 2nd output bit array information in the 1st reception MSB information, and the 1st reception SSB information, the 2nd reception SSB information, the 2nd reception LSB information, and the inverted 1st reception LSB information, based on the information of a region corresponding to a hard decision parity check region in the 1st MSB information, which is decided in advance and stored in the 1st reception MSB information (hereinafter referred to as "reception hard decision parity check region").

[0657] The hard-decision error correction decoding section 247 can also perform hard-decision error correction processing on the information in the first received MSB information corresponding to the second output bit array information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information, based on the information stored in the received hard-decision parity region in the first received MSB information.

[0658] Further, the hard-decision error correction decoding section 247 can also perform hard-decision error correction processing on the information in the first received MSB information corresponding to the second output bit array information, and the first output bit array information, based on the information stored in the received hard-decision parity region in the first received MSB information.

[0659] Figure 16 is a diagram showing a case where the hard-decision error correction decoding section 247 performs hard-decision error correction processing on the information in the first received MSB information corresponding to the second output bit array information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information, based on the information stored in the received hard-decision parity region in the first received MSB information.

[0660] Further, in a case where the hard-decision error correction decoding section 247 performs hard-decision error correction processing on the information in the first received MSB information corresponding to the second output bit array information, and the first received SSB information, the second received SSB information, the second received LSB information, and the inverted first received LSB information, the reception-side bit inversion section 243 performs an exclusive OR operation using the inverted first received LSB information after the seventh decoding processing and the first received MSB information in the third decoding processing, and the second output bit array generating section 245 generates the second output bit array information by extracting the information of a predetermined region in the first received MSB information after the seventh decoding processing in the fifth decoding processing.

[0661] Further, in a case where the hard-decision error correction decoding section 247 performs hard-decision error correction processing on the information in the first received MSB information corresponding to the second output bit array information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information, the probability distribution shaping decoding section 244 performs probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information after the seventh decoding processing in the fourth decoding processing, and the second output bit array generating section 245 generates the second output bit array information by extracting the information of a predetermined region in the first received MSB information after the seventh decoding processing in the fifth decoding processing.

[0662] Further, in a case where the hard-decision error correction decoding section 247 performs hard-decision error correction processing on the information of the 1st received MSB information corresponding to the 2nd output bit array information and the 1st output bit array information, the 2nd output bit array generating section 245 generates the 2nd output bit array information by extracting the information of the predetermined region of the 1st received MSB information after the 7th decoding processing in the 5th decoding processing, and the output information generating section 246 generates the output information based on the 2nd output bit array information and the 1st output bit array information after the 7th decoding processing in the 6th decoding processing.

[0663] The error correction device 200a can obtain output information with fewer residual errors by performing error correction based on hard-decision error correction processing, as compared to a case where hard-decision error correction processing is not performed.

[0664] Further, each function of the reception modulation symbol group information generating section 210, the hard-decision candidate generating section 220, the soft-decision information generating section 230, the decoding section 240a, and the output information generating section 290 included in the error correction device 200a of Embodiment 2 can be implemented by the processing circuit 903 in Embodiment 1. Figure 9A and Figure 9B The processor 901 and the memory 902 in the example hardware structure are shown to implement, or can also be implemented by, the processing circuit 903.

[0665] Referring to Figure 17A , Figure 17B and Figure 17C , the operation of the error correction device 200a of Embodiment 2 will be described

[0666] Figure 17A is a part of a flowchart showing an example of the processing of the error correction device 200a of Embodiment 2.

[0667] Figure 17B is another part of the flowchart showing an example of the processing of the error correction device 200a of Embodiment 2.

[0668] Figure 17C is the remaining part of the flowchart showing an example of the processing of the error correction device 200a of Embodiment 2.

[0669] Hereinafter, Embodiments 1 and 2 will be described together as Figure 17A , Figure 17B and Figure 17C will be described together as FIG. 17.

[0670] The error correction device 200a repeatedly performs the processing of the flowchart shown in FIG. 17.

[0671] Further, the flowchart shown in FIG. 17 is obtained by changing the step ST1030 in the flowchart shown in FIG. 10 to the step ST1730.

[0672] Further, as an example, the flowchart shown in Fig. 17 illustrates an action in a case where the hard-decision error correction decoding section 247 performs hard-decision error correction processing on the information in the 1st received MSB information corresponding to the 2nd output bit array information, and the 1st received SSB information, the 2nd received SSB information, the 2nd received LSB information, and the 1st received LSB information, based on the information stored in the received hard-decision parity check region in the 1st received MSB information.

[0673] In Fig. 17, the same reference numerals are annotated for the same processing as the processing of the flowchart shown in Fig. 10, and the explanation is omitted.

[0674] First, the error correction device 200a performs the processing of the steps ST1000 to ST1020.

[0675] After the step ST1020, in the step ST1730, the decoding section 240a generates the output information by performing the multi-stage error correction processing.

[0676] Specifically, the decoding section 240a performs the processing of the step ST1730 by performing the processing of the steps ST1031 to ST1036 and the processing of the step ST1731 in the following processing J.

[0677] The decoding section 240a performs the processing of the steps ST1031 to ST1033.

[0678] After the step ST1033, in the step ST1731, the hard-decision error correction decoding section 247 possessed by the decoding section 240a performs the hard-decision error correction processing.

[0679] After the step ST1731, the decoding section 240a performs the processing of the steps ST1034 to ST1036.

[0680] After the step ST1036, the decoding section 240a ends the processing J. That is, after the step ST1036, the decoding section 240a ends the processing of the step ST1730.

[0681] After the step ST1730, the error correction device 200a performs the processing of the step ST1050.

[0682] After the step ST1050, the error correction device 200a ends the processing of the flowchart shown in Fig. 17, and the error correction device 200a returns to the processing of the step ST1000 to repeat the processing of the flowchart shown in Fig. 17.

[0683] As described above, the error correction encoding device 100a is configured to include: an input information acquisition section 110 that acquires input information;

[0684] a coding section 120a that generates soft decision error correction frame information composed of a bit array of m rows and N columns by combining first bit string group information composed of a bit array of m rows and Nl columns, which can be pulse amplitude modulated into modulation symbols using a first symbol mapping rule decided in advance, with second bit string group information composed of a bit array of m rows and N2 columns, which can be pulse amplitude modulated into modulation symbols using a second symbol mapping rule decided in advance, based on the input information acquired by the input information acquisition section 110;

[0685] a modulation symbol conversion section 130 that pulse amplitude modulates the combination of the bit values of each column of the soft decision error correction frame information generated by the coding section 120a into modulation symbols according to each column of the soft decision error correction frame information using the first symbol mapping rule or the second symbol mapping rule, thereby generating modulation symbol group information composed of N modulation symbols; and

[0686] a transmission waveform shaping section 140 that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion section 130 and outputs the generated digital baseband modulation signal,

[0687] The coding section 120a generates the soft decision error correction frame information by the following processes:

[0688] generates first input bit array information composed of a bit array of m-1 rows and N columns and second input bit array information composed of a bit array of 1 row and N3 columns based on the input information acquired by the input information acquisition section 110, and stores the generated second input bit array information as a part of first MSB information composed of a bit array of 1 row and Nl columns in a predetermined region of the first row in the first bit string group information,

[0689] generates shaped bit array information composed of a bit array of m-1 rows and N columns by performing a probability distribution shaping coding process on the generated first input bit array information,

[0690] generates first group bit array information composed of a combination of Nl predetermined columns and second group bit array information composed of a combination of N2 predetermined columns by separating the generated shaped bit array information,

[0691] generates first LSB information composed of a bit array of 1 row and Nl columns by extracting a bit array of the m-1th row in the first group bit array information from the generated first group bit array information,

[0692] The bit values ​​of each column in the generated 1LSB information are XORed with the bit values ​​of each column in the information of the 1st row of the 1st bit string group information after storing the 2nd input bit array information, thereby generating the inverted 1LSB information consisting of a 1-row N1-column bit array, and storing the generated inverted 1LSB information in the mth row of the 1st bit string group information.

[0693] The second LSB information consisting of a 1-row N2-column bit array is generated by extracting the m-1-th row bit array from the generated second group of bit array information, and the generated second LSB information is stored in the m-th row of the second bit string group information.

[0694] Soft decision parity bits are generated by performing a systematic soft decision error correction coding process using the generated inverted first LSB information and the generated second LSB information. The generated soft decision parity bits are stored in the first row of the second bit string group information as the second MSB information consisting of a 1-row N2-column bit array.

[0695] When m is greater than or equal to 3, the first SSB information consisting of a bit array of m-2 rows and N1 columns is generated by extracting the first to m-2 rows of the first group of bit array information from the generated first group of bit array information, and the generated first SSB information is stored in the second to m-1 rows of the first bit string group information.

[0696] When m is greater than 3, the second SSB information consisting of a bit array of m-2 rows and N2 columns is generated by extracting the first row to the m-2th row in the second group of bit array information generated, and the generated second SSB information is stored in the second row to the m-1th row in the second bit string group information.

[0697] In addition, the error correction coding device 100a is constructed on the basis of the above-mentioned structure, such that the coding unit 120a uses the first input bit array information and the second input bit array information, or uses the first input bit array information, as well as the first SSB information, the second SSB information, the second LSB information and the first LSB information or the inverted 1 LSB information, to perform systematic hard decision error correction coding processing, thereby generating hard decision parity bits, and storing the generated hard decision parity bits as part of the 1st MSB information in a predetermined area of ​​the first row in the first bit string group information that is different from the area for storing the second input bit array information.

[0698] By being so configured, the error correction encoding device 100a can reduce the number of bits that are to be protected by the soft-decision error correction, as compared with the conventional soft-decision error correction encoding processing. Therefore, the error correction encoding device 100a can reduce the amount of computation of the soft-decision error correction encoding processing, as compared with the conventional soft-decision error correction encoding processing.

[0699] Further, by being so configured, in the error correction encoding device 100a, even if the number of bits of the pulse amplitude modulation changes, the number of bits that are to be protected by the soft-decision error correction can be fixed. Therefore, the error correction encoding device 100a can fix the amount of computation of the soft-decision error correction encoding processing in the pulse amplitude modulation of an arbitrary number of bits. Therefore, the error correction encoding device 100a does not need to change the program or the processing circuit for performing the soft-decision error correction encoding processing, in accordance with each number of bits of the pulse amplitude modulation.

[0700] Further, by being so configured, in the error correction device 200a, the error correction based on the hard-decision error correction processing can be performed, and therefore, in the error correction encoding device 100a, the output information in which the residual errors are less can be output from the error correction device 200a, as compared with the case where the hard-decision error correction processing is not performed.

[0701] Further, the hard-decision error correction encoding section 125 included in the encoding section 120a can perform the systematic hard-decision error correction encoding processing based on the second input bit array information stored in the second input bit region, the second MSB information stored in Dv[1][2], the first SSB information stored in Dv[2:m][1:2], the second SSB information, the inverted first LSB information, and the second LSB information, after the soft-decision error correction encoding section 124 performs the systematic soft-decision error correction encoding processing to generate the soft-decision parity bits, i.e., the second MSB information, and stores the second MSB information in the bit array space of the first row in the second bit string group information, i.e., Dv[1][2].

[0702] By being so configured, the error correction encoding device 100a can reduce the burst errors of the second received MSB information that corresponds to the soft-decision parity bits that are the second MSB information, at the time of the soft-decision error correction decoding processing in the error correction device 200a.

[0703] Further, as described above, the error correction device 200a is configured to include: a received modulation symbol group information generation section 210 that receives a signal based on the soft-decision error correction frame information generated by the error correction encoding device 100a, i.e., a received digital baseband modulation signal, and generates received modulation symbol group information composed of N received modulation symbols based on the received digital baseband modulation signal;

[0704] a hard decision candidate generation section 220 that generates first hard decision candidate bit array information composed of a bit array of 1 row and N1 columns, second hard decision candidate bit array information composed of a bit array of m-2 rows and N1 columns in a case where m is 3 or more, and third hard decision candidate bit array information composed of a bit array of m-2 rows and N2 columns in a case where m is 3 or more, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210, using the first symbol mapping rule or the second symbol mapping rule;

[0705] a soft decision information generation section 230 that generates first posterior L value sequence composed of N2 posterior L values corresponding to each column of the first row of the second bit string group information, second posterior L value sequence composed of N1 posterior L values corresponding to each column of the m-th row of the first bit string group information, and third posterior L value sequence composed of N2 posterior L values corresponding to each column of the m-th row of the second bit string group information, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210;

[0706] a decoding section 240a that performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation section 220, and the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence generated by the soft decision information generation section 230; and

[0707] an information output section 290 that outputs information generated by the decoding section 240a as output information,

[0708] In the first decoding processing of the multi-stage error correction processing, the decoding section 240a generates first reception LSB information after inversion composed of a bit array of 1 row and N1 columns corresponding to the inverted first LSB information, and second reception LSB information composed of a bit array of 1 row and N2 columns corresponding to the second LSB information, by performing soft decision error correction processing based on the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence,

[0709] In the second decoding process of the multi-stage error correction processing, the decoding section 240a generates first received MSB information corresponding to the first MSB information, which is constituted by a bit array of 1 row and Nl columns, based on the first hard-decision candidate bit array information and the inverted first received LSB information, generates first received SSB information corresponding to the first SSB information, which is constituted by a bit array of m-2 rows and Nl columns, based on the second hard-decision candidate bit array information and the inverted first received LSB information in the case where m is 3 or more, and generates second received SSB information corresponding to the second SSB information, which is constituted by a bit array of m-2 rows and N2 columns, based on the third hard-decision candidate bit array information and the second received LSB information in the case where m is 3 or more,

[0710] In the third decoding process of the multi-stage error correction processing, the decoding section 240a generates first received LSB information corresponding to the first LSB information by operating the bit values of each column in the inverted first received LSB information with the exclusive OR of the bit values of each column in the first received MSB information corresponding to each column in the inverted first received LSB information,

[0711] In the fourth decoding process of the multi-stage error correction processing, the decoding section 240a generates first output bit array information corresponding to the first input bit array information, which is constituted by a bit array of m-1 rows and N columns, by performing a probability distribution shaping decoding process on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information,

[0712] In the fifth decoding process of the multi-stage error correction processing, the decoding section 240a generates second output bit array information corresponding to the second input bit array information, which is constituted by a bit array of 1 row and N3 columns, by extracting information of a predetermined region in the first received MSB information,

[0713] In the sixth decoding process of the multi-stage error correction processing, the decoding section 240a generates output information corresponding to the input information based on the first output bit array information and the second output bit array information, and the information output section 290 outputs the output information generated by the decoding section 240a.

[0714] Further, the error correction device 200a is configured, on the basis of the above-described structure, such that the decoding section 240a performs, in the seventh decoding process of the multistage error correction processing, hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information or the inverted first received LSB information, or on the information corresponding to the second output bit array information in the first received MSB information and the first output bit array information, on the basis of the information stored in the predetermined region of the first received MSB information,

[0715] In a case where the decoding section 240a performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the inverted first received LSB information, the decoding section 240a performs, in the third decoding process, exclusive-OR operation using the inverted first received LSB information after the seventh decoding process and the first received MSB information, and generates the second output bit array information by extracting the information of the predetermined region of the first received MSB information after the seventh decoding process in the fifth decoding process,

[0716] In a case where the decoding section 240a performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information, the decoding section 240a performs, in the fourth decoding process, probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information after the seventh decoding process, and generates the second output bit array information by extracting the information of the predetermined region of the first received MSB information after the seventh decoding process in the fifth decoding process,

[0717] In a case where the decoding section 240a performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information and the first output bit array information, the decoding section 240a generates the second output bit array information by extracting the information of the predetermined region of the first received MSB information after the seventh decoding process in the fifth decoding process, and generates output information on the basis of the second output bit array information and the first output bit array information after the seventh decoding process in the sixth decoding process.

[0718] By being so configured, in the error correction device 200a, the number of bits that are to be protected by the soft-decision error correction can be reduced compared to the conventional soft-decision error correction encoding processing. Therefore, in the error correction device 200a, the amount of computation of the soft-decision error correction decoding processing can be reduced compared to the conventional soft-decision error correction decoding processing.

[0719] Further, by being so configured, in the error correction device 200a, the number of bits that are to be protected by the soft-decision error correction can be fixed even if the number of bits of the pulse amplitude modulation changes. Therefore, the error correction device 200a can fix the amount of computation of the soft-decision error correction decoding processing in the pulse amplitude modulation of an arbitrary number of bits. Therefore, the error correction device 200a does not need to change the program or the processing circuit for performing the soft-decision error correction decoding processing in accordance with each number of bits of the pulse amplitude modulation in the pulse amplitude modulation of a plurality of numbers of bits.

[0720] Further, by being so configured, the error correction device 200a can perform error correction based on the hard-decision error correction processing, and thus can output output information in which the number of residual errors is small compared to the case where the hard-decision error correction processing is not performed.

[0721] Variation of Embodiment 2

[0722] The variation of Embodiment 2 is particularly effective in a case where the input information includes information equivalent to the first input bit array information and the information is information of which the number of bits does not satisfy N3, or in a case where the input information does not include information equivalent to the first input bit array information or the second input bit array information.

[0723] Hereinafter, a case where the input information includes the first input bit array information composed of m-1 rows and N columns and information equivalent to the second input bit array information composed of N5 (N5 is an integer of 0 or more and smaller than N3) bits will be described.

[0724] Reference Signs Figure 35 The structure of the main part of the communication system Id of the variation of Embodiment 2 will be described.

[0725] Figure 35 is a structural diagram illustrating an example of the structure of the main part of the communication system Id of the variation of Embodiment 2.

[0726] In the variation of Embodiment 2, as an example, a case where the communication system Id is an optical communication system will be described, but the optical communication system is only an example, and the communication system Id is not limited to the optical communication system. For example, the communication system Id can also be a communication system based on wireless communication or metal communication, or the like.

[0727] The communication system Id has a transmission device 10d, a transmission path 30, and a reception device 20d.

[0728] The communication system Id is obtained by changing the transmission device 10a and the reception device 20a of Embodiment 2 to the transmission device 10d and the reception device 20d.

[0729] In Figure 35 , the same reference numerals are labeled to the same blocks as those shown in FIG. 1 and the explanation is omitted. Figure 11

[0730] The transmission device 10d acquires input information and outputs a signal based on the acquired input information. Since Figure 35 The communication system Id shown in FIG. 1 is an optical communication system, therefore, Figure 35 The transmission device 10d shown in FIG. 1 is an optical transmission device which outputs an optical signal.

[0731] The transmission device 10d has an error correction encoding device 100d, a D / A converter 11, a transmission light source 12, and an optical modulator 13.

[0732] The transmission device 10d is obtained by changing the error correction encoding device 100a of Embodiment 2 to the error correction encoding device 100d.

[0733] The error correction encoding device 100d acquires input information inputted from the outside and generates a digital baseband modulation signal based on the acquired input information. The error correction encoding device 100d outputs the generated digital baseband modulation signal to the D / A converter 11.

[0734] The reception device 20d receives a signal outputted by the transmission device 10d via the transmission path 30, generates output information corresponding to the input information based on the signal, and outputs the generated output information. Since Figure 35 The communication system Id shown in FIG. 1 is an optical communication system, therefore, Figure 35 The reception device 20d shown in FIG. 1 is an optical reception device which receives an optical signal.

[0735] The reception device 20d has a reception light source 22, an optical receiver 21, an A / D converter 23, and an error correction device 200d.

[0736] The reception device 20d is obtained by changing the error correction device 200a of Embodiment 2 to the error correction device 200d.

[0737] The error correction device 200d receives a reception digital baseband modulation signal outputted by the A / D converter 23, generates output information corresponding to the input information based on the reception digital baseband modulation signal, and outputs the generated output information.

[0738] Reference is made to Figure 36 ​The structure of the main part of the error correction encoding device 100d of the modification of Embodiment 2 will be described.

[0739] Figure 36 Fig. 17 is a structure diagram showing an example of the structure of the main part of the error correction encoding device 100d of the modification of Embodiment 2.

[0740] The error correction encoding device 100d includes an input information acquisition section 110, an encoding section 120d, a modulation symbol conversion section 130, and a transmission waveform shaping section 140.

[0741] The error correction encoding device 100d is obtained by changing the encoding section 120a of Embodiment 2 to the encoding section 120d.

[0742] In Figure 36 , the same reference numerals are labeled to the same blocks as those shown in Figure 12 , and the description is omitted.

[0743] The encoding section 120d generates soft-decision error correction frame information in which the first bit string group information and the second bit string group information are combined, on the basis of the input information acquired by the input information acquisition section 110.

[0744] Referring to Figure 37 , the structure of the main part of the encoding section 120d of the modification of Embodiment 2 will be described.

[0745] Figure 37 Fig. 18 is a structure diagram showing an example of the structure of the main part of the encoding section 120d of the modification of Embodiment 2.

[0746] The encoding section 120d includes an input bit array information generation section 121d, a probability distribution shaping encoding section 122, a bit inversion section 123, a soft-decision error correction encoding section 124, and a hard-decision error correction encoding section 125d.

[0747] The encoding section 120d is obtained by changing the input bit array information generation section 121 and the hard-decision error correction encoding section 125 of Embodiment 2 to the input bit array information generation section 121d and the hard-decision error correction encoding section 125d.

[0748] In Figure 37 , the same reference numerals are labeled to the same blocks as those shown in Figure 13 , and the description is omitted.

[0749] The input bit array information generation section 121d generates the first input bit array information composed of an m-1 row by N column bit array and the second input bit array information composed of a 1 row by N3 column bit array, on the basis of the input information acquired by the input information acquisition section 110.

[0750] Specifically, for example, the input bit array information generating section 121d generates the 1st input bit array information by extracting the 1st input bit array information consisting of m-1 rows and N columns included in the input information.

[0751] Further, when the input bit array information generating section 121d generates the 2nd input bit array information based on the input information acquired by the input information acquiring section 110, the input bit array information generating section 121d sets the bit values of the bits other than the bits corresponding to the input information in the 2nd input bit array information to the values decided in advance, thereby generating the 2nd input bit array information.

[0752] More specifically, for example, the input bit array information generating section 121d extracts the information equivalent to the 2nd input bit array information consisting of N5 number of bits included in the input information, sets a part of the 2nd input bit array information to the information, and sets the remaining part of the 2nd input bit array information to the values decided in advance, thereby generating the 2nd input bit array information.

[0753] The value applied to the remaining part of the 2nd input bit array information is, for example, "0". The value can also be "1". Further, if it is an array of values decided in advance, it can also be an array in which "0" or "1" is used for each column in the remaining part of the 2nd input bit array information.

[0754] The input bit array information generating section 121d stores the generated 2nd input bit array information as a part of the 1st MSB information consisting of 1 row and N1 columns in the 2nd input bit region.

[0755] Specifically, the input bit array information generating section 121d stores the 2nd input bit array information in the 2nd input bit region in D[1][1] as a bit array space in which the 1st MSB is stored. Hereinafter, a case where the 2nd input bit region is D[1][1][1:N3] will be described.

[0756] In particular, in the modified example of Embodiment 2, a case where the information consisting of N5 number of bits extracted by the input bit array information generating section 121d from the input information is stored in D[1][1][1:N5] in D[1][1][1:N3] as the 2nd input bit region will be described. Further, a case where the remaining part of the 2nd input bit array information set to the values decided in advance in order for the input bit array information generating section 121d to generate the 2nd input bit array information is stored in D[1][1][N5+1:N3] in D[1][1][1:N3] as the 2nd input bit region will be described. That is, the values decided in advance such as "0" or "1" are stored in D[1][1][N5+1:N3].

[0757] The hard-decision error correction encoding section 125d performs a hard-decision error correction encoding process of the system using the first input bit array information generated by the input bit array information generating section 121d and the second input bit array information generated by the input bit array information generating section 121d.

[0758] The hard-decision error correction encoding section 125d performs the following process as a pre-process when performing the hard-decision error correction encoding process of the system.

[0759] As the first pre-process, the hard-decision error correction encoding section 125d exchanges the bit values of the columns corresponding to each other between the bit value of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information in which the second input bit array information is stored as a part of the first MSB information and the bit value of the region in which the first LSB information is stored in the column of the m-th row of the first bit string group information corresponding to each column of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information.

[0760] As the second pre-process, the hard-decision error correction encoding section 125d calculates the XOR of each column corresponding to each other between the bit value after the bit value of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information is exchanged and the bit value after the bit value of the region in which the first LSB information is stored in the column of the m-th row of the first bit string group information corresponding to each column of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information is exchanged.

[0761] As the third pre-process, the hard-decision error correction encoding section 125d rewrites the bit value after the bit value of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information using the calculation result of the XOR of the corresponding column.

[0762] Specifically, as the first pre-process, first, the hard-decision error correction encoding section 125d exchanges the values of the columns corresponding to each other between B[l][l][N5+l:N3] which is the bit value of D[l][l][N5+l:N3] and B[m][l][N5+l:N3] which is the bit value of D[m][l][N5+l:N3].

[0763] Next, as the second pre-process, the hard-decision error correction encoding section 125d calculates the XOR of each column corresponding to each other between B[l][l][N5+l:N3] after the values are exchanged and B[m][l][N5+l:N3] after the values are exchanged.

[0764] Next, as the third preprocessing, the hard-decision error correction encoding section 125d rewrites the value of B[l][l][N5+l:N3] after the values are exchanged using the operation result of the exclusive OR of the corresponding columns.

[0765] The hard-decision error correction encoding section 125d performs the system hard-decision error correction encoding process after the above-described preprocessing, thereby generating hard-decision parity bits. The generated hard-decision parity bits are stored in the hard-decision parity region as a part of the first MSB information.

[0766] Specifically, the hard-decision error correction encoding section 125d stores the generated hard-decision parity bits in the hard-decision parity region in Dv[l][l] which is a bit array space storing the first MSB. Hereinafter, a case where the hard-decision parity region is D[l][l][N3+l:Nl] will be described.

[0767] In addition, each function of the input information acquisition section 110, the encoding section 120d, the modulation symbol conversion section 130, and the transmission waveform shaping section 140 included in the error correction encoding apparatus 100d of the modification example of Embodiment 2 can be implemented by the processing circuit 503 in Embodiment 2. Figure 5A and Figure 5B The processor 501 and the memory 502 in the example hardware structure are shown to be implemented, or can also be implemented by the processing circuit 503.

[0768] Referring to Figure 38A , Figure 38B and Figure 38C , the operation of the error correction encoding apparatus 100d of the modification example of Embodiment 2 will be described.

[0769] Figure 38A is a part of a flowchart showing an example of the process of the error correction encoding apparatus 100d of the modification example of Embodiment 2

[0770] Figure 38B is another part of a flowchart showing an example of the process of the error correction encoding apparatus 100d of the modification example of Embodiment 2.

[0771] Figure 38C is the remaining part of a flowchart showing an example of the process of the error correction encoding apparatus 100d of the modification example of Embodiment 2.

[0772] Hereinafter, Figure 38A , Figure 38B and Figure 38C will be collectively referred to as FIG. 38.

[0773] The error correction encoding apparatus 100d repeatedly performs the process of the flowchart shown in FIG. 38.

[0774] Further, the flowchart shown in Fig. 38 is obtained by changing the step ST1410 in the flowchart shown in Fig. 14 to the step ST3810.

[0775] In Fig. 38, the same reference numerals are given to the same processes as those of the flowchart shown in Fig. 14, and the explanation is omitted.

[0776] First, the error correction encoding device 100d performs the process of the step ST601.

[0777] Next, in the step ST3810, the encoding section 120d generates the soft-decision error correction frame information.

[0778] Specifically, the encoding section 120d performs the process of the step ST3810 by performing the processes of the steps ST612 to ST618, the processes of the steps ST1411 to ST1412, the process of the step ST3811, and the processes of the steps ST3815 to ST3817 in the following process O.

[0779] First, in the step ST3811, the input bit array information generating section 121d possessed by the encoding section 120d generates the 1st input bit array information and the 2nd input bit array information.

[0780] After the step ST3811, the encoding section 120d performs the processes of the steps ST612 to ST614.

[0781] After the step ST614, in the step ST3815, the hard-decision error correction encoding section 125d possessed by the encoding section 120d exchanges the value of B[l][l][N5+l:N3] and the value of B[m][l][N5+l:N3].

[0782] After the step ST3815, in the step ST3816, the hard-decision error correction encoding section 125d possessed by the encoding section 120d operates the exclusive OR of B[l][l][N5+l:N3] and B[m][l][N5+l:N3].

[0783] After the step ST3816, in the step ST3817, the hard-decision error correction encoding section 125d possessed by the encoding section 120d rewrites the value of B[l][l][N5+l:N3] using the operation result of the exclusive OR.

[0784] After the step ST3817, the encoding section 120d performs the processes of the steps ST1411 to ST1412.

[0785] After the step ST1412, the encoding section 120d performs the processes of the steps ST615 to ST618.

[0786] After the step ST618, the encoding section 120d ends the process O. That is, after the step ST618, the encoding section 120d ends the process of the step ST3810.

[0787] After the step ST3810, the error correction encoding apparatus 100d performs the process of the steps ST620 to ST630.

[0788] After the step ST630, the error correction encoding apparatus 100d ends the process of the flowchart shown in Fig. 38, and returns to the process of the step ST601, and repeatedly performs the process of the flowchart shown in Fig. 38.

[0789] Reference Figure 39 The structure of the main part of the error correction apparatus 200d of the modification example of Embodiment 2 will be described.

[0790] Figure 39 is a structural diagram showing an example of the structure of the main part of the error correction apparatus 200d of the modification example of Embodiment 2.

[0791] The error correction apparatus 200d includes a reception modulation symbol group information generating section 210, a hard decision candidate generating section 220, a soft decision information generating section 230, a decoding section 240d, and an information output section 290.

[0792] The error correction apparatus 200d is obtained by changing the decoding section 240a of Embodiment 2 to the decoding section 240d.

[0793] In Figure 39 , the same reference numerals are labeled to the same blocks as those shown in Fig. 38, and the description is omitted. Figure 15

[0794] The decoding section 240d performs a multi-stage error correction process based on the 1st hard decision candidate bit array information, the 2nd hard decision candidate bit array information, and the 3rd hard decision candidate bit array information generated by the hard decision candidate generating section 220, and the 1st posterior L value sequence, the 2nd posterior L value sequence, and the 3rd posterior L value sequence generated by the soft decision information generating section 230, and thereby generates output information.

[0795] Reference Figure 40 The structure of the main part of the decoding section 240d of the modification example of Embodiment 2 will be described.

[0796] Figure 40 is a structural diagram showing an example of the structure of the main part of the decoding section 240d of the modification example of Embodiment 2.

[0797] ​The decoding section 240d includes a soft decision error correction decoding section 241, a selection section 242, a received side bit inversion section 243, a probability distribution shaping decoding section 244, a second output bit array generating section 245d, an output information generating section 246, and a hard decision error correction decoding section 247d.

[0798] The decoding section 240d is obtained by changing the second output bit array generating section 245 and the hard decision error correction decoding section 247 of Embodiment 2 to the second output bit array generating section 245d and the hard decision error correction decoding section 247d.

[0799] In Figure 40 , the same reference numerals are labeled to the same blocks as those shown in the blocks, and the description is omitted. Figure 16 The hard decision error correction decoding section 247d performs the seventh decoding process in the multistage error correction processing.

[0800] The hard decision error correction decoding section 247d performs a hard decision error correction process on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the inverted first received LSB information, on the basis of the information stored in the predetermined received hard decision parity check region corresponding to the hard decision parity check region in the first MSB information, which is predetermined in the first received MSB information.

[0801] The hard decision error correction decoding section 247d performs the following process as a post-process in the seventh decoding process in the multistage error correction processing after the hard decision error correction process.

[0802] First, as the first post-process, the hard decision error correction decoding section 247d calculates the exclusive OR of each column corresponding to each other between the bit value of the column in the first received MSB information and the bit value of the column in the first received LSB information, which correspond to each column of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information in which the second input bit array information is stored as a part of the first MSB information.

[0803] Next, as the second post-process, the hard decision error correction decoding section 247d rewrites the bit value of the column in the first received MSB information corresponding to each column of the region in which the predetermined value is stored in the predetermined region of the first row of the first bit string group information, using the calculation result of the exclusive OR in the corresponding column.

[0804]

[0805] ​Specifically, first, as the first post-processing, the hard-decision error correction decoding section 247d calculates the exclusive OR of each column corresponding to each other between the values of the N5+1th column to the N3th column in the first received MSB information and the bit values of D[1][1][N5+1:N3], that is, B[1][1][N5+1:N3] corresponding to the bit array space storing the first LSB information. The hard-decision error correction decoding section 247d can also calculate the exclusive OR of each column corresponding to each other between the values of the N5+1th column to the N3th column in the first received MSB information and the N3-N5 fixed values stored in D[1][1][N5+1:N3] when the second input bit array information is generated by the input bit array information generating section 121d provided in the encoding section 120d of the error correction encoding apparatus 100d, instead of the values of the N5+1th column to the N3th column in the first received LSB information. Hereinafter, a case where, as the first post-processing, the hard-decision error correction decoding section 247d calculates the exclusive OR of each column corresponding to each other between the values of the N5+1th column to the N3th column in the first received MSB information and the values of the N5+1th column to the N3th column in the first received LSB information will be described.

[0806] Next, as the second post-processing, the hard-decision error correction decoding section 247d rewrites the values of the N5+1th column to the N3th column in the first received LSB information using the calculation result of the exclusive OR in the corresponding column.

[0807] The second output bit array generating section 245d performs the fifth decoding process in the multi-stage error correction processing.

[0808] Specifically, the second output bit array generating section 245d extracts the information of the region corresponding to the region in which the error correction encoding apparatus 100d stores the first MSB information, from the first received MSB information, thereby generating the second output bit array information of one row and N5 columns of bit arrays corresponding to the information of N5 bits included in the input information.

[0809] More specifically, for example, the second output bit array generating section 245d extracts the bit values of the first column to the N5th column in the region in which the error correction encoding apparatus 100d stores the first MSB information, thereby generating the second output bit array information.

[0810] The error correction device 200d performs error correction based on hard-decision error correction processing, and can obtain output information with fewer residual errors than in the case where hard-decision error correction processing is not performed.

[0811] In particular, the error correction device 200d performs multi-stage error correction processing based on the signal of the soft-decision error correction frame information generated by the error correction encoding device 100d described above, i.e., the received digital baseband modulation signal, and thus can perform error correction with higher performance than in the error correction performed by the error correction device 200a of Embodiment 2.

[0812] In addition, each function of the reception modulation symbol group information generation section 210, the hard-decision candidate generation section 220, the soft-decision information generation section 230, the decoding section 240d, and the information output section 290 included in the error correction device 200d of the modification example of Embodiment 2 can be implemented by the processing circuit 903 in Embodiment 2. Figure 9A and Figure 9B The processor 901 and the memory 902 in the example hardware structure are shown as being implemented, or can also be implemented by the processing circuit 903.

[0813] The operation of the error correction device 200d of the modification example of Embodiment 2 will be described with reference to Figure 41A , Figure 41B and Figure 41C .

[0814] Figure 41A is a part of a flowchart showing an example of the processing of the error correction device 200d of the modification example of Embodiment 2.

[0815] Figure 41B is another part of a flowchart showing an example of the processing of the error correction device 200d of the modification example of Embodiment 2.

[0816] Figure 41C is the remaining part of a flowchart showing an example of the processing of the error correction device 200d of the modification example of Embodiment 2.

[0817] Hereinafter, Figure 41A , Figure 41B and Figure 41C will be collectively referred to as FIG. 41.

[0818] The error correction device 200d repeatedly performs the processing of the flowchart shown in FIG. 41.

[0819] In addition, the flowchart shown in FIG. 41 is obtained by changing the step ST1730 in the flowchart shown in FIG. 17 to the step ST4130.

[0820] In FIG. 41, the same reference numerals are attached to the same processing as the processing of the flowchart shown in FIG. 17, and the description is omitted.

[0821] First, the error correction device 200d performs the processing of steps ST1000 to ST1020.

[0822] After step ST1020, in step ST4130, the decoding section 240d generates output information by performing a multi-stage error correction process.

[0823] Specifically, the decoding section 240d performs the processing of step ST4130 in the following processing P by performing the processing of steps ST1031 to ST1034 and step ST1036, the processing of step ST1731, and the processing of steps ST4132 to ST4133 and step ST4135.

[0824] More specifically, first, the decoding section 240d performs the processing of steps ST1031 to ST1033.

[0825] After step ST1033, the decoding section 240d performs the processing of step ST1731.

[0826] After step ST1731, in step ST4132, the hard decision error correction decoding section 247d possessed by the decoding section 240d calculates the exclusive OR of the values of the N5+1th column to the N3th column in the 1st received MSB information and the values of the N5+1th column to the N3th column in the 1st received LSB information.

[0827] After step ST4132, in step ST4133, the hard decision error correction decoding section 247d possessed by the decoding section 240d rewrites the values of the N5+1th column to the N3th column in the 1st received LSB information using the calculation result of the exclusive OR in the corresponding column.

[0828] After step ST4133, the decoding section 240d performs the processing of step ST1034.

[0829] After step ST1034, in step ST4135, the 2nd output bit array generating section 245d possessed by the decoding section 240d generates 2nd output bit array information composed of a bit array of 1 row and N5 columns.

[0830] After step ST4135, the decoding section 240d performs the processing of step ST1036.

[0831] After step ST1036, the decoding section 240d ends the processing P. That is, after step ST1036, the decoding section 240d ends the processing of step ST4130.

[0832] After step ST4130, the error correction device 200d performs the processing of step ST1050.

[0833] After the step ST1050, the error correction device 200d ends the processing of the flowchart shown in Fig. 41, and returns to the processing of the step ST1000 to repeat the processing of the flowchart shown in Fig. 41.

[0834] As above, the error correction encoding device 100d is configured to include: an input information acquisition section 110 that acquires input information;

[0835] an encoding section 120d that generates soft decision error correction frame information composed of an m-row by N-column bit array in which a first bit string group information composed of an m-row by Nl-column bit array and a second bit string group information composed of an m-row by N2-column bit array are combined, based on the input information acquired by the input information acquisition section 110, the first bit string group information being able to be pulse amplitude-modulated into modulation symbols by using a first symbol mapping rule with respect to a combination of bit values of each column of the first bit string group information, the second bit string group information being able to be pulse amplitude-modulated into modulation symbols by using a second symbol mapping rule with respect to a combination of bit values of each column of the second bit string group information;

[0836] a modulation symbol conversion section 130 that pulse amplitude-modulates a combination of bit values of each column of the soft decision error correction frame information generated by the encoding section 120d into modulation symbols by using the first symbol mapping rule or the second symbol mapping rule with respect to each column of the soft decision error correction frame information, thereby generating modulation symbol group information composed of N modulation symbols; and

[0837] a transmission waveform shaping section 140 that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion section 130, and outputs the generated digital baseband modulation signal,

[0838] The encoding section 120d generates the soft decision error correction frame information by the following processing:

[0839] generates first input bit array information composed of an m-1-row by N-column bit array and second input bit array information composed of a 1-row by N3-column bit array, based on the input information acquired by the input information acquisition section 110,

[0840] stores the generated second input bit array information as a part of the first MSB information composed of a 1-row by Nl-column bit array in a predetermined region of the first row in the first bit string group information,

[0841] generates shaped bit array information composed of an m-1-row by N-column bit array by performing a probability distribution shaping coding process on the generated first input bit array information,

[0842] The generated reshaped bit array information is separated to generate first group bit array information composed of combinations of Nl predetermined columns and second group bit array information composed of combinations of N2 predetermined columns,

[0843] The first LSB information composed of one row of Nl columns of bit arrays is generated by extracting the bit array of the m-1th row of the first group bit array information from the generated first group bit array information,

[0844] The post-inversion first LSB information is generated by operating the XOR of the bit values of each column in the generated first LSB information and the bit values of each column in the information of the first row of the first bit string group information after storing the second input bit array information, and the generated post-inversion first LSB information is stored in the mth row of the first bit string group information,

[0845] The second LSB information composed of one row of N2 columns of bit arrays is generated by extracting the bit array of the m-1th row of the second group bit array information from the generated second group bit array information, and the generated second LSB information is stored in the mth row of the second bit string group information,

[0846] The soft decision parity bits are generated by performing a soft decision error correction encoding process of the system using the generated post-inversion first LSB information and the generated second LSB information, and the generated soft decision parity bits are stored as the second MSB information composed of one row of N2 columns of bit arrays in the first row of the second bit string group information,

[0847] In the case where m is 3 or more, the first SSB information composed of m-2 rows of Nl columns of bit arrays is generated by extracting the first to m-2th rows of the first group bit array information from the generated first group bit array information, and the generated first SSB information is stored in the second to m-1th rows of the first bit string group information,

[0848] In the case where m is 3 or more, the second SSB information composed of m-2 rows of N2 columns of bit arrays is generated by extracting the first to m-2th rows of the second group bit array information from the generated second group bit array information, and the generated second SSB information is stored in the second to m-1th rows of the second bit string group information.

[0849] Further, the error correction coding device 100d is configured, on the basis of the above-described structure, such that the encoding section 120d generates the hard-decision parity bits using the first input bit array information and the second input bit array information, or using the first input bit array information and the first SSB information, the second SSB information, the second LSB information, and the first LSB information or the inverted first LSB information, and stores the generated hard-decision parity bits as a part of the first MSB information in a predetermined region of the first bit string group information different from the region in which the second input bit array information is stored in the first row.

[0850] Further, the error correction coding device 100d is configured, on the basis of the above-described structure, such that the encoding section 120d generates the second input bit array information by setting bit values of bits other than bits corresponding to the input information to predetermined values in the second input bit array information on the basis of the input information acquired by the input information acquisition section 110.

[0851] The encoding section 120d generates the hard-decision parity bits using the first input bit array information and the second input bit array information, or using the first input bit array information and the first SSB information, the second SSB information, the second LSB information, and the first LSB information or the inverted first LSB information.

[0852] As the first preprocessing, the bit values of the regions in which the predetermined values are stored in the predetermined region of the first row of the first bit string group information in which the second input bit array information is stored as a part of the first MSB information and the bit values of the columns corresponding to the regions in which the predetermined values are stored in the predetermined region of the first row of the first bit string group information are exchanged with each other,

[0853] As the second preprocessing, exclusive ORs of each column corresponding to each other are calculated between the bit values after the bit values of the regions in which the predetermined values are stored in the predetermined region of the first row of the first bit string group information are exchanged and the bit values after the bit values of the columns corresponding to the regions in which the predetermined values are stored in the predetermined region of the first row of the first bit string group information are exchanged.

[0854] As the third preprocessing, the bit values after the bit values of the regions in which the predetermined values are stored in the predetermined region of the first row of the first bit string group information are rewritten using the calculation results of the exclusive ORs of the corresponding columns.

[0855] By being configured like this, in the error correction device 200d, compared with the error correction device 200a that performs error correction based on hard decision error correction processing, it is possible to perform error correction with higher performance, and therefore, the error correction encoding device 100d can cause the error correction device 200d to output output information with fewer residual errors, compared with the case where hard decision error correction processing is not performed.

[0856] Further, as above, the error correction device 200d is configured to include: a reception modulation symbol group information generation section 210 that receives a signal based on the soft decision error correction frame information generated by the error correction encoding device 100d, that is, a reception digital baseband modulation signal, and generates reception modulation symbol group information composed of N reception modulation symbols based on the reception digital baseband modulation signal;

[0857] a hard decision candidate generation section 220 that generates, based on the first symbol mapping rule or the second symbol mapping rule, first hard decision candidate bit array information composed of a bit array of one row and N1 columns, second hard decision candidate bit array information composed of a bit array of m-2 rows and N1 columns in the case where m is 3 or more, and third hard decision candidate bit array information composed of a bit array of m-2 rows and N2 columns in the case where m is 3 or more, using the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210;

[0858] a soft decision information generation section 230 that generates, based on the reception modulation symbol group information generated by the reception modulation symbol group information generation section 210, first posterior L value sequence composed of N2 posterior L values corresponding to each column of the first row of the second bit string group information, second posterior L value sequence composed of N1 posterior L values corresponding to each column of the m-th row of the first bit string group information, and third posterior L value sequence composed of N2 posterior L values corresponding to each column of the m-th row of the second bit string group information;

[0859] a decoding section 240d that performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation section 220, and the first posterior L value sequence, the second posterior L value sequence, and the third posterior L value sequence generated by the soft decision information generation section 230; and

[0860] an information output section 290 that outputs, as output information, information generated by the decoding section 240d performing multi-stage error correction processing,

[0861] In the first decoding process of the multi-stage error correction processing, the decoding section 240d performs soft decision error correction processing based on the first, second, and third post-inversion L value sequences, thereby generating the post-inversion first received LSB information corresponding to the first LSB information, which is constituted by a bit array of 1 row and N1 columns, and the second received LSB information corresponding to the second LSB information, which is constituted by a bit array of 1 row and N2 columns,

[0862] In the second decoding process of the multi-stage error correction processing, the decoding section 240d generates the first received MSB information corresponding to the first MSB information, which is constituted by a bit array of 1 row and N1 columns, based on the first hard decision candidate bit array information and the post-inversion first received LSB information, and generates the first received SSB information corresponding to the first SSB information, which is constituted by a bit array of m-2 rows and N1 columns, based on the second hard decision candidate bit array information and the post-inversion first received LSB information in the case where m is 3 or more, and generates the second received SSB information corresponding to the second SSB information, which is constituted by a bit array of m-2 rows and N2 columns, based on the third hard decision candidate bit array information and the second received LSB information in the case where m is 3 or more,

[0863] In the third decoding process of the multi-stage error correction processing, the decoding section 240d generates the first received LSB information corresponding to the first LSB information by operating the bit values of each column in the post-inversion first received LSB information with the exclusive OR of the bit values of each column in the first received MSB information corresponding to each column in the post-inversion first received LSB information,

[0864] In the fourth decoding process of the multi-stage error correction processing, the decoding section 240d performs probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information, thereby generating the first output bit array information corresponding to the first input bit array information, which is constituted by a bit array of m-1 rows and N columns,

[0865] In the fifth decoding process of the multi-stage error correction processing, the decoding section 240d generates the second output bit array information corresponding to the second input bit array information, which is constituted by a bit array of 1 row and N3 columns, by extracting the information of a predetermined region in the first received MSB information,

[0866] In the sixth decoding process of the multi-stage error correction processing, the decoding section 240d generates the output information corresponding to the input information based on the first output bit array information and the second output bit array information, and the information output section 290 outputs the output information generated by the decoding section 240d.

[0867] Further, the error correction device 200d is configured on the basis of the above-described structure such that the decoding section 240d performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information or the inverted first received LSB information, or on the information corresponding to the second output bit array information in the first received MSB information and the first output bit array information, in the seventh decoding processing of the multistage error correction processing, and

[0868] In a case where the decoding section 240d performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the inverted first received LSB information, the decoding section 240d performs exclusive-OR operation using the inverted first received LSB information after the seventh decoding processing and the first received MSB information in the third decoding processing, and generates the second output bit array information by extracting the information of the predetermined region in the first received MSB information after the seventh decoding processing in the fifth decoding processing,

[0869] In a case where the decoding section 240d performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information, and the first received SSB information, the second received SSB information, the second received LSB information, and the first received LSB information, the decoding section 240d performs probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received LSB information, and the second received LSB information after the seventh decoding processing in the fourth decoding processing, and generates the second output bit array information by extracting the information of the predetermined region in the first received MSB information after the seventh decoding processing in the fifth decoding processing,

[0870] In a case where the decoding section 240d performs hard-decision error correction processing on the information corresponding to the second output bit array information in the first received MSB information and the first output bit array information, the decoding section 240d generates the second output bit array information by extracting the information of the predetermined region in the first received MSB information after the seventh decoding processing in the fifth decoding processing, and generates output information based on the second output bit array information and the first output bit array information after the seventh decoding processing in the sixth decoding processing.

[0871] Further, the error correction device 200d is configured, on the basis of the above-described structure, such that the decoding section 240d, after performing the hard-decision error correction processing, in the 7th decoding processing of the multi-stage error correction processing, as a 1st post-processing, calculates the exclusive OR of each column of the 1st received MSB information corresponding to the bit values of the column of the 1st received MSB information stored in each column of the predetermined region of the 1st bit string group information of the 1st row in which the 2nd input bit array information is stored as a part of the 1st MSB information, and the bit values of the column of the 1st received LSB information corresponding to the bit values of the column of the 1st received LSB information stored in each column of the predetermined region of the 1st row of the 1st bit string group information in which the 2nd input bit array information is stored as a part of the 1st MSB information, and as a 2nd post-processing, overwrites the bit values of the column of the 1st received MSB information corresponding to each column of the predetermined region of the 1st row of the 1st bit string group information in which the predetermined value is stored, using the calculation result of the exclusive OR of the corresponding column.

[0872] By being configured as such, the error correction device 200d is capable of performing error correction with higher performance than the error correction device 200a of Embodiment 2 which performs error correction based on hard-decision error correction processing.

[0873] Embodiment 3.

[0874] Reference Figure 18 The structure of the main part of the communication system 1b of Embodiment 3 will be described.

[0875] Figure 18 is a structural diagram illustrating an example of the structure of the main part of the communication system 1b of Embodiment 3.

[0876] In Embodiment 3, as an example, the case where the communication system 1b is an optical communication system will be described, but the optical communication system is only an example, and the communication system 1b is not limited to the optical communication system. For example, the communication system 1b can also be a communication system based on wireless communication or metal communication, or the like.

[0877] The communication system 1b has a transmission device 10b, a transmission path 30, and a reception device 20b.

[0878] The communication system 1b is obtained by changing the transmission device 10 and the reception device 20 of Embodiment 1 to the transmission device 10b and the reception device 20b.

[0879] In Figure 18 , the same reference numerals are labeled to the same blocks as those illustrated in Figure 1 , and the description will be omitted.

[0880] The transmission device 10b acquires input information and outputs a signal based on the acquired input information. SinceFigure 18 The communication system lb illustrated is an optical communication system, and thus, Figure 18 The transmission device 10b illustrated is an optical transmission device that outputs an optical signal.

[0881] The transmission device 10b includes an error correction encoding device 100b, a D / A converter 11, a transmission light source 12, and an optical modulator 13.

[0882] The transmission device 10b is obtained by changing the error correction encoding device 100 of Embodiment 1 to the error correction encoding device 100b.

[0883] The error correction encoding device 100b acquires input information input from the outside, generates a digital baseband modulation signal on the basis of the acquired input information. The error correction encoding device 100b outputs the generated digital baseband modulation signal to the D / A converter 11.

[0884] The reception device 20b receives a signal output by the transmission device 10b via the transmission path 30, generates output information corresponding to the input information on the basis of the signal, and outputs the generated output information. Since Figure 18 The communication system lb illustrated is an optical communication system, and thus, Figure 18 The reception device 20b illustrated is an optical reception device that receives an optical signal.

[0885] The reception device 20b includes a reception light source 22, an optical receiver 21, an A / D converter 23, and an error correction device 200b.

[0886] The reception device 20b is obtained by changing the error correction device 200 of Embodiment 1 to the error correction device 200b.

[0887] The error correction device 200b receives a reception digital baseband modulation signal output by the A / D converter 23, generates output information corresponding to the input information on the basis of the reception digital baseband modulation signal, and outputs the generated output information.

[0888] Reference will be made to Figure 19 The structure of the main part of the error correction encoding device 100b of Embodiment 3 will be described.

[0889] Figure 19 is a structural diagram illustrating an example of the structure of the main part of the error correction encoding device 100b of Embodiment 3.

[0890] The error correction encoding device 100b includes an input information acquisition unit 110, an encoding unit 120b, a modulation symbol conversion unit 130, a transmission waveform shaping unit 140, and an interleaving unit 150.

[0891] The error correction encoding device 100b is obtained by adding the interleaving section 150 to the error correction encoding device 100 of Embodiment 1 and changing the encoding section 120 of Embodiment 1 to the encoding section 120b.

[0892] In Figure 19 , the same reference numerals are labeled to the same blocks as those shown in the block and the explanation is omitted. Figure 2

[0893] The encoding section 120b generates soft-decision error correction frame information in which the first bit string group information and the second bit string group information are combined, based on the input information acquired by the input information acquisition section 110.

[0894] The encoding section 120b is described in detail later.

[0895] The interleaving section 150 exchanges information of an arbitrary column and information of another arbitrary column in the soft-decision error correction frame information generated by the encoding section 120b, based on a predetermined exchange rule (hereinafter referred to as "first exchange rule").

[0896] The bit array space in which the soft-decision error correction frame information is stored is described with reference to Figure 25A and Figure 25B .

[0897] In addition, as an example, a case where Nl is equal to N2 is shown for the D shown in Fig. 25 as the bit array space in which the soft-decision error correction frame information is stored.

[0898] Figure 25A is a explanatory diagram showing an example of the bit array space in which the soft-decision error correction frame information before the exchange by the interleaving section 150 is stored.

[0899] As shown in Figure 25A , in the D shown in Fig. 25 as the bit array space in which the soft-decision error correction frame information before the exchange by the interleaving section 150 is stored, the bit array space of m rows and Nl columns in which the first bit string group information is stored, that is, Dd[1] and the bit array space of m rows and N2 columns in which the second bit string group information is stored, that is, Dd[2] are respectively arranged in one bit array space.

[0900] The interleaving section 150 exchanges information of an arbitrary column and information of another arbitrary column in the D shown in Fig. 25 as the bit array space, based on the first exchange rule. Figure 25A

[0901] Figure 25B is a explanatory diagram showing an example of the bit array space in which the soft-decision error correction frame information after the exchange by the interleaving section 150 is stored.

[0902] For example, as shown in Figure 25B , in the D shown in Fig. 25 as the bit array space in which the soft-decision error correction frame information after the exchange by the interleaving section 150 is stored, the bit array space of m rows and Nl columns in which the first bit string group information is stored, that is, Dd[1] and the bit array space of m rows and N2 columns in which the second bit string group information is stored, that is, Dd[2] are respectively arranged in one bit array space.​As shown, the interleaving section 150 exchanges the column arrangement in the soft decision error correction frame information in a manner that arranges the bit array space storing the information of the kth column of the 2nd bit string group information, i.e., D[1:m][2][k], between the bit array spaces storing the information of the kth column of the 1st bit string group information, i.e., D[1:m][1][k] and D[1:m][1][k+1].

[0903] Figure 25B The bit array space shown is merely an example, and the bit array space after the exchange by the interleaving section 150 based on the 1st exchange rule is not limited to the bit array space shown. Figure 25B

[0904] The modulation symbol conversion section 130 performs pulse amplitude modulation based on the soft decision error correction frame information after the exchange of the column arrangement by the interleaving section 150.

[0905] Referring to Figure 26A and Figure 26B , the modulation symbol group information stored in the bit array space storing the modulation symbol group information generated by the modulation symbol conversion section 130 is described.

[0906] Figure 26A is a diagram showing an example of the modulation symbol group information in the case where the error correction encoding apparatus 100b does not have the interleaving section 150.

[0907] As shown in Figure 26A , in the modulation symbol group information in the case where the error correction encoding apparatus 100b does not have the interleaving section 150, Xv[1] as the 1st modulation symbol group information and Xv[2] as the 2nd modulation symbol group information are arranged respectively within one bit array space.

[0908] Figure 26B is a diagram showing an example of the modulation symbol group information in the case where the error correction encoding apparatus 100b has the interleaving section 150.

[0909] As shown in Figure 26B , the PAM symbol belonging to Xv[2] as the 2nd modulation symbol group information, i.e., X[2][k], is arranged between the PAM symbols belonging to Xv[1] as the 1st modulation symbol group information, i.e., X[1][k] and X[1][k+1], so that the modulation symbol group information in the case where the error correction encoding apparatus 100b has the interleaving section 150 corresponds to the soft decision error correction frame information after the exchange by the interleaving section 150 shown as an example in Figure 25B

[0910] ​​Also, the interleaving section 150 can exchange information of an arbitrary column and information of another arbitrary column in the modulation symbol group information generated by the modulation symbol conversion section 130 based on the first exchange rule.

[0911] The following describes a case where the interleaving section 150 exchanges information of an arbitrary column and information of another arbitrary column in the soft-decision error correction frame information generated by the encoding section 120b based on the first exchange rule.

[0912] Reference Signs Figure 20 The structure of the main part of the encoding section 120b of Embodiment 3 will be described.

[0913] Figure 20 is a structural diagram showing an example of the structure of the main part of the encoding section 120b of Embodiment 3.

[0914] The encoding section 120b includes an input bit array information generation section 121, a probability distribution shaping encoding section 122, a bit inversion section 123, a soft-decision error correction encoding section 124, an LSB interleaving section 126, and an LSB deinterleaving section 127.

[0915] The encoding section 120b is obtained by adding the LSB interleaving section 126 and the LSB deinterleaving section 127 to the structure of the encoding section 120 of Embodiment 1.

[0916] In Figure 20 , the same reference signs are labeled to the same blocks as those shown in Figure 3 , and the description is omitted.

[0917] The LSB interleaving section 126 exchanges information of an arbitrary column and information of another arbitrary column in the inverted first LSB information generated by the bit inversion section 123 based on a predetermined exchange rule (hereinafter referred to as "second exchange rule").

[0918] Further, the LSB interleaving section 126 exchanges information of an arbitrary column and information of another arbitrary column in the second LSB information generated by the probability distribution shaping encoding section 122 based on the second exchange rule.

[0919] Reference Signs Figure 27A and Figure 27B The bit array space in which the inverted first LSB information and the second LSB information are stored will be described.

[0920] Figure 27A is an explanatory diagram showing an example of the bit array space in which the soft-decision error correction frame information before exchange by the LSB interleaving section 126 is stored.

[0921] As Figure 27AAs shown, the LSB interleaving section 126 arranges the post-inversion first LSB information in Dd[1] which is a bit array space storing the first bit string group information, in such a manner that D[1:m-1][1][k] storing the k-th information of the first MSB information and the second SSB information and D[m][1][k] storing the k-th information of the post-inversion first LSB information are arranged in one column.

[0922] Further, as shown in Figure 27A As shown, the LSB interleaving section 126 arranges the post-inversion first LSB information in Dd[1] which is a bit array space storing the first bit string group information, in such a manner that D[1:m-1][1][k] storing the k-th information of the first MSB information and the second SSB information and D[m][1][k] storing the k-th information of the post-inversion first LSB information are arranged in one column.

[0923] The LSB interleaving section 126 exchanges, based on the second exchange rule, the information of any column in Dv[m][1] storing the post-inversion first LSB information with the information of any other column. Figure 27A

[0924] Further, the LSB interleaving section 126 exchanges, based on the second exchange rule, the information of any column in Dv[m][2] storing the second LSB information with the information of any other column. Figure 27A

[0925] Figure 27B is a diagram showing an example of a bit array space storing the soft decision error correction frame information after the exchange by the LSB interleaving section 126.

[0926] For example, as shown in Figure 27B As shown, the LSB interleaving section 126 exchanges the arrangement of columns in the post-inversion first LSB information in Dv[m][1] in such a manner that the information of odd-numbered columns in the post-inversion first LSB information is adjacent to each other and the information of even-numbered columns in the post-inversion first LSB information is adjacent to each other.

[0927] Further, for example, as shown in Figure 27B As shown, the LSB interleaving section 126 exchanges the arrangement of columns in the second LSB information in Dv[m][2] in such a manner that the information of odd-numbered columns in the second LSB information is adjacent to each other and the information of even-numbered columns in the second LSB information is adjacent to each other.

[0928] Further, Figure 27B The function f() shown is a top function.

[0929] Figure 27B ​​The illustrated bit array space is merely an example, and the bit array space after the exchange by the LSB interleaving section 126 based on the second exchange rule is not limited to Figure 27B The illustrated bit array space.

[0930] The modulation symbol conversion section 130 performs pulse amplitude modulation based on the soft decision error correction frame information after the exchange of the columns by the interleaving section 150.

[0931] The soft decision error correction encoding section 124 performs soft decision error correction encoding processing of the system using the inverted first LSB information and the second LSB information after the exchange by the LSB interleaving section 126, and thereby generates soft decision parity bits. The soft decision error correction encoding section 124 stores the generated soft decision parity bits as the second MSB information in Dv[1][2] as the bit array space.

[0932] The LSB deinterleaving section 127 returns the arrangement of the columns in the inverted first LSB information after the generation of the soft decision parity bits by the soft decision error correction encoding section 124 to the state before the arrangement of the columns is exchanged by the LSB interleaving section 126 based on the second exchange rule.

[0933] Further, the LSB deinterleaving section 127 returns the arrangement of the columns in the second LSB information after the generation of the soft decision parity bits by the soft decision error correction encoding section 124 to the state before the arrangement of the columns is exchanged by the LSB interleaving section 126 based on the second exchange rule.

[0934] Further, the LSB deinterleaving section 127 exchanges the arrangement of the columns based on the second exchange rule with respect to the soft decision parity bits stored in Dv[1][2] as the second MSB information as the bit array space, and makes the arrangement of the columns of the soft decision parity bits stored in Dv[1][2] the same as the arrangement of the columns in the case where the encoding section 120b does not have the LSB interleaving section 126.

[0935] In addition, each function of the input information acquisition section 110, the encoding section 120b, the modulation symbol conversion section 130, the transmission waveform shaping section 140, and the interleaving section 150 included in the error correction encoding apparatus 100b of Embodiment 3 can be implemented by the processing circuit 503 in Embodiment 1. Figure 5A and Figure 5B The processor 501 and the memory 502 in the example hardware structure are shown as being implemented, or can also be implemented by the processing circuit 503.

[0936] Referring to Figure 21A , Figure 21B and Figure 21C , the operation of the error correction encoding apparatus 100b of Embodiment 3 is described.

[0937] Figure 21A is a part of a flowchart showing an example of the process of the error correction encoding device 100b of Embodiment 3.

[0938] Figure 21B is another part of the flowchart showing an example of the process of the error correction encoding device 100b of Embodiment 3.

[0939] Figure 21C is the remaining part of the flowchart showing an example of the process of the error correction encoding device 100b of Embodiment 3.

[0940] Hereinafter, Figure 21A , Figure 21B and Figure 21C are collectively referred to as FIG. 21.

[0941] The error correction encoding device 100b repeatedly performs the process of the flowchart shown in FIG. 21.

[0942] In addition, the flowchart shown in FIG. 21 is obtained by changing the step ST610 in the flowchart shown in FIG. 6 to the step ST2110 and adding the step ST2120 between the step ST610 and the step ST620.

[0943] In FIG. 21, the same reference numerals are attached to the same processes as those of the flowchart shown in FIG. 6 and the explanation is omitted.

[0944] First, the error correction encoding device 100b performs the process of the step ST601.

[0945] Next, in the step ST2110, the encoding section 120b generates soft-decision error correction frame information.

[0946] Specifi...

Claims

1. An error correction coding device, characterized in that The error correction coding device comprises: an input information acquisition unit that acquires input information; an encoding unit that generates, based on the input information obtained by the input information obtaining unit, soft decision error correction frame information composed of a bit array of m rows and N columns, which is formed by combining the first bit string group information and the second bit string group information, wherein the first bit string group information is composed of a bit array of m rows and N1 columns, and can use a predetermined first symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the first bit string group information into a modulation symbol, and the second bit string group information is composed of a bit array of m rows and N2 columns, and can use a predetermined second symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the second bit string group information into a modulation symbol, wherein m is a natural number greater than 2, N1 is a natural number greater than 2, N2 is a natural number greater than 1, and N is a number obtained by adding N1 and N2; a modulation symbol conversion unit that uses the first symbol mapping rule or the second symbol mapping rule to perform pulse amplitude modulation on a combination of bit values ​​of each column of the soft decision error correction frame information generated by the encoding unit for each column of the soft decision error correction frame information to generate the modulation symbol, thereby generating modulation symbol group information consisting of N modulation symbols; and a transmission waveform shaping unit that generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion unit and outputs the generated digital baseband modulation signal; The encoding unit generates the soft decision error correction frame information by the following processing: Based on the input information acquired by the input information acquisition unit, first input bit array information consisting of a bit array of m-1 rows and N columns and second input bit array information consisting of a bit array of 1 row and N3 columns are generated, where N3 is a natural number greater than or equal to 1 and smaller than N1. The generated second input bit array information is stored in a predetermined area of ​​the first row in the first bit string group information as a part of the first most significant bit information consisting of a 1-row N1-column bit array. By performing probability distribution shaping coding processing on the generated first input bit array information, shaping bit array information consisting of a bit array of m-1 rows and N columns is generated, By separating the generated shaped bit array information, a first set of bit array information consisting of a combination of N1 predetermined columns and a second set of bit array information consisting of a combination of N2 predetermined columns are generated. The first least significant bit information consisting of a 1-row N1-column bit array is generated by extracting the bit array of the m-1th row in the first group of bit array information generated from the first group of bit array information, and the bit values ​​of each column in the generated first least significant bit information are XORed with the bit values ​​of each column in the information of the first row in the first bit string group information after storing the second input bit array information, thereby generating the inverted first least significant bit information consisting of a 1-row N1-column bit array, and the generated inverted first least significant bit information is stored in the mth row in the first bit string group information. The second least significant bit information consisting of a 1-row N2-column bit array is generated by extracting the bit array of the m-1th row in the second group of bit array information, and the generated second least significant bit information is stored in the mth row in the second bit string group information. Soft decision parity bits are generated by performing a systematic soft decision error correction coding process using the generated inverted first least significant bit information and the generated second least significant bit information, and the generated soft decision parity bits are stored in the first row of the second bit string group information as the second most significant bit information consisting of a 1-row N2-column bit array. When m is greater than or equal to 3, the first to m-2th rows of the first group of bit array information are extracted from the generated first group of bit array information, thereby generating the first SSB information consisting of a bit array of m-2 rows and N1 columns, and the generated first SSB information is stored in the second to m-1th rows of the first bit string group information. When m is greater than 3, the 1st to m-2th rows of the 2nd group of bit array information are extracted from the generated 2nd group of bit array information, thereby generating the 2nd SSB information consisting of a bit array of m-2 rows and N2 columns, and the generated 2nd SSB information is stored in the 2nd to m-1th rows in the 2nd bit string group information.

2. The error correction coding device according to claim 1, wherein The first symbol mapping rule is a symbol mapping rule corresponding to a bit value combination consisting of an m-row, 1-column bit array and a modulation symbol after one-dimensional pulse amplitude modulation, wherein the bit value combination of the 1st row to the m-1th row in the m-row, 1-column bit array corresponds to a binary reflected Gray code, and the bit value of the mth row is a different value from one another in the modulation symbols whose amplitude values ​​of the modulation symbols are adjacent to each other. The second symbol mapping rule is a symbol mapping rule corresponding to a bit value combination consisting of a bit array of m rows and 1 column and a modulation symbol after one-dimensional pulse amplitude modulation, wherein the combination of bit values ​​from the 1st row to the m-1th row in the bit array of m rows and 1 column is a combination corresponding to a binary reflected Gray code, the bit value of the mth row is different from each other in the modulation symbols whose amplitude values ​​have the same positive and negative signs and are adjacent to each other, and the bit value of the mth row is the same value in the modulation symbol with the smallest absolute value of the amplitude value among the modulation symbols with positive amplitude values ​​and the modulation symbol with the smallest absolute value of the amplitude value among the modulation symbols with negative amplitude values.

3. The error correction coding device according to claim 1, wherein When the encoding unit generates the first input bit array information and the second input bit array information based on the input information obtained by the input information acquisition unit, the bit values ​​of the bits other than the bits corresponding to the input information in the first input bit array information or the second input bit array information are set to 0, thereby generating the first input bit array information and the second input bit array information.

4. The error correction coding device according to claim 1, wherein The encoding unit uses the first input bit array information and the second input bit array information, or uses the first input bit array information, the first SSB information, the second SSB information, the second least significant bit information, and the first least significant bit information, or uses the first input bit array information, the first SSB information, the second SSB information, the second least significant bit information, and the inverted first least significant bit information to perform a hard decision error correction coding process on the system, thereby generating hard decision parity bits. The generated hard decision parity bits are stored as part of the first most significant bit information in a predetermined area of ​​the first row of the first bit string group information that is different from the area for storing the second input bit array information.

5. The error correction coding device according to claim 4, wherein When generating the second input bit array information based on the input information acquired by the input information acquisition unit, the encoding unit sets the bit values ​​of bits other than the bits corresponding to the input information in the second input bit array information to predetermined values, thereby generating the second input bit array information. The encoding unit performs the following processing when performing the hard decision error correction coding processing of the system: A first preprocessing of exchanging the bit values ​​of the corresponding columns between the bit values ​​of the area storing a predetermined value in the predetermined area of ​​the first row of the first bit string group information storing the second input bit array information as a part of the first most significant bit information and the bit values ​​of the columns corresponding to the columns of the area storing a predetermined value in the predetermined area of ​​the first row of the first bit string group information storing the first least significant bit information in the area of ​​the m-th row of the first bit string group information; A second preprocessing is to calculate an exclusive OR of each corresponding column between the bit values ​​after the bit values ​​in the area storing a predetermined value in the predetermined area of ​​the first row of the first bit string group information are exchanged and the bit values ​​in the columns corresponding to the columns in the area of ​​the mth row of the first bit string group information that store a predetermined value in the predetermined area of ​​the first row of the first bit string group information are exchanged; as well as The third preprocessing uses the XOR operation result in the corresponding column to rewrite the bit value after exchanging the bit value in the area storing the predetermined value in the predetermined area of ​​the first row in the first bit string group information.

6. The error correction coding device according to claim 1, wherein The encoding unit generates the soft decision error correction frame information by the following processing: Based on the input information acquired by the input information acquisition unit, in addition to generating the first input bit array information and the second input bit array information, third input bit array information consisting of a bit array of 1 row and N4 columns is generated, where N4 is a natural number greater than 1 and smaller than N2. The generated third input bit array information is stored in a predetermined area of ​​the first row in the second bit string group information as a part of the second most significant bit information consisting of a 1-row N2-column bit array. In addition to using the generated inverted first least significant bit information and the generated second least significant bit information, the third input bit array information stored as part of the second most significant bit information is also used to perform system soft decision error correction coding processing, thereby generating the soft decision parity bits, and the generated soft decision parity bits are stored in a predetermined area of ​​the first row in the second bit string group information that is different from the area that stores the third input bit array information.

7. An error correction coding method, characterized in that: The error correction coding method has the following features: an input information acquisition step, wherein the input information acquisition unit acquires input information; and The encoding step comprises the following steps: the encoding unit generates, based on the input information obtained by the input information acquisition unit, soft decision error correction frame information composed of a bit array of m rows and N columns, which is formed by combining the first bit string group information and the second bit string group information; the first bit string group information is composed of a bit array of m rows and N1 columns, and can use a predetermined first symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the first bit string group information into a modulation symbol; the second bit string group information is composed of a bit array of m rows and N2 columns, and can use a predetermined second symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the second bit string group information into a modulation symbol, wherein m is a natural number greater than 2, N1 is a natural number greater than 2, N2 is a natural number greater than 1, and N is a number obtained by adding N1 and N2. The encoding step comprises: a first encoding step of generating, based on the input information acquired by the input information acquisition unit, first input bit array information consisting of a bit array of m-1 rows and N columns and second input bit array information consisting of a bit array of 1 row and N3 columns, where N3 is a natural number greater than or equal to 1 and less than N1; A second encoding step of storing the second input bit array information generated by the first encoding step as a part of the first most significant bit information consisting of a 1-row N1-column bit array in a predetermined area of ​​the first row of the first bit string group information; a third encoding step of performing probability distribution shaping encoding processing on the first input bit array information generated in the first encoding step, thereby generating a shaped bit array information consisting of a bit array of m-1 rows and N columns; a fourth encoding step of separating the shaped bit array information generated in the third encoding step to generate a first set of bit array information consisting of a combination of N1 predetermined columns and a second set of bit array information consisting of a combination of N2 predetermined columns; A fifth encoding step, extracting the bit array of the m-1th row in the first group of bit array information generated by the fourth encoding step, thereby generating the first least significant bit information consisting of a 1-row N1-column bit array, performing an exclusive OR operation on the bit values ​​of each column in the generated first least significant bit information and the bit values ​​of each column in the information of the first row of the first bit string group information after storing the second input bit array information, thereby generating the inverted first least significant bit information consisting of a 1-row N1-column bit array, and storing the generated inverted first least significant bit information in the mth row of the first bit string group information; a sixth encoding step of extracting the bit array of the m-1th row in the second group of bit array information generated in the fourth encoding step, thereby generating second least significant bit information consisting of a bit array of 1 row and N2 columns, and storing the generated second least significant bit information in the mth row of the second bit string group information; a seventh encoding step of performing a systematic soft decision error correction encoding process using the inverted first least significant bit information generated in the fifth encoding step and the second least significant bit information generated in the sixth encoding step, thereby generating soft decision parity check bits, and storing the generated soft decision parity check bits as the second most significant bit information consisting of a 1-row N2-column bit array in the first row of the second bit string group information; an eighth encoding step, when m is greater than or equal to 3, extracting rows 1 to m-2 of the first group of bit array information generated in the fourth encoding step, thereby generating first SSB information consisting of a bit array of m-2 rows and N1 columns, and storing the generated first SSB information in rows 2 to m-1 of the first bit string group information; and In the 9th encoding step, when m is greater than 3, the 1st to m-2th rows of the 2nd group of bit array information are extracted from the 2nd group of bit array information generated by the 4th encoding step, thereby generating the 2nd SSB information consisting of a bit array of m-2 rows and N2 columns, and the generated 2nd SSB information is stored in the 2nd to m-1th rows of the 2nd bit string group information.

8. An error correction device, characterized in that: The error correction device comprises: a received modulation symbol group information generating unit configured to receive a received digital baseband modulation signal, which is a signal based on the soft decision error correction frame information generated by the error correction coding method according to claim 7, and to generate received modulation symbol group information consisting of N received modulation symbols based on the received digital baseband modulation signal; a hard decision candidate generating unit configured to generate, based on the first symbol mapping rule or the second symbol mapping rule, first hard decision candidate bit array information consisting of a 1-row, N1-column bit array, second hard decision candidate bit array information consisting of a m-2-row, N1-column bit array when m is greater than or equal to 3, and third hard decision candidate bit array information consisting of a m-2-row, N2-column bit array when m is greater than or equal to 3, using the received modulation symbol group information generated by the received modulation symbol group information generating unit; a soft decision information generating unit, which generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, a first a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the first row of the second bit string group information, a second a posteriori L value sequence consisting of N1 a posteriori L values ​​corresponding to each column of the m-th row of the first bit string group information, and a third a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the m-th row of the second bit string group information; a decoding unit configured to perform multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation unit, and the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence generated by the soft decision information generation unit; as well as an information output unit that outputs information generated by the multi-stage error correction process performed by the decoding unit as output information, In the first decoding process of the multi-stage error correction process, the decoding unit performs soft decision error correction processing based on the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence, thereby generating inverted first received least significant bit information consisting of a 1-row N1-column bit array corresponding to the inverted first least significant bit information, and second received least significant bit information consisting of a 1-row N2-column bit array corresponding to the second least significant bit information. In the second decoding process of the multi-stage error correction process, the decoding unit generates first received most significant bit information consisting of a 1-row N1-column bit array corresponding to the first most significant bit information based on the first hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates first received SSB information consisting of a m-2-row N1-column bit array corresponding to the first SSB information based on the second hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates second received SSB information consisting of a m-2-row N2-column bit array corresponding to the second SSB information based on the third hard decision candidate bit array information and the second received least significant bit information. In the third decoding process of the multi-stage error correction process, the decoding unit generates first received least significant bit information corresponding to the first least significant bit information by calculating an exclusive OR of the bit values ​​of each column in the inverted first received least significant bit information and the bit values ​​of each column in the first received most significant bit information corresponding to each column in the inverted first received least significant bit information. In the fourth decoding process of the multi-stage error correction process, the decoding unit performs probability distribution shaping decoding on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information, thereby generating first output bit array information consisting of a bit array of m-1 rows and N columns corresponding to the first input bit array information. In the fifth decoding process of the multi-stage error correction process, the decoding unit extracts information of a predetermined area in the first received most significant bit information, thereby generating second output bit array information consisting of a 1-row N3-column bit array corresponding to the second input bit array information. In the sixth decoding process of the multi-stage error correction process, the decoding unit generates the output information corresponding to the input information based on the first output bit array information and the second output bit array information. The information output unit outputs the output information generated by the decoding unit.

9. The error correction device according to claim 8, characterized in that The first symbol mapping rule is a symbol mapping rule corresponding to one modulation symbol after one-dimensional pulse amplitude modulation and one bit value combination consisting of a bit array of m rows and one column, wherein the combination of bit values ​​from the 1st row to the m-1th row in the bit array of m rows and one column corresponds to a binary reflected Gray code, and the bit values ​​in the mth row are different values ​​from each other in the modulation symbols whose amplitude values ​​of the modulation symbols are adjacent to each other. The second symbol mapping rule is a symbol mapping rule corresponding to one of the modulation symbols after one-dimensional pulse amplitude modulation and one bit value combination composed of a bit array of m rows and 1 column, wherein the combination of bit values ​​from the 1st row to the m-1th row in the bit array of m rows and 1 column is a combination corresponding to a binary reflected Gray code, the bit value of the mth row is different from each other in the modulation symbols whose amplitude values ​​have the same positive and negative signs and are adjacent to each other, and the bit value of the mth row is the same value in the modulation symbol with the smallest absolute value of the amplitude value among the modulation symbols with positive amplitude values ​​and the modulation symbol with the smallest absolute value of the amplitude value among the modulation symbols with negative amplitude values.

10. The error correction device according to claim 8, characterized in that: The decoding unit performs hard decision error correction processing on the information corresponding to the second output bit array information in the first reception most significant bit information, the first reception SSB information, the second reception SSB information, the second reception least significant bit information, and the first reception least significant bit information, or on the information corresponding to the second output bit array information in the first reception most significant bit information, the first reception SSB information, the second reception SSB information, the second reception least significant bit information, and the inverted first reception least significant bit information, or on the information corresponding to the second output bit array information in the first reception most significant bit information and the first output bit array information, based on the information stored in a predetermined area in the first reception most significant bit information. In a case where the decoding unit performs the hard decision error correction processing on the information corresponding to the second output bit array information in the first received most significant bit information, the first received SSB information, the second received SSB information, the second received least significant bit information, and the inverted first received least significant bit information, the decoding unit calculates an exclusive OR using the inverted first received least significant bit information and the first received most significant bit information after the seventh decoding process in the third decoding process, and generates the second output bit array information by extracting information of a predetermined area in the first received most significant bit information after the seventh decoding process in the fifth decoding process. In a case where the decoding unit performs the hard decision error correction processing on the information corresponding to the second output bit array information in the first received most significant bit information, as well as the first received SSB information, the second received SSB information, the second received least significant bit information, and the first received least significant bit information, the decoding unit performs probability distribution shaping decoding processing on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information after the seventh decoding processing in the fourth decoding processing, and generates the second output bit array information by extracting information of a predetermined area in the first received most significant bit information after the seventh decoding processing in the fifth decoding processing, In a case where the decoding unit performs the hard decision error correction processing on the information corresponding to the second output bit array information in the first received most significant bit information and the first output bit array information, the decoding unit generates the second output bit array information in the fifth decoding processing by extracting information of a predetermined area in the first received most significant bit information after the seventh decoding processing, and generates the output information based on the second output bit array information and the first output bit array information after the seventh decoding processing in the sixth decoding processing.

11. The error correction device according to claim 10, characterized in that: After the decoding unit performs the hard decision error correction process, the decoding unit performs the following process in the seventh decoding process of the multi-stage error correction process: A first post-processing is to calculate an exclusive OR of each corresponding column between the bit value of the column in the first received most significant bit information corresponding to each column of the area storing a predetermined value in the predetermined area of ​​the first row of the first bit string group information storing the second input bit array information as a part of the first most significant bit information, and the bit value of the column in the first received least significant bit information corresponding to each column of the area storing a predetermined value in the predetermined area of ​​the first row of the first bit string group information storing the second input bit array information as a part of the first most significant bit information; as well as The second post-processing uses the XOR operation results in the corresponding columns to rewrite the bit values ​​of the columns in the first received most significant bit information corresponding to the columns in the area storing predetermined values ​​in the predetermined area of ​​the first row of the first bit string group information.

12. The error correction device according to claim 8, characterized in that In the first encoding step, based on the input information acquired by the input information acquisition unit, in addition to generating the first input bit array information and the second input bit array information, third input bit array information consisting of a bit array of 1 row and N4 columns is generated, where N4 is a natural number greater than 1 and less than N2. In the second encoding step, the second input bit array information generated by the first encoding step is stored in a predetermined area of ​​the first row in the first bit string group information as a part of the first most significant bit information, and the third input bit array information generated by the first encoding step is stored in a predetermined area of ​​the first row in the second bit string group information as a part of the second most significant bit information. In the seventh encoding step, in addition to using the inverted first least significant bit information generated in the fifth encoding step and the second least significant bit information generated in the sixth encoding step, the third input bit array information generated in the first encoding step is also used to perform soft decision error correction coding processing on the system, thereby generating the soft decision parity bits, and storing the generated soft decision parity bits in an area of ​​the second most significant bit information that is different from the area where the third input bit array information is stored. The decoding unit performs soft decision error correction processing based on the first, second, and third a posteriori L-value sequences in a first decoding process of the multi-stage error correction process, thereby generating, in addition to generating first received least significant bit information after inversion consisting of a bit array of 1 row and N1 columns corresponding to the first least significant bit information after inversion and second received least significant bit information consisting of a bit array of 1 row and N2 columns corresponding to the second least significant bit information, second received most significant bit information consisting of a bit array of 1 row and N2 columns corresponding to the second most significant bit information. In the eighth decoding process of the multi-stage error correction process, information of a predetermined area in the second received most significant bit information is extracted, thereby generating third output bit array information consisting of a 1-row N4-column bit array corresponding to the third input bit array information. In the sixth decoding process of the multi-stage error correction process, the output information corresponding to the input information is generated based on the third output bit array information in addition to the first output bit array information and the second output bit array information.

13. An error correction method, characterized in that: The error correction method has the following features: a receiving modulation symbol group information generating step, wherein the receiving modulation symbol group information generating unit receives a signal based on the soft decision error correction frame information generated by the error correction coding method according to claim 7, i.e., a receiving digital baseband modulation signal, and generates receiving modulation symbol group information consisting of N receiving modulation symbols based on the receiving digital baseband modulation signal; a hard decision candidate generating step, wherein the hard decision candidate generating unit generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, first hard decision candidate bit array information consisting of a 1-row N1-column bit array, second hard decision candidate bit array information consisting of a m-2-row N1-column bit array when m is greater than or equal to 3, and third hard decision candidate bit array information consisting of a m-2-row N2-column bit array when m is greater than or equal to 3, using the first symbol mapping rule or the second symbol mapping rule; a soft decision information generating step, wherein the soft decision information generating unit generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, a first a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the first row of the second bit string group information, a second a posteriori L value sequence consisting of N1 a posteriori L values ​​corresponding to each column of the m-th row of the first bit string group information, and a third a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the m-th row of the second bit string group information; a decoding step, wherein a decoding unit performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation unit, and the first a posteriori L value sequence, the second a posteriori L value sequence, and the third a posteriori L value sequence generated by the soft decision information generation unit; as well as an information output step, wherein the information output unit outputs information generated by the multi-stage error correction processing performed by the decoding unit as output information, In the first decoding process of the multi-stage error correction process, the decoding unit performs soft decision error correction processing based on the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence, thereby generating inverted first received least significant bit information consisting of a 1-row N1-column bit array corresponding to the inverted first least significant bit information, and second received least significant bit information consisting of a 1-row N2-column bit array corresponding to the second least significant bit information. In the second decoding process of the multi-stage error correction process, the decoding unit generates first received most significant bit information consisting of a 1-row N1-column bit array corresponding to the first most significant bit information based on the first hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates first received SSB information consisting of a m-2-row N1-column bit array corresponding to the first SSB information based on the second hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates second received SSB information consisting of a m-2-row N2-column bit array corresponding to the second SSB information based on the third hard decision candidate bit array information and the second received least significant bit information. In the third decoding process of the multi-stage error correction process, the decoding unit generates first received least significant bit information corresponding to the first least significant bit information by calculating an exclusive OR of the bit values ​​of each column in the inverted first received least significant bit information and the bit values ​​of each column in the first received most significant bit information corresponding to each column in the inverted first received least significant bit information. In the fourth decoding process of the multi-stage error correction process, the decoding unit performs probability distribution shaping decoding on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information, thereby generating first output bit array information consisting of a bit array of m-1 rows and N columns corresponding to the first input bit array information. In the fifth decoding process of the multi-stage error correction process, the decoding unit extracts information of a predetermined area in the first received most significant bit information, thereby generating second output bit array information consisting of a 1-row N3-column bit array corresponding to the second input bit array information. In the sixth decoding process of the multi-stage error correction process, the decoding unit generates the output information corresponding to the input information based on the first output bit array information and the second output bit array information. The information output unit outputs the output information generated by the decoding unit.

14. A communication method, characterized in that: The communication method comprises an error correction coding step, a modulation symbol conversion step, a transmission waveform shaping step, a transmission step, a receiving step, and an error correction step. In the error correction coding step, soft decision error correction frame information based on input information is generated by an error correction coding method. The error correction coding method has the following features: an input information acquisition step, wherein an input information acquisition unit acquires the input information; and The encoding step comprises the following steps: the encoding unit generates the soft decision error correction frame information composed of a bit array of m rows and N columns, which is formed by combining the first bit string group information and the second bit string group information based on the input information obtained by the input information acquisition unit; the first bit string group information is composed of a bit array of m rows and N1 columns, and can use a predetermined first symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the first bit string group information into a modulation symbol; the second bit string group information is composed of a bit array of m rows and N2 columns, and can use a predetermined second symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the second bit string group information into a modulation symbol, wherein m is a natural number greater than 2, N1 is a natural number greater than 2, N2 is a natural number greater than 1, and N is a number obtained by adding N1 and N2. The encoding step comprises: a first encoding step of generating, based on the input information acquired by the input information acquisition unit, first input bit array information consisting of a bit array of m-1 rows and N columns and second input bit array information consisting of a bit array of 1 row and N3 columns, where N3 is a natural number greater than or equal to 1 and less than N1; A second encoding step of storing the second input bit array information generated by the first encoding step as a part of the first most significant bit information consisting of a 1-row N1-column bit array in a predetermined area of ​​the first row of the first bit string group information; a third encoding step of performing probability distribution shaping encoding processing on the first input bit array information generated in the first encoding step, thereby generating a shaped bit array information consisting of a bit array of m-1 rows and N columns; a fourth encoding step of separating the shaped bit array information generated in the third encoding step to generate a first set of bit array information consisting of a combination of N1 predetermined columns and a second set of bit array information consisting of a combination of N2 predetermined columns; A fifth encoding step, extracting the bit array of the m-1th row in the first group of bit array information generated by the fourth encoding step, thereby generating the first least significant bit information consisting of a 1-row N1-column bit array, performing an exclusive OR operation on the bit values ​​of each column in the generated first least significant bit information and the bit values ​​of each column in the information of the first row of the first bit string group information after storing the second input bit array information, thereby generating the inverted first least significant bit information consisting of a 1-row N1-column bit array, and storing the generated inverted first least significant bit information in the mth row of the first bit string group information; a sixth encoding step of extracting the bit array of the m-1th row in the second group of bit array information generated in the fourth encoding step, thereby generating second least significant bit information consisting of a bit array of 1 row and N2 columns, and storing the generated second least significant bit information in the mth row of the second bit string group information; a seventh encoding step of performing a systematic soft decision error correction encoding process using the inverted first least significant bit information generated in the fifth encoding step and the second least significant bit information generated in the sixth encoding step, thereby generating soft decision parity check bits, and storing the generated soft decision parity check bits as the second most significant bit information consisting of a 1-row N2-column bit array in the first row of the second bit string group information; an eighth encoding step, when m is greater than or equal to 3, extracting rows 1 to m-2 of the first group of bit array information generated in the fourth encoding step, thereby generating first SSB information consisting of a bit array of m-2 rows and N1 columns, and storing the generated first SSB information in rows 2 to m-1 of the first bit string group information; and In the ninth encoding step, when m is greater than or equal to 3, the first to m-2th rows of the second group of bit array information are extracted from the second group of bit array information generated by the fourth encoding step, thereby generating the second SSB information consisting of a bit array of m-2 rows and N2 columns, and storing the generated second SSB information in the second to m-1th rows of the second bit string group information. In the modulation symbol conversion step, a modulation symbol conversion unit pulse-amplitude-modulates a combination of bit values ​​of each column of the soft-decision error correction frame information generated in the error correction encoding step into the modulation symbol for each column of the soft-decision error correction frame information based on the first symbol mapping rule or the second symbol mapping rule, thereby generating modulation symbol group information consisting of N modulation symbols. In the transmission waveform shaping step, the transmission waveform shaping unit generates a digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion unit, and outputs the generated digital baseband modulation signal; In the transmitting step, the transmitting unit receives the digital baseband modulated signal output by the transmitting waveform shaping unit and transmits a signal based on the digital baseband modulated signal; In the receiving step, the receiving unit receives the signal transmitted by the transmitting unit and generates a received digital baseband modulated signal based on the signal; In the error correction step, based on the received digital baseband modulated signal generated by the receiving unit, output information corresponding to the input information is generated and output by an error correction method, The error correction method has the following features: a receiving modulation symbol group information generating step, wherein the receiving modulation symbol group information generating unit generates receiving modulation symbol group information consisting of N receiving modulation symbols based on the received digital baseband modulation signal; a hard decision candidate generating step, wherein the hard decision candidate generating unit generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, first hard decision candidate bit array information consisting of a 1-row N1-column bit array, second hard decision candidate bit array information consisting of a m-2-row N1-column bit array when m is greater than or equal to 3, and third hard decision candidate bit array information consisting of a m-2-row N2-column bit array when m is greater than or equal to 3, using the first symbol mapping rule or the second symbol mapping rule; a soft decision information generating step, wherein the soft decision information generating unit generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, a first a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the first row of the second bit string group information, a second a posteriori L value sequence consisting of N1 a posteriori L values ​​corresponding to each column of the m-th row of the first bit string group information, and a third a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the m-th row of the second bit string group information; a decoding step, wherein the decoding unit performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation unit, and the first a posteriori L value sequence, the second a posteriori L value sequence, and the third a posteriori L value sequence generated by the soft decision information generation unit; and an information output step, wherein the information output unit outputs information generated by the multi-stage error correction processing performed by the decoding unit as output information, In the first decoding process of the multi-stage error correction process, the decoding unit performs soft decision error correction processing based on the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence, thereby generating inverted first received least significant bit information consisting of a 1-row N1-column bit array corresponding to the inverted first least significant bit information, and second received least significant bit information consisting of a 1-row N2-column bit array corresponding to the second least significant bit information. In the second decoding process of the multi-stage error correction process, the decoding unit generates first received most significant bit information consisting of a 1-row N1-column bit array corresponding to the first most significant bit information based on the first hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates first received SSB information consisting of a m-2-row N1-column bit array corresponding to the first SSB information based on the second hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates second received SSB information consisting of a m-2-row N2-column bit array corresponding to the second SSB information based on the third hard decision candidate bit array information and the second received least significant bit information. In the third decoding process of the multi-stage error correction process, the decoding unit generates first received least significant bit information corresponding to the first least significant bit information by calculating an exclusive OR of the bit values ​​of each column in the inverted first received least significant bit information and the bit values ​​of each column in the first received most significant bit information corresponding to each column in the inverted first received least significant bit information. In the fourth decoding process of the multi-stage error correction process, the decoding unit performs probability distribution shaping decoding on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information, thereby generating first output bit array information consisting of a bit array of m-1 rows and N columns corresponding to the first input bit array information. In the fifth decoding process of the multi-stage error correction process, the decoding unit extracts information of a predetermined area in the first received most significant bit information, thereby generating second output bit array information consisting of a 1-row N3-column bit array corresponding to the second input bit array information. In the sixth decoding process of the multi-stage error correction process, the decoding unit generates the output information corresponding to the input information based on the first output bit array information and the second output bit array information. The information output unit outputs the output information generated by the decoding unit.

15. An optical communication system comprising an optical transmission path for transmitting an optical signal, a transmitting device, and a receiving device, wherein: The sending device has: error correction coding device; a D / A converter receiving a digital baseband modulated signal output by the error correction coding device, converting the digital baseband modulated signal into a transmission electrical signal as an analog baseband modulated signal, and outputting the converted transmission electrical signal; a light source for transmission, which outputs unmodulated light of a single wavelength; as well as an optical modulator that receives the transmission electrical signal output by the D / A converter and the unmodulated light output by the transmission light source, modulates the unmodulated light with the transmission electrical signal to generate modulated light, and outputs the generated modulated light as a modulated light signal to the optical transmission path; The error correction coding device comprises: an input information acquisition unit that acquires input information; an encoding unit that generates, based on the input information obtained by the input information obtaining unit, soft decision error correction frame information composed of a bit array of m rows and N columns, which is formed by combining the first bit string group information and the second bit string group information, wherein the first bit string group information is composed of a bit array of m rows and N1 columns, and can use a predetermined first symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the first bit string group information into a modulation symbol, and the second bit string group information is composed of a bit array of m rows and N2 columns, and can use a predetermined second symbol mapping rule to modulate the combined pulse amplitude of the bit values ​​of each column of the second bit string group information into a modulation symbol, wherein m is a natural number greater than 2, N1 is a natural number greater than 2, N2 is a natural number greater than 1, and N is a number obtained by adding N1 and N2; a modulation symbol conversion unit configured to pulse amplitude modulate a combination of bit values ​​of each column of the soft decision error correction frame information generated by the encoding unit into the modulation symbol for each column of the soft decision error correction frame information using the first symbol mapping rule or the second symbol mapping rule, thereby generating modulation symbol group information consisting of N modulation symbols; and a transmission waveform shaping unit that generates the digital baseband modulation signal based on the modulation symbol group information generated by the modulation symbol conversion unit and outputs the generated digital baseband modulation signal; The encoding unit generates the soft decision error correction frame information by the following processing: Based on the input information acquired by the input information acquisition unit, first input bit array information consisting of a bit array of m-1 rows and N columns and second input bit array information consisting of a bit array of 1 row and N3 columns are generated, where N3 is a natural number greater than or equal to 1 and smaller than N1. The generated second input bit array information is stored in a predetermined area of ​​the first row in the first bit string group information as a part of the first most significant bit information consisting of a 1-row N1-column bit array. By performing probability distribution shaping coding processing on the generated first input bit array information, shaping bit array information consisting of a bit array of m-1 rows and N columns is generated, By separating the generated shaped bit array information, a first set of bit array information consisting of a combination of N1 predetermined columns and a second set of bit array information consisting of a combination of N2 predetermined columns are generated. The first least significant bit information consisting of a 1-row N1-column bit array is generated by extracting the bit array of the m-1th row in the first group of bit array information generated from the first group of bit array information, and the bit values ​​of each column in the generated first least significant bit information are XORed with the bit values ​​of each column in the information of the first row in the first bit string group information after storing the second input bit array information, thereby generating the inverted first least significant bit information consisting of a 1-row N1-column bit array, and the generated inverted first least significant bit information is stored in the mth row in the first bit string group information. The second least significant bit information consisting of a 1-row N2-column bit array is generated by extracting the bit array of the m-1th row in the second group of bit array information, and the generated second least significant bit information is stored in the mth row in the second bit string group information. Soft decision parity bits are generated by performing a systematic soft decision error correction coding process using the generated inverted first least significant bit information and the generated second least significant bit information, and the generated soft decision parity bits are stored in the first row of the second bit string group information as the second most significant bit information consisting of a 1-row N2-column bit array. When m is greater than or equal to 3, the first to m-2th rows of the first group of bit array information are extracted from the generated first group of bit array information, thereby generating the first SSB information consisting of a bit array of m-2 rows and N1 columns, and the generated first SSB information is stored in the second to m-1th rows of the first bit string group information. When m is greater than 3, the first to m-2th rows of the second group of bit array information are extracted from the generated second group of bit array information, thereby generating the second SSB information consisting of a bit array of m-2 rows and N2 columns, and the generated second SSB information is stored in the second to m-1th rows of the second bit string group information. The receiving device has: a receiving light source that outputs unmodulated light of a single wavelength corresponding to the center wavelength of the modulated light signal output by the transmitting device to the optical transmission path; an optical receiver that receives the modulated optical signal output by the transmitter to the optical transmission path and the unmodulated light output by the receiving light source, performs coherent detection using the modulated light as the modulated optical signal and the unmodulated light to generate a received electrical signal as a received analog baseband modulated signal, and outputs the generated received electrical signal; an A / D converter that receives a reception electrical signal output by the optical receiver, converts the reception electrical signal into a reception digital baseband modulated signal, and outputs the converted reception digital baseband modulated signal; and Error correction device, The error correction device comprises: a received modulation symbol group information generating unit, which generates received modulation symbol group information consisting of N received modulation symbols based on the received digital baseband modulation signal; a hard decision candidate generating unit configured to generate, based on the first symbol mapping rule or the second symbol mapping rule, first hard decision candidate bit array information consisting of a 1-row, N1-column bit array, second hard decision candidate bit array information consisting of a m-2-row, N1-column bit array when m is greater than or equal to 3, and third hard decision candidate bit array information consisting of a m-2-row, N2-column bit array when m is greater than or equal to 3, using the received modulation symbol group information generated by the received modulation symbol group information generating unit; a soft decision information generating unit, which generates, based on the received modulation symbol group information generated by the received modulation symbol group information generating unit, a first a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the first row of the second bit string group information, a second a posteriori L value sequence consisting of N1 a posteriori L values ​​corresponding to each column of the m-th row of the first bit string group information, and a third a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the m-th row of the second bit string group information; a decoding unit that performs multi-stage error correction processing based on the first hard decision candidate bit array information, the second hard decision candidate bit array information, and the third hard decision candidate bit array information generated by the hard decision candidate generation unit, and the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence generated by the soft decision information generation unit; and an information output unit that outputs information generated by the multi-stage error correction process performed by the decoding unit as output information, In the first decoding process of the multi-stage error correction process, the decoding unit performs soft decision error correction processing based on the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence, thereby generating inverted first received least significant bit information consisting of a 1-row N1-column bit array corresponding to the inverted first least significant bit information, and second received least significant bit information consisting of a 1-row N2-column bit array corresponding to the second least significant bit information. In the second decoding process of the multi-stage error correction process, the decoding unit generates first received most significant bit information consisting of a 1-row N1-column bit array corresponding to the first most significant bit information based on the first hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates first received SSB information consisting of a m-2-row N1-column bit array corresponding to the first SSB information based on the second hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, the decoding unit generates second received SSB information consisting of a m-2-row N2-column bit array corresponding to the second SSB information based on the third hard decision candidate bit array information and the second received least significant bit information. In the third decoding process of the multi-stage error correction process, the decoding unit generates first received least significant bit information corresponding to the first least significant bit information by calculating an exclusive OR of the bit values ​​of each column in the inverted first received least significant bit information and the bit values ​​of each column in the first received most significant bit information corresponding to each column in the inverted first received least significant bit information. In the fourth decoding process of the multi-stage error correction process, the decoding unit performs probability distribution shaping decoding on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information, thereby generating first output bit array information consisting of a bit array of m-1 rows and N columns corresponding to the first input bit array information. In the fifth decoding process of the multi-stage error correction process, the decoding unit extracts information of a predetermined area in the first received most significant bit information, thereby generating second output bit array information consisting of a 1-row N3-column bit array corresponding to the second input bit array information. In the sixth decoding process of the multi-stage error correction process, the decoding unit generates the output information corresponding to the input information based on the first output bit array information and the second output bit array information. The information output unit outputs the output information generated by the decoding unit.

16. A communication system using a soft decision error correction frame data structure, wherein a transmitting device transmits a signal based on input information input to the transmitting device to a receiving device, and the receiving device receives the signal sent by the transmitting device and generates output information corresponding to the input information based on the signal, characterized in that: The soft decision error correction frame data structure is composed of a bit array of m rows and N columns formed by combining the first bit string group information and the second bit string group information. The first bit string group information is composed of a bit array of m rows and N1 columns, and can modulate the combined pulse amplitude of the bit values ​​of each column of the first bit string group information into a modulation symbol based on a predetermined first symbol mapping rule. The second bit string group information is composed of a bit array of m rows and N2 columns, and can modulate the combined pulse amplitude of the bit values ​​of each column of the second bit string group information into a modulation symbol based on a predetermined second symbol mapping rule, wherein m is a natural number greater than 2, N1 is a natural number greater than 2, N2 is a natural number greater than 1, and N is a number obtained by adding N1 and N2. The first row in the second bit string group information stores soft decision parity bits, which are generated by performing systematic soft decision error correction coding processing using the bit values ​​of each column of the mth row in the first bit string group information and the bit values ​​of each column of the mth row in the second bit string group information. The soft decision error correction frame data structure enables the following processing: generating received modulation symbol group information consisting of N received modulation symbols based on a received digital baseband modulation signal, wherein the received digital baseband modulation signal is generated based on a signal based on the soft decision error correction frame information having the soft decision error correction frame data structure; Based on the generated received modulation symbol group information, using the first symbol mapping rule or the second symbol mapping rule, generate first hard decision candidate bit array information consisting of a 1-row N1-column bit array, second hard decision candidate bit array information consisting of an m-2-row N1-column bit array when m is greater than or equal to 3, and third hard decision candidate bit array information consisting of an m-2-row N2-column bit array when m is greater than or equal to 3, Based on the generated received modulation symbol group information, a first a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the first row of the second bit string group information, a second a posteriori L value sequence consisting of N1 a posteriori L values ​​corresponding to each column of the m-th row of the first bit string group information, and a third a posteriori L value sequence consisting of N2 a posteriori L values ​​corresponding to each column of the m-th row of the second bit string group information are generated. performing multi-stage error correction based on the generated first hard decision candidate bit array information, the second hard decision candidate bit array information, the third hard decision candidate bit array information, the first a posteriori L value sequence, the second a posteriori L value sequence, and the third a posteriori L value sequence, thereby performing error correction. Furthermore, the soft decision error correction frame data structure enables the following processing: In the first decoding process of the multi-stage error correction process, soft decision error correction is performed based on the first a posteriori L-value sequence, the second a posteriori L-value sequence, and the third a posteriori L-value sequence, thereby generating inverted first received least significant bit information consisting of a 1-row N1-column bit array and second received least significant bit information consisting of a 1-row N2-column bit array. In the second decoding process of the multi-stage error correction process, first received most significant bit information consisting of a 1-row N1-column bit array is generated based on the first hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, first received SSB information consisting of a m-2-row N1-column bit array is generated based on the second hard decision candidate bit array information and the inverted first received least significant bit information. When m is 3 or greater, second received SSB information consisting of a m-2-row N2-column bit array is generated based on the third hard decision candidate bit array information and the second received least significant bit information. In the third decoding process of the multi-stage error correction process, first reception least significant bit information is generated by calculating an exclusive OR of the bit values ​​of each column in the inverted first reception least significant bit information and the bit values ​​of each column in the first reception most significant bit information corresponding to each column in the inverted first reception least significant bit information. In the fourth decoding process of the multi-stage error correction process, probability distribution shaping decoding is performed on the first received SSB information, the second received SSB information, the first received least significant bit information, and the second received least significant bit information, thereby generating first output bit array information consisting of a bit array of m-1 rows and N columns. In the fifth decoding process of the multi-stage error correction process, information of a predetermined area in the first received most significant bit information is extracted to generate second output bit array information consisting of a 1-row N3-column bit array. In the sixth decoding process of the multi-stage error correction process, the output information corresponding to the input information is generated based on the first output bit array information and the second output bit array information.

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