Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes a first display area and a second display area, the second display area array is provided with a plurality of pixel units, each pixel unit corresponds to a driving circuit, each column of pixel units is connected to the driving circuit through the same data line, the first display area includes a transition area, the second display area includes a hole-digging area, the pixel unit includes a second pixel unit located in the hole-digging area, and the second pixel unit is connected to the driving circuit in the transition area; the data line includes a first routing line, a switching line, and a second routing line, the first routing line is located in the second display area and bypasses the hole-digging area, the second routing line is located in the transition area, the switching line connects the first routing line and the second routing line respectively, and the connection between the switching line and the first routing line is located outside the hole-digging area. The present application will be able to avoid the data lines from being switched out in the normal pixel area to cause mutual interference, while improving the brightness uniformity of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] In order to improve the screen-to-body ratio and aesthetics of display devices, more and more display devices are using Full Display with Camera (FDC) technology. FDC technology refers to removing the opening reserved for the front camera on the screen and building the front camera under the screen. However, when the front camera is placed under the screen, in order to reduce the impact of the screen on the outside light entering the under-screen camera, the pixel circuit corresponding to the pixel unit in the FDC hole is usually moved to the transition area on both sides. The data signal (data) is horizontally wound in the normal display area below the FDC hole to the transition area and connected to the pixel circuit corresponding to the pixel unit in the FDC hole. After the signal is written, it is wound back from the upper frame to the original column of pixels to complete the signal writing to the circuit above the FDC area. However, the data signal winding is too long, resulting in excessive load, which is easy to cause poor dark lines in the column where the FDC hole area is located, and the data signal winding interferes with the pixel circuit in the normal display area. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device.

[0004] The display panel of the embodiment of the present application includes a first display area and a second display area adjacent to each other;

[0005] The second display area array is provided with a plurality of pixel units, each of the pixel units corresponds to a driving circuit, and each column of the pixel units is connected to the driving circuit via a same data line, and the data line is used to provide a data signal to the driving circuit;

[0006] The first display area includes a transition area, the second display area includes a hole-punching area, the transition area is located on both sides of the hole-punching area, the pixel unit includes a second pixel unit located in the hole-punching area, and the second pixel unit is connected to the driving circuit in the transition area;

[0007] The data line includes a first line, a transfer line and a second line. The first line is located in the second display area and bypasses the hole area. The second line is located in the transition area. The transfer line connects the first line and the second line respectively. The connection between the transfer line and the first line is located outside the hole area.

[0008] In some embodiments, the first routing line and the adapter line are formed in different layers, and the adapter line is connected to the first routing line through a via.

[0009] In some embodiments, the adapter line and the second routing line are formed in different layers, and the adapter line is connected to the second routing line through a via.

[0010] In some embodiments, the first trace and the second trace are formed on the same layer.

[0011] In some embodiments, the display panel includes a base substrate, a driving layer and a pixel layer stacked in sequence, the data line and the driving circuit are formed in the driving layer, and the pixel unit is formed in the pixel layer;

[0012] The driving layer includes a first conductive layer and a second conductive layer, the first wiring and the second wiring are formed in the second conductive layer, and the switching line is formed in the first conductive layer.

[0013] In some embodiments, the driving layer further comprises:

[0014] A buffer layer located on the substrate

[0015] A first insulating layer located on the buffer layer away from the substrate;

[0016] A second insulating layer located on a side of the first insulating layer away from the substrate;

[0017] A first planar layer located on a side of the second insulating layer away from the substrate;

[0018] A second flat layer located on a side of the first flat layer away from the substrate;

[0019] The first conductive layer is located between the second insulating layer and the first planar layer, and the second conductive layer is located between the first planar layer and the second planar layer.

[0020] In some embodiments, the driving circuit is formed in the driving layer, and the driving circuit includes:

[0021] A driving transistor and a storage capacitor, wherein the driving transistor comprises:

[0022] a first active layer located on the substrate;

[0023] A first gate located on a side of the first active layer away from the substrate;

[0024] A first insulating layer located on a side of the first gate away from the substrate;

[0025] A second insulating layer located on a side of the first insulating layer away from the substrate;

[0026] A source electrode and a drain electrode located on a side of the second insulating layer away from the substrate and electrically connected to the first active layer;

[0027] Storage capacitors, including:

[0028] A first electrode plate, located at the same layer as the first grid; and

[0029] The second electrode plate is located between the first insulating layer and the second insulating layer.

[0030] The pixel unit comprises:

[0031] In some embodiments, a first electrode, the first electrode is electrically connected to the source electrode;

[0032] A functional layer located on a side of the first electrode away from the substrate;

[0033] The second electrode is located on the side of the functional layer away from the substrate.

[0034] In some embodiments, the pixel layer includes a pixel definition layer, a support layer, and an encapsulation layer that define the pixel unit.

[0035] In some embodiments, the adapter wires of each of the data lines are of equal length.

[0036] In some embodiments, intervals between the transfer lines of adjacent data lines are equal.

[0037] In some embodiments, the first direction is the same as a column arrangement direction of the second pixel units, and the second direction is the same as a row arrangement direction of the second pixel units.

[0038] In some embodiments, the hollow area is circular.

[0039] The display device provided in the embodiment of the present application includes the display panel of the above embodiment.

[0040] In the display panel and display device of the present application, by locating the first routing line of the data line corresponding to the second pixel unit in the second display area and bypassing the hole area, and arranging the second routing line in the transition area, and then connecting the first routing line outside the hole area and connecting the second routing line located in the transition area through a switching line, the data lines are prevented from interfering with each other when they are routed out of the normal pixel area, and the brightness uniformity of the display panel is improved, and the data lines are prevented from interfering with each other when they are routed out of the first display area. At the same time, the length of the data lines can be effectively reduced, thereby avoiding excessive load due to excessively long data lines, and improving the brightness uniformity of the display panel. In addition, there is no need to occupy the space of the upper frame, and the screen-to-body ratio of the display panel is further improved.

[0041] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0043] Figure 1 It is a schematic plan view of a display panel according to an embodiment of the present application.

[0044] Figure 2 yes Figure 1 Section II is a partial enlarged schematic diagram of certain embodiments.

[0045] Figure 3 yes Figure 1 Section II is a partial enlarged schematic diagram of certain embodiments.

[0046] Figure 4 yes Figure 1 Section II is a partial enlarged schematic diagram of certain embodiments.

[0047] Figure 5 yes Figure 2 V in the middle is a partial enlarged schematic diagram of certain embodiments.

[0048] Figure 6 yes Figure 5 VI is a schematic cross-sectional view of certain embodiments.

[0049] Figure 7 yes Figure 1 VII is a schematic cross-sectional view of certain embodiments.

[0050] Figure 8 yes Figure 4 Section VIII is a schematic cross-sectional view of certain embodiments.

[0051] Description of main component symbols:

[0052] Display device 100, display panel 10, first display area 11, transition area 111, second display area 12, hole area 121, first pixel unit 311, second pixel unit 312;

[0053] Data line 15, first wiring 151, adapter line 152, second wiring 153;

[0054] Base substrate 110, driving layer 120, active layer 1201, gate dielectric layer 1202, first insulating layer 1203, second insulating layer 1204, first flat layer 1205, second flat layer 1206, first conductive layer 1207, second conductive layer 1208, driving circuit 21, driving transistor T0, first active layer 1211, first gate 1212, source 1213, drain 1214, storage capacitor C1, first electrode plate 1215, second electrode plate 1216;

[0055] Pixel layer 130, pixel unit 31, first pixel unit 311, second pixel unit 312, first electrode 131, functional layer 132, second electrode 133, pixel defining layer 134, support layer 135, encapsulation layer 136, first organic layer 1361, second organic layer 1362;

[0056] Transparent conductor ITO. DETAILED DESCRIPTION

[0057] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0058] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0059] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0061] Please combine Figure 1-4 The embodiment of the present application provides a display panel 10, which includes a first display area 11 and a second display area 12 adjacent to the first display area 11. The second display area 12 is provided with a plurality of pixel units 31 in an array, each pixel unit 31 corresponds to a driving circuit 21, and each column of pixel units 31 is connected to the same data line 15 through the driving circuit 21, and the data line 15 is used to provide a data signal to the driving circuit 21.

[0062] The first display area 11 includes a transition area 111, the second display area 12 includes a hole area 121, the transition area 111 is located on both sides of the hole area 121, the pixel unit 31 includes a second pixel unit 312 located in the hole area 11, and the second pixel unit 312 is connected to the driving circuit 21 of the transition area 11;

[0063] The data line 15 includes a first line 151, a transfer line 152 and a second line 153. The first line 151 is located in the second display area 12 and bypasses the hole area 121. The second line 153 is located in the transition area 111. The transfer line 152 connects the first line 151 and the second line 153 respectively. The connection between the transfer line 152 and the first line 151 is located outside the hole area 121.

[0064] The present application also provides a display device 100 . The display panel 10 provided in the embodiment of the present application can be applied to the display device 100 in the embodiment of the present application. That is, the display device 100 in the embodiment of the present application can display images through the display panel 10 in the embodiment of the present application.

[0065] In the display panel 10 and the display device 100 of the embodiment of the present application, by locating the first routing line 151 of the data line 15 corresponding to the second pixel unit 312 in the second display area 12 and bypassing the hole area 121, and arranging the second routing line 153 in the transition area 111, and then connecting the first routing line 151 at the edge of the hole area 121 and connecting the second routing line 153 located in the transition area 121 through the adapter line 152, it is avoided that the data line 15 is avoided from rotating out in the normal display area to cause mutual interference, and at the same time, the brightness uniformity of the display panel 10 is improved, and the data line 15 is avoided from rotating out in the first display area 11 and causing mutual interference with the first display area 11. At the same time, the length of the data line 15 can be effectively reduced, thereby avoiding excessive load due to the excessive length of the data line 15, and improving the brightness uniformity of the display panel 10. Since the refresh rate of the display panel 10 is improved, in addition, there is no need to occupy the space of the upper frame, and the screen-to-body ratio of the display panel 10 is further improved.

[0066] Please further combine Figures 1 to 8 , the specific structures of the display panel 10 and the display device 100 are described below.

[0067] In some embodiments, the display device 100 may be a display device 100 that can display images, such as a smart phone, a tablet computer, a smart bracelet, a virtual reality device, a personal data terminal, a laptop computer, etc., but is not limited thereto. For example, in this embodiment, the display device 100 may be illustrated by taking a mobile phone that uses under-screen camera technology as an example.

[0068] The display device 100 also includes optical elements disposed in the display panel 10 , and the optical elements may include but are not limited to photosensitive elements such as cameras, infrared sensors, and fingerprint collectors.

[0069] The display panel 10 may be an OLED display panel 10. The display panel 10 includes a display area, where a plurality of pixel units 31, a plurality of driving circuits 21 and a plurality of data lines 15 are formed.

[0070] Please further combine Figure 1, multiple pixel units 31 are arranged in an array to form multiple rows and columns. The pixel units 31 and the driving circuit 21 both include multiple, each pixel unit 31 is correspondingly provided with a driving circuit 21, the driving circuit 21 is used to drive the pixel unit 31 to emit light, and multiple data lines 15 are arranged in sequence in the display area. The number of data lines 15 is equal to the number of columns of the pixel units 31, that is, each column of pixel units 31 is connected to the same data line 15 through the corresponding driving circuit 21. The data line 15 is used to transmit a data signal to the driving circuit 21 so that the driving circuit 21 drives the corresponding pixel unit 31 to emit light.

[0071] Further, the display area can be divided into a first display area 11 and a second display area 12, wherein the first display area 11 is adjacent to the second display area 12, for example, the first display area 11 can be located on both sides of the second display area 12, and the first display area 11 includes a transition area 111, and the second display area 12 includes a hole area 121, and the transition area 111 is located on both sides of the hole area 121, and the hole area 121 can be an under-screen camera area, and the optical element is arranged in the hole area 121. The hole area 121 can be circular, square, teardrop-shaped, elliptical or other regular or irregular images, that is, the specific shape of the hole area 121 is not limited. In this embodiment, the hole area 121 can be described as a circle, and the diameter of the hole area 121 is smaller than the width of the second display area 12.

[0072] The pixel unit 31 includes a first pixel unit 311 arrayed outside the hole-punching area 121 in the second display area 12 and a second pixel unit 312 arrayed in the hole-punching area 121. The driving circuit 21 corresponding to the first pixel unit 31 is arranged in the area outside the hole-punching area 121 in the second display area 12, and the driving circuit 21 corresponding to the second pixel unit 312 is arranged in the transition area 111 in the first display area 11 on both sides, that is, the driving circuit 21 is not arranged in the hole-punching area 121. It can be understood that since an optical element is arranged in the hole-punching area 121, if the driving circuit 21 is arranged in the hole-punching area 121, it will block the external light from being transmitted to the optical element, causing the optical element to fail to work normally. Therefore, the driving circuit 21 corresponding to the second pixel unit 312 is arranged in the transition area 111 on both sides of the hole-punching area 121.

[0073] Please further combine Figure 2 The data line 15 includes a first wiring 151 , a transfer line 152 and a second wiring 153 .

[0074] Among them, the first lines 151 of the plurality of data lines 15 are sequentially arranged in the second display area 12 along the second direction, and are at least partially arranged around the transition area 111, the second lines 153 are located in the transition area 111, the first lines 151 are at least partially parallel to the second lines 153, and extend along the first direction, the adapter lines 152 extend along the second direction, and the first direction and the second direction can be perpendicular, that is, the first lines 151 are at least partially arranged perpendicular to the adapter lines 152. It should be noted that the first direction can be the column direction (or vertical direction) of the pixel unit, and the second direction can be the row direction (or horizontal direction) of the pixel unit.

[0075] The first wiring 151 is used to connect the driving circuit 21 of the first pixel unit 311, and the second wiring 153 is used to connect the driving circuit 21 corresponding to the second pixel unit 312. The adapter line 152 is a adapter line connecting the first wiring 151 and the second wiring 153, that is, the first wiring 151 is connected to the second wiring 153 located in the transition area 111 through the adapter line 152.

[0076] Furthermore, the first wiring 151 and the adapter line 152 are connected in the second display area 12 outside the hole area 121. In this way, the data line 15 is prevented from being connected out of the first display area 11 and causing mutual interference with the data line 15 and the driving circuit 21 of the first display area 11. At the same time, the length of the data line 15 can be effectively reduced, thereby avoiding excessive load due to the excessive length of the data line 15, thereby improving the brightness uniformity of the display panel 10.

[0077] Please combine Figure 5 and Figure 6 In some embodiments, the first wiring 151 and the adapter 152 are formed in different layers, and the adapter 152 is connected to the first wiring 151 through a via. That is, the first wiring 151 and the adapter 152 are formed in different film layers. It can be understood that the first wiring 151 extends along the first direction, and the adapter 152 extends along the second direction, and the first direction is perpendicular to the second direction. The adapter 152 will have an overlapping area with the first wiring 151 of other data lines 15. Therefore, by arranging the adapter 152 and the first wiring 151 in different layers, the adapter 152 can be prevented from intersecting with the first wiring 151 at the overlapping area. Avoid the adapter 152 from interfering with the first wiring 151 of other data lines 15.

[0078] In some embodiments, the adapter 152 and the second routing line 153 are formed in different layers, and the adapter 152 is connected to the second routing line 153 through a via. That is, the adapter 152 and the second routing line 153 are formed in different film layers. It can be understood that the second routing line 153 extends along the first direction, and the adapter 152 is extended along the second direction, and the first direction is perpendicular to the second direction. Therefore, the adapter 152 may have an overlapping area with the adapter 152 in other data lines 15. Therefore, by arranging the adapter 152 and the second routing line 153 in different layers, the adapter 152 can be prevented from intersecting at the overlapping area with the second routing line 153. It is prevented that the adapter 152 causes interference to the second routing line 153 of other data lines 15.

[0079] In some embodiments, the first trace 151 and the second trace 153 are formed on the same layer.

[0080] It should be noted that the same layer may refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a composition process. Depending on the specific pattern, a composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are composed of the same material and are formed by the same composition process. It can be seen that by setting the film layers included in the above-mentioned first wiring 151 and the second wiring 153 to be located in the same layer, the manufacturing process can be simplified, the manufacturing cost can be saved, and the manufacturing efficiency can be improved.

[0081] Please combine Figure 6 In some embodiments, the display panel 10 includes a base substrate 110, a driving layer 120 and a pixel layer 130 stacked in sequence, the data line 15 and the driving circuit 21 are formed on the driving layer 120, the driving layer 120 includes a first conductive layer 1205 and a second conductive layer 1207, the first routing line 151 and the second routing line 153 are formed on the second conductive layer 1207, and the adapter line 152 is formed on the first conductive layer 1205.

[0082] Specifically, the base substrate 110 may be a flexible substrate. The driving layer 120 includes a buffer layer 1201 , a gate dielectric layer 1202 , a first insulating layer 1203 , a second insulating layer 1204 , a first planar layer 1205 and a second planar layer 1206 .

[0083] Among them, the buffer layer 1201 is formed on the base substrate 110, the gate dielectric layer 1202 is located on the side of the buffer layer 1201 away from the base substrate 110, the first insulating layer 1203 is located on the side of the gate dielectric layer 1202 away from the base substrate 110, the second insulating layer 1204 is located on the side of the first insulating layer 1203 away from the base substrate 110, the first planarizing layer 1205 is located on the side of the second insulating layer 1204 away from the base substrate 110, and the second planarizing layer 1206 is located on the side of the first planarizing layer 1205 away from the base substrate 110.

[0084] The driving layer 120 further includes a first conductive layer 1207 and a second conductive layer 1208 forming the data line 15, wherein the first conductive layer 1207 is located between the second insulating layer 1204 and the first flat layer 1205, and the second conductive layer 1208 is located between the first flat layer 1205 and the second flat layer 1206. The first wiring 151 and the second wiring 153 of the data line 15 are formed in the second conductive layer 1208, and the adapter line 152 is formed in the first conductive layer 1207.

[0085] Furthermore, the first routing 151 includes a first adapter portion, the second routing 153 includes a second adapter portion, the orthographic projection of the first adapter portion on the base substrate 110 at least partially overlaps with the orthographic projection of the adapter line 152 on the base substrate 110, and the orthographic projection of the second adapter portion on the base substrate 110 at least partially overlaps with the orthographic projection of the adapter line 152 on the base substrate 110.

[0086] The first flat layer 1205 is provided with a first via hole 12051 and a second via hole 12052, wherein the first via hole 12051 is located at the overlap of the first adapter portion 1521 and the first wiring 151, and the second via hole 12052 is located at the overlap of the second adapter portion 1252 and the second wiring 153. The first adapter portion at least partially passes through the first via hole 12051 to be connected to the adapter wire 152, and the second adapter portion at least partially passes through the second via hole 12052 to be connected to the adapter wire 152.

[0087] In conjunction with the figures, in some embodiments, a plurality of driving circuits 21 are formed in the driving layer 120 , and at least one driving circuit 21 includes a driving transistor T0 and a storage capacitor C1 .

[0088] The driving transistor T0 includes a first active layer 1211 located on the base substrate 11, a first gate electrode 1212 located on a side of the first active layer 1211 away from the base substrate 11, and a source electrode 1213 and a drain electrode 1214 located on a side of the first gate electrode 1212 away from the base substrate 11 and electrically connected to the first active layer 1211. The first active layer 1211 is provided in the same layer as the gate dielectric layer, for example, the source electrode 1213 and the drain electrode 1214 are electrically connected to the first active layer 1211 through via holes penetrating the second insulating layer 1215, the first insulating layer 1214 and the gate dielectric layer 1212, respectively.

[0089] The storage capacitor C1 includes a first electrode plate 1221 located at the same layer as the first gate 1212, and a second electrode plate 1222 located between the first insulating layer 1214 and the second insulating layer 1215. It should be understood that the storage capacitor C1 also includes a first insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222.

[0090] Please combine Figure 7 or Figure 8 , the pixel unit 31 may be a light emitting diode, for example, an OLED. The pixel unit 31 includes a first electrode 131 (for example, an anode), a functional layer 132 located on a side of the first electrode 131 away from the substrate 11, and a second electrode 133 (for example, a cathode) located on a side of the functional layer 132 away from the substrate 11. Here, the functional layer 132 includes at least a light emitting layer, for example, an organic light emitting layer. In some embodiments, the functional layer 132 may also include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

[0091] Furthermore, please combine Figure 7 When the pixel unit 31 is the first pixel unit 311 , the first electrode 131 may be electrically connected to the drain 1214 of the corresponding driving transistor T0 through the second planar layer 1206 and the first planar layer 1205 .

[0092] Please combine Figure 8The display panel 10 further includes a transparent electrode ITO, which is located on the side of the second flat layer 1206 away from the substrate bottom plate 110. When the pixel unit 31 is the second pixel unit 312, the first electrode 131 can be electrically connected to the transparent electrode ITO, and is electrically connected to the source 1213 of the driving transistor through the transparent electrode ITO through the second flat layer 1206 and the first flat layer 1205. It can be understood that since the driving circuit of the second pixel unit 312 is located in the transition region 111, the first electrode of the second pixel unit 312 is directly connected to the drain 1214 of the corresponding driving transistor T0 through the second flat layer 1206 and the first flat layer 1205. Therefore, the connection between the second pixel unit 312 and the driving circuit 21 can be achieved through the setting of the transparent electrode ITO.

[0093] In some embodiments, see Figure 7 or Figure 8 The pixel layer 130 further includes a pixel defining layer 134 , a supporting layer 127 and an encapsulation layer 136 for defining a plurality of pixel units 31 .

[0094] For example, the pixel defining layer 134 has a plurality of openings corresponding to the plurality of pixel units 31, and the plurality of pixel units 31 are located in the plurality of openings. For example, the encapsulation layer 136 may include a thin film encapsulation layer. In some embodiments, the encapsulation layer 136 may include a first inorganic layer 1361, a second inorganic layer 1362, and an organic layer 1363 located between the first inorganic layer 1361 and the second inorganic layer 1362.

[0095] As some implementations, one or more layers of the second insulating layer 1215, the first insulating layer 1214, the gate dielectric layer 1212, the buffer layer 124, the planarization layer 125, the pixel defining layer 134, and the supporting layer 127 may include an organic insulating material such as polyimide, a resin material, or the like, or an inorganic insulating material including silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0096] In some embodiments, the adapter wires 152 of each data line 15 are of equal length.

[0097] In this way, the load difference of the adapter wire 152 of each data line 15 can be minimized, thereby improving the brightness uniformity of the second display area 12 .

[0098] In some embodiments, the intervals between the transition lines 152 of adjacent data lines 15 are equal.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display panel, It is characterized in that including a first display area and a second display area adjacent to each other; The second display area array is provided with a plurality of pixel units, each of the pixel units corresponds to a driving circuit, and each column of the pixel units is connected to the same data line through the driving circuit, and the data line is used to provide a data signal to the driving circuit; The first display area includes a transition area, the second display area includes a hole-punching area, the transition area is located on both sides of the hole-punching area, the pixel unit includes a second pixel unit located in the hole-punching area, and the second pixel unit is connected to the driving circuit in the transition area; The data line includes a first line, a transfer line and a second line. The first line is located in the second display area and bypasses the hole area. The second line is located in the transition area. The transfer line connects the first line and the second line respectively. The connection between the transfer line and the first line is located outside the hole area.

2. The display panel according to claim 1, It is characterized in that The first routing line and the adapter line are formed in different layers, and the adapter line is connected to the first routing line through a via.

3. The display panel according to claim 2, It is characterized in that The transfer line and the second routing line are formed in different layers, and the transfer line is connected to the second routing line through a via.

4. The display panel according to claim 3, It is characterized in that The first routing line and the second routing line are formed in the same layer.

5. The display panel according to claim 4, It is characterized in that The display panel comprises a base substrate, a driving layer and a pixel layer stacked in sequence, and the pixel unit is formed in the pixel layer; The driving layer includes a first conductive layer and a second conductive layer, the first wiring and the second wiring are formed in the second conductive layer, and the switching line is formed in the first conductive layer.

6. The display panel according to claim 5, It is characterized in that The driving layer also includes: a buffer layer located on the substrate; A gate dielectric layer located on a side of the buffer layer away from the substrate; A first insulating layer located on a side of the gate dielectric layer away from the substrate; A second insulating layer located on a side of the first insulating layer away from the substrate; A first planar layer located on a side of the second insulating layer away from the substrate; A second flat layer located on a side of the first flat layer away from the substrate; The first conductive layer is located between the second insulating layer and the first planar layer, and the second conductive layer is located between the first planar layer and the second planar layer.

7. The display panel according to claim 5, It is characterized in that The driving circuit is formed on the driving layer, and the driving circuit includes: A driving transistor and a storage capacitor, wherein the driving transistor comprises: a first active layer located on the substrate; A first gate located on a side of the first active layer away from the substrate; A first insulating layer located on a side of the first gate away from the substrate; A second insulating layer located on a side of the first insulating layer away from the substrate; A source electrode and a drain electrode located on a side of the second insulating layer away from the substrate and electrically connected to the first active layer; Storage capacitors, including: A first electrode plate, located at the same layer as the first grid; and The second electrode plate is located between the first insulating layer and the second insulating layer.

8. The display panel according to claim 7, It is characterized in that The pixel unit comprises: a first electrode, the first electrode being electrically connected to the source electrode; A functional layer located on a side of the first electrode away from the substrate; The second electrode is located on the side of the functional layer away from the substrate.

9. The display panel according to claim 5, It is characterized in that The pixel layer includes a pixel defining layer, a supporting layer and a packaging layer which define the pixel units.

10. The display panel according to claim 1, It is characterized in that The pixel unit also includes a first pixel unit arranged in an array outside the hole area in the second display area, the first wiring is connected to a driving circuit of the first pixel unit, and the second wiring is connected to a driving circuit of the second pixel unit.

11. The display panel according to claim 1, It is characterized in that The adapter wires of each of the data lines are of equal length.

12. The display panel according to claim 1, It is characterized in that The intervals between the switching wires of adjacent data lines are equal.

13. The display panel according to claim 1, It is characterized in that The hole area includes a circular shape, a square shape, or a teardrop shape.

14. A display device, It is characterized in that The display panel comprises the display panel according to any one of claims 1 to 13, and an optical element located on a non-display surface side of the display panel, wherein the orthographic projection of the optical element on the display panel at least partially overlaps with the hole area.

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