A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, which comprises: a substrate, the substrate having a storage area, a selection area and a peripheral logic area, the storage area being located between the selection area and the peripheral logic area; a tunneling oxide layer, located on the substrate of the storage area; a nitride layer, located on the tunneling oxide layer; a blocking oxide layer, comprising a first part and a second part, the first part being located on the substrate of the selection area and the peripheral logic area, and the second part being located on the nitride layer, the thickness of the first part being greater than the thickness of the second part in the application, so that the thickness requirement of the blocking oxide layer on the selection area and the peripheral logic area is met, and the blocking oxide layer on the storage area has a relatively thin thickness, so as to avoid the reduction of the longitudinal electric field intensity on the storage area, and further ensure the reliability of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory is a kind of charge trap memory, which has the advantages of small cell size, low operating voltage and compatibility with COMS process. Since the emergence of SONOS memory, it has been continuously promoting the development of memory towards miniaturization, large capacity and low cost. However, the existing SONOS memory has the problem of weak vertical electric field, which seriously affects the reliability of the memory. SUMMARY

[0003] The present application aims to provide a semiconductor structure and a preparation method thereof to solve the problem of weak vertical electric field in the existing SONOS memory.

[0004] In order to achieve the above-mentioned purpose, the present application provides a semiconductor structure, comprising:

[0005] a substrate, the substrate having a storage area, a selection area and a peripheral logic area, the storage area being located between the selection area and the peripheral logic area;

[0006] a tunneling oxide layer located on the substrate of the storage area;

[0007] a nitride layer located on the tunneling oxide layer;

[0008] a blocking oxide layer comprising a first part and a second part, the first part being located on the substrate of the selection area and the peripheral logic area, the second part being located on the nitride layer, the thickness of the first part being greater than the thickness of the second part.

[0009] Optionally, the first part comprises a first oxide layer and a second oxide layer, the second oxide layer being located on the first oxide layer, the second part comprising a third oxide layer, the second oxide layer and the third oxide layer being different parts of the same film layer.

[0010] Optionally, the first part comprises a first oxide layer and a second oxide layer, the second oxide layer being located on the first oxide layer, the second part comprising a third oxide layer and a fourth oxide layer, the fourth oxide layer being located on the third oxide layer.

[0011] The first oxide layer and the third oxide layer are different parts of the same film layer, the second oxide layer and the fourth oxide layer are different parts of the same film layer, and the thickness of the fourth oxide layer is less than the thickness of the second oxide layer.

[0012] Optionally, the thickness of the first part is and / or, the thickness of the second part is

[0013] Optionally, further comprising: a high dielectric constant medium layer and a metal layer stacked on the blocking oxide layer in sequence.

[0014] Based on the same inventive concept, the application further provides a preparation method of a semiconductor structure, comprising:

[0015] providing a substrate, the substrate having a storage area, a selection area and a peripheral logic area, the storage area being between the selection area and the peripheral logic area;

[0016] forming a tunnel oxide layer and a nitride layer on the substrate in the storage area in sequence, the nitride layer covering the tunnel oxide layer;

[0017] forming a blocking oxide layer on the substrate, the blocking oxide layer comprising a first part and a second part, the first part being on the substrate in the selection area and the peripheral logic area, the second part being on the nitride layer, the thickness of the first part being greater than the thickness of the second part.

[0018] Optionally, the step of forming the blocking oxide layer comprises:

[0019] forming a first oxide layer on the substrate, the first oxide layer covering the substrate in the selection area and the peripheral logic area;

[0020] simultaneously forming a second oxide layer and a third oxide layer, the second oxide layer covering the first oxide layer, the third oxide layer covering the nitride layer, the first oxide layer and the second oxide layer constituting the first part, and the third oxide layer constituting the second part.

[0021] Optionally, the process of forming the first oxide layer comprises a thermal oxygen process.

[0022] Optionally, the process of forming the second oxide layer and the third oxide layer comprises an in-situ growth process or a low-pressure radical oxidation process.

[0023] Optionally, the step of forming the blocking oxide layer comprises:

[0024] forming a first oxide layer and a third oxide layer on the substrate synchronously, the first oxide layer covering the substrate of the select region and the peripheral logic region, and the third oxide layer covering the nitride layer;

[0025] forming a second oxide layer and a fourth oxide layer synchronously, the second oxide layer covering the first oxide layer, the fourth oxide layer covering the third oxide layer, and the thickness of the fourth oxide layer being less than the thickness of the second oxide layer, the first oxide layer and the second oxide layer constituting the first part, and the third oxide layer and the fourth oxide layer constituting the second part.

[0026] Optionally, the process of forming the first oxide layer and the third oxide layer comprises an in-situ growth process or a low-pressure radical oxidation process.

[0027] Optionally, the process of forming the second oxide layer and the fourth oxide layer comprises a thermal oxidation process.

[0028] In summary, the embodiment of the present application provides a semiconductor structure and a preparation method thereof, which comprises: a substrate, the substrate having a storage region, a select region and a peripheral logic region, the storage region being located between the select region and the peripheral logic region; a tunnel oxide layer located on the substrate of the storage region; a nitride layer located on the tunnel oxide layer; a blocking oxide layer comprising a first part and a second part, the first part being located on the substrate of the select region and the peripheral logic region, and the second part being located on the nitride layer, the thickness of the first part being greater than the thickness of the second part in the present application, so as to meet the requirement of the thickness of the blocking oxide layer on the select region and the peripheral logic region, reduce the thickness of the blocking oxide layer on the storage region, avoid the reduction of the longitudinal electric field intensity on the storage region, and further ensure the reliability of the semiconductor device.

[0029] In addition, in the preparation method of the semiconductor structure, no new mask is added, and no film layer of other material is added, the growth position of the blocking oxide layer is controlled by adjusting the growth process, so as to form the blocking oxide layer with different thicknesses, save the cost, the process is simple, and mass production can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 a flow chart of the preparation method of the semiconductor structure is provided for the embodiment of the present application;

[0031] Figures 2 to 5 a structure schematic diagram corresponding to the corresponding steps of the preparation method of the semiconductor structure provided by the first embodiment of the present application, wherein, Figure 5 a structure schematic diagram of the semiconductor structure provided by the first embodiment of the present application;

[0032] Figures 6 to 7The corresponding structure schematic diagram of the corresponding step of the preparation method of the semiconductor structure provided in Embodiment Two of the present application, wherein, Figure 7 The structure schematic diagram of the semiconductor structure provided in Embodiment Two of the present application;

[0033] In the figure, the reference signs are as follows:

[0034] A - storage area; B - selection area; C - peripheral logic area;

[0035] 100 - substrate; 101 - shallow trench isolation structure; 102 - tunnel oxide layer; 103 - nitride layer; 104 - first oxide layer; 105 - second oxide layer; 106 - third oxide layer; 107 - fourth oxide layer; 108 - high dielectric constant dielectric layer; 109 - metal layer. DETAILED DESCRIPTION

[0036] The substrate of the SONOS memory has a storage area, a selection area and a peripheral logic area, the storage area is between the selection area and the peripheral logic area, and a gate structure is formed on the substrate of the storage area, the selection area and the peripheral logic area. In order to make the memory obtain a better threshold voltage, a high dielectric constant metal gate (HKMG) technology is usually introduced to prepare the gate structure. Specifically, the gate structure on the storage area includes an ONO layer, a high dielectric constant dielectric layer and a metal layer stacked on the substrate in sequence, and the gate structure on the selection area and the peripheral logic area includes a blocking oxide layer, a high dielectric constant dielectric layer and a metal layer stacked on the substrate in sequence, wherein the blocking oxide layer is formed synchronously with the oxide layer above the nitride layer in the ONO layer.

[0037] Since the high dielectric constant layer with a higher dielectric constant such as hafnium dioxide is introduced in the gate structure, it is required that the gate structure on the selection area and the peripheral logic area provides a thicker blocking oxide layer to meet the requirement of the high dielectric constant dielectric layer for ETO (Effective oxide thickness). However, since the blocking oxide layer is formed synchronously with the oxide layer above the nitride layer in the ONO layer, increasing the thickness of the blocking oxide layer will also increase the thickness of the oxide layer above the nitride layer, which makes it difficult for the electrons in the nitride layer to pass through the oxide layer, thereby causing the reduction of the longitudinal electric field strength of the SONOS memory and affecting the reliability of the memory.

[0038] The specific embodiments of the present application will be described in more detail below with reference to the schematic diagrams. According to the following description, the advantages and features of the present application will be more apparent. It should be noted that the figures are very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0039] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It is to be understood that these terms as used herein can be replaced, where appropriate, with one another. Similarly, if the method described herein comprises a series of steps, and the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described can be omitted and / or other steps not described herein can be added to the method.

[0040] Embodiment One

[0041] Figure 5 The structural schematic diagram of the semiconductor structure provided for the embodiment is shown in Figure 5 The semiconductor structure comprises a substrate 100, a tunneling oxide layer 102, a nitride layer 103 and a blocking oxide layer.

[0042] Specifically, the substrate 100 has a storage area A, a selection area B and a peripheral logic area C, the storage area A is located between the peripheral logic area C and the selection area B, and the substrate 100 between the peripheral logic area C and the storage area A has a shallow trench isolation structure 101; the tunneling oxide layer 102 is located on the substrate 100 of the storage area A, and the nitride layer 103 is located on the tunneling oxide layer 102. The blocking oxide layer comprises a first part and a second part, the first part is located on the substrate 100 of the selection area B and the peripheral logic area C, and the second part is located on the substrate 100 of the storage area A, and the thickness of the first part is greater than the thickness of the second part.

[0043] The first part comprises a first oxide layer 104 and a second oxide layer 105, the first oxide layer 104 covers the substrate 100 of the peripheral logic area C and the selection area B, and the second oxide layer 105 is located on the first oxide layer 104. The second part comprises a third oxide layer 106, and the second oxide layer 105 and the third oxide layer 106 are different parts of the same film layer, so the thickness of the second oxide layer 105 and the third oxide layer 106 is the same. The tunneling oxide layer 102, the nitride layer 103 and the third oxide layer 106 constitute an ONO layer.

[0044] The thickness of the first oxide layer 104 is The thickness of the second oxide layer 105 and the third oxide layer 106 is The thickness of the first part is The thickness of the second part is

[0045] Further, the semiconductor structure further comprises a high dielectric constant medium layer 108 and a metal layer 109 stacked on the blocking oxide layer in sequence.

[0046] In the embodiment, the semiconductor structure is formed when the SONOS memory is prepared by using the HKMG preparation technology, the high dielectric constant medium layer 108 is generally a material with high dielectric constant such as hafnium dioxide, and in order to meet the requirement of equivalent oxide thickness (ETO) of the high dielectric constant medium layer 108, the first oxide layer 104 and the second oxide layer 105 are respectively formed on the substrate 100 in the selection region B and the peripheral logic region C to increase the thickness of the first part. Since the storage region A further covers the tunneling oxide layer 102 and the nitride layer 103 compared with the selection region B and the peripheral logic region C, the thickness of the ONO layer only needs to meet the requirement of ETO of the high dielectric constant medium layer 108, and therefore the third oxide layer 106 is only formed on the nitride layer 103, which can not only meet the requirement of ETO of the high dielectric constant medium layer 108 but also thin the thickness of the blocking oxide layer on the nitride layer 103, thereby avoiding the reduction of the longitudinal electric field intensity of the storage region A and ensuring the reliability of the SONOS memory.

[0047] Based on this, the embodiment further provides a preparation method of a semiconductor structure, Figure 1 The semiconductor structure is shown in the flowchart. As shown in the figure, Figure 1 The preparation method of the semiconductor structure comprises the following steps.

[0048] Step S1: providing a substrate, the substrate has a storage region, a selection region and a peripheral logic region, the storage region is located between the selection region and the peripheral logic region;

[0049] Step S2: forming a tunneling oxide layer and a nitride layer on the substrate in the storage region in sequence, the nitride layer covers the tunneling oxide layer;

[0050] Step S3: forming a blocking oxide layer on the substrate, the blocking oxide layer comprises a first part and a second part, the first part is located on the substrate in the selection region and the peripheral logic region, the second part is located on the nitride layer, and the thickness of the first part is greater than the thickness of the second part.

[0051] Figures 2 to 5 The structure schematic diagram of the corresponding steps of the preparation method of the semiconductor structure provided in the embodiment is shown in the figure. Next, the preparation method of the semiconductor structure will be described in detail. Figures 2 to 5

[0052] As shown in the figure, Figure 2 ​As shown, a substrate 100 is provided, the substrate 100 having a storage area A, a selection area B and a peripheral logic area C, the storage area A being located between the selection area B and the peripheral logic area C, and a shallow trench isolation structure 101 being provided in the substrate 100 between the storage area A and the peripheral logic area C.

[0053] In this embodiment, the upper surface of the substrate 100 of the storage area A may be lower than the upper surface of the substrate 100 of the selection area B and the peripheral logic area C, so as to reduce the height difference between subsequent film layers.

[0054] Further, a tunneling oxide layer 102 and a nitride layer 103 are sequentially formed on the substrate 100 of the storage area A, wherein the nitride layer 103 covers the tunneling oxide layer 102.

[0055] like Figure 3 As shown, a first oxide layer 104 is formed on the substrate 100, covering the selected region B and the peripheral logic region C of the substrate 100. The thickness of the first oxide layer 104 is [missing information].

[0056] In this embodiment, the first oxide layer 104 is formed using a thermal oxidation (RTO) process. The RTO process provides high temperature and oxygen conditions to oxidize the silicon on the surface of the substrate 100 to form silicon oxide. Since the materials of the exposed film layers on the surfaces of the memory region A, the select region B, and the peripheral logic region C are different, the silicon nitride layer on the memory region A will not generate silicon oxide during the RTO process. However, the substrate 100 on the select region B and the peripheral logic region C will generate the first oxide layer 104 on its surface under the action of the RTO process. This achieves the formation of the first oxide layer 104 only on the select region B and the peripheral logic region C, eliminating the need for photolithography or polishing processes and saving process steps.

[0057] like Figure 4 As shown, a second oxide layer 105 and a third oxide layer 106 are simultaneously formed on the substrate 100. The second oxide layer 105 covers the first oxide layer 104, and the third oxide layer 106 covers the nitride layer 103. The first oxide layer 104 and the second oxide layer 105 constitute a first portion, and the third oxide layer 106 constitutes a second portion. The first portion and the second portion constitute a barrier oxide layer, and the thickness of the first portion is greater than the thickness of the second portion. The tunneling oxide layer 102, the nitride layer 103, and the third oxide layer 106 on the storage region A constitute an ONO layer.

[0058] The thicknesses of the second oxide layer 105 and the trioxide layer 106 are: The processes for simultaneously forming the second oxide layer 105 and the third oxide layer 106 include in-situ steam generation or low-pressure radical oxidation (LPRO).

[0059] In the SONOS memory, the nitride layer 103 in the ONO layer is used to store electrons. When a voltage is applied to the SONOS memory, electrons in the nitride layer 103 will pass through the tunnel oxide layer 102 or the third oxide layer 106 to achieve the purpose of reading or writing. If the third oxide layer 106 is too thick, it will cause a reduction in the longitudinal electric field strength of the SONOS memory. Therefore, in this embodiment, by adjusting the growth process of the barrier oxide layer, a thinner barrier oxide layer is formed on the storage area A to avoid the reduction in the longitudinal electric field strength of the SONOS memory, thereby ensuring the reliability of the device.

[0060] like Figure 5 As shown, a high dielectric constant dielectric layer 108 and a metal layer 109 are sequentially formed on the barrier oxide layer. The high dielectric constant dielectric layer 108 covers the barrier oxide layer, and the metal layer 109 covers the high dielectric constant dielectric layer 108. The material of the high dielectric constant dielectric layer 108 is an insulating material with a high dielectric constant, such as hafnium dioxide.

[0061] Then, the metal layer 109, the high-dielectric-constant dielectric layer 108, the barrier oxide layer, the nitride layer 103, and the tunnel oxide layer 102 are etched to form gate structures on the memory region A, the select region B, and the peripheral logic region C, respectively. The high-dielectric-constant dielectric layer 108 and the metal layer 109 (HKMG) are used as the gate structure to improve the performance of the SONOS memory. In this embodiment, the thickness of the ONO layer on the memory region A and the thickness of the first portion on the select region B and the peripheral logic region C are both requirements of the high-dielectric-constant material layer for the equivalent oxide (ETO) thickness.

[0062] It should be noted that, due to process limitations, the surface flatness of the nitride layer 103 is poor, and the thickness of the barrier oxide layer is relatively thin. If the barrier oxide layer on the nitride layer 103 is thinned through etching or polishing processes, the nitride layer 103 beneath the barrier oxide layer may be damaged during the etching or polishing process, affecting the device performance of the SONOS memory. The method provided in this embodiment can reduce the thickness of the barrier oxide layer on the nitride layer 103 without damaging the nitride layer 103, thereby improving the reliability of the SONOS memory.

[0063] Example 2

[0064] Figure 7 This is a schematic diagram of the semiconductor structure provided in Embodiment 2 of the present invention. Figure 7 As shown, the difference from Embodiment 1 is that in this embodiment, the first part includes a first oxide layer 104 and a second oxide layer 105, with the second oxide layer 105 located on the first oxide layer 104. The second part of the blocking oxide layer includes a third oxide layer 106 and a fourth oxide layer 107, with the fourth oxide layer 107 located on the third oxide layer 106. The first oxide layer 104 and the third oxide layer 106 are different parts of the same film layer, the second oxide layer 105 and the fourth oxide layer 107 are different parts of the same film layer, and the thickness of the fourth oxide layer 107 is less than the thickness of the second oxide layer 105.

[0065] Wherein, the thickness of the second oxide layer 105 is The thicknesses of the first oxide layer 104 and the third oxide layer 106 are:

[0066] Figures 6 to 7 This is a schematic diagram of the corresponding steps in the semiconductor structure fabrication method provided in Embodiment 2 of the present invention. (See attached diagram.) Figures 6 to 7 The first oxide layer 104 and the third oxide layer 106 are simultaneously formed on the substrate 100 by an in-situ growth process or a low-pressure free radical oxidation process. The first oxide layer 104 covers the substrate 100 of the selected region B and the peripheral logic region C, and the third oxide layer 106 covers the nitride layer 103. Then, the second oxide layer 105 and the fourth oxide layer 107 are simultaneously formed by a thermal oxidation process. The second oxide layer 105 covers the first oxide layer 104, and the fourth oxide layer 107 covers the third oxide layer 106.

[0067] It should be noted that during the thermal oxidation process, since the film materials on the lower surfaces of the first oxide layer 104 and the third oxide layer 106 are different, the growth rates of the second oxide layer 105 and the fourth oxide layer 107 are also different. The growth rate of the fourth oxide layer 107 on the storage area A is much smaller than the growth rate of the second oxide layer 105 on the selection area B and the peripheral logic area C. Furthermore, since the thickness of the second oxide layer 105 is small, the required growth time is short. In a short time, the thickness of the fourth oxide layer 107 grown on the storage area A can be basically ignored.

[0068] In summary, the embodiment of the present application provides a semiconductor structure and a preparation method thereof, which comprises: a substrate 100, the substrate 100 has a storage area A, a selection area B and a peripheral logic area C, the storage area A is located between the selection area B and the peripheral logic area C; a tunnel oxide layer 102 located on the substrate 100 of the storage area A; a nitride layer 103 located on the tunnel oxide layer 102; a blocking oxide layer comprising a first part and a second part, the first part is located on the substrate 100 of the selection area B and the peripheral logic area C, and the second part is located on the nitride layer 103, the thickness of the first part is greater than the thickness of the second part in the present application, which meets the thickness requirement of the blocking oxide layer on the selection area B and the peripheral logic area C, and ensures that the blocking oxide layer on the storage area A has a relatively thin thickness, so as to avoid the reduction of the vertical electric field intensity on the storage area A, and further ensure the reliability of the semiconductor device.

[0069] In addition, in the preparation method of the semiconductor structure, no new mask is added, and no film layer of other materials is added, the growth position of the blocking oxide layer is controlled by adjusting the growth process, so as to form the blocking oxide layer with different thicknesses, save the cost, the process is simple, and mass production can be realized.

[0070] The above is only the preferred embodiment of the present application, and does not limit the present application in any way. Any person skilled in the art can make any equivalent replacement, modification or change of the technical scheme and technical content disclosed in the present application without departing from the scope of the technical scheme of the present application, which still belongs to the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a storage region, a selection region, and a peripheral logic region, wherein the storage region is located between the selection region and the peripheral logic region; The oxide layer is then penetrated and located on the substrate of the storage region; A nitrided layer is located on the tunneling oxide layer; The barrier oxide layer includes a first portion and a second portion, the first portion being located on the substrate of the selected region and the peripheral logic region, the second portion being located on the nitride layer, and the thickness of the first portion being greater than the thickness of the second portion; The first part includes a first oxide layer and a second oxide layer, with the second oxide layer located on the first oxide layer. The second part includes a third oxide layer and a fourth oxide layer, with the fourth oxide layer located on the third oxide layer. The first oxide layer and the third oxide layer are different parts of the same film layer, and the second oxide layer and the fourth oxide layer are different parts of the same film layer. The thickness of the fourth oxide layer is less than the thickness of the second oxide layer.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first part is 55 Å to 71 Å; and / or, the thickness of the second part is 48 Å to 58 Å.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A high dielectric constant dielectric layer and a metal layer are sequentially stacked on the barrier oxide layer.

4. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a storage area, a selection area and a peripheral logic area, the storage area being located between the selection area and the peripheral logic area; A tunneling oxide layer and a nitride layer are sequentially formed on the substrate of the storage area, wherein the nitride layer covers the tunneling oxide layer; A barrier oxide layer is formed on the substrate. The barrier oxide layer includes a first portion and a second portion. The first portion is located on the substrate of the selected region and the peripheral logic region. The second portion is located on the nitride layer. The thickness of the first portion is greater than the thickness of the second portion. The first part includes a first oxide layer and a second oxide layer, with the second oxide layer located on the first oxide layer. The second part includes a third oxide layer and a fourth oxide layer, with the fourth oxide layer located on the third oxide layer. The first oxide layer and the third oxide layer are different parts of the same film layer, and the second oxide layer and the fourth oxide layer are different parts of the same film layer. The thickness of the fourth oxide layer is less than the thickness of the second oxide layer.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, The steps for forming the barrier oxide layer include: A first oxide layer and a third oxide layer are simultaneously formed on the substrate, wherein the first oxide layer covers the substrate of the selected region and the peripheral logic region, and the third oxide layer covers the nitride layer; A second oxide layer and a fourth oxide layer are formed simultaneously. The second oxide layer covers the first oxide layer, and the fourth oxide layer covers the third oxide layer. The thickness of the fourth oxide layer is less than the thickness of the second oxide layer. The first oxide layer and the second oxide layer constitute the first part, and the third oxide layer and the fourth oxide layer constitute the second part.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The process for forming the first oxide layer and the third oxide layer includes in-situ growth process or low-pressure free radical oxidation process.

7. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The process for forming the second oxide layer and the fourth oxide layer includes a thermal oxidation process.

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