An IGBT device with a reverse recovery diode and a manufacturing method thereof

Abstract

The present invention provides an IGBT device with a reverse recovery diode and a preparation method thereof. The IGBT device includes: an NPN doping region, which includes two near-edge regions doped with N+-type doping ions, two sub-edge regions doped with N++-type doping ions, and a central region doped with P+-type doping ions. Among them, the ion concentration of the N++-type doping is greater than that of the N+-type doping. The present invention redefines the arrangement and doping concentration of the fast recovery diode integrated in the IGBT by doping different doping concentrations in the doping region, optimizes the structure of the IGBT integrated with the fast recovery diode, so that while integrating the fast recovery diode, effectively optimizes the current distribution inside the chip, increases the protection ability for the chip, makes the chip more robust, and provides more effective protection for the chip structurally.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBT device preparation, and particularly relates to an IGBT device with a reverse recovery diode and a preparation method thereof. Background Art

[0002] IGBT needs to be used in parallel with a fast recovery diode (FRD). Some IGBTs and fast recovery diodes are implemented on two chips, and are used in parallel through a frame and wire bonding during packaging; another type is to implement both the IGBT and the fast recovery diode on the same chip, as shown in Figure 1 (a) and (b) in the appendix are the IGBT and the fast recovery diode respectively.

[0003] Generally, for the solution of implementing both the IGBT and the fast recovery diode on the same chip, that is, the IGBT integrated with the fast recovery diode, it will occupy the current capacity of the IGBT, and there is no re-optimization of the current distribution, no reasonable arrangement of the current density region, and insufficient protection for the chip. The appendix Figure 2 shows the structure with only the IGBT and no fast recovery diode, and the appendix Figure 3 shows the structure of the IGBT and the fast recovery diode on the same chip.

[0004] Figure 4 For the IGBT without a fast recovery diode, the current is evenly distributed in the body as shown by the dotted arrow; Figure 5 For the IGBT with a fast recovery diode, a region with a lower current density is formed in the region where the fast recovery diode is integrated, and this structure does not provide greater protection for the chip due to the integration of the fast recovery diode.

[0005] Therefore, the existing IGBT with a fast recovery diode does not have the ability to form a reasonable current density distribution, and it is necessary to make improvements. Summary of the Invention

[0006] In view of this, it is necessary to provide an IGBT device with a reverse recovery diode and a preparation method thereof. By optimizing the arrangement and doping concentration of the fast recovery diode integrated in the IGBT, a reasonable distribution of the current density is achieved.

[0007] To achieve the above object, the present invention provides an IGBT device with a reverse recovery diode, including:

[0008] It includes an NPN doping region, and the NPN doping region includes two near-edge regions with N+-type doping ions, two sub-edge regions with N++-type doping ions, and a central region with P+-type doping ions;

[0009] Among them, the ion concentration of the N++-type doping is greater than that of the N+-type doping.

[0010] Preferably, the ions of the N+-type and N++-type dopings are both phosphorus ions, and the ions of the P+-type doping are boron ions.

[0011] Preferably, in the two near-edge regions, the concentration of phosphorus ions is 2E17, and the width is 50 microns; in the two sub-edge regions, the concentration of phosphorus ions is 1E17, and the width is 50 microns; in the central region, the concentration of boron ions is 1E17.

[0012] Preferably, it further includes: an N region and an N-type drift layer provided on the upper part of the NPN doping region, a P-type body region and an N+-type body region in contact with the upper part of the N-type drift layer, and a top metal layer provided on the upper part of the N+-type body region.

[0013] To achieve the above object, the present invention also provides a preparation method of an IGBT device with a reverse recovery diode, including:

[0014] Fabricating a polycrystalline gate on an N-type substrate;

[0015] Activating to form a P-type body region and an N+-type body region by ion implantation;

[0016] Forming contact holes by deposition and photolithography on the upper parts of the N+-type body region and the polycrystalline gate, and forming an ohmic contact, and performing top metal deposition and etching;

[0017] Grinding away the N-type drift region, and implanting ions to activate and form an N-type field stop region, and performing photolithography and exposure on the lower part of the N-type field stop region to form a back P+-implantation region;

[0018] Continuously implanting the P+-type doping ions in the back P+-implantation region to obtain the central region, continuously implanting the N++-type doping ions in the back P+-implantation region to obtain the two sub-edge regions, and continuously implanting the N+-type doping ions in the back P+-implantation region to obtain the two near-edge regions.

[0019] Preferably, the fabricating a polycrystalline gate on an N-type substrate includes:

[0020] Step 1: Using a deep trench mask, forming a deep trench pattern on the wafer of the N-type substrate through a photolithography step;

[0021] Step 2: Using plasma dry etching technology to perform deep trench etching;

[0022] Step 3: Removing the photoresist;

[0023] Step 4: Forming a polycrystalline gate through gate polycrystalline filling and gate polycrystalline back etching.

[0024] Preferably, the P-type body region and the N+ body region are formed by activation through ion implantation, including:

[0025] Step Five: Through boron ion implantation and high-temperature activation, and arsenic ion implantation and high-temperature activation, the emitters of the P-type body region and the N+ body region are respectively formed.

[0026] Preferably, contact holes are formed by deposition and photolithography on the N+ body region and the upper part of the polycrystalline gate, and ohmic contacts are formed, and top metal deposition and etching are performed, including:

[0027] Step Six: Through interlayer film deposition, contact hole photolithography, and contact hole dry etching on the upper part of the N+ body region and the polycrystalline gate, contact holes are formed;

[0028] Step Seven: Through contact hole boron ion implantation, ohmic contacts are formed;

[0029] Step Eight: Top metal deposition and etching are performed to form the gate and the emitter.

[0030] Preferably, the N-type drift region is ground off, and ions are implanted and activated to form an N-type field stop region. Photolithography and exposure are performed below the N-type field stop region to form a back P+ implantation region, including:

[0031] Step Nine: Back thinning is performed to grind off the excess drift region;

[0032] Step Ten: Phosphorus ions are implanted and activated to form an N-type field stop region;

[0033] Step Eleven: Photoresist is coated, and exposure is performed using a P+ photomask. After development, the back P+ implantation region is obtained.

[0034] Preferably, the P+ type doping ions are continuously implanted in the back P+ implantation region to obtain the central region, the N++ type doping ions are continuously implanted in the back P+ implantation region to obtain the two sub-edge regions, and the N+ type doping ions are continuously implanted in the back P+ implantation region to obtain the two near-edge regions, including:

[0035] Step Twelve: The P+ type doping ions are continuously implanted in the back P+ implantation region to obtain the central region, and the central region is the collector;

[0036] Step Thirteen: N++ photolithography, N++ implantation of phosphorus ions, and N++ activation are performed in the back P+ implantation region to form an N++ region, and the two sub-edge regions are obtained;

[0037] Step Fourteen: N+ photolithography, N+ implantation of phosphorus ions, and N+ activation are respectively performed in the back P+ implantation region to form an N+ region, and the two near-edge regions are obtained.

[0038] The beneficial effects of adopting the above embodiments are as follows:

[0039] Through doping with different doping concentrations in the doping region, the present invention redefines the arrangement and doping concentration of the fast-recovery diode integrated in the IGBT, optimizes the structure of the integrated fast-recovery diode IGBT, enables effective optimization of the current distribution inside the chip while integrating the fast-recovery diode, enhances the protection ability of the chip, makes the chip more robust, and provides more effective protection for the chip structurally. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0041] Figure 1 Schematic structural diagrams of an IGBT and a fast-recovery diode in the prior art;

[0042] Figures 2 - 3 Schematic structural diagrams of an IGBT device without integrated fast-recovery diode and an IGBT device with integrated fast-recovery diode in the prior art;

[0043] Figures 4 - 5 Schematic structural diagrams of the current distribution of an IGBT device without integrated fast-recovery diode and an IGBT device with integrated fast-recovery diode in the prior art;

[0044] Figure 6 Schematic structural diagram of an embodiment of an IGBT device with a reverse-recovery diode provided by the present invention;

[0045] Figures 7 - 25 Schematic diagram of the change in the device structure when preparing an IGBT device with a reverse-recovery diode provided by the present invention;

[0046] Figure 26 Schematic structural diagram of the current distribution of an embodiment of an IGBT device with a reverse-recovery diode provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0048] Before presenting the embodiments, a supplementary statement is made regarding the prior art. According to Figure 4 it can be known that the current distribution of IGBT devices without integrated fast recovery diodes in the prior art is uniform and does not affect chip performance. However, the current distribution of IGBT devices with integrated fast recovery diodes in the prior art is non-uniform, specifically manifested as a region with a lower current density formed in the region where the fast recovery diode is integrated. Such a current distribution cannot effectively protect the chip.

[0049] To solve the technical problem that the current distribution of IGBT devices with integrated fast recovery diodes in the prior art is non-uniform and cannot effectively protect the chip, the embodiments of the present invention provide an IGBT device with a reverse recovery diode and a manufacturing method thereof, which will be described separately below.

[0050] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of an embodiment of an IGBT device with a reverse recovery diode provided by the present invention. The IGBT device with a reverse recovery diode includes:

[0051] It includes an NPN doping region, and the NPN doping region includes two near-edge regions with N+-type doped ions, two sub-edge regions with N++-type doped ions, and a central region with P+-type doped ions;

[0052] Among them, the ion concentration of the N++-type doping is greater than that of the N+-type doping.

[0053] Specifically, the two near-edge regions are the 1a region and the 1b region, and their doped ions are N+, referring to relatively concentrated N-type regions; the two sub-edge regions are the 2a region and the 2b region, and their doped ions are N++, referring to more concentrated N-type regions; and the region in the middle is the central region, and its doped ions are P+.

[0054] It can be understood that the more concentrated N-type region obviously has a higher N ion concentration than the relatively concentrated N-type region.

[0055] In some embodiments, the doped ions of the N+-type and N++-type are both phosphorus ions, and the doped ions of the P+-type are boron ions.

[0056] In some embodiments, in the two near-edge regions, the concentration of phosphorus ions is 2E17 and the width is 50 microns; in the two sub-edge regions, the concentration of phosphorus ions is 1E17 and the width is 50 microns; in the central region, the concentration of boron ions is 1E17, and its width is variable and is determined according to the wafer width, the two near-edge regions, and the two sub-edge regions. Specifically, the width of the central region is the difference between the wafer width and the sum of the two near-edge regions and the two sub-edge regions.

[0057] In some embodiments of the present invention, the IGBT device with a reverse recovery diode further includes: an N region 1011 and an N-type drift layer 1012 disposed on the upper part of the NPN doping region, a P-type body region 104 and an N+ body region 105 in contact with the upper part of the N-type drift layer, and a top metal layer 107 disposed on the upper part of the N+ body region 105.

[0058] The IGBT device integrated with a fast recovery diode provided by the present invention redefines the arrangement and doping concentration of the fast recovery diode integrated in the IGBT by doping different doping concentrations in the doping region, optimizes the structure of the IGBT integrated with the fast recovery diode, so that while integrating the fast recovery diode, it effectively optimizes the current distribution inside the chip, increases the protection ability of the chip, makes the chip more robust, and provides more effective protection for the chip structurally.

[0059] In order to solve the technical problem that the current distribution of the IGBT device integrated with a fast recovery diode in the prior art is uneven and cannot effectively protect the chip, the present invention also provides a preparation method of an IGBT device with a reverse recovery diode, including:

[0060] Fabricate a polycrystalline gate 103 on the N-type substrate 101;

[0061] Activate to form a P-type body region 104 and an N+ body region 105 by ion implantation;

[0062] Form contact holes 106 by deposition and photolithography on the upper parts of the N+ body region 105 and the polycrystalline gate 103, and form an ohmic contact, and deposit and etch the top metal 107;

[0063] Grind off the N-type drift region, and implant ions to activate and form an N-type field stop region 108, and perform photolithography and exposure on the lower part of the N-type field stop region 108 to form a back P+ implantation region;

[0064] Continuously implant the P+ type doping ions in the back P+ implantation region to obtain the central region, continuously implant the N++ type doping ions in the back P+ implantation region to obtain the two sub-edge regions, and continuously implant the N+ type doping ions in the back P+ implantation region to obtain the two near-edge regions.

[0065] To specifically illustrate the preparation method of the IGBT device with a reverse recovery diode provided by the embodiments of the present invention, please further refer to Figures 7 - 25 , Figures 7 - 25 which is a schematic diagram of the device structure change when preparing the IGBT device with a reverse recovery diode provided by the present invention.

[0066] In some embodiments of the present invention, preparing the polycrystalline gate 103 on the N-type substrate 101 includes:

[0067] Step 1: As shown in Figure 7 , using a deep trench mask, through a photolithography step, form a pattern of the deep trench 102 on the wafer of the N-type substrate 101;

[0068] Step 2: As shown in Figure 8 , use plasma dry etching technology to etch the deep trench 102;

[0069] Step 3: As shown in Figure 9 , remove the photoresist of the deep trench 102;

[0070] Step 4: As shown in Figure 10 , form the polycrystalline gate 103 through gate polycrystalline filling and gate polycrystalline back etching.

[0071] In some embodiments of the present invention, activating to form the P-type body region 104 and the N+ body region 105 by ion implantation includes:

[0072] Step 5: As shown in Figure 11 , through boron ion implantation and high-temperature activation, and arsenic ion implantation and high-temperature activation, respectively form the emitters of the P-type body region 104 and the N+ body region 105.

[0073] In some embodiments of the present invention, forming contact holes 106 by deposition and photolithography on the upper part of the N+ body region 105 and the polycrystalline gate 103, and constituting an ohmic contact, and performing top metal 107 deposition and etching includes:

[0074] Step 6: As shown in Figure 12 , through interlayer film deposition, contact hole 106 photolithography, and contact hole 106 dry etching on the upper part of the N+ body region 105 and the polycrystalline gate 103, form the contact holes 106;

[0075] Step 7: As shown in Figure 13 , through boron ion implantation through the contact holes 106, form an ohmic contact;

[0076] Step 8: As shown in Figure 14 , perform the deposition and etching of the top layer metal 107 to form the gate and the emitter.

[0077] In some embodiments of the present invention, the N-type drift region is ground away, and ions are implanted and activated to form the N-type field stop region 108. Lithography and exposure are performed below the N-type field stop region 108 to form the back P+ implantation region, including:

[0078] Step Nine: As Figure 15 , perform back thinning to grind away the excess drift region. For a 650V IGBT, the thickness of the drift region is retained at 80 microns.

[0079] Step Ten: As Figure 16 , implant phosphorus ions to activate and form the N-type field stop region 108. The implantation conditions are: phosphorus ions, dose 1E13, energy 1MKev, and then activate through 450 degrees for 60 minutes to form the field stop region.

[0080] Step Eleven: As Figure 17 , apply photoresist coating, perform exposure using a P+ mask, and develop to obtain the back P+ implantation region.

[0081] In some embodiments of the present invention, continuously implant the P+ type doping ions in the back P+ implantation region to obtain the central region, continuously implant the N++ type doping ions in the back P+ implantation region to obtain the two sub-edge regions, and continuously implant the N+ type doping ions in the back P+ implantation region to obtain the two near-edge regions, including:

[0082] Step Twelve: As Figure 18 and Figure 19 , continuously implant the P+ type doping ions in the back P+ implantation region 109 to obtain the central region, and the central region is the collector. The implantation conditions are: boron ions, dose 1E13, energy 40Kev.

[0083] Step Thirteen: As Figure 20 , Figure 21 and Figure 22 , perform N++ lithography, N++ implantation of phosphorus ions, and N++ activation in the back P+ implantation region 109 to form the N++ region and obtain the two sub-edge regions. The implantation conditions are: phosphorus ions, dose 2E17, energy 1Mev; the activation conditions are 400 degrees for 60 minutes.

[0084] Step Fourteen: As Figure 23 , Figure 24 and Figure 25 , respectively perform N+ lithography in the back P+ implantation region, N+ implantation of phosphorus ions, and N+ activation to form the N+ region and obtain the two near-edge regions. The implantation conditions are: phosphorus ions, dose 1E17, energy 1Mev; the activation conditions are 450 degrees for 60 minutes.

[0085] It should be noted that the core inventive concept of the present invention is from step twelve to step fourteen, which requires three backside lithographies. First, the P+ region is defined for ion implantation, and after activation, the P+ region is formed; then, N++ lithography is performed to define the N++ implantation region, and the N++ region is formed through phosphorus ion implantation and activation; finally, N+ lithography is used to define the N+ implantation region, and the N+ region is formed through phosphorus ion implantation and activation. Finally, a structure with three juxtaposed regions of P+, N++, and N+ is formed on the backside, realizing the reasonable distribution of the chip current, and while integrating the fast recovery diode, effectively protecting the chip.

[0086] In summary, the preparation method of the IGBT device with an integrated fast recovery diode provided by the present invention redefines the arrangement and doping concentration of the fast recovery diode integrated in the IGBT by doping different doping concentrations in the doping regions, optimizes the structure of the IGBT with the integrated fast recovery diode, so that while integrating the fast recovery diode, effectively optimizes the current distribution inside the chip, increases the protection ability of the chip, makes the chip more robust, and provides more effective protection for the chip structurally.

[0087] The IGBT device with a reverse recovery diode provided by the present invention has been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A preparation method of an IGBT device with a reverse recovery diode, characterized in that, The IGBT device with a reverse recovery diode includes an NPN doping region, which includes two near-edge regions doped with N+-type doping ions, two sub-edge regions doped with N++-type doping ions, and a central region doped with P+-type doping ions. The sub-edge regions are located between the near-edge regions and the central region. Among them, the ion concentration of the N++-type doping is greater than that of the N+-type doping. The preparation method includes: Preparing a polycrystalline gate on an N-type substrate. Activating to form a P-type body region and an N+ body region by ion implantation. Forming contact holes by deposition and photolithography on the N+ body region and the polycrystalline gate, and performing top metal deposition and etching to form an ohmic contact. Grinding off part of the N-type substrate and implanting ions to activate and form an N-type field termination region. Performing photolithography and exposure on the lower part of the N-type field termination region to form a back P+ implantation region. Continuously implanting the P+-type doping ions in the back P+ implantation region to obtain the central region, continuously implanting the N++-type doping ions outside the back P+ implantation region to obtain the two sub-edge regions, and continuously implanting the N+-type doping ions outside the back P+ implantation region to obtain the two near-edge regions.

2. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 1, characterized in that, The doping ions of the N+-type and N++-type are both phosphorus ions, and the doping ions of the P+-type are boron ions.

3. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 2, characterized in that, In the two near-edge regions, the concentration of phosphorus ions is 1E17 cm⁻³, and the width is 50 microns; in the two sub-edge regions, the concentration of phosphorus ions is 2E17 cm⁻³, and the width is 50 microns; in the central region, the concentration of boron ions is 1E17 cm⁻³.

4. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 1, characterized in that, The IGBT device with a reverse recovery diode includes: an N-type field termination region and an N-type drift layer arranged on the upper part of the NPN doping region, a P-type body region and an N+ body region in contact with the upper part of the N-type drift layer, and a top metal layer arranged on the upper part of the N+ body region.

5. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 1, characterized in that, The preparation of the polycrystalline gate on the N-type substrate includes: Step 1: Using a deep trench mask, forming a deep trench pattern on the wafer of the N-type substrate through a photolithography step. Step 2: Using plasma dry etching technology to perform deep trench etching. Step 3: Removing the photoresist. Step 4: Forming a polycrystalline gate through gate polycrystalline filling and gate polycrystalline back etching.

6. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 5, characterized in that, Activating to form a P-type body region and an N+ body region by ion implantation includes: Step 5: Forming the emitters of the P-type body region and the N+ body region respectively through boron ion implantation, high-temperature activation, arsenic ion implantation, and high-temperature activation.

7. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 6, characterized in that, Forming contact holes by deposition and photolithography on the N+ body region and the polycrystalline gate, and performing top metal deposition and etching to form an ohmic contact includes: Step 6: Forming contact holes by interlayer film deposition, contact hole photolithography, and contact hole dry etching on the upper part of the N+ body region and the polycrystalline gate. Step 7: Contact hole boron ion implantation. Step 8: Performing top metal deposition and etching to form the gate and the emitter.

8. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 7, characterized in that Grinding off part of the N-type substrate and implanting ions to activate and form an N-type field termination region. Performing photolithography and exposure on the lower part of the N-type field termination region to form a back P+ implantation region includes: Step 9: Performing back thinning to grind off the excess N-type substrate. Step Ten: Inject phosphorus ions to activate and form an N-type field termination region; Step Eleven: Apply photoresist, expose it using a P+ photomask, and develop it to obtain a back P+ implantation region.

9. The manufacturing method of the IGBT device with a reverse recovery diode according to claim 8, characterized in that, Continuously implant the P+-type doping ions within the back P+ implantation region to obtain the central region, continuously implant the N++-type doping ions outside the back P+ implantation region to obtain the two sub-edge regions, and continuously implant the N+-type doping ions outside the back P+ implantation region to obtain the two near-edge regions, including: Step Twelve: Continuously implant the P+-type doping ions within the back P+ implantation region to obtain the central region, and the central region is the collector; Step Thirteen: Perform N++ lithography, N++ implantation of phosphorus ions, and N++ activation outside the back P+ implantation region to form an N++ region and obtain the two sub-edge regions; Step Fourteen: Perform N+ lithography outside the back P+ implantation region respectively, N+ implantation of phosphorus ions, and N+ activation to form an N+ region and obtain the two near-edge regions.

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