Method for reducing reverse recovery loss of bidirectional conduction GaN power device

Abstract

The invention provides a method for reducing reverse recovery loss of a bidirectional conduction GaN power device, belongs to the technical field of chip design, and analyzes a Miller capacitance value generated in a grid electrode and drain electrode overlapping region through finite element simulation. Designing grid electrode and drain electrode structures with different sizes, accurately controlling a spacing parameter and calculating an overlapping rate; a double-field-plate structure is adopted, and a Nash equilibrium game model is applied to analyze the relation between the field plate length and the parasitic capacitance. The multi-finger gate structure is utilized to reduce the gate resistance value per unit area and disperse the parasitic capacitance. The reverse recovery characteristic is measured through the test circuit, the charge and discharge current waveform of the capacitor is analyzed, and the influence factor of the parasitic capacitance on the reverse recovery loss is calculated. An optimization model is established based on test data, a parameter decision space is constructed by applying a Pareto optimization method, and meanwhile, reverse recovery loss and on resistance are optimized, so that the technical problem that the reverse recovery loss of a bidirectional conduction GaN power device is too high is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a method for reducing reverse recovery loss of a bidirectionally conducting GaN power device. Background Art

[0002] Bidirectionally conducting gallium nitride (GaN) power devices are widely used in power electronics conversion systems due to their high-frequency switching performance and low on-resistance. Traditional bidirectionally conducting GaN power device design focuses primarily on forward conduction performance and voltage withstand capability. By optimizing device structure to reduce on-resistance and increase breakdown voltage, various technology approaches have emerged, including enhancement-mode high-electron-mobility transistors (E-HEMTs) and gate injection transistors (GITs). These devices show great application prospects in high-frequency power systems, automotive electronics, and industrial control.

[0003] However, conventional GaN power devices suffer from significant power loss during reverse recovery. This is primarily due to the Miller effect caused by the parasitic capacitance between the gate and drain (Cgd) during high-voltage switching, which leads to additional current paths and energy consumption during the reverse recovery phase. Particularly in high-frequency switching applications, reverse recovery loss significantly increases the proportion of total power loss, becoming a bottleneck limiting device efficiency.

[0004] Existing technologies attempt to address this issue by modifying the gate structure or adding a field plate structure, but these approaches often compromise one over the other, making it difficult to simultaneously reduce reverse recovery losses and maintain low on-resistance. In particular, the lack of a systematic approach to precisely control the gate-drain overlap region, as well as in-depth analysis of the relationship between reverse recovery mechanisms and parasitic capacitance, makes it difficult for existing technologies to effectively address the high reverse recovery losses in bidirectionally conducting GaN power devices. Summary of the Invention

[0005] In view of this, the present invention provides a method for reducing the reverse recovery loss of a bidirectionally conducting GaN power device, which can solve the technical problem of excessively high reverse recovery loss of a bidirectionally conducting GaN power device in the prior art.

[0006] The present invention is implemented as follows: The present invention provides a method for reducing the reverse recovery loss of a bidirectionally conducting GaN power device, comprising: establishing a precise electrical model of the bidirectionally conducting GaN power device, analyzing the Miller capacitance value generated in the gate-drain overlap region; designing multiple sets of gate and drain structures, controlling the gate-drain spacing parameters, measuring the parasitic capacitance value, and calculating the ratio of the necessary overlap rate to the unnecessary overlap rate; using a double field plate structure technology to form an electric field distribution optimization region, and analyzing the relationship between the field plate length and the parasitic capacitance through a Nash equilibrium game model; using an extended gate structure technology to design the gate into a multi-finger structure; constructing a test circuit to measure the reverse recovery characteristics of the device; analyzing the capacitor charge and discharge current waveform; establishing a reverse recovery loss optimization model; preparing device samples and verifying the effectiveness of the optimized structure; iteratively optimizing and ultimately determining process parameters to guide the reduction of the reverse recovery loss of the bidirectionally conducting GaN power device.

[0007] Among them, the establishment of a precise electrical model of a bidirectionally conducting gallium nitride power device and the analysis of the Miller capacitance value generated in the gate-drain overlap region refer to analyzing the Miller capacitance value generated in the gate-drain overlap region through finite element simulation, wherein the Miller capacitance value refers to the value of the negative feedback effect caused by the overlapping capacitance between the gate and the drain during the high-voltage switching process. The Miller capacitance value will cause additional current paths to be generated during the switching process, increasing power loss.

[0008] Among them, the design of multiple sets of gate and drain structures, controlling the gate and drain spacing parameters, measuring the parasitic capacitance value, and calculating the ratio of necessary overlap rate to unnecessary overlap rate means precisely controlling the gate and drain spacing parameters from 25μm to 75μm, measuring the corresponding parasitic capacitance value, and calculating the ratio of necessary overlap rate to unnecessary overlap rate.

[0009] The required overlap ratio refers to the ratio of the minimum overlap area between the gate and drain to the total overlap area that must be maintained to ensure the basic electrical characteristics and reliability of the bidirectionally conducting gallium nitride power device. The required overlap ratio is used to determine the lower limit of the gate-drain spacing parameter.

[0010] Among them, the non-essential overlap ratio refers to the ratio of the overlapping area between the gate and the drain to the total overlapping area reduced by optimized design without affecting the basic function of the device. The non-essential overlap ratio is used to determine the optimization space of the gate-drain spacing parameters.

[0011] Among them, the use of double field plate structure technology to form an electric field distribution optimization area and the analysis of the relationship between the field plate length and parasitic capacitance through the Nash equilibrium game model refers to setting a first field plate and a second field plate with a length of 5μm to 15μm on the source side and the gate side respectively to form an electric field distribution optimization area, and analyzing the relationship between the field plate length and parasitic capacitance through the Nash equilibrium game model.

[0012] Among them, the Nash equilibrium game model refers to the design of the field plate structure, in which the reverse recovery performance and the voltage resistance are regarded as two rational game parties. Each game party attempts to maximize its own utility function and reach an equilibrium state without cooperation. The Nash equilibrium game model is used to determine the optimal parameter combination of the field plate structure.

[0013] Among them, the use of extended gate structure technology to design the gate into a multi-finger structure means designing the gate into a multi-finger structure, controlling the gate finger width in the range of 2μm to 6μm, and maintaining the gate finger spacing between 3μm to 8μm, thereby reducing the gate resistance value per unit area and the dispersed parasitic capacitance value.

[0014] Among them, the multi-finger structure refers to dividing a single wide gate into multiple parallel narrow gate fingers, which increases the total circumference of the gate, reduces the gate resistance per unit area, and disperses the parasitic capacitance between the gate and the drain. The multi-finger structure is used to improve the switching characteristics of the device.

[0015] Among them, the construction of a test circuit to measure the reverse recovery characteristics of the device refers to constructing a bidirectional conduction test circuit to measure the reverse recovery time and reverse recovery loss of the device under 350V / 10A working conditions under different structural designs, and analyzing the carrier migration characteristics through the Coulomb scattering relaxation time equation.

[0016] This invention systematically addresses the issue of excessive reverse recovery losses by establishing a precise electrical model, optimizing the gate-drain structure, and employing dual field plate technology and an extended gate structure. This method precisely controls the gate-drain separation, scientifically analyzes the ratio of necessary to unnecessary overlap, and combines a Nash equilibrium game model to determine the optimal field plate parameters, forming a comprehensive device structure optimization strategy.

[0017] Through multi-finger gate structure design and Coulomb scattering relaxation time analysis, this invention effectively reduces the gate resistance per unit area, while also distributing the parasitic capacitance distribution, significantly reducing power losses caused by the Miller effect. The application of Pareto optimization methods balances the two mutually constrained parameters of reverse recovery loss and on-resistance, achieving comprehensive optimization of device performance. This addresses the technical issue of excessive reverse recovery loss in bidirectionally conducting GaN power devices, significantly reduces energy consumption under high-frequency switching conditions, and improves device efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of the method of the present invention.

[0019] Figure 2 Schematic diagram of the overall structure of the bidirectionally conducting GaN power device in Example 2.

[0020] Figure 3 Schematic diagram of the field plate structure of the bidirectionally conducting GaN power device in Example 2.

[0021] Figure 4 Schematic top view of the multi-finger gate structure of the bidirectionally conducting GaN power device in Example 2.

[0022] Figure 5 Schematic cross-sectional view of the multi-finger gate structure of the bidirectionally conducting GaN power device in Example 2.

[0023] Figure 6 Detailed schematic diagram of the gate-drain overlap region of the bidirectionally conducting GaN power device in Example 2.

[0024] Figure 7 Schematic diagram of the reverse recovery characteristics test circuit of the bidirectionally conducting GaN power device in Example 2. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] like Figure 1 FIG. 1 is a flow chart of a method for reducing reverse recovery loss of a bidirectionally conducting GaN power device provided by the present invention. The method comprises the following steps:

[0027] S01. Finite Element Analysis: Establish an accurate electrical model of a bidirectionally conducting GaN power device and analyze the Miller capacitance generated in the gate-drain overlap region through finite element simulation.

[0028] S02. Determine the gate and drain structure: Design multiple gate and drain structures of different sizes, and measure the corresponding parasitic capacitance C by precisely controlling the gate and drain spacing parameters from 25μm to 75μm. gd The ratio of the necessary overlap ratio to the unnecessary overlap ratio is calculated, where the necessary overlap ratio is defined as the percentage of the gate-drain overlap area required to maintain the basic function of the device to the total overlap area, and the unnecessary overlap ratio is defined as the percentage of the overlap area eliminated by structural optimization to the total overlap area;

[0029] S03. Determine the optimal parameter combination: Use the double field plate structure technology, set the first field plate and the second field plate with a length of 5μm to 15μm on the source side and the gate side respectively, to form an optimized electric field distribution area, and analyze the relationship between the field plate length and the parasitic capacitance C through the Nash equilibrium game model. gd The relationship between the reverse recovery loss E rrThe pressure resistance is used as the utility function of the two game participants, and the optimal parameter combination of the field plate structure is determined by finding the optimal solution of the utility function of both parties;

[0030] S04. Gate structure expansion: Using the extended gate structure technology, the gate is designed into a multi-finger structure, with the gate finger width controlled in the range of 2μm to 6μm and the gate finger spacing maintained between 3μm and 8μm, reducing the gate resistance per unit area and the dispersed parasitic capacitance C gd value;

[0031] S05. Reverse test: Construct a bidirectional conduction test circuit and measure the reverse recovery time t of the device under 350V / 10A working conditions under different structural designs. rr and reverse recovery loss E rr and analyze the carrier migration characteristics through the Coulomb scattering relaxation time equation;

[0032] S06. Data analysis: Analyze the capacitor charging and discharging current waveform during the reverse recovery process and calculate the parasitic capacitance C under different structural designs. gd Value and reverse recovery loss E rr The correlation coefficient between them is used to obtain the parasitic capacitance C gd Value for reverse recovery loss E rr Impact factor;

[0033] S07, Optimization solution: Based on the test data, a reverse recovery loss optimization model is established, and the parameter decision space is constructed through the Pareto optimization method. At the same time, the reverse recovery loss E is optimized. rr and on-resistance R DS(on) Two mutually constrained goals: determining the optimal gate-drain spacing parameters, field plate length parameters, and gate finger structure parameters;

[0034] S08. Experimental Verification: Design and prepare bidirectionally conducting GaN power device samples with reduced reverse recovery loss based on the optimization model. Apply the optimal gate-drain spacing parameters, the field plate length parameters, and the gate finger structure parameters to the device fabrication process, and conduct experimental verification under 350V / 20A conditions.

[0035] S09. Obtain the optimal process parameters: By comparing and analyzing the total loss of samples at different switching frequencies, verify that the optimized structure has the effect of reducing the reverse recovery loss E rr The effectiveness of the verification is evaluated, and the verification results are fed back to the precise electrical model in step S01 for iterative optimization, and the process parameters are finally determined to guide the reduction of reverse recovery loss of bidirectionally conducting GaN power devices.

[0036] The Miller capacitance value specifically refers to the value of the negative feedback effect caused by the overlapping capacitance between the gate and the drain during high voltage switching. The Miller capacitance value may cause an additional current path to be generated during the switching process, thereby increasing power loss.

[0037] Among them, the parasitic capacitance C gd The value specifically refers to the value of the parasitic capacitance formed between the gate and the drain. The parasitic capacitance C gd The values are obtained through measurement in step S02 and used as key parameters for structural optimization analysis in steps S03 to S07.

[0038] Among them, the reverse recovery time t rr Specifically, it refers to the delay time caused by the minority carrier storage effect during the process of bidirectionally conducting GaN power devices changing from the on state to the blocking state. rr Obtained through testing in step S05 and used to calculate the reverse recovery loss E in step S06 rr .

[0039] Among them, the reverse recovery loss E rr Specifically refers to the power loss generated during the reverse recovery process of the bidirectionally conducting GaN power device, the reverse recovery loss E rr By measuring the product of reverse recovery current and drain-source voltage during reverse recovery time t rr The integral within is obtained and used as the optimization target in steps S05 to S09.

[0040] Among them, the on-resistance R DS(on) Specifically refers to the resistance value between the drain and source of the bidirectionally conductive GaN power device in the on state. The on resistance R DS(on) In step S04, it is affected by the gate finger structure and is used as one of the optimization targets in step S07.

[0041] The required overlap ratio specifically refers to the ratio of the minimum overlap area that must be maintained between the gate and the drain to the total overlap area in order to ensure the basic electrical characteristics and reliability of the bidirectionally conducting gallium nitride power device. The required overlap ratio is obtained by calculation in step S02 and is used to determine the lower limit of the gate-drain spacing parameter.

[0042] Among them, the non-essential overlap rate specifically refers to the ratio of the overlapping area between the gate and the drain that is reduced through optimized design to the total overlapping area without affecting the basic function of the device. The non-essential overlap rate is obtained by calculation in step S02 and is used to determine the optimization space of the gate-drain spacing parameters.

[0043] The multi-finger structure specifically refers to dividing a single wide gate into multiple parallel narrow gate fingers, which increases the total perimeter of the gate, reduces the gate resistance per unit area, and disperses the parasitic capacitance C between the gate and the drain. gd value, the multi-finger structure is designed and implemented in step S04 to improve the switching characteristics of the device.

[0044] Among them, the Coulomb scattering relaxation time equation specifically refers to a physical equation that describes the scattering behavior of carriers in gallium nitride semiconductor materials under high electric fields and its influence on the reverse recovery characteristics. The input of the Coulomb scattering relaxation time equation includes five parameters: carrier concentration, lattice temperature, impurity concentration, electric field strength, and dielectric constant of the material. The output is the effective mobility of the carriers and the Coulomb scattering relaxation time. These output parameters are used to analyze the minority carrier recombination rate and parasitic capacitance C during the reverse recovery process. gd The charge and discharge characteristics of the value.

[0045] Among them, the influencing factor specifically refers to the parasitic capacitance C gd The effect of the value change on the reverse recovery loss E rr The sensitivity coefficient of the change, the influencing factor is obtained by calculation in step S06 and is used for weight distribution in step S07.

[0046] The Pareto optimization method specifically refers to finding a set of solutions in a multi-objective optimization problem so that the improvement of any one objective will inevitably lead to the deterioration of at least one other objective. The Pareto optimization method is used in step S07 to simultaneously optimize the reverse recovery loss E rr and on-resistance R DS(on) Two mutually constrained parameters.

[0047] Specifically, the Nash equilibrium game model refers to treating reverse recovery performance and voltage resistance as two rational players in the field plate structure design, each of which attempts to maximize its own utility function and reach an equilibrium state without cooperation. The Nash equilibrium game model is used in step S03 to determine the optimal parameter combination of the field plate structure.

[0048] The gate-drain spacing parameter specifically refers to the physical distance between the gate edge and the drain edge. The gate-drain spacing parameter is designed in step S02, the optimal value is determined by optimization in step S07, and the optimal value is applied to device preparation in step S08.

[0049] The field plate length parameter specifically refers to the physical length values of the first field plate and the second field plate. The field plate length parameter is designed in step S03, the optimal value is determined by optimization in step S07, and applied to device preparation in step S08.

[0050] The gate finger structure parameters specifically refer to the numerical combination of gate finger width and gate finger spacing in the multi-finger structure. The gate finger structure parameters are designed in step S04, the optimal values are determined by optimization in step S07, and applied to device preparation in step S08.

[0051] The specific implementation of the above steps is described in detail below.

[0052] The specific implementation of step S01 is as follows: A three-dimensional model of a bidirectionally conducting GaN power device is constructed using finite element analysis software. First, the device geometric parameters, including gate width, thickness, drain size, source location, and GaN material layer thickness, are imported. Material physical parameters, including GaN dielectric constant, carrier mobility, saturation velocity, and other physical quantities, are then set. A finite element meshing algorithm is then applied to mesh the model, with a focus on increasing the mesh density in the gate-drain overlap region, with the mesh cell size controlled to below 0.1 μm. An electric field distribution calculation model is then established, and the potential distribution is calculated using a Poisson equation solver. The electric field distribution in the gate-drain overlap region is determined based on the potential gradient. Finally, the Miller capacitance is calculated based on the electric field distribution. This capacitance exhibits a nonlinear relationship with gate-drain voltage. Under conditions of a gate voltage of 2 V and a drain voltage of 200 V, the typical Miller capacitance ranges from 50 to 120 pF. This step utilizes the finite element method to accurately simulate the electric field distribution in the device and calculate the Miller capacitance, providing a theoretical basis for subsequent structural optimization.

[0053] The specific implementation of step S02 is as follows: design six groups of structures with gate-drain spacing of 25μm, 35μm, 45μm, 55μm, 65μm, and 75μm, respectively, and make test samples; use an impedance analyzer at a frequency of 1MHz, apply a small signal excitation voltage of 0.1V, and measure the parasitic capacitance C under different gate-drain spacings. gd value; Based on the measurement results, establish the gate-drain spacing distance and parasitic capacitance C gd The relationship curve between the gate-drain capacitance and the capacitance value was plotted. The electromagnetic boundary element method was used to analyze the gate-drain overlap area, dividing the total overlap area into the necessary overlap required to maintain basic functionality and the unnecessary overlap area that can be eliminated through structural optimization. The ratio of the necessary overlap rate to the unnecessary overlap rate was calculated. When the gate-drain spacing was 45μm, the necessary overlap rate was approximately 40% and the unnecessary overlap rate was approximately 60%. Based on the calculation results, the optimal gate-drain spacing range was determined to be 40-50μm. This step, through systematic measurement and analysis, determined the influence of the gate-drain spacing on parasitic capacitance, providing data support for structural optimization.

[0054] The specific implementation of step S03 is as follows: designing a first field plate with a length of 5μm, 10μm, and 15μm on the source side, and designing a second field plate with a length of 5μm, 10μm, and 15μm on the gate side, forming nine different combinations of double field plate structures; using electric field simulation software to calculate the electric field distribution under different field plate structures, focusing on analyzing the electric field peak value and electric field distribution uniformity at the edge of the field plate; measuring the withstand voltage value and parasitic capacitance C of the device under different field plate structures gd value; establish a Nash equilibrium game model and reverse recovery loss E rr As the utility function of the first player, the withstand voltage capability is the utility function of the second player; the strategy space of the two players is defined as the field plate length parameter combination; the utility value of the two players under each strategy combination is calculated to construct a utility matrix; the Nash equilibrium point is solved by the iterative approximation algorithm, and the parameter combination with the optimal length of the first field plate of 10μm and the optimal length of the second field plate of 8μm is obtained. At this time, the electric field peak is reduced by 32%, and the parasitic capacitance C is 0. gd The increase should not exceed 15%. This step uses game theory to analyze the impact of the field plate structure on device performance and find a balance between withstand voltage and parasitic capacitance.

[0055] The specific implementation of step S04 is as follows: designing nine multi-finger gate structures with gate finger widths of 2μm, 4μm, and 6μm, and gate finger spacings of 3μm, 5μm, and 8μm; using semiconductor process design software to establish a layout model of the multi-finger gate and calculate the total gate perimeter under different gate finger structures; using a distributed gate resistance network model to analyze the impact of the multi-finger structure on the gate resistance; and measuring the on-resistance R of the device under different gate finger structures. DS(on) and parasitic capacitance C gd The influence of multi-finger structure on parasitic capacitance distribution is analyzed by using high-frequency equivalent circuit model. According to the measurement results, when the gate finger width is 4μm and the gate finger spacing is 5μm, the gate resistance per unit area decreases by 42%, and the parasitic capacitance C gd The dispersion effect is optimal, and the switching speed is increased by 25%. This step improves the switching performance of the device by optimizing the gate finger structure, reducing gate resistance, and dispersing parasitic capacitance.

[0056] The specific implementation of step S05 is as follows: design a bidirectional conduction test circuit, including a main circuit power supply, a resistive load, a test sample, and a drive circuit; set the test conditions to a drain-source voltage of 350V, a conduction current of 10A, a gate-source drive voltage of 0V to 15V, and a switching frequency of 100kHz; use a high-bandwidth oscilloscope and a current probe to measure the drain-source voltage V during the reverse recovery process. DS and drain current I D Waveform; record reverse recovery time t rr , that is, the time interval from the beginning of the reverse current decrease to the time it drops to 10% of the peak value; measure the reverse recovery peak current Irrm and reverse recovery charge Q rr ; Apply the Coulomb scattering relaxation time equation to analyze the carrier migration characteristics, and its input parameters include carrier concentration 10 17 cm -3 , lattice temperature 25 ° C, impurity concentration 5 × 10 16 cm -3 , an electric field strength of 3 MV / cm, and a GaN dielectric constant of 8.9; calculate the effective carrier mobility and Coulomb scattering relaxation time, analyze carrier behavior during reverse recovery; measure samples with different structural designs and record reverse recovery parameters. This step obtains device reverse recovery characteristic data through actual testing, providing a basis for subsequent optimization.

[0057] The specific implementation of step S06 is: collecting the capacitor charging and discharging current waveforms of different structural design samples during the reverse recovery process; using a spectrum analyzer, performing Fourier transform on the current waveform to analyze its frequency domain characteristics; calculating the reverse recovery loss E according to the current waveform and voltage waveform rr , that is, the integral value of the product of current and voltage during the reverse recovery time; establish the parasitic capacitance C gd Value and reverse recovery loss E rr Data set; Apply the Pearson correlation coefficient method to calculate the parasitic capacitance C gd Value and reverse recovery loss E rr The correlation coefficient between the parasitic capacitance C gd When the capacitance changes within the range of 50 to 150 pF, the correlation coefficient reaches 0.86, indicating that the two have a significant positive correlation. Through linear regression analysis, the parasitic capacitance C gd Value for reverse recovery loss E rr The influence factor is 0.78, that is, the parasitic capacitance C gd When the value decreases by 10%, the reverse recovery loss E rr This step quantifies the impact of parasitic capacitance on reverse recovery loss through correlation analysis, providing guidance for structural optimization.

[0058] The specific implementation of step S07 is: integrating the test data obtained in the above steps, establishing a reverse recovery loss E rr and on-resistance R DS(on) Multivariate mathematical model of two output variables; Apply response surface method to construct the objective function surface in parameter space; Introduce Pareto optimization method to convert the reverse recovery loss E rr and on-resistance R DS(on) As two mutually constrained optimization objectives; set the reverse recovery loss E rrThe threshold does not exceed 100μJ, and the on-resistance R DS(on) The threshold does not exceed 150mΩ. A multi-objective optimization algorithm, such as a non-dominated sorting genetic algorithm, is used to find the Pareto optimal solution set. Decision weight analysis is used to determine the optimal parameter combination: a gate-drain spacing of 45μm, a first field plate length of 10μm, a second field plate length of 8μm, a gate finger width of 4μm, and a gate finger spacing of 5μm. This step utilizes multi-objective optimization theory to find a balance between reverse recovery loss and on-resistance, ultimately determining the optimal structural parameter combination.

[0059] The specific implementation of step S08 is as follows: according to the optimal parameters determined in step S07, a bidirectionally conducting gallium nitride power device layout is designed; a device sample is prepared using a standard semiconductor process flow, including epitaxial layer growth, source and drain ion implantation, gate metal deposition, electrode formation and other process steps; the device is packaged in a TO-247 package format, using a low parasitic inductance packaging method; a 350V / 20A test platform is established, including a high-precision voltage source, an electronic load, a high-speed drive circuit and precision measuring equipment; a test plan is designed, including two parts: static parameter testing and dynamic parameter testing; static parameters such as withstand voltage, leakage current, and on-resistance of the device are measured; dynamic parameters such as switching time, switching loss, and reverse recovery characteristics of the device are measured; and the reverse recovery time t of the optimized device is recorded. rr and reverse recovery loss E rr In this step, actual device samples are prepared based on the optimization results and performance tests are performed to verify them.

[0060] The specific implementation of step S09 is as follows: design a multi-frequency switching test circuit with a frequency range of 50kHz to 500kHz, using the same voltage and current operating conditions; measure the total loss of the optimized structure device and the control device at different switching frequencies; the total loss includes three parts: conduction loss, switching loss and reverse recovery loss; use a thermal imager to measure the temperature rise of the device and verify the heat loss distribution; analyze the trend of total loss with frequency to verify the advantages of the optimized structure in high-frequency applications; calculate the reverse recovery loss E rr The proportion of total loss, at 100kHz frequency, the reverse recovery loss E before optimization rr It accounts for 32% of the total loss, which is reduced to 18% after optimization; the test data is compared with the electrical model established in step S01 to analyze the source of the error; based on the verification results, the parameters in the electrical model, such as the nonlinear coefficient of capacitance and the temperature coefficient of carrier mobility, are corrected; the iterative optimization method is used to run steps S01 to S08 again to further optimize the process parameters; after two rounds of iterative optimization, the optimal process parameter combination is finally determined: the gate-drain spacing is 48μm, the first field plate length is 11μm, the second field plate length is 7μm, the gate finger width is 3.5μm, and the gate finger spacing is 6μm. At this time, the reverse recovery loss Err Reduce the on-resistance R by 45% DS(on) The increase was only 5%, achieving optimal overall performance. This step verified the optimization effect through experiments, further optimized the parameters through iterative adjustments, and ultimately determined the optimal process parameters to guide the production process and achieve reduced reverse recovery losses in bidirectionally conducting GaN power devices.

[0061] The mathematical model or calculation process involved in the present invention is described in detail below.

[0062] In step S01, when establishing an accurate electrical model of the bidirectionally conducting GaN power device, the finite element method is used to solve the Poisson equation and calculate the potential distribution, which is specifically expressed as follows:

[0063]

[0064] Where, is the gradient operator; ε is the dielectric constant of gallium nitride, which is 8.9; is the potential distribution function; ρ is the charge density function.

[0065] The charge density function ρ is determined by the following equation:

[0066] ρ=q(p-n+N D -N A );

[0067] Where q is the basic charge, which is 1.602×10 -19 Coulomb; p is the hole concentration; n is the electron concentration; N D is the donor impurity concentration; N A is the acceptor impurity concentration.

[0068] The electron and hole concentrations are solved by the carrier continuity equation:

[0069]

[0070] Where, J n and J p are the current densities of electrons and holes, respectively; G n and G p are the generation rates of electrons and holes, respectively; R n and R p are the recombination rates of electrons and holes, respectively.

[0071] The current density is calculated using the drift-diffusion model:

[0072]

[0073] Where μ n and μ pare the mobility of electrons and holes respectively; D n and D p are the diffusion coefficients of electrons and holes, respectively, which are related to the mobility through the Einstein relation: k B is the Boltzmann constant, which is 1.38×10 -23 Joule / Kelvin; T is the absolute temperature in Kelvin.

[0074] The Miller capacitance is calculated from the electric field distribution in the gate-drain overlap region:

[0075]

[0076] Where Q gd is the charge between the gate and drain; V gd is the gate-drain voltage; E is the electric field intensity; S is the area of the gate-drain overlapping region.

[0077] The parameter acquisition method for calculating the Miller capacitance value is as follows: the gate-drain overlap area S is determined by device layout design; the electric field strength E is obtained by solving the Poisson equation by finite element method; the gate-drain voltage V gd Set by externally applied voltage.

[0078] In step S02, the equation for calculating the ratio of the necessary overlap ratio to the unnecessary overlap ratio is specifically expressed as follows:

[0079]

[0080] Where η ratio is the ratio of the necessary overlap rate to the unnecessary overlap rate; η essential is the necessary overlap ratio; η non-essential is the unnecessary overlap rate; A essential The overlapping area required to maintain basic functions; A non-essential is the overlapping area that can be optimized and eliminated; A total is the total overlapping area.

[0081] Required overlapping area A essential The calculation equation is:

[0082]

[0083] Where C gd，min The minimum parasitic capacitance required to maintain the basic function of the device is determined through circuit simulation; d is the dielectric thickness in the gate-drain overlap region; and ε is the dielectric constant of the dielectric.

[0084] Total overlapping area A total and the unnecessary overlapping area A non-essential The relationship is:

[0085] A total =A essential +A non-essential ;

[0086] The parameters of the necessary overlap ratio and the unnecessary overlap ratio are obtained by analyzing the parasitic capacitance distribution under different gate-drain spacing distances using the electromagnetic field boundary element method; and determining the minimum parasitic capacitance value C required to maintain the basic function of the device through circuit simulation. gd，min ; Obtain the geometric dimensions of the overlapping area through layout measurement.

[0087] In step S03, the Nash equilibrium game model is used to analyze the relationship between the length of the field plate and the parasitic capacitance C gd The relationship between , construct the utility function matrix:

[0088]

[0089] Where U is the utility function matrix; represents the i-th strategy of the first player (reverse recovery loss), corresponding to the first field plate length values of 5μm, 10μm, and 15μm; The jth strategy of the second player (pressure resistance) corresponds to the second field plate length of 5μm, 10μm, and 15μm; Indicates the strategy chosen by both parties in the game The utility value at time.

[0090] The utility function of the first player (reverse recovery loss) is:

[0091]

[0092] Where, For the first player in the strategy combination The utility value under is the reverse recovery loss under the corresponding strategy; E rr，max and E rr，min are the maximum and minimum values of reverse recovery loss respectively; is the parasitic capacitance value under the corresponding strategy; C gd，max and C gd，min are the maximum and minimum values of the parasitic capacitance respectively; α1 and β1 are weight coefficients, satisfying α1+β1=1.

[0093] The utility function of the second player (pressure tolerance) is:

[0094]

[0095] Where, For the second player in the strategy combination The utility value under is the breakdown voltage under the corresponding strategy; BV max and BV min are the maximum and minimum values of breakdown voltage respectively; is the peak electric field under the corresponding strategy; E peak，max and E peak，min are the maximum and minimum values of the electric field peak respectively; α2 and β2 are weight coefficients, satisfying α2+β2=1.

[0096] The solution equation of the Nash equilibrium point is:

[0097] For any s1∈S1;

[0098] For any s2∈S2;

[0099] Where, is the Nash equilibrium point; S1 and S2 are the strategy sets of the two sides of the game respectively.

[0100] The method for obtaining the parameters of the Nash equilibrium game model is as follows: the electric field distribution and breakdown voltage under different field plate structures are calculated through electric field simulation software; the reverse recovery loss and parasitic capacitance under different field plate structures are measured through a test circuit; and the values of the weight coefficients α1, β1, α2, and β2 are determined through expert evaluation. By default, α1=α2=0.618 and β1=β2=0.382 can be used.

[0101] In step S04, the effect of the multi-finger structure on the gate resistance is calculated using a distributed resistance network model:

[0102]

[0103] Where R gate is the total gate resistance; ρ g is the resistivity of the gate metal; L g is the gate lead length; W g is the gate lead width; t g is the gate metal thickness; R contact is the contact resistance; L finger is the gate finger length; n is the gate finger quantity; W finger is the gate finger width.

[0104] Multi-finger structure for parasitic capacitance C gd The dispersion effect is calculated by the following equation:

[0105]

[0106] Where C gd，total is the total parasitic capacitance; C gd，iis the parasitic capacitance corresponding to the i-th gate finger; C gd，unit is the parasitic capacitance per gate finger, which is related to the gate finger width and the gate finger spacing.

[0107] Unit gate finger parasitic capacitance C gd，unit The relationship with the gate finger structure parameters is:

[0108]

[0109] Where A overlap is the overlapping area between the unit gate finger and the drain; W finger is the gate finger width; L overlap is the overlapping length between the gate finger and the drain; d gd is the dielectric thickness between the gate and drain.

[0110] The method for obtaining the multi-finger structure parameters is as follows: establishing a multi-finger gate layout model through semiconductor process design software and measuring the geometric dimensions of the gate fingers; measuring the gate resistance through a resistance tester; and measuring the parasitic capacitance through an impedance analyzer.

[0111] In step S05, the Coulomb scattering relaxation time equation is used to analyze the carrier migration characteristics:

[0112]

[0113] Where, τ c is the Coulomb scattering relaxation time; m * is the effective mass of the carrier; ε is the dielectric constant of the semiconductor; k B is the Boltzmann constant; T is the absolute temperature; q is the elementary charge; n is the carrier concentration; β is the screening parameter, which is calculated as follows:

[0114]

[0115] Where, E F is the Fermi level, which is related to the carrier concentration.

[0116] The effective carrier mobility is calculated from the relaxation time:

[0117]

[0118] Where μ is the effective carrier mobility.

[0119] Considering the high electric field effect, the carrier mobility is corrected to:

[0120]

[0121] Where μ e is the effective mobility under high electric field; μ0 is the mobility under low electric field; E is the electric field strength; vsat is the carrier saturation velocity.

[0122] The parameters of the Coulomb scattering relaxation time equation are obtained as follows: the carrier concentration n is determined by Hall effect measurement; the lattice temperature T is measured by thermocouple; the impurity concentration is measured by secondary ion mass spectrometry; the electric field strength E is calculated by device simulation; the dielectric constant of gallium nitride is taken as 8.9; the effective carrier mass m * Take 0.2 times the electron rest mass; carrier saturation velocity v sat Take 2.5×10 7 cm / s.

[0123] In step S06, the reverse recovery loss E rr Calculated by the following integral:

[0124]

[0125] Where V DS (t) is the drain-source voltage during reverse recovery; I D (t) is the drain current during the reverse recovery process; t rr is the reverse recovery time.

[0126] Parasitic capacitance C gd Value and reverse recovery loss E rr The correlation coefficient between them is calculated using the Pearson formula:

[0127]

[0128] Where r is the correlation coefficient; C gd，i is the parasitic capacitance value of the i-th sample; is the average value of parasitic capacitance; E rr，i is the reverse recovery loss of the i-th sample; is the average value of reverse recovery loss; m is the number of samples.

[0129] Parasitic capacitance C gd Value for reverse recovery loss E rr The impact factors were determined by linear regression analysis:

[0130] E rr =k·C gd +b+ε;

[0131] Where k is the influencing factor; b is the constant term; ε is the error term, and its range is ±5%.

[0132] The method for obtaining the correlation coefficient and influencing factor parameters is: measuring the parasitic capacitance value and reverse recovery loss of samples with different structural designs through a test circuit; and performing correlation analysis and linear regression analysis through statistical software.

[0133] In step S07, the Pareto optimization method is used to simultaneously optimize the reverse recovery loss E rr and on-resistance R DS(on) :

[0134] The optimization objective function is:

[0135] minF(x)=[minf1(x), minf2(x)];

[0136] Where F(x) is the multi-objective optimization function; f1(x)=E rr (x) is the reverse recovery loss objective function; f2(x) = R DS(on) (x) is the on-resistance objective function; x is the design parameter vector, x = [d gd , L fp1 , L fp2 , W finger , S finger ], where d gd is the gate-drain distance, L fp1 is the length of the first field plate, L fp2 is the length of the second field plate, W finger is the gate finger width, S finger is the gate finger spacing.

[0137] The constraints are:

[0138] 25μm≤d gd ≤75μm;

[0139] 5μm≤L fp1 ≤15μm;

[0140] 5μm≤L fp2 ≤15μm;

[0141] 2μm≤W finger ≤6μm;

[0142] 3μm≤S finger ≤8μm;

[0143] E rr (x)≤E rr，threshold =100 μJ;

[0144] R DS(on) (x)≤R DS(on)，threshold =150mΩ;

[0145] The Pareto solution set is defined as:

[0146] If there does not exist x′∈Ω such that And there exists at least one j∈{1,2} such that fj (x′) <f j (x), then x is the Pareto optimal solution and Ω is the feasible solution space.

[0147] The Pareto optimization parameter acquisition method is as follows: establishing a relationship model between design parameters and objective function through response surface method; solving the Pareto optimal solution set through multi-objective optimization algorithm, such as non-dominated sorting genetic algorithm.

[0148] The construction principle and significance of the above equation are as follows:

[0149] 1. The Poisson equation is used to calculate potential distribution. Its principle is that the electric field divergence is proportional to the charge density. It takes into account the spatial variation of the dielectric constant and can accurately reflect the electric field distribution at the interface of different materials. It is suitable for analyzing the electric field distribution of heterostructured GaN devices.

[0150] 2. The carrier continuity equation takes into account the generation, recombination, and transport processes of electrons and holes, enabling the model to reflect the transient behavior of carriers in semiconductors, which is crucial for understanding the dynamic changes of minority carriers during reverse recovery.

[0151] 3. The Miller capacitance calculation equation is based on the definition of capacitance and calculates the capacitance value from the microscopic charge distribution. It is more accurate than the traditional parallel plate capacitance model and can reflect the nonlinear characteristics of capacitance.

[0152] 4. The calculation equation for the ratio of necessary overlap to unnecessary overlap quantifies the optimization space, provides the direction and limit of structural optimization, and helps determine the optimal range of gate-drain spacing.

[0153] 5. The Nash equilibrium game model considers reverse recovery performance and voltage resistance as two competing parties, quantitatively describes the trade-off relationship between the two through a utility function, and finds a balance point where neither party can improve independently. This model is suitable for solving multi-objective optimization problems.

[0154] 6. The distributed resistance network model takes into account the contribution of each resistance in the multi-finger structure, can accurately calculate the gate resistance of complex structures, and guide the design of gate finger structures.

[0155] 7. The Coulomb scattering relaxation time equation describes the carrier scattering process from a microscopic physical perspective, taking into account the effects of carrier concentration, temperature, and electric field strength on mobility. It can accurately predict the carrier mobility characteristics under high electric fields and is crucial for understanding carrier behavior during reverse recovery.

[0156] 8. The Pearson correlation coefficient calculation equation quantifies the degree of linear correlation between two variables, helps determine the strength of the relationship between parasitic capacitance and reverse recovery loss, and guides the direction of structural optimization.

[0157] 9. The Pareto optimization method seeks the best balance among multiple mutually constrained objectives. It is suitable for simultaneously optimizing the two conflicting objectives of reverse recovery loss and on-resistance, ultimately obtaining the design parameter combination with the best overall performance.

[0158] Specifically, the principle of the present invention is as follows: the principle of reducing the reverse recovery loss of bidirectionally conducting GaN power devices is based on the precise analysis and optimization of the relationship between the device structural parameters and electrical characteristics. The energy loss of bidirectionally conducting GaN power devices during reverse recovery mainly comes from the charging and discharging process of the parasitic capacitance Cgd between the gate and the drain. During high-voltage switching, this parasitic capacitance generates an additional current path through the Miller effect, resulting in increased power loss. Therefore, the present invention reduces unnecessary overlapping areas in a targeted manner by precisely controlling the structural parameters of the gate and drain, thereby fundamentally reducing the parasitic capacitance value.

[0159] The design principle of the dual field plate structure is to optimize the electric field distribution of the device. The first and second field plates form extended regions on the source and gate sides, making the electric field distribution more uniform and reducing the electric field concentration between the gate and drain. This electric field redistribution reduces the parasitic capacitance of the space charge region while maintaining the device's voltage resistance. This invention innovatively applies the Nash equilibrium game model, treating reverse recovery loss and voltage resistance as two competing objectives to find the optimal balance point, ensuring that the basic performance of the device is not sacrificed while reducing parasitic capacitance.

[0160] The multi-finger gate structure is another key principle of this invention. By dividing a single wide gate into multiple narrow gate fingers, the total gate perimeter is increased, effectively reducing the gate resistance per unit area. Simultaneously, this structure disperses the parasitic capacitance Cgd, reducing local electric field concentration and minimizing the Miller effect. Precise control of gate finger width and spacing creates an optimal electric field distribution pattern, further optimizing the device's switching characteristics.

[0161] This paper establishes a mathematical model for the relationship between reverse recovery loss and parasitic capacitance, and analyzes carrier migration characteristics using the Coulomb scattering relaxation time equation, thereby deeply revealing the physical mechanisms underlying the reverse recovery process. The application of the Pareto optimization method allows for finding the optimal solution to a multi-parameter, multi-objective optimization problem, reducing reverse recovery loss while maintaining low on-resistance, thereby achieving an overall improvement in device performance. Finally, experimental verification and feedback iteration ensure the effectiveness and reliability of the optimization method.

[0162] A specific embodiment 1 of the present invention is provided below. The specific implementation of each step in this embodiment 1 is described in detail as follows.

[0163] The specific implementation of step S01 is as follows: a three-dimensional model of a bidirectionally conducting GaN power device is constructed using finite element analysis software. First, the device geometric parameters are imported, including gate width, thickness, drain size, source position, and GaN material layer thickness; then, the material physical parameters are set, including GaN dielectric constant, carrier mobility, saturation velocity, and other physical quantities; then, a finite element mesh subdivision algorithm is applied to mesh the model, with a focus on increasing the mesh density in the gate-drain overlap region, with the mesh unit size controlled to below 0.1 μm; then, an electric field distribution calculation model is established, and the potential distribution is calculated using a Poisson equation solver. The mathematical expression is: Where, is the gradient operator, ε is the dielectric constant of GaN, which is 8.9, is the potential distribution function, and ρ is the charge density function; the charge density function is determined by the following equation: ρ = q(p-n+N D -N A ), where q is the basic charge, which is 1.602×10 -19 Coulomb, p is the hole concentration, n is the electron concentration, N D is the donor impurity concentration, N A is the acceptor impurity concentration; the electron and hole concentrations are solved by the carrier continuity equation: and Where, J n and J p are the current densities of electrons and holes, G n and G p are the generation rates of electrons and holes, R n and R p are the recombination rates of electrons and holes respectively; the Miller capacitance value is calculated by the electric field distribution, and the calculation formula is: Where Q gd is the charge between the gate and drain, V gd is the gate-drain voltage, E is the electric field strength, and S is the area of the gate-drain overlap region. According to calculations, the typical Miller capacitance ranges from 50 to 120 pF under conditions of a gate voltage of 2 V and a drain voltage of 200 V. This step uses the finite element method to accurately simulate the electric field distribution in the device and calculate the Miller capacitance, providing a theoretical basis for subsequent structural optimization.

[0164] The specific implementation of step S02 is as follows: design six groups of structures with gate-drain spacing of 25μm, 35μm, 45μm, 55μm, 65μm, and 75μm, respectively, and make test samples; use an impedance analyzer at a frequency of 1MHz, apply a small signal excitation voltage of 0.1V, and measure the parasitic capacitance C under different gate-drain spacings. gdvalue; Based on the measurement results, establish the gate-drain spacing distance and parasitic capacitance C gd The relationship curve between the gate-drain overlap area is plotted using the electromagnetic field boundary element method, and the total overlap area is divided into the necessary overlap area required to maintain basic functions and the unnecessary overlap area that can be eliminated through structural optimization. The ratio of the necessary overlap rate to the unnecessary overlap rate is calculated using the following equation: Where η ratio is the ratio of the necessary overlap rate to the unnecessary overlap rate, η essential is the necessary overlap ratio, η non-essential is the unnecessary overlap rate, A essential To maintain the overlapping area required for basic functions, A non-essential is the overlap area that can be optimized and eliminated, A total is the total overlap area; the required overlap area is calculated using the following equation: Where C gd，min The minimum parasitic capacitance required to maintain the basic function of the device is determined through circuit simulation. d is the dielectric thickness of the gate-drain overlap area, and ε is the dielectric constant of the dielectric. The relationship between the total overlap area and the unnecessary overlap area is: A total =A essential +A non-essential When the gate-drain spacing is 45μm, the necessary overlap is approximately 40%, and the unnecessary overlap is approximately 60%. Based on the calculation results, the optimal gate-drain spacing range is determined to be 40-50μm. This step, through systematic measurement and analysis, determines the influence of the gate-drain spacing on parasitic capacitance, providing data support for structural optimization.

[0165] The specific implementation of step S03 is as follows: designing a first field plate with a length of 5μm, 10μm, and 15μm on the source side, and designing a second field plate with a length of 5μm, 10μm, and 15μm on the gate side, forming nine different combinations of double field plate structures; using electric field simulation software to calculate the electric field distribution under different field plate structures, focusing on analyzing the electric field peak value and electric field distribution uniformity at the edge of the field plate; measuring the withstand voltage value and parasitic capacitance C of the device under different field plate structures gd value; establish a Nash equilibrium game model and reverse recovery loss E rr As the utility function of the first player, pressure resistance as the utility function of the second player; define the strategy space of both players as the combination of field plate length parameters; construct the utility function matrix: Where U is the utility function matrix, represents the i-th strategy of the first player, corresponding to the first field board length values of 5μm, 10μm, and 15μm, represents the j-th strategy of the second player, corresponding to the second field board length values of 5μm, 10μm, and 15μm, Indicates the strategy chosen by both parties in the game The utility value when ; the utility function of the first player is: Where, For the first player in the strategy combination The utility value under is the reverse recovery loss under the corresponding strategy, E rr，max and E rr，min are the maximum and minimum values of reverse recovery loss, is the parasitic capacitance value under the corresponding strategy, C gd，max and C gd，min are the maximum and minimum values of the parasitic capacitance, respectively. α1 and β1 are weight coefficients, satisfying α1+β1=1. The utility function of the second player is: Where, For the second player in the strategy combination The utility value under is the breakdown voltage under the corresponding strategy, BV max and BV min are the maximum and minimum breakdown voltages, respectively. is the peak electric field under the corresponding strategy, E peak，max and E peak，min are the maximum and minimum values of the electric field peak respectively, α2 and β2 are weight coefficients, satisfying α2+β2=1; the solution equation of the Nash equilibrium point is: For any s1∈S1; For any s2∈S2, where is the Nash equilibrium point, S1 and S2 are the strategy sets of the two sides of the game respectively; the Nash equilibrium point is solved by the iterative approximation algorithm, and the parameter combination of the optimal length of the first field plate is 10μm and the optimal length of the second field plate is 8μm is obtained. At this time, the electric field peak is reduced by 32%, and the parasitic capacitance C gd The increase should not exceed 15%. This step uses game theory to analyze the impact of the field plate structure on device performance and find a balance between withstand voltage and parasitic capacitance.

[0166] The specific implementation of step S04 is as follows: designing nine multi-finger gate structures with gate finger widths of 2 μm, 4 μm, and 6 μm, and gate finger pitches of 3 μm, 5 μm, and 8 μm, respectively; using semiconductor process design software to establish a layout model of the multi-finger gate and calculate the total gate perimeter under different gate finger structures; using a distributed gate resistance network model to analyze the effect of the multi-finger structure on the gate resistance, the calculation formula is: Where R gate is the total gate resistance, ρg is the resistivity of the gate metal, L g is the gate lead length, W g is the gate lead width, t g is the gate metal thickness, R contact is the contact resistance, L finger is the gate finger length, n is the gate finger quantity, W finger is the gate finger width; the multi-finger structure has a parasitic capacitance C gd The dispersion effect is calculated by the following equation: Where C gd，total is the total parasitic capacitance, C gd，i is the parasitic capacitance corresponding to the i-th gate finger, C gd，unit is the parasitic capacitance of a unit gate finger; the relationship between the parasitic capacitance of a unit gate finger and the gate finger structure parameters is: Where A overlap is the overlapping area between the unit gate finger and the drain, W finger is the gate finger width, L overlap is the overlapping length between the gate finger and the drain, d gd is the dielectric thickness between the gate and drain; the on-resistance R of the device under different gate finger structures is measured DS(on) and parasitic capacitance C gd According to the measurement results, when the gate finger width is 4μm and the gate finger spacing is 5μm, the gate resistance per unit area decreases by 42%, and the parasitic capacitance C gd The dispersion effect is optimal, and the switching speed is increased by 25%. This step improves the switching performance of the device by optimizing the gate finger structure, reducing gate resistance, and dispersing parasitic capacitance.

[0167] The specific implementation of step S05 is as follows: design a bidirectional conduction test circuit, including a main circuit power supply, a resistive load, a test sample, and a drive circuit; set the test conditions to a drain-source voltage of 350V, a conduction current of 10A, a gate-source drive voltage of 0V to 15V, and a switching frequency of 100kHz; use a high-bandwidth oscilloscope and a current probe to measure the drain-source voltage V during the reverse recovery process. DS and drain current I D Waveform; record reverse recovery time t rr , that is, the time interval from the beginning of the reverse current decrease to the time it drops to 10% of the peak value; measure the reverse recovery peak current I rrm and reverse recovery charge Q rr ; Apply the Coulomb scattering relaxation time equation to analyze carrier migration characteristics: Where, τ c is the Coulomb scattering relaxation time, m * is the effective mass of the carrier, ε is the dielectric constant of the semiconductor, k Bis the Boltzmann constant, T is the absolute temperature, q is the basic charge, n is the carrier concentration, and β is the screening parameter; the effective carrier mobility is calculated using the relaxation time: Where μ is the effective carrier mobility. Considering the high electric field effect, the carrier mobility is corrected to: Where μ e is the effective mobility under high electric field, μ0 is the mobility under low electric field, E is the electric field strength, v sat is the carrier saturation velocity; the input parameters required for calculation and analysis include carrier concentration 10 17 cm -3 , lattice temperature 25 ° C, impurity concentration 5 × 10 16 cm -3 , electric field strength 3MV / cm, GaN dielectric constant 8.9; measure samples with different structural designs and record reverse recovery characteristic parameters. This step obtains device reverse recovery characteristic data through actual testing to provide a basis for subsequent optimization.

[0168] The specific implementation of step S06 is: collecting the capacitor charging and discharging current waveforms of different structural design samples during the reverse recovery process; using a spectrum analyzer, performing Fourier transform on the current waveform to analyze its frequency domain characteristics; calculating the reverse recovery loss E according to the current waveform and voltage waveform rr , using the integral formula: Where V DS (t) is the drain-source voltage during reverse recovery, I D (t) is the drain current during the reverse recovery process, t rr is the reverse recovery time; establish the parasitic capacitance C gd Value and reverse recovery loss E rr Data set; Apply the Pearson correlation coefficient method to calculate the parasitic capacitance C gd Value and reverse recovery loss E rr The correlation coefficient between: , where r is the correlation coefficient, C gd，i is the parasitic capacitance value of the i-th sample, is the average value of parasitic capacitance, E rr，i is the reverse recovery loss of the i-th sample, is the average value of reverse recovery loss, m is the number of samples; through linear regression analysis, the parasitic capacitance C is determined gd Value for reverse recovery loss E rr Impact Factor: E rr =k·C gd +b+ε, where k is the influencing factor, b is the constant term, and ε is the error term, with a range of ±5%. When the parasitic capacitance C gdWhen the value changes within the range of 50 to 150 pF, the correlation coefficient reaches 0.86, indicating that the two have a significant positive correlation. By calculation, we know that the parasitic capacitance C gd Value for reverse recovery loss E rr The influence factor is 0.78, that is, the parasitic capacitance C gd When the value decreases by 10%, the reverse recovery loss E rr This step quantifies the impact of parasitic capacitance on reverse recovery loss through correlation analysis, providing guidance for structural optimization.

[0169] The specific implementation of step S07 is: integrating the test data obtained in the above steps, establishing a reverse recovery loss E rr and on-resistance R DS(on) Multivariate mathematical model of two output variables; Apply response surface method to construct the objective function surface in parameter space; Introduce Pareto optimization method to convert the reverse recovery loss E rr and on-resistance R DS(on) As two mutually constrained optimization objectives; set the reverse recovery loss E rr The threshold does not exceed 100μJ, and the on-resistance R DS(on) The threshold does not exceed 150mΩ; the optimization objective function is: minF(x) = [minf1(x), minf2(x)], where F(x) is the multi-objective optimization function, f1(x) = E rr (x) is the reverse recovery loss objective function, f2(x)=R DS(on) (x) is the on-resistance objective function, x is the design parameter vector, x = [d gd , L fp1 , L fp2 , W finger , S finger ], where d gd is the gate-drain distance, L fp1 is the length of the first field plate, L fp2 is the length of the second field plate, W finger is the gate finger width, S finger is the gate finger spacing; the constraint condition is: 25μm≤d gd ≤75μm, 5μm≤L fp1 ≤15μm, 5μm≤L fp2 ≤15μm, 2μm≤W finger ≤6μm, 3μm≤S finger ≤8μm, E rr (x)≤E rr，threshold =100μJ, R DS(on) (x)≤R DS(on)，threshold=150mΩ; the Pareto solution set is defined as: if there is no x′∈Ω such that And there exists at least one j∈{1,2} such that f j (x′) <f j (x), where x is the Pareto optimal solution and Ω is the feasible solution space. A multi-objective optimization algorithm, such as a non-dominated sorting genetic algorithm, is used to find the Pareto optimal solution set. Decision weight analysis is used to determine the optimal parameter combination: a gate-drain spacing of 45 μm, a first field plate length of 10 μm, a second field plate length of 8 μm, a gate finger width of 4 μm, and a gate finger spacing of 5 μm. This step utilizes multi-objective optimization theory to find a balance between reverse recovery loss and on-resistance, determining the optimal structural parameter combination.

[0170] The specific implementation of step S08 is as follows: according to the optimal parameters determined in step S07, a bidirectionally conducting gallium nitride power device layout is designed; a device sample is prepared using a standard semiconductor process flow, including epitaxial layer growth, source and drain ion implantation, gate metal deposition, electrode formation and other process steps; the device is packaged in a TO-247 package format, using a low parasitic inductance packaging method; a 350V / 20A test platform is established, including a high-precision voltage source, an electronic load, a high-speed drive circuit and precision measuring equipment; a test plan is designed, including two parts: static parameter testing and dynamic parameter testing; static parameters such as withstand voltage, leakage current, and on-resistance of the device are measured; dynamic parameters such as switching time, switching loss, and reverse recovery characteristics of the device are measured; and the reverse recovery time t of the optimized device is recorded. rr and reverse recovery loss E rr In this step, actual device samples are prepared based on the optimization results and performance tests are performed to verify them.

[0171] The specific implementation of step S09 is as follows: design a multi-frequency switching test circuit with a frequency range of 50kHz to 500kHz, using the same voltage and current operating conditions; measure the total loss of the optimized structure device and the control device at different switching frequencies; the total loss includes three parts: conduction loss, switching loss and reverse recovery loss; use a thermal imager to measure the temperature rise of the device and verify the heat loss distribution; analyze the trend of total loss with frequency to verify the advantages of the optimized structure in high-frequency applications; calculate the reverse recovery loss E rr The proportion of total loss, at 100kHz frequency, the reverse recovery loss E before optimization rrIt accounts for 32% of the total loss, which is reduced to 18% after optimization; the test data is compared with the electrical model established in step S01 to analyze the source of the error; based on the verification results, the parameters in the electrical model, such as the nonlinear coefficient of capacitance and the temperature coefficient of carrier mobility, are corrected; the iterative optimization method is used to run steps S01 to S08 again to further optimize the process parameters; after two rounds of iterative optimization, the optimal process parameter combination is finally determined: the gate-drain spacing is 48μm, the first field plate length is 11μm, the second field plate length is 7μm, the gate finger width is 3.5μm, and the gate finger spacing is 6μm. At this time, the reverse recovery loss E rr Reduce the on-resistance R by 45% DS(on) The increase is only 5%, and the overall performance is optimal. This step verifies the optimization effect through experiments, further optimizes the parameters through iterative adjustments, and finally determines the optimal process parameters.

[0172] In order to better understand and implement the present invention, Example 2 of a specific application scenario of the present invention is provided below: Based on the method of the present invention, researchers conducted a series of bidirectional conductive GaN power device structure optimization experiments to reduce reverse recovery loss. The overall structure of the bidirectional conductive GaN power device and its field plate structure used are as follows: Figure 2-3 As shown in the figure, a three-dimensional electric field distribution model was first established using ANSYS Maxwell software. The minimum mesh cell size was set to 0.08μm, with a focus on densifying the gate-drain overlap region. By solving the Poisson equation, the Miller capacitance was calculated to be 87pF under the conditions of a gate voltage of 2V and a drain voltage of 250V. This value differed from the measured value by no more than 5%, verifying the effectiveness of the model.

[0173] Subsequently, the researchers designed six groups of samples with different gate-drain spacing parameters and conducted tests, as shown in Table 1:

[0174] Table 1 Parasitic capacitance test results of different gate-drain spacing

[0175]

[0176] From the data in Table 1, it can be seen that as the gate-drain distance increases, the parasitic capacitance C gd The value is significantly reduced, and the reverse recovery loss is also reduced accordingly. However, when the spacing exceeds 45μm, the downward trend of parasitic capacitance and reverse recovery loss slows down. Based on the calculation results of the necessary overlap rate and the unnecessary overlap rate, 45~55μm is determined to be the optimal gate-drain spacing range. For an explanation of the overlap area, please refer to Figure 6 .

[0177] Next, the researchers designed nine combinations of double field plate structures, as shown in Table 2:

[0178] Table 2 Effects of different field plate structural parameters on device performance

[0179]

[0180]

[0181] The Nash equilibrium game model was applied to analyze the data in Table 2, with reverse recovery loss and withstand voltage as the two game parties, and the utility value was calculated. The results show that the combination of a first field plate length of 10μm and a second field plate length of 8μm reaches the optimal balance point with a utility value of 0.78. At this time, the electric field peak is reduced by 2.86MV / cm, the breakdown voltage is increased to 675V, and the parasitic capacitance C is 0. gd The value is 96pF and the reverse recovery loss is 71μJ.

[0182] Subsequently, the researchers designed and tested a multi-finger gate structure, as shown in Table 3:

[0183] Table 3 Test results of different gate finger structure parameters

[0184]

[0185] According to the data in Table 3, when the gate finger width is 4μm and the gate finger spacing is 5μm, the gate resistance and parasitic capacitance C gd value and on-resistance R DS(on) This achieves a good balance and achieves the fastest switching speed of 24ns. Using a distributed resistor network model, calculations show that this structure reduces gate resistance per unit area by 42%, significantly improving high-frequency switching performance compared to traditional structures. Figure 4-5 A top-down schematic diagram and a cross-sectional schematic diagram of the multi-finger gate structure of a bidirectionally conducting GaN power device are given to facilitate the understanding of the above experimental data.

[0186] The researchers constructed a bidirectional conduction test circuit, specifically a reverse recovery characteristic test circuit such as Figure 7 As shown in Table 4, the reverse recovery characteristics of the device before and after optimization were measured under 350V / 10A operating conditions. A 1GHz bandwidth oscilloscope and a 0.1A current probe were used in the test, with a sampling rate set to 5GS / s.

[0187] Table 4 Comparison of device reverse recovery characteristics before and after optimization

[0188] parameter Device before optimization Optimized device Improvement rate (%) <![CDATA[Reverse recovery time t rr (ns)]]> 48 32 33.3 <![CDATA[Reverse recovery peak current I rrm (A)]]> 8.6 5.7 33.7 <![CDATA[Reverse recovery charge Q rr (nC)]]> 152 85 44.1 <![CDATA[Reverse recovery loss E rr (μJ)]]> 89 52 41.6

[0189] By applying the Coulomb scattering relaxation time equation to analyze the carrier mobility characteristics, it was calculated that the effective carrier mobility of the optimized device increased by 28% and the scattering relaxation time was shortened by 35%, which is the microscopic physical mechanism for the improvement of reverse recovery performance.

[0190] The parasitic capacitance C is calculated using the Pearson correlation coefficient method. gd Value and reverse recovery loss E rr The correlation coefficient between them is 0.89, indicating that there is a strong positive correlation between the two. The linear regression analysis shows that the impact factor is 0.81, that is, the parasitic capacitance C gd For every 10% reduction, the reverse recovery loss E rr The average reduction was 8.1%.

[0191] Based on all the test data, the researchers applied the Pareto optimization method to optimize the reverse recovery loss E at the same time. rr and on-resistance R DS(on) Two mutually restrictive goals. As shown in Table 5:

[0192] Table 5 Partial solutions in the Pareto optimal solution set

[0193]

[0194] Finally, the fourth group of parameters in Table 5 was selected as the optimal solution, that is, the gate-drain spacing is 48μm, the first field plate length is 11μm, the second field plate length is 7μm, the gate finger width is 3.5μm, and the gate finger spacing is 6μm. Experimental verification under 350V / 20A conditions shows that this structure reduces the device reverse recovery loss E rr The on-resistance R DS(on) It only increased by 5%.

[0195] Tests at different switching frequencies further verified the effectiveness of the optimized structure, as shown in Table 6:

[0196] Table 6 Comparison of total losses at different switching frequencies

[0197]

[0198] Traditional methods for reducing reverse recovery losses in bidirectionally conducting GaN power devices primarily involve reducing the drain doping concentration, increasing the drift region length, or increasing the channel width. While these methods can reduce reverse recovery losses, they typically result in a significant increase in on-resistance, reducing the device's current density and negatively impacting its high-frequency performance. For example, reducing the drain doping concentration can reduce reverse recovery losses by approximately 25%, but on-resistance increases by over 30%. Increasing the drift region length can reduce reverse recovery losses by approximately 20%, but increases device area by approximately 35%, significantly increasing costs.

[0199] In contrast, the present invention solves the reverse recovery loss problem from the perspective of parasitic capacitance by optimizing the gate-drain spacing, field plate structure, and gate finger structure, reducing the reverse recovery loss by 45%, while increasing the on-resistance by only 5%, maintaining excellent static characteristics. In particular, the advantages of the present invention are more significant in high-frequency applications. At a switching frequency of 500kHz, the total loss is reduced by 42%, far exceeding the 20% or so of traditional methods. In addition, the Nash equilibrium game model and Pareto optimization method introduced in the present invention achieve systematic optimization of electrical and heat dissipation performance, avoid the blindness and limitations of traditional empirical design, improve design efficiency, and provide theoretical guidance and design methods for the research and development of bidirectionally conducting GaN power devices.

[0200] It should be noted that the variables involved in the present invention are explained in detail as shown in Tables 7 and 8 below.

[0201] Table 7 Variable Explanation Table (Part 1)

[0202]

[0203]

[0204] Table 8 Variable Explanation Table (Part 2)

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[0206] Table 9 Variable Explanation Table (Part 3)

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[0208]

[0209] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered by the scope of protection of the present invention.

Claims

1. A method for reducing reverse recovery loss of a bidirectionally conducting GaN power device, characterized in that: include: Establish an accurate electrical model for bidirectionally conducting GaN power devices and analyze the Miller capacitance generated in the gate-drain overlap region; Design multiple gate and drain structures, control the gate-drain spacing parameters, measure parasitic capacitance, and calculate the ratio of necessary overlap to unnecessary overlap. Use a double field plate structure to create an optimized electric field distribution region, and analyze the relationship between field plate length and parasitic capacitance using a Nash equilibrium game model. Using extended gate structure technology, the gate is designed into a multi-finger structure; a test circuit is constructed to measure the reverse recovery characteristics of the device; and the capacitor charge and discharge current waveforms are analyzed; Establish a reverse recovery loss optimization model; prepare device samples and verify the effectiveness of the optimized structure; iteratively optimize and ultimately determine process parameters to guide the reduction of reverse recovery losses in bidirectionally conducting GaN power devices.

2. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 1, wherein: Establishing a precise electrical model of a bidirectionally conducting gallium nitride power device and analyzing the Miller capacitance value generated in the gate-drain overlap region refers to analyzing the Miller capacitance value generated in the gate-drain overlap region through finite element simulation. The Miller capacitance value refers to the value of the negative feedback effect caused by the overlapping capacitance between the gate and the drain during high-voltage switching. The Miller capacitance value can cause additional current paths to be generated during the switching process, increasing power loss.

3. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 2, wherein: The method of designing multiple sets of gate and drain structures, controlling the gate and drain spacing parameters, measuring the parasitic capacitance values, and calculating the ratio of necessary overlap rate to unnecessary overlap rate refers to precisely controlling the gate and drain spacing parameters from 25μm to 75μm, measuring the corresponding parasitic capacitance values, and calculating the ratio of necessary overlap rate to unnecessary overlap rate.

4. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 3, wherein: The required overlap ratio refers to the ratio of the minimum overlap area that must be maintained between the gate and drain to the total overlap area in order to ensure the basic electrical characteristics and reliability of the bidirectionally conducting gallium nitride power device. The required overlap ratio is used to determine the lower limit of the gate-drain spacing parameter.

5. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 4, wherein: The non-essential overlap ratio refers to the ratio of the overlapping area between the gate and the drain to the total overlapping area, which is reduced through optimized design without affecting the basic function of the device. The non-essential overlap ratio is used to determine the optimization space of the gate-drain spacing parameter.

6. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 5, characterized in that: The use of dual field plate structure technology to form an electric field distribution optimization area and analyzing the relationship between the field plate length and parasitic capacitance through a Nash equilibrium game model refers to setting a first field plate and a second field plate with a length of 5μm to 15μm on the source side and the gate side, respectively, to form an electric field distribution optimization area, and analyzing the relationship between the field plate length and parasitic capacitance through a Nash equilibrium game model.

7. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 6, wherein: The Nash equilibrium game model refers to treating reverse recovery performance and voltage resistance as two rational game parties in the design of field plate structures. Each game party attempts to maximize its own utility function and reach an equilibrium state without cooperation. The Nash equilibrium game model is used to determine the optimal parameter combination of the field plate structure.

8. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 7, wherein: The use of extended gate structure technology to design the gate into a multi-finger structure means designing the gate into a multi-finger structure, controlling the gate finger width in the range of 2μm to 6μm, and maintaining the gate finger spacing between 3μm to 8μm, thereby reducing the gate resistance value per unit area and the dispersed parasitic capacitance value.

9. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 8, characterized in that: The multi-finger structure refers to dividing a single wide gate into multiple parallel narrow gate fingers. By increasing the total circumference of the gate, the gate resistance per unit area is reduced, and the parasitic capacitance between the gate and the drain is dispersed. The multi-finger structure is used to improve the switching characteristics of the device.

10. The method for reducing reverse recovery loss of a bidirectionally conducting GaN power device according to claim 9, wherein: The construction of a test circuit to measure the reverse recovery characteristics of the device refers to constructing a bidirectional conduction test circuit to measure the reverse recovery time and reverse recovery loss of the device under 350V / 10A working conditions under different structural designs, and analyzing the carrier migration characteristics through the Coulomb scattering relaxation time equation.

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