SiC trench mosfet super junction for enhanced reverse recovery performance and method of fabrication

Abstract

The present application relates to SiC trench MOSFET super junction for enhancing reverse recovery performance and its preparation method, it includes drain, n+ substrate, n type drift region and two sources which are left-right symmetrical, n-drift region is equipped with n column region above, n column region both ends includes left-right symmetrical p1+ base region, high concentration first n+ source region and low concentration n1+ region formed super junction region, n column region top both ends includes left-right symmetrical p+ source region, p body region and high concentration second n+ source region, n column region top recess is equipped with p+ shielding region, n column region, p+ shielding region, p body region, second n+ source region jointly form the trench, the trench is equipped with a layer of gate oxide layer, the gate oxide layer is equipped with gate metal;The source is located at the left and right ends of the gate oxide layer respectively.The present application has the ability of strong reverse recovery, improve voltage resistance, reduce parasitic capacitance, improve switching speed, reduce on-resistance.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of transistors, and particularly relates to a SiC trench MOSFET super junction for enhancing reverse recovery performance and a preparation method thereof. BACKGROUND

[0002] Power MOSFETs exhibit faster switching capability, making them more popular than traditional bipolar devices in high-frequency power switching applications. The emergence of super junction technology has proven to be a significant advantage in power devices. Unlike traditional planar structures, super junction technology combines vertical pn junctions, significantly increasing the breakdown voltage without expanding the chip area. This technology also significantly reduces the on-resistance, minimizes power loss, and improves overall performance.

[0003] However, the introduction of super junctions also presents significant challenges. In super junction devices, the reverse recovery performance of diodes or MOSFETs is poor. To address this issue, various techniques have been proposed at home and abroad to optimize and improve the reverse recovery performance of MOS devices. One approach is to use Si / SiC heterojunction diodes, although they have benefits, but their interface state density is high, which adversely affects device performance. The complexity of the heterojunction structure further complicates packaging, and fast switching can result in higher frequency electromagnetic interference.

[0004] Schottky diodes, while advantageous in some respects, have a high interface state density, leading to Fermi level pinning effects. This results in difficulty in controlling the on-voltage, leading to poor thermal performance and reliability. On the other hand, channel diodes compromise the reliability of the device, resulting in poor heat conduction and dissipation, and generally exhibit longer reverse recovery times compared to Schottky diodes.

[0005] A SiC trench MOSFET device is disclosed in Chinese Patent Publication No. CN219017662U, which comprises a substrate layer, the upper side of the substrate layer has an epitaxially formed N-drift region, the upper surface of the N-drift region is formed with a gate region trench, the bottom and sidewall of the gate region trench are formed with a silicon dioxide layer, the remaining gap on the silicon dioxide layer in the trench is filled with gate polysilicon, the left and right sides of the gate region trench each have a P-well region, each P-well region has an N+ region and a P+ region formed thereon, respectively, the thickness of the P+ region is greater than that of the N+ region, the P+ region is arranged on the outer side of the device, and the N+ region is arranged on the inner side of the device, the upper surface of the polysilicon is formed with a gate, the two ends of the gate extend to the edge of the N+ region, the upper surface of the P+ region is formed with a source, and the source extends to the upper surface of the N+ region, and the lower surface of the substrate layer is formed with a drain. Although it can solve the problem of easy early breakdown at the corner of the trench, it still needs a long reverse recovery time. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a SiC trench MOSFET super junction for enhancing reverse recovery performance and a preparation method thereof, which has the ability of strong reverse recovery, improved voltage resistance, reduced parasitic capacitance, improved switching speed, and reduced on-resistance.

[0007] The present application provides a SiC trench MOSFET super junction for enhancing reverse recovery performance, which comprises a drain, an n+ substrate, an n-type drift region, and two left-right symmetrical sources, the drain, the n+ substrate, and the n-type drift region are arranged in sequence from bottom to top, an n-column region is arranged above the n-drift region, the n-column region is in a concave shape, the left and right ends of the n-column region each comprise a left-right symmetrical p1+ base region, a high-concentration first n+ source region, and a low-concentration n1+ region to form a super junction region, the p1+ base region is in an L shape, the bottom of the p1+ base region is connected to the n-type drift region, the side of the p1+ base region is closely attached to the n-column region and extends upward, the first n+ source region and the n1+ region are each located in the L-shaped groove of the p1+ base region, the n1+ region is closely attached to the n-column region and extends upward, and the first n+ source region is located above the n1+ region; the top of the n-column region comprises left-right symmetrical p+ source regions, a p-body region, and a high-concentration second n+ source region at both ends, the p+ source regions and the p-body region are closely attached to the n-column region, the second n+ source region is located above the p-body region, and the p+ source regions are located between the first n+ source region and the second n+ source region; a p+ shielding region is arranged in the top groove of the n-column region, and the n-column region, the p+ shielding region, the p-body region, and the second n+ source region jointly form a trench, a gate oxide layer is arranged on the trench, and a gate metal is arranged on the gate oxide layer; the sources are respectively located at both ends of the gate oxide layer and cover the second n+ source region, the p+ source region, the first n+ source region, and the p1+ base region.

[0008] Preferably, the thickness and concentration of the first n+ source region and the second n+ source region are the same.

[0009] Preferably, the doping concentration of the n-pillar region is 1.0 × 10⁻⁶. 19 cm -3 .

[0010] Preferably, the thickness of the first n+ source region is 0.3 μm, and the doping concentration is 1.0 × 10⁻⁶. 19 cm -3 The second n+ source region has a thickness of 0.3 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0011] Preferably, the doping concentration of the p1+ base region is 5.0 × 10⁻⁶. 16 cm -3 .

[0012] Preferably, the doping concentration of the n1+ region is 1.0 × 10⁻⁶. 16 cm -3 .

[0013] Preferably, the p+ shielding region has a thickness of 0.2 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0014] Preferably, the source width is 2.5 μm, the gate width is 3.0 μm, and the gate thickness is 1.7 μm.

[0015] Preferably, the thickness of the gate oxide layer is 0.05 μm.

[0016] A method for fabricating a SiC trench MOSFET superjunction to enhance reverse recovery performance includes the following steps:

[0017] S1: An epitaxial layer is grown on a 4H-SiC substrate to form an n-drift region, and an n-pillar region is grown above the n-drift region;

[0018] S2: Epitaxial growth and ion implantation are performed on the n-pillar region to form a left-right symmetrical p1+ base region;

[0019] S3: Repeat the epitaxial and ion implantation process to generate the first n+ source region and n1+ region in the p1+ base region;

[0020] S4: Further ion implantation is performed above the n-column region to complete the formation of the two p+ source regions, the p-body region, and the second n+ source region;

[0021] S5: Etching is then performed starting at the top of the second n+ source region to form a recess through to the n-pillar region;

[0022] S6: A p+ shielding region is formed on the recess, and a trench is formed;

[0023] S7: A gate oxide layer is grown on the trench by thermal oxidation; after the thermal oxidation step, the oxide layer in the trench source is selectively removed using a mask;

[0024] S8: A gate metal is formed in the gate oxide layer;

[0025] S9: Source and drain metals are deposited to establish ohmic contact and create a polysilicon gate, respectively.

[0026] The present application has the following technical effects:

[0027] 1. The super-junction region is connected to the n-type drift region through the p1+ base region, which helps to smooth current conduction, eliminates electron potential barriers, improves switching speed, and reduces switching loss; the high-concentration first n+ source region and the low-concentration n1+ region form a potential concentration difference, which helps to reduce switching time, improve the switching speed of the device, thereby reducing switching loss and shortening reverse recovery time; the existence of the super-junction region increases the pn junction area formed by the overall device and increases the number of minority carriers in the depletion region, thereby making it have stronger reverse recovery performance, improving the voltage resistance, reducing the parasitic capacitance, improving the switching speed, and reducing the on-resistance.

[0028] 2. The p+ shielding region provides charge compensation for the n-pillar region and assists in depleting the n-pillar region; the n-pillar region and the p+ shielding region together achieve charge balance, improve the overall voltage resistance, and reduce the parasitic capacitance. The n-pillar region and the p+ shielding region are alternately doped regions that can maintain charge balance under zero bias conditions. This charge balance allows the device to withstand higher breakdown voltage without the need for heavily doped drift regions. The n-pillar region helps to evenly distribute the electric field when the device is in the off state, and this uniform electric field distribution allows the device to have a higher breakdown voltage. The vertical arrangement of the n-pillar region and the p+ shielding region allows the device to achieve high breakdown voltage without sacrificing on-resistance. When the device is turned on, the n-pillar region can be used to reduce the on-resistance. The n-pillar region acts as part of the current path when the device is in operation (gate on); when the device is turned on, the current flows vertically through the n-pillar region, enhancing the overall current capacity of the device. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of a traditional 4H-SiC UMOSFET structure;

[0030] Figure 2Structure of step 1 of the preparation method of the present application;

[0031] Figure 3 Structure of step 1 of the preparation method of the present application;

[0032] Figure 4 Structure of step 2 of the preparation method of the present application;

[0033] Figure 5 Structure of step 3 of the preparation method of the present application;

[0034] Figure 6 Structure of step 4 of the preparation method of the present application;

[0035] Figure 7 Structure of step 5 of the preparation method of the present application;

[0036] Figure 8 Structure of step 6 of the preparation method of the present application;

[0037] Figure 9 Structure of step 7 of the preparation method of the present application;

[0038] Figure 10 Structure of step 8 of the preparation method of the present application;

[0039] Figure 11 Structure of step 9 of the preparation method of the present application.

[0040] In the figure: 1, drain; 2, n+ substrate; 3, n-type drift region; 4, source; 5, n column region; 6, p1+ base region; 7, first n+ source region; 8, n1+ region; 9, p+ source region; 10, p body region; 11, second n+ source region; 12, p+ shielding region; 13, gate oxide layer; 14, gate metal. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is specifically described below in combination with the drawings.

[0042] As Figure 1 Structure of traditional 4H-SiC UMOSFET.

[0043] As Figure 2As shown, the SiC trench MOSFET super junction for enhancing reverse recovery performance includes a drain 1, an n+ substrate 2, an n-type drift region 3 and two left-right symmetrical source electrodes 4, the drain 1, the n+ substrate 2 and the n-type drift region 3 are arranged in sequence from bottom to top, an n-column region 5 is arranged above the n-type drift region 3, the n-column region 5 is in a concave shape, the n-column region 5 includes left-right symmetrical p1+ base regions 6, high-concentration first n+ source regions 7 and low-concentration n1+ regions 8 forming super junction regions at both ends of the n-column region 5, the p1+ base regions 6 are in an L shape, the bottom of the p1+ base regions 6 is connected with the n-type drift region 3, the side of the p1+ base regions 6 is tightly attached to the n-column region 5 and extends upward, the first n+ source regions 7 and the n1+ regions 8 are located in the L-shaped groove of the p1+ base regions 6, the n1+ regions 8 are tightly attached to the n-column region 5 and extend upward, and the first n+ source regions 7 are located above the n1+ regions 8; the n-column region 5 includes left-right symmetrical p+ source regions 9, p-body regions 10 and high-concentration second n+ source regions 11 at the top of the n-column region 5, the p+ source regions 9 and the p-body regions 10 are tightly attached to the n-column region 5, the second n+ source regions 11 are located above the p-body regions 10, and the p+ source regions 9 are located between the first n+ source regions 7 and the second n+ source regions 11; a p+ shielding region 12 is arranged in the groove at the top of the n-column region 5, and the n-column region 5, the p+ shielding region 12, the p-body regions 10 and the second n+ source regions 11 form a trench together, a gate oxide layer 13 is arranged on the trench, and a gate metal 14 is arranged on the gate oxide layer 13; the source electrodes 4 are respectively located at both ends of the gate oxide layer 13 and cover the second n+ source regions 11, the p+ source regions 9, the first n+ source regions 7 and the p1+ base regions 6.

[0044] The super junction region is connected to the n-type drift region 3 through the p1+ base regions 6, which helps to smooth current conduction, eliminate electron potential barrier, improve switching speed and reduce switching loss; the high-concentration first n+ source regions 7 and the low-concentration n1+ regions 8 form a potential concentration difference, so that the super junction region has a high saturation electron velocity, which helps to reduce switching time, improve switching speed of the device, thereby reducing switching loss and shortening reverse recovery time; the pn junction area formed by the super junction region is increased, and the number of minority carriers in the depletion region is increased, so that the device has stronger reverse recovery performance, improved voltage resistance, reduced parasitic capacitance, improved switching speed and reduced on-resistance. Through the existence of the super junction region, a more heavily doped n-type drift region 3 can be used without increasing the on-resistance of the device, thereby improving the efficiency during operation.

[0045] The thickness and concentration of the first n+ source regions 7 and the second n+ source regions 11 are consistent. The thickness of the first n+ source regions 7 is 0.3 μm, and the doping concentration is 1.0×10 19 cm -3 The thickness of the second n+ source regions 11 is 0.3 μm, and the doping concentration is 1.0×10 19cm -3 The p-body region 10 has a thickness of 0.6 μm and a doping concentration of 2.0 × 10⁻⁶. 17 cm -3 The source electrode 4 has a width of 2.5 μm, the gate electrode has a width of 3.0 μm, and the gate electrode thickness is 1.7 μm. The gate oxide layer 13 has a thickness of 0.05 μm. The n-type drift region 3 has a thickness of 0.3 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 The p+ shielding region 12 has a thickness of 0.2 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 The thickness of the n+ substrate 2 is 0.2 μm. The doping concentration of the n-pillar region 5 is 1.0 × 10⁻⁶. 19 cm -3 The doping concentration of p1+ base region 6 is 5.0 × 10⁶. 16 cm -3 The doping concentration of region n1+ is 1.0 × 10⁸. 16 cm -3 .

[0046] The p+ shielding region 12 provides charge compensation for the n-pillar region 5, assisting in the depletion of n-pillar region 5. Together, n-pillar region 5 and p+ shielding region 12 achieve charge balance, improving overall voltage resistance and reducing parasitic capacitance. The n-pillar region 5 and p+ shielding region 12 are alternately doped regions, maintaining charge balance under zero bias conditions. This charge balance allows the device to withstand higher breakdown voltages without requiring heavily doped drift regions. When the device is off, n-pillar region 5 helps to uniformly distribute the electric field, resulting in a higher breakdown voltage. The vertical arrangement of n-pillar region 5 and p+ shielding region 12 allows the device to achieve high breakdown voltage without sacrificing on-resistance. When the device is on, n-pillar region 5 can reduce on-resistance. During device operation (gate on), n-pillar region 5 serves as part of the current path; when the device is on, current flows perpendicularly through n-pillar region 5, enhancing the overall current capability of the device.

[0047] A method for fabricating a SiC trench MOSFET superjunction to enhance reverse recovery performance includes the following steps:

[0048] S1: As Figure 3 As shown, an epitaxial layer is grown on a 4H-SiC substrate, and the doping concentration of this layer in the n-drift region is 3.0 × 10⁻⁶. 15 cm 3 The thickness is 19.2 μm. Subsequently, a doping concentration of 1.0 × 10⁻⁶ is grown. 16 cm 3 5. n-pillar region with a thickness of 19.2 μm.

[0049] S2: Epitaxial growth and ion implantation are performed on the n-pillar region 5 to form a p1+ base region 6 with a doping concentration of 5.0 x 10 16 cm 3 -1. Figure 4

[0050] S3: The process of epitaxial growth and ion implantation is repeated to create a first n+ source region 7 with a doping concentration of 1.0 x 10 19 cm 3 -1.and an n1+ region 8 domain with a doping concentration of 1.0 x 10 16 cm 3 -1.in the p1+ base region 6, thereby forming a super junction region. Figure 5

[0051] S4: Further ion implantation is performed above the n-pillar region 5 to complete the formation of a p+ source region 9 with a doping concentration of 1.0 x 10 19 cm 3 -1., a p-body region 10 with a doping concentration of 2.0 x 10 17 cm 3 -1., and a second n+ source region 11 with a doping concentration of 1.0 x 10 19 cm 3 -1.. Figure 6

[0052] S5: Etching is then performed starting at the top of the second n+ source region 11 to form a recess that extends through to the n-pillar region 5. Figure 7

[0053] S6: A p+ shield region 12 with a doping concentration of 1.0 x 10 19 cm 3 -1.is formed in the recess, and a trench is formed. Figure 8

[0054] S7: A gate oxide layer 13 with a thickness of 0.05 μm is grown on the trench by thermal oxidation. After the thermal oxidation step, the oxide layer in the trench source 4 is selectively removed using a mask. Figure 9

[0055] S8: A gate metal 14 is formed within the gate oxide layer 13. Figure 10

[0056] S9: The source 4 and drain 1 metals are deposited to establish ohmic contacts and create a polysilicon gate, respectively. Figure 11

[0057] ​​The above described embodiments are only to illustrate the preferred modes of the present application, and are not intended to limit the scope of the present application. Any modification and improvement made by those skilled in the art to the technical solutions of the present application without departing from the design spirit of the present application shall fall within the protection scope of the present application as defined by the claims.

Claims

1. A SiC trench MOSFET superjunction for enhancing reverse recovery performance, comprising a drain, an n+ substrate, an n-type drift region, and two symmetrically arranged sources, wherein the drain, n+ substrate, and n-type drift region are arranged sequentially from bottom to top, characterized in that: The n-type drift region is provided with an n-column region, the n-column region is in a concave shape, and the left and right ends of the n-column region each include a left-right symmetrical p1+ base region, a high-concentration first n+ source region, and a low-concentration n1+ region to form a super junction region, the p1+ base region is in an L shape, the bottom of the p1+ base region is connected to the n-type drift region, the side of the p1+ base region is closely attached to the n-column region and extends upward, the first n+ source region and the n1+ region are located in the L-shaped groove of the p1+ base region, the n1+ region is closely attached to the n-column region and extends upward, and the first n+ source region is located above the n1+ region; the top of the n-column region includes left-right symmetrical p+ source regions, p body regions, and a high-concentration second n+ source region at both ends, the p+ source regions and the p body regions are closely attached to the n-column region, the second n+ source region is located above the p body region, and the p+ source regions are located between the first n+ source region and the second n+ source region; a p+ shielding region is arranged in the groove at the top of the n-column region, the n-column region, the p+ shielding region, the p body region, and the second n+ source region jointly form a trench, a gate oxide layer is arranged on the trench, and a gate metal is arranged on the gate oxide layer; the source electrodes are respectively arranged at the left and right ends of the gate oxide layer and cover the second n+ source region, the p+ source region, the first n+ source region, and the p1+ base region.

2. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The thickness and concentration of the first n+ source region and the second n+ source region are consistent.

3. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The n-column region has a doping concentration of 1.0 x 1018cm-3 19 cm -3 .

4. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The first n+ source region has a thickness of 0.3 μm and a doping concentration of 1.0 x 10 19 cm -3 The second n+ source region has a thickness of 0.3 μm and a doping concentration of 1.0 x 10 19 cm -3 .

5. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The p1+ base region doping concentration is 5.0 x 1017cm-3. 16 cm -3 .

6. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The n1+ region has a doping concentration of 1.0 x 1018cm-3 16 cm -3 .

7. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The p+ shielding region has a thickness of 0.2 μm and a doping concentration of 1.0 x 1019 cm-3. 19 cm -3 .

8. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The width of the source electrode is 2.5 μm, the width of the gate electrode is 3.0 μm, and the thickness of the gate electrode is 1.7 μm.

9. The SiC trench MOSFET super junction for enhanced reverse recovery performance of claim 1, wherein: The thickness of the gate oxide layer is 0.05 μm.

10. A method for fabricating a SiC trench MOSFET super junction for enhanced reverse recovery performance according to claim 1, characterized by: It includes the following steps: S1: growing an epitaxial layer on a 4H-SiC substrate to form an n-type drift region and growing an n-column region above the n-type drift region; S2: performing epitaxy and ion implantation on the n-column region to form left-right symmetrical p1+ base regions; S3: repeating the process of epitaxy and ion implantation to generate a first n+ source region and an n1+ region in the p1+ base region; S4: further performing ion implantation above the n-column region to complete the formation of p+ source regions, p body regions, and a second n+ source region at both ends; S5: then performing etching starting from the top of the second n+ source region to form a groove penetrating the n-column region; S6: forming a p+ shielding region in the groove and forming a trench; S7: growing a gate oxide layer on the trench by thermal oxidation; after the step of thermal oxidation, the oxide layer in the source electrode in the trench is selectively removed using a mask; S8: forming a gate metal in the gate oxide layer; S9: depositing source and drain metals to establish ohmic contact and generate a polysilicon gate.

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