Ultrahigh-voltage fast recovery diode and preparation method thereof

Abstract

The invention relates to an ultrahigh-voltage fast recovery diode and a preparation method thereof, and the method comprises the steps: selecting an N-drift layer, and growing an oxide layer on the front surface of the N-drift layer; preparing a P-type anode layer on the front surface of the N-drift layer; preparing an N-type buffer layer on the back surface of the N-drift layer; preparing a plurality of P + regions which are arranged at intervals along the transverse direction on the back surface of the N-type buffer layer; and preparing an N + cathode layer on the back surface of the N-type buffer layer. According to the preparation method of the ultrahigh-voltage fast recovery diode, the N-type buffer layer is designed between the N-type drift layer and the N + cathode layer, and the plurality of P + regions are injected into the region of the N-type buffer layer at intervals to form a staggered P + N structure, so that the forward conduction voltage drop of the diode is not sacrificed while the reverse recovery softness of the diode is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an ultra-high voltage fast recovery diode and its fabrication method. Background Technology

[0002] With industrial development, the demand for ultra-high voltage power devices is increasing. However, ultra-high voltage fast recovery diodes (FRDs) have poor reverse recovery softness due to high application voltage and high substrate resistivity, which easily causes oscillation and voltage overshoot.

[0003] A conventional ultra-high voltage fast recovery diode consists of three parts: a P-type anode layer, an N-drift layer, and an N+ cathode layer. Under reverse bias, the carriers in the N-drift layer are extracted under the influence of an external electric field, forming a depletion region. The diode switches to a reverse blocking state. Outside the depletion layer, there are very few or no excess carriers to maintain the continuously decreasing current, causing the current to trip and the diode to hard recover. This can lead to current oscillations and voltage overshoot, and in severe cases, device failure due to overvoltage.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses an ultra-high voltage fast recovery diode and its fabrication method.

[0006] The technical solutions adopted in the embodiments of the present invention are as follows: A method for fabricating an ultra-high voltage fast recovery diode includes the following steps: S1. Select an N-drift layer and grow an oxide layer on the front side of the N-drift layer; S2. Prepare a P-type anode layer on the front side of the N-drift layer; S3. Prepare an N-type buffer layer on the back side of the N-drift layer; S4. Prepare multiple P+ regions arranged laterally on the back side of the N-type buffer layer; S5. Prepare an N+ cathode layer on the back side of the N-type buffer layer.

[0007] A further technical solution is that, in step S1, the resistivity of the N-drift layer is 400-450 ohm·cm, and the thickness of the oxide layer is 200-350 angstroms.

[0008] A further technical solution is that step S2 includes: Boron impurities are implanted from the front of the N-drift layer at a dose of 5e13-1e14 and an energy of 80-120 keV. Annealing treatment is performed to form a P-type anode layer; the annealing conditions are 1150-1250℃ and the annealing time is 200-350min.

[0009] A further technical solution is that step S3 includes: Thinning the back side of the N-drift layer yields 450-550. N-drift layer; Phosphorus impurities were injected multiple times from the back side of the N-drift layer; Laser annealing is used to form an N-type buffer layer; the annealing energy of laser annealing is 3.4-4 mJ, and the annealing time is 30-60 s.

[0010] A further technical solution involves injecting phosphorus impurities five times from the back side of the N-drift layer, with the following conditions for each injection: The first injection of phosphorus impurities was performed at a dose of 5e12-7e12 and an energy of 2500 keV. The second injection of phosphorus impurities was performed at a dose of 9e12-1.1e13 and an energy of 1800 keV. The third injection of phosphorus impurities was performed at a dose of 1.5e13-2e13 and an energy of 1200 keV. The fourth injection of phosphorus impurities was performed at a dose of 1.5e13-2e13 and an energy of 800 keV. The fifth injection of phosphorus impurities was performed at a dose of 3e13-3.5e13 and an energy of 400 keV.

[0011] A further technical solution is that step S4 includes: Photoresist is applied to the back of the N-type buffer layer to define the preset injection area; Boron impurities are injected into the interior of the N-type buffer layer from the injection region at a dose of 6e14-8e14 and an injection energy of 500 keV. Laser annealing is used to form multiple P+ regions arranged laterally at intervals along one end of the back side of the N-type buffer layer; the annealing conditions are 3.4-4 mJ and the annealing time is 30-60 s.

[0012] A further technical solution is that step S5 includes: Phosphorus impurities were injected into the back side of the N-type buffer layer at a dose of 3e15-5e15 and an energy of 80keV. Annealing treatment is performed to form an N+ cathode layer; the annealing conditions are 400-420℃ and the annealing time is 30min.

[0013] An ultra-high voltage fast recovery diode includes a P-type anode layer, an N-drift layer, an N-type buffer layer and an N+ cathode layer arranged sequentially from top to bottom. One end of the N-type buffer layer is provided with a plurality of P+ regions arranged laterally at intervals, and the P+ regions are located within the N-type buffer layer.

[0014] A further technical solution is that the resistivity of the N-drift layer is 400-450 ohm·cm, and the thickness is 450-550 ohm·cm. .

[0015] A further technical solution is that the injection dose in the P+ region is 6e14-8e14.

[0016] The beneficial effects of the embodiments of the present invention are as follows: The proposed method for fabricating an ultra-high voltage fast recovery diode involves designing an N-type buffer layer between the N-type drift layer and the N+ cathode layer. Multiple P+ regions are then injected at intervals within the N-type buffer layer, forming an interleaved P+N structure. During reverse recovery, the PNP transistor composed of the P+ region, N-type buffer layer, and P-type anode layer conducts, allowing holes to be injected from the P+ region into the buffer layer and N-drift region. This ensures that excess charge carriers remain at the end of the reverse recovery phase, maintaining a continuously decreasing current and preventing current jumps. During forward conduction, holes flowing into the P+ region through the N-type buffer layer cause a rise in the P+ region potential, turning on the NPN transistor composed of the N+ cathode layer, P+ region, and N-drift layer. This allows electrons to be injected from the N+ cathode layer into the N-drift layer, improving the diode's reverse recovery softness without sacrificing its forward voltage drop. Attached Figure Description

[0017] Figure 1 This is a flowchart of the fabrication method of the ultra-high voltage fast recovery diode proposed in Embodiment 1 of the present invention.

[0018] Figure 2 It corresponds Figure 1 A schematic diagram of the device structure in step S1.

[0019] Figure 3 It corresponds Figure 1 A schematic diagram of the device structure in step S2.

[0020] Figure 4 It corresponds Figure 1 A schematic diagram of the device structure in step S3.

[0021] Figure 5 It corresponds Figure 1 A schematic diagram of the device structure in step S4.

[0022] Figure 6 It corresponds Figure 1A schematic diagram of the device structure in step S5.

[0023] Figure 7 This is a schematic diagram of the ultra-high voltage fast recovery diode proposed in Embodiment 2 of the present invention.

[0024] In the figure: 1. N- drift layer; 2. P-type anode layer; 3. N-type buffer layer; 4. P+ region; 5. N+ cathode layer; 11. Oxide layer. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the device proposed by this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0027] Example 1 Figure 1 This is a flowchart of a method for fabricating an ultra-high voltage fast recovery diode according to Embodiment 1 of the present invention. Figures 2 to 6 Corresponding to Figure 1 The schematic diagram of the device structure in steps S1-S5 is shown below. Figure 1 As shown, the fabrication method of the ultra-high voltage fast recovery diode in this embodiment includes the following steps: S1. Select N-drift layer 1, and grow oxide layer 11 on the front side of N-drift layer 1; Specifically, such as Figure 2 As shown, in this embodiment, a high-resistivity N-substrate is preferred for fabricating the N-drift layer to ensure sufficient reverse breakdown voltage. The resistivity is preferably 400-450 ohm·cm, and the thickness of the N-substrate is chosen to be 650 mm. The oxide layer 11 has a thickness of 200-350 angstroms. This extremely thin oxide layer prevents tunneling during doping processes such as ion implantation. Specifically, the oxide layer 11 is preferably a silicon dioxide oxide layer. The oxide layer 11 can be removed together in the subsequent hole etching process.

[0028] S2. Prepare a P-type anode layer 2 on the front side of the N-drift layer 1; Specifically, such as Figure 3 As shown, boron impurities are implanted from the front side of the N-drift layer 1 at a dose of 5e13-1e14 and an implantation energy of 80-120 keV. Then, annealing is performed to form the P-type anode layer 2; in this step, the annealing conditions are 1150-1250℃ for 200-350 min. This pushes the P-ring deeper, improving the device's breakdown voltage performance at reverse cutoff.

[0029] S3. Prepare an N-type buffer layer 3 on the back side of the N-drift layer 1; Specifically, such as Figure 4 As shown, the back side of the N-drift layer 1 is thinned to 450-550 mm. Then, phosphorus impurities are repeatedly injected from the back side of the N-drift layer 1. Laser annealing is then performed to form the N-type buffer layer 3. In this step, the annealing energy for laser annealing is preferably 3.4-4 mJ, and the annealing time is 30-60 s. Laser annealing is a short-duration, localized high-temperature treatment that does not affect the front structure and has higher activation efficiency.

[0030] In this embodiment, it is preferable to inject phosphorus impurities five times, with the following conditions for the five injections: The first injection of phosphorus impurities was performed at a dose of 5e12-7e12 and an energy of 2500 keV. The second injection of phosphorus impurities was performed at a dose of 9e12-1.1e13 and an energy of 1800 keV. The third injection of phosphorus impurities was performed at a dose of 1.5e13-2e13 and an energy of 1200 keV. The fourth injection of phosphorus impurities was performed at a dose of 1.5e13-2e13 and an energy of 800 keV. The fifth injection of phosphorus impurities was performed at a dose of 3e13-3.5e13 and an energy of 400 keV.

[0031] In step S3 of this embodiment, the energy of the five implantations is reduced, which allows the phosphorus ion implantation to proceed from deep to shallow, and the concentration to decrease from one side of the N+ cathode layer 5 to the other side of the N- drift layer 1, forming a gradual transition state. This makes the reverse recovery of the formed diode device softer.

[0032] S4. Prepare multiple P+ regions 4 that are uniformly distributed laterally on the back side of the N-type buffer layer 3. Specifically, such as Figure 5As shown, photoresist is applied to the back side of the N-type buffer layer 3 to define a predetermined implantation region. Then, boron impurities are implanted into the interior of the N-type buffer layer 3 from the implantation region, with a preferred implantation dose of 6e14-8e14 and a preferred implantation energy of 500 keV. Laser annealing is then performed to form multiple P+ regions 4 uniformly distributed laterally along one end of the back side of the N-type buffer layer 3. In this step, the annealing conditions are 3.4-4 mJ, and the annealing time is 30-60 s.

[0033] S5. An N+ cathode layer 5 is prepared on the back side of the N-type buffer layer 3.

[0034] Specifically, such as Figure 6 As shown, phosphorus impurities are implanted on the back side of the N-type buffer layer 3, with a preferred implantation dose of 3e15-5e15 and an implantation energy of 80 keV. Then, annealing is performed to form the N+ cathode layer 5; the annealing conditions in this step are 400-420℃ and annealing time of 30 min.

[0035] The main manifestation of hard reverse recovery in fast recovery diodes is a sharp drop in reverse recovery current during turn-off. This phenomenon is primarily caused by a small number of excess carriers outside the depletion layer, or even a lack of excess carriers to sustain the continuously decreasing current, leading to current interruption, current oscillation, and voltage overshoot. In severe cases, this can result in device overvoltage failure. This embodiment addresses this problem by designing an N-type buffer layer 3 between the N-drift layer 1 and the N+ cathode layer 5. Multiple P+ regions 4 are injected at intervals within the N-type buffer layer 3, forming an interleaved P+N structure. This improves the softness of the diode's reverse recovery without sacrificing the forward voltage drop.

[0036] Specifically, in this embodiment, during reverse recovery, the PNP transistor composed of P+ region 4, N-type buffer layer 3 and P-type anode layer 2 is turned on, and holes are injected from P+ region 4 into buffer layer 3 and N-drift layer 1, ensuring that there are still excess charge carriers at the end of the reverse recovery period to maintain the continuously shrinking current, avoiding current jumps, effectively improving the reverse recovery softness of the diode device, and suppressing oscillations and voltage spikes.

[0037] In this embodiment, a P+ region 4 is designed within the N-type buffer layer 3, and the P+ region 4 is in contact with the N+ cathode layer 5, forming a concentration difference. The N+ concentration on the back side is much higher than that of N-, resulting in a high emission efficiency for the NPN structure. Therefore, during forward conduction, the N+ cathode layer 5 acts as the emitter, forming an N+PN- conduction, injecting a larger electron current into the N-drift layer 1, which effectively improves the forward conduction voltage drop. Specifically, in this design structure of this embodiment, when the diode is forward-conducting, the P-type anode 1 injects holes into the N-drift layer 1. These holes then flow through the N-type buffer layer 3 into the P+ region 4 on the back side, causing the potential of the P+ region 4 to rise. This turns on the NPN transistor composed of the N+ cathode layer 5, the P+ region 4, and the N-drift layer 1 on the back side. The N+ cathode layer 5 on the back side injects electrons into the N-drift layer 1. Therefore, the P+ region 4 introduced in this embodiment does not reduce the back side injection efficiency during forward conduction, ensuring a low forward conduction voltage drop.

[0038] Example 2 Figure 7 This is a schematic diagram of the structure of an ultra-high voltage fast recovery diode proposed in Embodiment 2 of the present invention. Figure 2 As shown, the ultra-high voltage fast recovery diode of this embodiment includes, from top to bottom, a P-type anode layer 2, an N-drift layer 1, an N-type buffer layer 3, and an N+ cathode layer 5. The N-type buffer layer 3 has multiple P+ regions 4 evenly distributed laterally at one end, and the P+ regions 4 are located within the N-type buffer layer 3. In this embodiment, the resistivity of the N-drift layer 1 is preferably 400-450 ohm·cm, and its thickness is 450-550 ohm·cm. The injection dose in P+ region 4 is 6e14-8e14.

[0039] The ultra-high voltage recovery diode of this embodiment is preferably prepared using the preparation method in Embodiment 1.

[0040] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method of manufacturing an ultra-high voltage fast recovery diode, characterized by, The method comprises the steps of: S1, selecting an N-drift layer (1), and growing an oxide layer (11) on the front surface of the N-drift layer (1); S2, preparing a P-type anode layer (2) on the front surface of the N-drift layer (1); S3, preparing an N-type buffer layer (3) on the back surface of the N-drift layer (1); S4, preparing a plurality of P+ regions arranged along the lateral direction on the back surface of the N-type buffer layer (3); S5, preparing an N+ cathode layer (5) on the back surface of the N-type buffer layer (3).

2. The method for fabricating an ultra-high voltage fast recovery diode as described in claim 1, characterized in that: In the step S1, the resistivity of the N-drift layer (1) is 400-450 ohm·cm, and the thickness of the oxide layer (11) is 200-350 angstroms.

3. The method of claim 1, wherein the super high voltage fast recovery diode is formed by the steps of: The step S2 comprises: ​ injecting boron impurities from the front surface of the N-drift layer (1) with an injection dose of 5e13-1e14 and an injection energy of 80-120 kev; annealing to form the P-type anode layer (2); wherein the annealing condition is 1150-1250℃, and the annealing time is 200-350 min.

4. The method of claim 1, wherein the super high voltage fast recovery diode is prepared by the steps of: The step S3 comprises: ​ The back surface of the N-drift layer (1) is thinned to 450-550 of the N-drift layer (1); injecting phosphorus impurities from the back surface of the N-drift layer (1) multiple times; laser annealing to form the N-type buffer layer (3); wherein the annealing energy of the laser annealing is 3.4-4 mJ, and the annealing time is 30-60 s.

5. The method of claim 4, wherein the step of forming the super-junction region is performed by ion implantation. Injecting phosphorus impurities from the back surface of the N-drift layer (1) 5 times with the following injection conditions: injecting phosphorus impurities for the first time with an injection dose of 5e12-7e12 and an injection energy of 2500 kev; injecting phosphorus impurities for the second time with an injection dose of 9e12-1.1e13 and an injection energy of 1800 kev; injecting phosphorus impurities for the third time with an injection dose of 1.5e13-2e13 and an injection energy of 1200 kev; injecting phosphorus impurities for the fourth time with an injection dose of 1.5e13-2e13 and an injection energy of 800 kev; injecting phosphorus impurities for the fifth time with an injection dose of 3e13-3.5e13 and an injection energy of 400 kev.

6. The method of manufacturing an ultra-high voltage fast recovery diode as defined in claim 1, wherein, The step S4 comprises: coating photoresist on the back surface of the N-type buffer layer (3) to define a preset injection region; injecting boron impurities from the injection region to the inside of the N-type buffer layer (3) with an injection dose of 6e14-8e14 and an injection energy of 500 kev; laser annealing to form a plurality of P+ regions (4) arranged along the back surface of the N-type buffer layer (3) in the lateral direction; wherein the annealing condition is 3.4-4 mJ, and the annealing time is 30-60 s.

7. The method of claim 1, wherein the super high voltage fast recovery diode is prepared by the steps of: The step S5 comprises: ​ injecting phosphorus impurities on the back surface of the N-type buffer layer (3) with an injection dose of 3e15-5e15 and an injection energy of 80 kev; annealing to form the N+ cathode layer (5); wherein the annealing condition is 400-420℃, and the annealing time is 30 min.

8. An ultra-high voltage fast recovery diode, characterized by: The device comprises a P-type anode layer (2), an N-drift layer (1), an N-type buffer layer (3), and an N+ cathode layer (5) arranged in sequence from top to bottom, wherein one end of the N-type buffer layer (3) is provided with a plurality of P+ regions (4) arranged in the lateral direction, and the P+ regions (4) are located in the N-type buffer layer (3).

9. The super high voltage fast recovery diode as claimed in claim 8, wherein: The resistivity of the N-drift layer (1) is 400-450 ohm-cm, and the thickness is 450-550 .

10. The super high voltage fast recovery diode as claimed in claim 8, wherein: The injection dose of the P+ region (4) is 6e14-8e14.

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