An offset compensation circuit and system

Abstract

The present invention discloses an offset compensation circuit and system, which belongs to the technical field of circuit optimization. The scheme includes an operational amplifier module, an offset judgment module and an offset compensation module. The offset compensation module includes a first compensation submodule and a second compensation submodule connected in series with the operational amplifier module. The operational amplifier module and the offset judgment module are connected in series, and the offset judgment module and the offset compensation module are connected in series. The operational amplifier module includes a comparator. The first compensation submodule includes several groups of first current compensation circuits for reducing the current at the forward input end of the comparator. The second compensation submodule includes several groups of second current compensation circuits for increasing the current at the reverse input end of the comparator. The offset judgment module is used to receive and store the potential information output by the operational amplifier module. The offset compensation module is used to cut off the input current to the operational amplifier module when the potential information stored in the offset judgment module is 0. The present application has the effect of eliminating the influence of the comparator offset on the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit optimization, and in particular to an offset compensation circuit and system. Background Art

[0002] Since the on-resistance of the MOS tube is relatively small, the MOS tube is generally used as the driver in the synchronous rectification chip.

[0003] The existing synchronous rectification chip includes a first comparator and a second comparator. The first comparator is used to control the MOS tube to open the circuit, and the second comparator is used to control the MOS tube to close. When the voltage across the MOS tube changes from positive to negative, it is detected whether the voltage across the MOS tube is less than -150mv. When the voltage across the MOS tube is less than -150mv, the MOS tube is controlled to open the circuit. After the MOS tube is open, the voltage drop across the MOS tube is equal to the current of the MOS tube multiplied by the on-resistance of the MOS tube, and a callback process will be generated at this time. As the current decreases, when the current of the MOS tube drops to 0, the MOS tube is controlled to close.

[0004] In the process of implementing the present application, the inventors found that the above technology has at least the following problems: since conventional comparators are offset, it is difficult to accurately turn off the MOS tube when the current of the MOS tube is 0. Summary of the invention

[0005] In order to solve the problem that it is difficult to accurately turn off the MOS tube when the current of the MOS tube is 0, the present application provides an offset compensation circuit and system.

[0006] In a first aspect, the present application provides an offset compensation circuit, which adopts the following technical solution;

[0007] An offset compensation circuit comprises an operational amplifier module, an offset determination module and an offset compensation module, wherein the offset compensation module comprises a first compensation submodule and a second compensation submodule, wherein the first compensation submodule and the second compensation submodule are respectively connected in series with the operational amplifier module, the operational amplifier module is connected in series with the offset determination module, and the offset determination module is connected in series with the offset compensation module;

[0008] The operational amplifier module includes a comparator, a first resistor R1 is connected in series to a positive input terminal of the comparator, and a second resistor R2 is connected in series to a negative input terminal of the comparator;

[0009] The first compensation submodule includes a plurality of groups of first current compensation circuits connected in parallel, and the first current compensation circuit is used to reduce the current at the positive input terminal of the comparator;

[0010] The second compensation submodule includes a plurality of groups of second current compensation circuits connected in parallel, and the second current compensation circuit is used to increase the current of the reverse input terminal of the comparator;

[0011] The imbalance determination module is used to receive and store the potential information output by the operational amplifier module;

[0012] The offset compensation module is used to cut off the current input into the operational amplifier module by the first current compensation circuit and the second current compensation circuit when the potential information stored in the offset determination module is 0.

[0013] By adopting the above technical solution, when the circuit cannot be accurately controlled to stop when the current is 0, the first current compensation circuit reduces the current at the positive input terminal of the comparator, and the second current compensation circuit increases the current at the reverse input terminal of the comparator. The first current compensation circuit and the second current compensation circuit cooperate with each other to adjust the current when the circuit stops to 0, thereby eliminating the influence of the comparator offset on the circuit as much as possible.

[0014] In a specific implementation scheme, the first current compensation circuit is used to reduce the current at the positive input terminal of the comparator, and the second current compensation circuit is used to increase the current at the reverse input terminal of the comparator when the current at the positive input terminal of the comparator drops to 0 and the output of the operational amplifier module does not flip.

[0015] By adopting the above technical solution, the second current compensation circuit assists the first current compensation circuit in adjusting the current in the operational amplifier module, so as to adjust the current to 0 when the circuit stops, thereby eliminating the influence of the comparator offset on the circuit.

[0016] In a specific implementation scheme, each group of the first current compensation circuits includes a first current source and a first switch connected in series; each group of the second current compensation circuits includes a second current source and a second switch connected in series.

[0017] By adopting the above technical solution, a first switch and a second switch are set, and the required first current compensation circuit and second current compensation circuit are turned on as required, so that the turned-on first current compensation circuit and second current compensation circuit can adjust the current to 0 when the circuit is stopped.

[0018] In a specific possible implementation manner, a short-circuit switch for short-circuiting the comparator is connected between the positive input terminal of the comparator and the negative input terminal of the comparator.

[0019] By adopting the above technical solution, the short-circuit switch can short-circuit the comparator, thereby facilitating elimination of the influence of the comparator offset on the circuit.

[0020] In a specific implementation scheme, the offset compensation module further includes a counter unit, which is connected in series with the offset determination module and is used to cut off the current output of the first compensation submodule and the second compensation submodule according to the determination result of the offset determination module.

[0021] By adopting the above technical solution, the counter unit can cut off the current output of the first compensation submodule and the second compensation submodule in time, and ensure that the current is adjusted to 0 when the circuit stops as much as possible.

[0022] In a specific implementation scheme, the current flowing into the first resistor R1 after the plurality of groups of the first current compensation circuits are connected in parallel and divided is I csp , the current flowing into the second resistor R2 after the plurality of groups of the second current compensation circuits are connected in parallel and divided is I csn ; in,

[0023]

[0024]

[0025] The Q and Q N They are inverted signals to each other, and i is the reference current.

[0026] By adopting the above technical solution, I csp To reduce the current, I csn For the increased current, by calculating I csp and I csn Effectively regulate the current in the circuit to ensure that the current is 0 when the circuit stops.

[0027] In a specific implementation scheme, the comparator has an offset voltage ΔV th , the op amp module is used to th < I csp ·R1-I csn · Output high level when R2; at ΔV th =I csp ·R1-I csn · When R2, the output is low level.

[0028] By adopting the above technical solution, when a high level is output, it means that the influence caused by the comparator offset has not been eliminated, and when a low level is output, it means that the current adjustment when the circuit stops is 0, which effectively eliminates the influence of the comparator offset on the circuit.

[0029] In a specific implementation scheme, the input end of the mismatch determination module is connected to the output end of the operational amplifier module, and the mismatch determination module includes a latch unit, and the latch unit is connected in series with the counter unit;

[0030] The latch unit is used to store the potential information output by the operational amplifier module and synchronize the potential information to the counter unit.

[0031] By adopting the above technical solution, the counter unit can cut off the current input of the first current compensation circuit and the second current compensation circuit in time according to the potential information, and ensure that the current is adjusted to 0 when the circuit stops as much as possible.

[0032] In a specific implementation manner, the imbalance determination module further includes a third current source connected in series with the latch unit, and the third current source is grounded.

[0033] In a second aspect, the present application provides an offset compensation system, which adopts the following technical solution;

[0034] An offset compensation system, the offset compensation system is configured with the offset compensation circuit as described above, the offset compensation system is used for comparator having an offset voltage ΔV th When the current is input into the comparator, the offset voltage ΔV of the comparator is eliminated. th Impact on the circuit.

[0035] By adopting the above technical solution, when the circuit cannot be accurately controlled to stop when the current is 0, the first current compensation circuit reduces the current at the positive input terminal of the comparator, and the second current compensation circuit increases the current at the reverse input terminal of the comparator. The first current compensation circuit and the second current compensation circuit cooperate with each other to adjust the current when the circuit stops to 0, thereby eliminating the influence of the comparator offset on the circuit as much as possible.

[0036] In summary, the present application includes at least one of the following beneficial technical effects:

[0037] 1. When the circuit cannot be accurately controlled to stop when the current is 0, the first current compensation circuit reduces the current at the positive input terminal of the comparator, and the second current compensation circuit increases the current at the reverse input terminal of the comparator. The first current compensation circuit and the second current compensation circuit cooperate with each other to adjust the current when the circuit stops to 0, thereby eliminating the influence of the comparator offset on the circuit as much as possible.

[0038] 2. The counter unit can cut off the current output of the first compensation submodule and the second compensation submodule in time, and ensure that the current is adjusted to 0 when the circuit stops as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a logic schematic diagram of an offset compensation circuit in an embodiment of the present application.

[0040] Figure 2It is a structural schematic diagram of an offset compensation circuit in an embodiment of the present application.

[0041] Description of reference numerals:

[0042] 1. Operational amplifier module; 11. Comparator; 2. Offset judgment module; 21. Latch unit; 22. Third current source; 3. Offset compensation module; 31. First compensation submodule; 311. First current compensation circuit; 3111. First current source; 3112. First switch; 32. Second compensation submodule; 321. Second current compensation circuit; 3211. Second current source; 3212. Second switch; 33. Counter unit; 4. Short-circuit switch. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0044] An embodiment of the present application discloses an offset compensation circuit, referring to Figure 1 and Figure 2 The circuit includes an operational amplifier module 1, an offset judgment module 2 and an offset compensation module 3. The operational amplifier module 1 and the offset judgment module 2 are connected in series, the offset compensation module 3 and the operational amplifier module 1 are connected in series, and the offset judgment module 2 and the offset compensation module 3 are connected in series. The operational amplifier module 1 includes a comparator 11, and the comparator 11 itself has an offset voltage ΔV th The operational amplifier module 1 is used to output a potential signal to the offset judgment module 2, the offset judgment module 2 is used to receive and store the potential information output by the storage comparator 11, and the offset compensation module 3 is used to obtain the potential information in the offset judgment module 2 and to compensate the offset voltage ΔV in the operational amplifier module 1. th Make compensation.

[0045] Specifically, the operational amplifier module 1 further includes a first resistor R1 and a second resistor R2, wherein the first resistor R1 is connected in series with the positive output terminal of the comparator, and the second resistor R2 is connected in series with the negative input terminal of the comparator 11. A short-circuit switch 4 is connected between the positive input terminal of the comparator 11 and the negative input terminal of the comparator 11, and the short-circuit switch 4 is used to short-circuit the positive input terminal and the negative input terminal of the comparator 11.

[0046] Reference Figure 2 The offset judgment module 2 includes a latch unit 21 and a third current source 22. One end of the third current source 22 is connected in series with the latch unit 21, and the other end is grounded. The latch unit 21 is used to store the potential information output by the comparator 11 at the current time point, and synchronize the potential information to the offset compensation module 3.

[0047] In the embodiment of the present application, the output end of the operational amplifier module 1 is connected to the input end of the offset determination module 2, the current at the positive input end of the comparator 11 is large, the operational amplifier module 1 outputs a high potential, and at the same time, the input end of the offset determination module 2 inputs a high potential, and the latch unit 21 stores a high potential. The operational amplifier module 1 outputs a high potential, indicating that the offset of the comparator 11 has not been compensated.

[0048] Reference Figure 2 The offset compensation module 3 includes a first compensation submodule 31 and a second compensation submodule 32. The first compensation submodule 31 is connected in series with the positive input terminal of the comparator 11 in the operational amplifier module 1, and the second compensation submodule 32 is connected in series with the negative input terminal of the comparator 11 in the operational amplifier module 1. The first compensation submodule 31 includes a plurality of groups of first current compensation circuits 311 connected in parallel, and the second compensation submodule 32 includes a plurality of groups of second current compensation circuits 321 connected in parallel. The first current compensation circuit 311 is used to reduce the current at the positive input terminal of the comparator 11, and the second current compensation circuit 321 is used to increase the current at the negative input terminal of the comparator 11.

[0049] Each group of first current compensation circuits 311 includes a first current source 3111 and a first switch 3112 connected in series, and each group of second current compensation circuits 321 includes a second current source 3211 and a second switch 3212 connected in series. The offset compensation module 3 also includes a counter unit 33, which is used to adjust the closing of the first switch 3112 and the second switch 3212. The latch unit 21 is connected in series with the counter unit 33, and the counter unit 33 is also used to cut off the current output of the first compensation submodule 31 and the second compensation submodule 32 according to the judgment result of the offset judgment module 2.

[0050] In an embodiment of the present application, the first current compensation circuit 311 is used to reduce the current at the positive input terminal of the comparator 11, and the second current compensation circuit 321 is used to increase the current at the reverse input terminal of the comparator 11 when the current at the positive input terminal of the comparator 11 drops to 0 and the output of the operational amplifier module 1 does not flip.

[0051] For example, when the short-circuit switch 4 is closed, the current flowing into the first resistor is the largest, and the current flowing into the second resistor is 0. At this time, the operational amplifier module 1 outputs a high potential, and the latch stores a high potential. The first switches 3112 of the first current compensation circuits 311 are closed one by one, and the first current source 3111 outputs current and flows into the operational amplifier module 1, so that the current on the positive input end of the comparator 11 is reduced. If the current on the positive input end of the comparator 11 is reduced to 0, and the high potential stored in the latch has not yet turned to a low potential, the second switches 3212 of the second current compensation circuit 321 are closed one by one, so that the current on the reverse input end of the comparator 11 increases, until the high potential stored in the latch is turned to a low potential, and the current output of the first compensation submodule 31 and the second compensation submodule 32 is cut off.

[0052] Specifically, the current flowing into the first resistor R1 after the plurality of first current compensation circuits 311 are connected in parallel and divided is I csp , the current flowing into the second resistor R2 after the plurality of second current compensation circuits 321 are connected in parallel and divided is I csn , the counter unit 33 includes Q and Q N , Q and Q N They are inverted signals to each other, and the reference current in the circuit is i.

[0053] in,

[0054]

[0055]

[0056] In the embodiment of the present application, the output of the operational amplifier module 1 is affected by the offset voltage ΔV of the comparator 11. th The impact of csp ·R1-I csn ·The influence of R2. When ΔV th <I csp ·R1-I csn ·R2, the operational amplifier module 1 outputs a high level; when ΔV th =I csp ·R1-I csn When R2 is set, the operational amplifier module 1 outputs a low level. In implementation, a high level output indicates that the influence caused by the offset of the comparator 11 has not been eliminated, and a low level output indicates that the influence caused by the offset of the comparator 11 on the circuit has been effectively eliminated.

[0057] In one embodiment, the RST signal in the counter unit 33 jumps from low to high, and the counter unit 33 initializes the output Q<9:0>=000000000, Q N <9:0>=1111111111. At this time, the output of the operational amplifier module 1 receives the offset voltage ΔV of the comparator 11.th The impact of csp ·R1-I csn ·The influence of R2, as long as I csp ·R1-I csn R2>ΔV th , then the output of op amp module 1 is high. After the RST signal jumps high, Q<9:0> increases with the number of clocks. N <9:0> increases with the number of clocks. csp -I csn Each clock cycle decreases by 2i until I csp ·R1-I csn R2+ΔV th = 0, the output of the op amp module 1 jumps from high potential to low potential, and at this time, the Latch signal on the counter unit 33 and the latch unit 21 jumps from high potential to low potential. When Latch becomes low potential, the counter unit 33 stops timing, and Q<9:0> and Q N <9:0> remains unchanged, so I csp ·R1-I csn R2+ΔV th =0, indicating compensation amount I csp ·R1-I csn R2 just compensates for the offset voltage ΔV of comparator 11 th At this time, the comparator 11 has zero offset relative to the input signal of the operational amplifier module 1.

[0058] The embodiment of the present application also provides an offset compensation system, the offset compensation system is configured as above Figures 1 to 2 The offset compensation circuit shown in the figure is used to compensate for the offset voltage in the comparator 11. When the current is input into the comparator 11, the offset voltage of the comparator 11 is eliminated. Impact on the circuit.

[0059] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. An offset compensation circuit, characterized in that: The invention comprises an operational amplifier module (1), an offset determination module (2) and an offset compensation module (3), wherein the offset compensation module (3) comprises a first compensation submodule (31) and a second compensation submodule (32), wherein the first compensation submodule (31) and the second compensation submodule (32) are respectively connected in series with the operational amplifier module (1), the operational amplifier module (1) and the offset determination module (2) are connected in series, and the offset determination module (2) and the offset compensation module (3) are connected in series; The operational amplifier module (1) comprises a comparator (11), a first resistor R1 is connected in series to a positive input terminal of the comparator (11), and a second resistor R2 is connected in series to a negative input terminal of the comparator (11); The first compensation submodule (31) comprises a plurality of groups of first current compensation circuits (311) connected in parallel, and the first current compensation circuits (311) are used to reduce the current at the positive input terminal of the comparator (11); The second compensation submodule (32) comprises a plurality of groups of second current compensation circuits (321) connected in parallel, and the second current compensation circuits (321) are used to increase the current at the reverse input terminal of the comparator (11); The imbalance determination module (2) is used to receive and store the potential information output by the operational amplifier module (1); The offset compensation module (3) is used to cut off the current input from the first current compensation circuit (311) and the second current compensation circuit (321) to the operational amplifier module (1) when the potential information stored in the offset determination module (2) is 0; The offset compensation module (3) further comprises a counter unit (33), the counter unit (33) being connected in series with the offset determination module (2), the counter unit (33) being used to cut off the current output of the first compensation submodule (31) and the second compensation submodule (32) according to the determination result of the offset determination module (2); The input end of the mismatch determination module (2) is connected to the output end of the operational amplifier module (1), and the mismatch determination module (2) comprises a latch unit (21), and the latch unit (21) is connected in series with a counter unit (33); The latch unit (21) is used to store the potential information output by the operational amplifier module (1) and synchronize the potential information to the counter unit (33).

2. The offset compensation circuit according to claim 1, characterized in that: The first current compensation circuit (311) is used to reduce the current at the positive input terminal of the comparator (11), and the second current compensation circuit (321) is used to increase the current at the negative input terminal of the comparator (11) when the current at the positive input terminal of the comparator (11) drops to 0 and the output of the operational amplifier module (1) does not flip.

3. The offset compensation circuit according to claim 1, characterized in that: Each group of the first current compensation circuits (311) includes a first current source (3111) and a first switch (3112) connected in series; each group of the second current compensation circuits (321) includes a second current source (3211) and a second switch (3212) connected in series.

4. The offset compensation circuit according to claim 1, characterized in that: A short-circuit switch (4) for short-circuiting the comparator (11) is connected between the positive input end of the comparator (11) and the negative input end of the comparator (11).

5. The offset compensation circuit according to claim 2, characterized in that: The current flowing into the first resistor R1 after the plurality of groups of the first current compensation circuits (311) are connected in parallel and divided is I csp , the current flowing into the second resistor R2 after the plurality of groups of the second current compensation circuits (321) are connected in parallel and divided is I csn ; in, The Q and Q N They are inverted signals to each other, and i is the reference current.

6. The offset compensation circuit according to claim 5, characterized in that: The comparator (11) has an offset voltage ΔV th , the op amp module is used to th csp ·R1-I csn · Output high level when R2; at ΔV th =I csp ·R1-I csn · When R2, the output is low level.​ 7. The offset compensation circuit according to claim 6, characterized in that: The imbalance determination module (2) further comprises a third current source (22) connected in series with the latch unit (21), and the third current source (22) is grounded.

8. An offset compensation system, characterized in that: The offset compensation system is configured with an offset compensation circuit as claimed in any one of claims 1 to 7, and the offset compensation system is used for comparator (11) having an offset voltage ΔV th When the current is input into the comparator (11), the offset voltage ΔV of the comparator (11) is eliminated. th Impact on the circuit.

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