A high-speed digital feedback equalization device and method

Abstract

This application relates to the field of semiconductor integrated circuit technology, and more specifically, to a high-speed digital feedback equalization device and method. The device includes a pre-feedback filter array and a decision sorting module, which are connected. The pre-feedback filter array is used for pre-decision processing of the input signal, and the decision sorting module is used for final decision processing of the input signal. This application decomposes the long feedback chain of parallel feedback filtering into multiple sub-sorting units, thereby shortening the feedback chain length and increasing the circuit operating frequency. In particular, by changing the number of sub-sorting stages, this application can achieve feedback equalization speeds from 50Gbps to 500Gbps or even higher.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and more specifically, to a high-speed digital feedback equalization device and method. Background Technology

[0002] With the development of 5G, high-speed feedback equalization is required for 50Gbps and 100Gbps data reception to achieve data recovery. However, existing digital integrated circuits have a main frequency in the GHz range, and their feedback equalization requires multiple units to execute in parallel. This parallel execution forms a long feedback chain, which in turn introduces huge path delays, thereby reducing the circuit frequency.

[0003] Therefore, achieving high-speed parallel feedback equalization is a key challenge in high-speed digital reception. The challenge of achieving 50GHz and 100Gbps feedback equalization at a GHz clock frequency remains a subject of ongoing research. Summary of the Invention

[0004] Based on the above-mentioned technical problems, the present invention aims to decompose the long feedback chain of parallel feedback filtering into multiple sub-sorting units, thereby shortening the length of the feedback chain and improving the circuit operating frequency.

[0005] The first aspect of the present invention provides a high-speed digital feedback equalization device, the device comprising a pre-feedback filter array and a decision sorting module, the pre-feedback filter array being connected to the decision sorting module, the pre-feedback filter array being used for pre-decision of the input signal, and the decision sorting module being used for final decision of the input signal.

[0006] In some embodiments of the present invention, the prefeedback filter array includes a first preset number of prefeedback filters, the first preset number of prefeedback filters being independent and parallel, and the prefeedback filters including a forward feedback equalizer and a decision feedback equalizer.

[0007] In some embodiments of the present invention, each of the first preset number of pre-feedback filters is configured with a second preset number of feedback inputs to output a second preset number of pre-decisions.

[0008] In some embodiments of the present invention, the decision sorting module includes a sub-decision sorting module and a total decision sorting module, wherein the output of the sub-decision sorting module is connected to the input of the total decision sorting module.

[0009] In some embodiments of the present invention, the sub-decision sorting module includes multi-level serial decision paths, wherein the decision output of the previous level serves as the decision input of the next level, so as to realize the operation of the multi-level decision chain.

[0010] In some embodiments of the present invention, a first preset number is multiplied by a second preset number to obtain a third preset number, and the sub-decision sorting module sorts and groups the pre-decisions of the third preset number.

[0011] In some embodiments of the present invention, the sub-decision sorting module outputs a first preset number of sub-decisions, and the total decision sorting module converts the first preset number of sub-decisions into a second preset number of sequences, wherein each sequence has a first preset number of positions.

[0012] In some embodiments of the present invention, the total decision sorting module uses the sub-decision output of the previous clock cycle as the total decision input of the current clock cycle.

[0013] Preferably, the device further includes a delay circuit.

[0014] A second aspect of the present invention provides a high-speed digital feedback equalization method, the method comprising:

[0015] A preliminary decision is made by combining a first preset number of input signals with a second preset number of feedback inputs;

[0016] The preliminary decision results are sorted and grouped, and then sub-decisions are obtained based on multi-level decisions. The output of the decision of the previous level is used as the input of the decision of the next level to realize the operation of the multi-level decision chain.

[0017] The first preset number of sub-decisions are converted into a second preset number of sequences, where each sequence has a first preset number of bits, and a total decision is made.

[0018] A third aspect of the present invention provides a data receiving system for 5G networks, wherein the data receiving system for 5G networks applies the high-speed digital feedback equalization device described in various embodiments of the present invention.

[0019] The beneficial effects of this application are as follows: The device described in this application includes a pre-feedback filter array and a decision sorting module, which are connected. The pre-feedback filter array is used for pre-decision of the input signal, and the decision sorting module is used for final decision of the input signal. The decision sorting module includes a sub-decision sorting module and a total decision sorting module. The sub-decision sorting module includes multi-stage serial decision paths, wherein the decision output of the previous stage serves as the decision input of the next stage, thereby realizing the operation of a multi-stage decision chain. The long feedback chain of parallel feedback filtering is decomposed into multiple sub-sorting units, thereby shortening the length of the feedback chain and improving the circuit operating frequency. In particular, this application can achieve feedback equalization at speeds of 50Gbps to 500Gbps or even higher by changing the number of sub-sorting stages.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, illustrate embodiments of this application and, together with the description, serve to explain the principles of this application.

[0022] This application can be more clearly understood with reference to the accompanying drawings and the following detailed description, wherein:

[0023] Figure 1 A schematic diagram of the structure of a high-speed digital feedback equalization device in an exemplary embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of the pre-feedback filter structure in an exemplary embodiment of this application is shown;

[0025] Figure 3 This invention provides a schematic diagram of the structure of a decision sorting module according to an exemplary embodiment of the present application.

[0026] Figure 4 This illustration shows a schematic diagram of the working process of the sub-decision sorting module in an exemplary embodiment of this application;

[0027] Figure 5 This illustration shows a schematic diagram of the overall decision sorting module's operation in an exemplary embodiment of this application;

[0028] Figure 6 A schematic diagram of a conventional high-speed digital feedback equalization device based on a feedback chain is shown in an exemplary embodiment of this application.

[0029] Figure 7 A schematic diagram illustrating the steps of a high-speed digital feedback equalization method in an exemplary embodiment of this application is shown.

[0030] Figure 8 This application shows a schematic diagram of the structure of a computer device provided in an exemplary embodiment.

[0031] Figure 9 A schematic diagram of a storage medium provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0032] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application. It will be apparent to those skilled in the art that this application can be implemented without one or more of these details. In other instances, some technical features well-known in the art have not been described to avoid confusion with this application.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0034] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. The drawings are not drawn to scale, and some details may be enlarged and omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] The following is in conjunction with the instruction manual appendix. Figure 1-9 Several embodiments are given to describe exemplary implementations according to this application. It should be noted that the following application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementations of this application are not limited in any way. Rather, the implementations of this application can be applied to any applicable scenario.

[0036] Example 1:

[0037] This embodiment provides a high-speed digital feedback equalization device, such as... Figure 1 As shown, the device includes a pre-feedback filter array and a decision sorting module, which are connected together. The pre-feedback filter array is used for pre-decision of the input signal, and the decision sorting module is used for final decision of the input signal.

[0038] In a preferred embodiment, the pre-feedback filter array includes a first preset number of pre-feedback filters, which are independent and parallel, such as... Figure 2 As shown, the pre-feedback filter includes a forward feedback equalizer and a decision feedback equalizer. Each of the first preset number of pre-feedback filters is configured with a second preset number of feedback inputs to output a second preset number of pre-decisions. For example... Figure 2 As shown, FFE (Feed Forward Equalization) represents a forward feedback equalizer, and DFE (Decision Feedback Equalization) represents a decision feedback equalizer, where f0, f1, ... f N-1 This indicates feedback input; here we can see that the second preset number is N. f0, f1, ... f N-1 This indicates that feedback inputs can be supplied in different ways based on existing technologies.

[0039] Example 2:

[0040] This embodiment provides a high-speed digital feedback equalization device, which includes a pre-feedback filter array and a decision sorting module. The pre-feedback filter array is connected to the decision sorting module. The pre-feedback filter array is used for pre-decision of the input signal, and the decision sorting module is used for final decision of the input signal.

[0041] In some implementations, the pre-feedback filter array includes a first preset number of pre-feedback filters, which operate independently and in parallel. Each pre-feedback filter includes a forward feedback equalizer and a decision feedback equalizer. For example, the forward filter implements a 10th-order FIR filter on the input signal; the four feedback filters implement four feedback filters and decision outputs for multiple feedback inputs 0, 1, 2, and 3, where 4 represents the second preset number.

[0042] In some implementations, each of the first preset number of pre-feedback filters is configured with a second preset number of feedback inputs to output a second preset number of pre-decisions.

[0043] In some embodiments, the decision sorting module includes a sub-decision sorting module and a total decision sorting module, with the output of the sub-decision sorting module connected to the input of the total decision sorting module. For example... Figure 3 As shown, the sub-decision sorting module receives the output results of the pre-decision sequence, i.e., the pre-feedback filter array, and the total decision sorting module then makes the final decision.

[0044] In some implementations, the sub-decision sorting module includes multi-level cascaded decision paths, such as... Figure 4As shown, the decision output of the previous level serves as the decision input of the next level, thus realizing the operation of a multi-level decision chain. Figure 4 In this context, N represents the second preset number. Since the numbers start from 0, a number of N-1 indicates the Nth element. Assuming the first preset number is 32 and the second preset number is 4, then N equals 4. 0,0 The first 0 in d represents the series, i.e., the first level, and the second 0 represents the first input in the first level. 0,N-1 The first 0 in the sequence represents the series, i.e., the first level. N-1 represents the Nth input in the first level. The output of the first level serves as the input for the second level, and so on. Figure 2 This is only a partial diagram and does not show the situation where all pre-decision decisions reach the sub-decision sorting module; it only serves as an illustration.

[0045] In some implementations, a first preset number is multiplied by a second preset number to obtain a third preset number, and the sub-decision sorting module sorts and groups the pre-decisions of the third preset number. For example, if the first preset number is 32 and the second preset number is 4, 32 multiplied by 4 equals 128. The sub-decision sorting module sorts and groups the 128 pre-decisions. Since the first level has 4 inputs, it can output 4 decision chains, each decision chain having 8 outputs, thereby achieving an 8-level decision chain.

[0046] In some implementations, the sub-decision sorting module outputs a first preset number of sub-decisions, and the total decision sorting module converts the first preset number of sub-decisions into a second preset number of sequences, wherein each sequence has a first preset number of positions.

[0047] In some implementations, such as Figure 5 As shown, the total decision sorting module uses the sub-decision output of the previous clock cycle as the total decision input of the current clock cycle. Following the example of the sub-decision sorting module, by using the previous sub-decision output as the total decision input for the next cycle, four 8-level decision chains are linked. Figure 5 As shown, for example, if the first preset number is 32 and the second preset number is 4, the total decision sorting module will have four 32-bit sequences, where Q equals 8 and N equals 4. Using the 31st decision from the previous sub-decision output, the first input selection for this total decision is chosen, thus obtaining outputs 0 to 7 for this decision. Then, the 7th output is used as the second-level selection input to obtain outputs 8 to 15, and so on, until all total decision outputs are obtained.

[0048] In some preferred embodiments, the device further includes a delay circuit to enable the operation of a multi-stage decision chain.

[0049] The device described in this application includes a pre-feedback filter array and a decision sorting module, which are connected. The pre-feedback filter array is used for pre-decision processing of the input signal, and the decision sorting module is used for final decision processing of the input signal. The decision sorting module includes a sub-decision sorting module and a total decision sorting module. The sub-decision sorting module includes multi-stage cascaded decision paths, where the decision output of the previous stage serves as the decision input of the next stage, thereby realizing the operation of a multi-stage decision chain. This decomposes the long feedback chain of parallel feedback filtering into multiple sub-sorting units, thus shortening the length of the feedback chain and increasing the circuit operating frequency. In particular, this application can achieve feedback equalization at speeds of 50Gbps to 500Gbps or even higher by changing the number of sub-sorting stages.

[0050] Example 3:

[0051] This embodiment provides a data receiving system for 5G networks, which utilizes the high-speed digital feedback equalization device described in various embodiments of this application. The device includes a pre-feedback filter array and a decision sorting module, which are connected. The pre-feedback filter array is used for pre-decision processing of the input signal, and the decision sorting module is used for final decision processing of the input signal.

[0052] Figure 6 For traditional high-speed digital feedback equalization devices based on feedback chains, such as Figure 6 As shown, this parallel execution forms a long feedback chain, which in turn introduces significant path delay, thus reducing circuit frequency. However, data receiving systems for 5G networks can achieve feedback equalization at speeds from 50Gbps to 500Gbps or even higher.

[0053] Example 4:

[0054] This embodiment provides a high-speed digital feedback equalization method, such as Figure 7 As shown, the method includes:

[0055] S1. Make a preliminary decision by combining the first preset number of input signals with the second preset number of feedback inputs;

[0056] S2. Sort and group the pre-judgment results, and then obtain sub-judgments based on multi-level judgments. The output of the previous level judgment is used as the input of the next level judgment to realize the operation of the multi-level judgment chain.

[0057] S3. Convert the first preset number of sub-decisions into a second preset number of sequences, wherein each sequence has a first preset number of bits, and perform a total decision.

[0058] In practical implementation, feedback inputs can be supplied in different ways according to existing technologies. In some preferred embodiments, the first preset number is set to 32, and the second preset number is set to 4. After pre-decision, the pre-decision result is 32*4 equal to 128. The 128 pre-decisions are sorted and grouped. Since there are 4 inputs in the first level, 4 decision chains can be output, each with 8 outputs, thus realizing an 8-level decision chain. When making the final decision, the sub-decision output of the previous clock cycle is used as the final decision input for the current clock cycle. For example, if the first preset number is 32 and the second preset number is 4, the final decision will have 4 32-bit sequences. The 31st decision from the previous sub-decision output is used to select the first input for the current final decision, thus obtaining the 0th to 7th outputs of the current decision. Then, the 7th output is used as the second-level selection input to obtain the 8th to 15th outputs, and so on, until all final decision outputs are obtained.

[0059] It should also be emphasized that the system provided in this application embodiment can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results. Basic AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing technology, operating / interactive systems, and mechatronics. AI software technologies mainly include computer vision technology, robotics technology, biometrics technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0060] Please refer to the following. Figure 8 This illustrates a schematic diagram of a computer device provided by some embodiments of this application. For example... Figure 8 As shown, the computer device 2 includes: a processor 200, a memory 201, a bus 202, and a communication interface 203. The processor 200, the communication interface 203, and the memory 201 are connected via the bus 202. The memory 201 stores a computer program that can run on the processor 200. When the processor 200 runs the computer program, it executes the steps of the high-speed digital feedback equalization method provided in any of the foregoing embodiments of this application.

[0061] The memory 201 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 203 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0062] Bus 202 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs. After receiving an execution instruction, the processor 200 executes the program. The high-speed digital feedback equalization method disclosed in any of the foregoing embodiments of this application can be applied to the processor 200, or implemented by the processor 200.

[0063] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the above method.

[0064] This application also provides a computer-readable storage medium corresponding to the high-speed digital feedback equalization method provided in the foregoing embodiments. Please refer to... Figure 9 , Figure 9The computer-readable storage medium shown is an optical disc 30, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it executes the steps performed by the high-speed digital feedback equalization method provided in any of the foregoing embodiments.

[0065] In addition, examples of the computer-readable storage medium may include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be described in detail here.

[0066] The computer-readable storage medium provided in the above embodiments of this application and the quantum key distribution channel allocation method in the space division multiplexing optical network provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0067] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the high-speed digital feedback equalization method provided in any of the foregoing embodiments, including: performing a pre-decision on a first preset number of input signals combined with a second preset number of feedback inputs; sorting and grouping the pre-decision results, and then obtaining sub-decisions based on multi-level decisions, wherein the decision output of the previous level serves as the decision input of the next level to realize the operation of a multi-level decision chain; converting the first preset number of sub-decisions into a second preset number of sequences, wherein each sequence has a first preset number of bits, and performing a total decision.

[0068] It should be noted that the algorithms and displays provided herein are not inherently related to any particular computer, virtual device, or other equipment. Various general-purpose devices can also be used in conjunction with the teachings herein. The required structure for constructing such devices is obvious from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application. Numerous specific details are set forth in the specification provided herein. However, it is to be understood that embodiments of this application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0069] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0070] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed herein and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed herein may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0071] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the virtual machine creation apparatus according to embodiments of this application. This application can also be implemented as a device or apparatus program for performing part or all of the methods described herein. The program implementing this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0072] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-speed digital feedback equalization device, characterized in that, The device includes a pre-feedback filter array and a decision sorting module, which are connected together. The pre-feedback filter array is used for pre-decision of the input signal, and the decision sorting module is used for final decision of the input signal. The decision sorting module includes a sub-decision sorting module and a total decision sorting module. The output of the sub-decision sorting module is connected to the input of the total decision sorting module to achieve feedback equalization at speeds of 50Gbps to 500Gbps or even higher. The prefeedback filter array includes a first preset number of prefeedback filters, which are independent and parallel. The prefeedback filters include a forward feedback equalizer and a decision feedback equalizer.

2. The high-speed digital feedback equalization device according to claim 1, characterized in that, Each of the first preset number of pre-feedback filters is configured with a second preset number of feedback inputs to output a second preset number of pre-decisions.

3. The high-speed digital feedback equalization device according to claim 1, characterized in that, The sub-decision sorting module includes multi-level serial decision paths, where the decision output of the previous level serves as the decision input of the next level, thereby enabling the operation of the multi-level decision chain.

4. The high-speed digital feedback equalization device according to claim 1, characterized in that, The first preset number is multiplied by the second preset number to obtain the third preset number, and the sub-decision sorting module sorts and groups the pre-decision of the third preset number.

5. The high-speed digital feedback equalization device according to claim 4, characterized in that, The sub-decision sorting module outputs a first preset number of sub-decisions, and the total decision sorting module converts the first preset number of sub-decisions into a second preset number of sequences, wherein each sequence has a first preset number of positions.

6. The high-speed digital feedback equalization device according to claim 5, characterized in that, The total decision sorting module uses the sub-decision output of the previous clock cycle as the total decision input of the current clock cycle.

7. A high-speed digital feedback equalization method, characterized in that, The method includes: By using independent and parallel forward feedback equalizers and decision feedback equalizers, a pre-decision is made on a first preset number of input signals combined with a second preset number of feedback inputs. The preliminary decision results are sorted and grouped, and then sub-decisions are obtained based on multi-level decisions. The output of the decision of the previous level is used as the input of the decision of the next level to realize the operation of the multi-level decision chain. The first preset number of sub-decisions are converted into a second preset number of sequences, where each sequence has a first preset number of bits, and a total decision is made to achieve feedback equalization at speeds of 50Gbps to 500Gbps or even higher.

8. A data receiving system for 5G networks, characterized in that, The data receiving system for 5G networks uses the high-speed digital feedback equalization device as described in any one of claims 1-6.

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