Display device and its driving method

Abstract

In display devices with external compensation, the reduction in compensation accuracy caused by coupling noise generated on the data signal lines is prevented. The source driver has an integrating circuit that measures the current corresponding to the characteristics of the driving transistor. The emitter driver applies an emitting control signal to each emitting control line based on multiple emitting control clock signals (ECK1 to ECK4) output from the display control circuit. During current measurement, at the edge timing when the level of at least one of the multiple emitting control clock signals (ECK1 to ECK4) changes, the inflow of current corresponding to the characteristics of the driving transistor into the integrating circuit is stopped.

Description

Technical Field

[0001] The following disclosure relates to a display device and a driving method thereof, and more specifically, to a display device and a driving method thereof having a pixel circuit comprising display elements such as organic EL elements that are driven by current. Background Technology

[0002] In recent years, organic EL display devices, which incorporate pixel circuits containing organic EL elements, have been put into practical use. Organic EL elements, also known as OLEDs (Organic Light-Emitting Diodes), are self-emissive display elements that emit light in a brightness corresponding to the current flowing through them. Thus, because organic EL elements are self-emissive, organic EL display devices can easily achieve thinner designs, lower power consumption, and higher brightness compared to liquid crystal display devices that require backlights and color filters.

[0003] In active-matrix OLED display devices, multiple pixel circuits are formed in a matrix. Each pixel circuit includes a driving transistor that controls the supply of current to the OLED element. Typically, a thin-film transistor (TFT) is used as this driving transistor. However, the threshold voltage of a TFT changes due to degradation. Since many driving transistors are provided in the display section of an OLED display device, the degree of degradation varies for each individual driving transistor, resulting in a deviation in the threshold voltage. As a result, brightness deviations occur, and display quality is reduced. Furthermore, the current efficiency of the OLED element decreases over time. That is, even if a constant current is supplied to the OLED element, its brightness gradually decreases over time. As a result, image retention occurs. Due to these factors, in active-matrix OLED display devices, compensation for the degradation of the driving transistors and the OLED element has been performed in the past.

[0004] As one method of compensation processing, external compensation is known. According to external compensation, a circuit located outside the pixel circuit measures the current flowing through the driving transistor or organic EL element under specified conditions. Then, based on this measurement result, correction is applied to the input image signal. Thus, degradation of the driving transistor and the organic EL element is compensated.

[0005] Furthermore, the following refers to a series of processes that measure the current flowing through the pixel circuit outside the pixel circuit in order to compensate for the degradation of the driving transistor or organic EL element (display element), called "monitoring process," and the period during which the monitoring process is performed is called "monitoring period." Additionally, lines that are subject to monitoring process within a unit period such as one frame are called "monitored lines," and lines other than the monitored lines are called "non-monitored lines." Furthermore, the characteristics of the driving transistor provided in the pixel circuit are called "TFT characteristics," and the characteristics of the organic EL element provided in the pixel circuit are called "OLED characteristics." Finally, the process of applying a desired potential (voltage) to the data signal line to charge the capacitor (holding capacitor) in the pixel circuit is called "writing."

[0006] Here, the method of monitoring during normal display (hereinafter referred to as "real-time monitoring") will be explained. In real-time monitoring, typically, monitoring is performed on at least one line during each frame. That is, in the case of real-time monitoring, such as... Figure 15 As shown, each frame period includes a monitoring period. Regarding each frame period, the period outside the monitoring period is the scanning period. The scanning period is the time during which the scan signal lines are scanned for image display. Furthermore, in Figure 15 In the diagram, a slanted thick line schematically illustrates the process of sequentially scanning the scan signal lines GL(1) of the first row to GL(n) of the nth row for writing to an image display.

[0007] Figure 16 This is a schematic diagram illustrating the shift of the off range (the range within the pixel circuit where the organic EL element stops emitting light) 90 during a frame. From Figure 16 It can be seen that the extinguishing range 90 shifts from row 1 to row n. In the monitored row, the organic EL elements within the pixel circuit stop emitting light throughout the monitoring period.

[0008] Figure 5 This is a circuit diagram showing a portion of the pixel circuitry 110 and the source driver in an organic EL display device employing external compensation. Furthermore, Figure 5 The pixel circuit 110 in the i-th row and j-th column is shown, as well as the portion of the source driver corresponding to the data signal line SL(j) in the j-th column. The source driver includes: a portion that functions as a data signal line driving unit 310 that drives the data signal line SL(j); and a portion that functions as a current monitoring unit 320 that measures the current output from the pixel circuit 110 to the data signal line SL(j).

[0009] The pixel circuit 110 includes: one organic EL element L1; four transistors T1 to T4 (a write control transistor T1 that controls writing to capacitor C, a drive transistor T2 that controls the supply of current to the organic EL element L1, a monitoring control transistor T3 that controls whether to detect TFT characteristics or OLED characteristics, and a light-emitting control transistor T4 that controls whether to make the organic EL element L1 emit light); and one capacitor C as a holding capacitor. The current monitoring unit 320 includes an operational amplifier 301, a D / A converter 306, a capacitor 322, a switch 323 whose state is controlled by control signal S2, a switch 324 whose state is controlled by control signal S1, and a switch 325 whose state is controlled by control signal S0. (Regarding...) Figure 5 The scan signal line in the i-th row is labeled with reference numeral GL(i), the monitoring control line in the i-th row with reference numeral ML(i), the illumination control line in the i-th row with reference numeral EM(i), and the data signal line in the j-th column with reference numeral SL(j). Furthermore, the same reference numerals are used for scan signal lines and scan signals, monitoring control lines and monitoring control signals, illumination control lines and illumination control signals, and data signal lines and data signals thereafter.

[0010] Furthermore, within the current monitoring unit 320, an integrating circuit 35 is constructed from an operational amplifier 301, a capacitor 322, and a switch 323. This integrating circuit 35 measures the current corresponding to the characteristics of the TFT and the OLED, and outputs the time integral of this current.

[0011] In such a configuration, for example, the detection of TFT characteristics for one row or the detection of OLED characteristics for one row is performed during each frame period (each vertical scan period). Figure 17 This is a signal waveform diagram used to illustrate the operation during the monitoring period when detecting TFT characteristics. The operation of each period within the monitoring period is explained below. Furthermore, it is assumed that the i-th row is the monitoring row.

[0012] When the time period P11 arrives, the light emission control signal EM(i) changes from high to low. This turns off the light emission control transistor T4, stopping the current supply to the organic EL element L1. During P11, control signals S2 and S1 are high, and control signal S0 is low. Therefore, switches 323 and 324 are on, and switch 325 is off. At this time, the data signal line SL(j) is electrically connected to the internal data line Sin(j). During P11, the scan signal GL(i) and the monitoring control signal ML(i) remain high. Therefore, the write control transistor T1 and the monitoring control transistor T3 remain on. Under these conditions, the initialization potential Vpc is applied to the data signal line SL(j). This initializes the state of capacitor C and the potential of node 111 (the node connected to the anode terminal of the organic EL element L1 via the light emission control transistor T4).

[0013] When the time period P12 is reached, the monitoring control signal ML(i) changes from high to low. This turns the monitoring control transistor T3 off. In this state, the characteristic detection potential Vr_TFT is applied to the data signal line SL(j). This turns the drive transistor T2 on.

[0014] When the time period P13 is reached, the scan signal GL(i) changes from high to low, and the monitoring control signal ML(i) changes from low to high. As a result, the write control transistor T1 becomes off, and the monitoring control transistor T3 becomes on. In this state, the current measurement potential Vm_TFT is applied to the data signal line SL(j). Consequently, the current flowing through the drive transistor T2 flows to the current monitoring unit 320 via the monitoring control transistor T3 and the data signal line SL(j). At this time, the control signal S2 is high, therefore the switch 323 is on, and no charge accumulates in the capacitor 322.

[0015] When the period P14 occurs, the control signal S2 changes from high to low. As a result, switch 323 becomes open, and the operational amplifier 301 and capacitor 322 perform time integration of the current. That is, the output voltage of the operational amplifier 301 becomes the voltage corresponding to the current flowing through the data signal line SL(j). Hereinafter, the period during which the voltage proportional to the integral of the current is calculated by the integrator circuit 35, as in period P14, will be referred to as the "integration period".

[0016] When the time interval P15 is reached, control signal S1 changes from high to low, and control signal S0 changes from low to high. As a result, switch 324 becomes open, and switch 325 becomes on. Since switch 324 is open, data signal line SL(j) and internal data line Sin(j) are electrically disconnected. In this state, the output voltage of operational amplifier 301 (monitoring data MOa) is converted into monitoring data MOd as digital data by A / D converter 31. Thus, the detection of the TFT characteristics for the i-th row ends. Furthermore, the AD-converted monitoring data Mod is used for digital video signal correction.

[0017] Subsequently, during period P16, the light emission control signal EM(i) changes from low to high. This turns on the light emission control transistor T4. Additionally, during period P16, control signals S2 and S1 change from low to high, and control signal S0 changes from high to low. This turns on switches 323 and 324, and off switch 325. Furthermore, during period P16, the scan signal GL(i) changes from low to high. This turns on the write control transistor T1. Under these conditions, the data potential Vd(i) for image display is applied to the data signal line SL(j), and writing based on this data potential Vd(i) is performed in the pixel circuit 110 of the i-th row and j-th column. This causes the organic EL element L1 to emit light.

[0018] When the period P17 is reached, the scan signal GL(i) changes from high to low. As a result, the write control transistor T1 becomes off. Furthermore, during period P17, a data potential Vd(i+1) for image display is written to the (i+1)th row.

[0019] In existing organic EL display devices, monitoring processing is performed as shown above, and the digital video signal is corrected based on the results of the monitoring processing, thereby compensating for the degradation of the drive transistor T2.

[0020] Furthermore, inventions relating to organic EL display devices employing external compensation methods are disclosed, for example, in International Publication No. 2015 / 190407.

[0021] Prior art literature

[0022] Patent documents

[0023] Patent Document 1: International Publication No. 2015 / 190407 Summary of the Invention

[0024] The problem the invention aims to solve

[0025] However, the timing of the light emission control signal EM changing from high to low and the timing of the light emission control signal EM changing from low to high are as follows: Figure 18 As shown, they are staggered slightly between each row. Additionally, when focusing on the light-emitting control clock signals ECK1 to ECK4 used to generate the light-emitting control signal EM, as... Figure 19 As shown by reference numeral 94 in the attached figure, a change in level also occurs during the integration period P14 described above. Therefore, as... Figure 17 The part labeled 91 in the attached figure. Figure 18 As shown in the figures labeled 92 and 93, a light emission control signal EM with a changing level exists in P14 during the integration period. Additionally, as... Figure 5 As shown, the light-emitting control line EM is configured to cross the data signal line SL. Therefore, there is a distance between the light-emitting control line EM and the data signal line SL. Figure 5 The parasitic capacitance is indicated by reference numeral 99 in the attached figure. Accordingly, during the integration period P14, as... Figure 19 As shown by reference numeral 95 in the attached figure, coupling noise is generated on the data signal line SL due to variations in the level of the light emission control signal EM for the non-monitored row. Therefore, it is impossible to accurately measure the current flowing through the data signal line SL.

[0026] Figure 20 and Figure 21 This diagram illustrates the impact of coupling noise on each line. Here, it is assumed that the width L of the light emission control signal EM (the length of time the light emission control signal EM remains low) is 20H (during the horizontal scan period), and the 16th H of 20H corresponds to the integration period. Furthermore, it is assumed that the number of lines in the display section (the number of pixel circuits in the direction in which the data signal line SL extends) is 720.

[0027] The current measurement results during the integration period in row 1 are affected by the decrease in the light emission control signal EM(17). The current measurement results during the integration period in row 4 are affected by the decrease in the light emission control signal EM(20). Thus, the current measurement results during the integration period in rows 1 to 4 are only affected by the decrease in the light emission control signal EM in the other rows.

[0028] The current measurement result during the integration period in row 5 is affected by the rise of the light emission control signal EM(1) and the fall of the light emission control signal EM(21). The current measurement result during the integration period in row 704 is affected by the rise of the light emission control signal EM(700) and the fall of the light emission control signal EM(720). Thus, the current measurement results during the integration period in rows 5 to 704 are affected by both the rise and fall of the light emission control signal EM in the other rows.

[0029] The current measurement result during the integration period in line 705 is affected by the rise of the light emission control signal EM (701). The current measurement result during the integration period in line 720 is affected by the rise of the light emission control signal EM (716). Thus, the current measurement results during the integration period in lines 705 to 720 are only affected by the rise of the light emission control signal EM in other lines.

[0030] As shown above, the effect of coupling noise on the current measurement results is not the same across all rows. Therefore, even if the digital video signal is corrected based on the current measurement results, the degradation of the drive transistor will not be adequately compensated.

[0031] Therefore, the purpose of the following disclosure is to prevent a decrease in compensation accuracy caused by coupling noise generated on the data signal line in a display device with external compensation function.

[0032] Solutions for solving problems

[0033] Some embodiments of the display device disclosed herein include a pixel circuit comprising a display element driven by a current and a drive transistor controlling the drive current of the display element. The display device also has a function of performing monitoring processing, which is a series of processes that measure a current flowing through the pixel circuit outside the pixel circuit, corresponding to the characteristics of the drive transistor. The display device further includes:

[0034] The display unit includes: multiple data signal lines; multiple scan signal lines; and multiple light emission control lines, which are configured to correspond one-to-one with the multiple scan signal lines and cross the multiple data signal lines.

[0035] The data signal line driving circuit applies data signals to the aforementioned multiple data signal lines;

[0036] A scan signal line driving circuit that applies scan signals to the aforementioned plurality of scan signal lines; and

[0037] The light-emitting control line driving circuit applies light-emitting control signals to the plurality of light-emitting control lines, and includes a shift register comprising multiple unit circuits corresponding to the plurality of light-emitting control lines in a one-to-one manner.

[0038] The pixel circuit described above is provided at each intersection of the plurality of data signal lines and the plurality of scan signal lines.

[0039] The aforementioned data signal line driving circuit includes an integrating circuit for measuring the current corresponding to the characteristics of the aforementioned driving transistor.

[0040] The aforementioned shift register, based on multiple light-emitting control clock signals, generates light-emitting control signals to be applied to each light-emitting control line while transmitting the light-emitting control start pulse signal from the first-stage unit circuit to the last-stage unit circuit.

[0041] The monitoring period for performing the above monitoring process includes: a measurement writing period for writing a data signal that causes a current corresponding to the characteristics of the driving transistor to flow into the pixel circuit; and a current measurement period for measuring the current corresponding to the characteristics of the driving transistor by the integrating circuit.

[0042] During the aforementioned current measurement, at the edge timing when the level of at least one of the aforementioned multiple light-emitting control clock signals changes, the inflow of current into the aforementioned integrating circuit, corresponding to the characteristics of the aforementioned driving transistor, is stopped.

[0043] In some embodiments of the driving method of the display device disclosed herein, the display device includes a pixel circuit comprising a display element driven by a current and a driving transistor controlling the driving current of the display element. The display device also has a function of performing monitoring processing, which is a series of processes that measure the current flowing through the pixel circuit, corresponding to the characteristics of the driving transistor, outside the pixel circuit. In the driving method of the display device...

[0044] The above-mentioned display device includes:

[0045] The display unit includes: multiple data signal lines; multiple scan signal lines; and multiple light emission control lines, which are configured to correspond one-to-one with the multiple scan signal lines and cross the multiple data signal lines.

[0046] The data signal line driving circuit applies data signals to the aforementioned multiple data signal lines;

[0047] A scan signal line driving circuit that applies scan signals to the aforementioned plurality of scan signal lines; and

[0048] The light-emitting control line driving circuit applies light-emitting control signals to the plurality of light-emitting control lines, and includes a shift register comprising multiple unit circuits corresponding to the plurality of light-emitting control lines in a one-to-one manner.

[0049] The pixel circuit described above is provided at each intersection of the plurality of data signal lines and the plurality of scan signal lines.

[0050] The aforementioned data signal line driving circuit includes an integrating circuit for measuring the current corresponding to the characteristics of the aforementioned driving transistor.

[0051] The aforementioned shift register, based on multiple light-emitting control clock signals, generates light-emitting control signals to be applied to each light-emitting control line while transmitting the light-emitting control start pulse signal from the first-stage unit circuit to the last-stage unit circuit.

[0052] The monitoring period for performing the above monitoring process includes: a measurement writing period for writing a data signal that causes a current corresponding to the characteristics of the driving transistor to flow into the pixel circuit; and a current measurement period for measuring the current corresponding to the characteristics of the driving transistor by the integrating circuit.

[0053] The above driving method includes:

[0054] The integration stop step stops the flow of current corresponding to the characteristics of the aforementioned driving transistor into the aforementioned integration circuit; and

[0055] The integration recovery step restores the current flowing into the integration circuit corresponding to the characteristics of the aforementioned driving transistor.

[0056] During the aforementioned current measurement, the aforementioned integration stop step is performed immediately before the edge timing of the timing at which the level of at least one of the aforementioned plurality of light emission control clock signals changes, and the aforementioned integration recovery step is performed immediately after the aforementioned edge timing.

[0057] Invention Effects

[0058] According to some embodiments of this disclosure, during the edge timing (timing when the level of at least one of the plurality of light-emitting control clock signals changes) of the current measurement period, the inflow of current corresponding to the characteristics of the driving transistor into the integrating circuit is stopped. Therefore, the actual calculation of the time integration of the current corresponding to the characteristics of the driving transistor is performed during the current measurement period when a stable current flows without being affected by coupling noise. Therefore, even if coupling noise caused by the presence of parasitic capacitance between the light-emitting control line and the data signal line occurs during the current measurement period, the current corresponding to the characteristics of the driving transistor can be detected with good accuracy. Accordingly, in a display device with external compensation function, the reduction in compensation accuracy caused by coupling noise generated on the data signal line can be prevented. Attached Figure Description

[0059] Figure 1 This is a signal waveform diagram used to illustrate the control of the current monitoring unit during the integration period in one embodiment.

[0060] Figure 2 This is a block diagram showing the overall configuration of the organic EL display device in the above embodiment.

[0061] Figure 3This is a diagram used to illustrate the function of the scan driver in the above embodiments.

[0062] Figure 4 This is a diagram used to illustrate the function of the source driver in the above embodiments.

[0063] Figure 5 This is a circuit diagram showing a portion of the pixel circuit and source driver in the above embodiment.

[0064] Figure 6 This is a block diagram illustrating the configuration of the five stages of the shift register constituting the gate driver in the above embodiment.

[0065] Figure 7 This is a circuit diagram showing the configuration of the unit circuit within the gate driver in the above embodiment.

[0066] Figure 8 This is a signal waveform diagram used to illustrate the operation of the unit circuit within the gate driver during monitoring processing in the above embodiments.

[0067] Figure 9 This is a block diagram illustrating the configuration of the five stages of the shift register constituting the transmit driver in the above embodiment.

[0068] Figure 10 This is a circuit diagram showing the configuration of the unit circuit within the transmitter driver in the above embodiment.

[0069] Figure 11 This is a signal waveform diagram used to illustrate the operation of the unit circuit within the transmitter driver in the above embodiments.

[0070] Figure 12 This is a signal waveform diagram used to illustrate the operation of the pixel circuit and the current monitoring unit during monitoring processing in the above embodiments.

[0071] Figure 13 This is a signal waveform diagram used to illustrate the effects of the above-described embodiments.

[0072] Figure 14 This is a circuit diagram showing a portion of the pixel circuit and source driver in a variation of the above-described embodiment.

[0073] Figure 15 This is a diagram used to illustrate real-time monitoring of an existing example.

[0074] Figure 16 This is a diagram schematically illustrating the shift in the range of extinction during a frame in an existing example.

[0075] Figure 17 This is a signal waveform diagram used to illustrate the operation during monitoring in the case of detecting TFT characteristics in an existing example.

[0076] Figure 18 This is a signal waveform diagram used to illustrate the existing example of a light emission control signal whose level changes during the integration period.

[0077] Figure 19 This is a signal waveform diagram used to illustrate the change in the level of the light emission control clock signal during the integration period in a conventional example.

[0078] Figure 20 This is a diagram used to illustrate the effect of coupling noise on each row of the existing example.

[0079] Figure 21 This is a diagram used to illustrate the effect of coupling noise on each row of the existing example. Detailed Implementation

[0080] The implementation method will now be described with reference to the accompanying drawings. Furthermore, it is assumed that m and n are integers of 2 or more, i is an integer of 3 or more and (n-2) or less, and j is an integer of 1 or more and m or less.

[0081] <1. Overall Composition>

[0082] Figure 2 This is a block diagram showing the overall configuration of the active matrix type organic EL display device according to the first embodiment. The organic EL display device includes a display unit 10, a scan driver 20, a source driver (data signal line drive circuit) 30, an A / D converter 31, a correction calculation unit 32, a correction data storage unit 33, and a display control circuit 40. The A / D converter 31, the correction calculation unit 32, and the correction data storage unit 33 are components used to compensate for the degradation of the drive transistors and organic EL elements. That is, the organic EL display device has an external compensation function. Furthermore, in order to perform compensation processing in the external compensation method, the aforementioned real-time monitoring is performed in the organic EL display device. The display unit 10 and the scan driver 20 are integrally formed on the substrate constituting the display unit 10. That is, the scan driver 20 is monolithically formed.

[0083] The display unit 10 is provided with m data signal lines SL(1) to SL(m) and n scan signal lines GL(1) to GL(n) orthogonal to them. Additionally, the display unit 10 is provided with n monitoring control lines ML(1) to ML(n) in a one-to-one correspondence with the n scan signal lines GL(1) to GL(n). Furthermore, the display unit 10 is provided with n light emission control lines EM(1) to EM(n) in a one-to-one correspondence with the n scan signal lines GL(1) to GL(n). The scan signal lines GL(1) to GL(n), the monitoring control lines ML(1) to ML(n), and the light emission control lines EM(1) to EM(n) are parallel to each other. Furthermore, the display unit 10 is provided with (n×m) pixel circuits 110 corresponding to the intersections of the data signal lines SL(1) to SL(m) and the scan signal lines GL(1) to GL(n). Thus, an n-row × m-column pixel matrix is ​​formed in the display unit 10. The display unit 10 is also equipped with a power line (not shown) shared by all pixel circuits 110. More specifically, it is equipped with a power line (hereinafter referred to as "high-level power line") supplying a high-level power supply voltage ELVDD for driving the organic EL element and a power line (hereinafter referred to as "low-level power line") supplying a low-level power supply voltage ELVSS for driving the organic EL element. The high-level power supply voltage ELVDD and the low-level power supply voltage ELVSS are supplied by a power supply circuit (not shown).

[0084] The display control circuit 40 receives the input image signal DIN and timing signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG sent from the outside, and outputs the digital video signal VD1, the control signal SCTL controlling the operation of the source driver 30, the control signal GCTL controlling the operation of the gate driver (described later) within the scan driver 20, and the control signal ECTL controlling the operation of the transmit driver (described later) within the scan driver 20. The control signal SCTL includes the source start pulse signal, the source clock signal, and the latch strobe signal. The control signal GCTL includes the gate start pulse signal, the gate clock signal, and the enable signal. The control signal ECTL includes the light emission control start pulse signal and the light emission control clock signal.

[0085] The A / D converter 31 converts the monitoring data MOa (data measured to determine TFT and OLED characteristics) output from the source driver 30 as analog data into monitoring data MOd as digital data. The correction data storage unit 33 stores the correction data required for the correction calculation performed by the correction calculation unit 32. Based on the monitoring data MOd output from the A / D converter 31, the correction calculation unit 32 updates the correction data stored in the correction data storage unit 33. Furthermore, referring to the correction data stored in the correction data storage unit 33, the correction calculation unit 32 corrects the digital video signal VD1 output from the display control circuit 40 and outputs the corrected digital video signal VD2.

[0086] like Figure 3 As shown, the scan driver 20 functionally includes a portion that functions as a gate driver (scan signal line drive circuit) 210 driving the scan signal lines GL(1) to GL(n) and the monitoring control lines ML(1) to ML(n), and a portion that functions as an emitter driver (light emission control line drive circuit) 220 driving the light emission control lines EM(1) to EM(n). The gate driver 210 is connected to the scan signal lines GL(1) to GL(n) and the monitoring control lines ML(1) to ML(n). As described later, the gate driver 210 includes a shift register comprising multiple unit circuits. The gate driver 210 applies scan signals to the scan signal lines GL(1) to GL(n) and applies monitoring control signals to the monitoring control lines ML(1) to ML(n) based on the control signal GCTL output from the display control circuit 40. The emitter driver 220 is connected to the light emission control lines EM(1) to EM(n). Similar to the gate driver 210, the emitter driver 220 includes a shift register comprising multiple unit circuits. The emitter driver 220 applies the light emission control signal to the light emission control lines EM(1) to EM(n) based on the control signal ECTL output from the display control circuit 40.

[0087] The source driver 30 is connected to the data signal lines SL(1) to SL(m). The source driver 30 selectively drives the data signal lines SL(1) to SL(m) and measures the current flowing through the data signal lines SL(1) to SL(m). That is, as... Figure 4As shown, the source driver 30 functionally includes a data signal line driving unit 310 that drives the data signal lines SL(1) to SL(m) and a current monitoring unit 320 that measures the current output from the pixel circuit 110 to the data signal lines SL(1) to SL(m). The current monitoring unit 320 measures the current flowing through the data signal lines SL(1) to SL(m) and outputs monitoring data MOa based on the measured values. As described above, in this embodiment, the data signal lines SL(1) to SL(m) are used not only for transmitting data signals for image display but also as signal lines through which current corresponding to the characteristics of the driving transistor or organic EL element flows during monitoring processing.

[0088] As shown above, scan signals are applied to scan signal lines GL(1) to GL(n), monitoring control signals are applied to monitoring control lines ML(1) to ML(n), light emission control signals are applied to light emission control lines EM(1) to EM(n), and data signals, which serve as brightness signals, are applied to data signal lines SL(1) to SL(m), thereby displaying an image based on the input image signal DIN on the display unit 10. Furthermore, since monitoring processing is performed, compensation calculations are conducted based on the results of this monitoring processing, thus compensating for the degradation of the driving transistors and organic EL elements.

[0089] <2. Pixel Circuit and Source Driver>

[0090] Next, the pixel circuit 110 and the source driver 30 will be described in detail. When the source driver 30 functions as the data signal line driver 310, it operates as follows: The source driver 30 receives the control signal SCTL output from the display control circuit 40 and applies voltages corresponding to the target brightness as data signals to the m data signal lines SL(1) to SL(m). At this time, in the source driver 30, triggered by the pulse of the source start pulse signal, and at the timing of the pulse generating the source clock signal, the digital video signal VD2, representing the voltage to be applied to each data signal line SL, is held sequentially. Furthermore, at the timing of the pulse generating the latch strobe signal, the held digital video signal VD2 is converted into an analog voltage. This converted analog voltage is then applied as a data signal to all the data signal lines SL(1) to SL(m). When the source driver 30 functions as a current monitoring unit 320, it applies an appropriate voltage for monitoring processing as a data signal to the data signal lines SL(1) to SL(m), thereby converting the current flowing through the data signal lines SL(1) to SL(m) into voltages. The converted voltage is output from the source driver 30 as monitoring data Moa.

[0091] Figure 5This is a circuit diagram showing a portion of the pixel circuit 110 and the source driver 30. Furthermore, in Figure 5 The image shows the pixel circuit 110 in the i-th row and j-th column, and the portion of the source driver 30 corresponding to the data signal line SL(j) in the j-th column. The pixel circuit 110 includes: one organic EL element L1 as a display element; four transistors T1 to T4 (a write control transistor T1 that controls writing to a capacitor C, a drive transistor T2 that controls the supply of current to the organic EL element L1, a monitoring control transistor T3 that controls whether TFT or OLED characteristics are detected, and a light-emitting control transistor T4 that controls whether the organic EL element L1 emits light); and one capacitor (capacitor element) C as a holding capacitor. In this embodiment, transistors T1 to T4 are n-channel thin-film transistors. Furthermore, oxide TFTs (thin-film transistors using oxide semiconductors as the channel layer), amorphous silicon TFTs, etc., can be used as transistors T1 to T4. Examples of oxide TFTs include TFTs containing InGaZnO (indium gallium zinc oxide). By using oxide TFTs, for example, high definition and low power consumption can be achieved.

[0092] For the write control transistor T1, its control terminal is connected to the scan signal line GL(i), its first on terminal is connected to the data signal line SL(j), and its second on terminal is connected to the control terminal of the drive transistor T2 and one end of the capacitor C. For the drive transistor T2, its control terminal is connected to the second on terminal of the write control transistor T1 and one end of the capacitor C, its first on terminal is connected to the other end of the capacitor C and the high-level power supply line, and its second on terminal is connected to the first on terminal of the monitoring control transistor T3 and the first on terminal of the light-emitting control transistor T4. For the monitoring control transistor T3, its control terminal is connected to the monitoring control line ML(i), its first on terminal is connected to the second on terminal of the drive transistor T2 and the first on terminal of the light-emitting control transistor T4, and its second on terminal is connected to the data signal line SL(j). For the light-emitting control transistor T4, its control terminal is connected to the light-emitting control line EM(i), its first on terminal is connected to the second on terminal of the drive transistor T2 and the first on terminal of the monitoring control transistor T3, and its second on terminal is connected to the anode terminal (first terminal) of the organic EL element L1. For capacitor C, one end is connected to the second on terminal of the write control transistor T1 and the control terminal of the drive transistor T2, and the other end is connected to the first on terminal of the drive transistor T2 and the high-level power supply line. For organic EL element L1, its anode terminal is connected to the second on terminal of the light-emitting control transistor T4, and its cathode terminal (second terminal) is connected to the low-level power supply line.

[0093] Next, the part of the source driver 30 that functions as the current monitoring unit 320 will be explained. For example... Figure 5 As shown, the current monitoring unit 320 includes a D / A converter 306, an operational amplifier 301, a capacitor 322, and three switches (switches 323, 324, and 325). Furthermore, the operational amplifier 301 and the D / A converter 306 also function as components of the data signal line driver unit 310. The current monitoring unit 320 is provided with control signals S0, S1, and S2 to control the state of the three switches as control signal SCTL. These control signals S0, S1, and S2 are output from the display control circuit 40. The internal data line Sin(j) of the current monitoring unit 320 is connected to the data signal line SL(j) via switch 324. For the operational amplifier 301, its inverting input terminal is connected to the internal data line Sin(j), and its non-inverting input terminal is provided with the output from the D / A converter 306. The capacitor 322 and switch 323 are disposed between the output terminal of the operational amplifier 301 and the internal data line Sin(j). Switch 323 is provided with control signal S2. An integrating circuit 35 is formed by an operational amplifier 301, a capacitor 322, and a switch 323. The operation of this integrating circuit 35 will be explained here. When the switch 323 is on, the output terminal of the operational amplifier 301 and the inverting input terminal (i.e., the two electrodes of the capacitor 322) are short-circuited. At this time, no charge is accumulated in the capacitor 322, and the potential of the output terminal of the operational amplifier 301 and the internal data line Sin(j) is equal to the output potential from the D / A converter 306. When the switch 323 switches from on to off, the capacitor 322 is charged based on the current flowing through the internal data line Sin(j). That is, the time integral of the current flowing through the internal data line Sin(j) is accumulated in the capacitor 322. Therefore, the potential of the output terminal of the operational amplifier 301 changes accordingly to the magnitude of the current flowing through the internal data line Sin(j). The output from the operational amplifier 301 is output from the source driver 30 as monitoring data Moa. As described above, the monitoring data Moa is converted into monitoring data MOd as digital data by the A / D converter 31.

[0094] A switch 324 is disposed between the data signal line SL(j) and the internal data line Sin(j). A control signal S1 is provided to the switch 324. By switching the state of the switch 324 based on this control signal S1, the electrical connection state between the data signal line SL(j) and the internal data line Sin(j) is controlled. In this embodiment, if the control signal S1 is high, the data signal line SL(j) and the internal data line Sin(j) are electrically connected; if the control signal S1 is low, the data signal line SL(j) and the internal data line Sin(j) are electrically disconnected. Furthermore, in this embodiment, the switch control signal is implemented by the control signal S1.

[0095] A switch 325 is disposed between the data signal line SL(j) and the control line CL. A control signal S0 is provided to the switch 325. By switching the state of the switch 325 based on this control signal S0, the electrical connection state between the data signal line SL(j) and the control line CL is controlled. In this embodiment, if the control signal S0 is high, the data signal line SL(j) and the control line CL are electrically connected; if the control signal S0 is low, the data signal line SL(j) and the control line CL are electrically disconnected. When the data signal line SL(j) and the control line CL are electrically connected, the data signal line SL(j) is in a high-impedance state.

[0096] As described above, when switch 324 is in the open state, the data signal line SL(j) and the internal data line Sin(j) are electrically disconnected. At this time, if switch 323 is in the open state, the potential of the internal data line Sin(j) is maintained. In this embodiment, while maintaining the potential of the internal data line Sin(j), the A / D converter 31 performs AD conversion.

[0097] <3. Gate Driver>

[0098] <3.1 Structure of a Shift Register>

[0099] The detailed configuration of the gate driver 210 in this embodiment will be described. Furthermore, the configuration described herein is an example and is not limited thereto. The gate driver 210 includes a shift register comprising multiple stages (at least n unit circuits). When the display unit 10 has an n-row × m-column pixel matrix, each stage (unit circuit) of the shift register is arranged in a one-to-one correspondence with each row of the pixel matrix.

[0100] Figure 6 This is a block diagram showing the configuration of a 5-stage shift register. Here, we assume i is an integer greater than 3 and less than (n-2), focusing on the unit circuits 21(i-2), 21(i-1), 21(i), 21(i+1), and 21(i+2) of stages (i-2), (i-1), (i), (i+1), and (i+2). The shift register is provided with a gate start pulse signal, gate clock signals GCK1, GCK2, GCK3, GCK4, enable signals EN1 and EN2, and a control signal MON as the control signal GCTL. Furthermore, the gate start pulse signal is provided as a set signal SG to the unit circuit 21(1) of stage 1. Figure 6 Omitted in .

[0101] Each unit circuit 21 includes: an input terminal for receiving clock signal GKA, clock signal GKB, enable signal EN, control signal MON, set signal SG, and reset signal RG respectively; and an output terminal for outputting output signal QG1 and output signal QG2 respectively.

[0102] For unit circuit 21(i-2), it is provided with gate clock signal GCK3 as clock signal GKA, gate clock signal GCK1 as clock signal GKB, and enable signal EN1 as enable signal EN. For unit circuit 21(i-1), it is provided with gate clock signal GCK4 as clock signal GKA, gate clock signal GCK2 as clock signal GKB, and enable signal EN2 as enable signal EN. For unit circuit 21(i), it is provided with gate clock signal GCK1 as clock signal GKA, gate clock signal GCK3 as clock signal GKB, and enable signal EN1 as enable signal EN. For unit circuit 21(i+1), it is provided with gate clock signal GCK2 as clock signal GKA, gate clock signal GCK4 as clock signal GKB, and enable signal EN2 as enable signal EN. This configuration is repeated every 4 levels. The control signal MON is provided to all unit circuits 21. Furthermore, each unit circuit 21 is provided with the output signal QG1 from the previous unit circuit 21 as a set signal SG, and with the output signal QG1 from the unit circuit 21 two levels later as a reset signal RG. The output signal QG1 from each unit circuit 21 is provided to the unit circuit 21 two levels earlier as a reset signal RG, to the next unit circuit 21 as a set signal SG, and to the corresponding scan signal line GL as a scan signal. The output signal QG2 from each unit circuit 21 is provided to the corresponding monitoring control line ML as a monitoring control signal. Additionally, as... Figure 5 As shown, the scan signal line GL is connected to the control terminal of the write control transistor T1 in the pixel circuit 110, and the monitoring control line ML is connected to the control terminal of the monitoring control transistor T3 in the pixel circuit 110.

[0103] <3.2 Composition of a Unit Circuit>

[0104] Figure 7 This is a circuit diagram showing the configuration of unit circuit 21. For example... Figure 7As shown, the unit circuit 21 includes seven transistors M1 to M7 and two capacitors C11 and C12. In addition to input terminals connected to the control signal line transmitting the control signal MON and input terminals connected to the power supply line (hereinafter referred to as the "first reference potential line") provided with a low-level potential VSS, the unit circuit 21 also has five input terminals 51 to 55 and two output terminals 58 and 59. Figure 7 In the figure, the input terminal for receiving the set signal SG is labeled with reference numeral 51, the input terminal for receiving the reset signal RG is labeled with reference numeral 52, the input terminal for receiving the clock signal GKA is labeled with reference numeral 53, the input terminal for receiving the clock signal GKB is labeled with reference numeral 54, the input terminal for receiving the enable signal EN is labeled with reference numeral 55, the output terminal for outputting the output signal QG1 is labeled with reference numeral 58, and the output terminal for outputting the output signal QG2 is labeled with reference numeral 59.

[0105] The second conducting terminal of transistor M1, the first conducting terminal of transistor M2, the control terminal of transistor M3, the first conducting terminal of transistor M5, and one end of capacitor C11 are interconnected. Furthermore, the area (wiring) connecting these interconnections is called the "first internal node." The first internal node is labeled with reference numeral N1. The second conducting terminal of transistor M5, the control terminal of transistor M6, and one end of capacitor C12 are interconnected. Furthermore, the area (wiring) connecting these interconnections is called the "second internal node." The second internal node is labeled with reference numeral N2.

[0106] Furthermore, unit circuit 21 includes: a first output control circuit 211 that controls the output of output signal QG1; and a second output control circuit 212 that controls the output of output signal QG2. The first output control circuit 211 includes transistors M3 and M4. The second output control circuit 212 includes transistors M6 and M7.

[0107] For transistor M1, its control terminal and first conducting terminal are connected to input terminal 51 (i.e., diode connection), and its second conducting terminal is connected to the first internal node N1. For transistor M2, its control terminal is connected to input terminal 52, its first conducting terminal is connected to the first internal node N1, and its second conducting terminal is connected to the first reference potential line. For transistor M3, its control terminal is connected to the first internal node N1, its first conducting terminal is connected to input terminal 53, and its second conducting terminal is connected to output terminal 58. For transistor M4, its control terminal is connected to input terminal 54, its first conducting terminal is connected to output terminal 58, and its second conducting terminal is connected to the first reference potential line. For transistor M5, its control terminal is connected to the control signal line, its first conducting terminal is connected to the first internal node N1, and its second conducting terminal is connected to the second internal node N2. For transistor M6, its control terminal is connected to the second internal node N2, its first conducting terminal is connected to input terminal 55, and its second conducting terminal is connected to output terminal 59. For transistor M7, its control terminal is connected to input terminal 54, its first conducting terminal is connected to output terminal 59, and its second conducting terminal is connected to the first reference potential line. For capacitor C11, one end is connected to the first internal node N1, and the other end is connected to output terminal 58. For capacitor C12, one end is connected to the second internal node N2, and the other end is connected to output terminal 59.

[0108] Here, we focus on transistor M5. While the control signal MON supplied to the control signal line is high, transistor M5 remains in the on state except when the potential of the second internal node N2 is higher than the normal high level. When the potential of the second internal node N2 becomes above a predetermined value, transistor M5 becomes off, electrically cutting off the first internal node N1 and the second internal node N2. Thus, transistor M5 assists in the rise of the potential of the second internal node N2 when it enters a boost state.

[0109] <3.3 Operation of a Unit Circuit>

[0110] Reference Figure 8 Let's describe the operation of the unit circuit 21(i) of the i-th stage. Here, we assume that the i-th row is the monitoring row, and we focus on the operation when monitoring the i-th row is performed. Immediately before time point t01, the potentials of the first internal node N1 and the second internal node N2 are low, and the control signal MON is low.

[0111] When time point t01 arrives, the control signal MON changes from low to high. This turns transistor M5 on. Additionally, when time point t01 arrives, the set signal SG changes from low to high. Due to the pulse of the set signal SG, transistor M1 turns on, and capacitor C11 is charged. At this time, since transistor M5 is on, capacitor C12 is also charged. Consequently, the potential of the first internal node N1 increases, and transistor M3 turns on, and the potential of the second internal node N2 increases, and transistor M6 turns on. However, during the period from time point t01 to time point t02, the clock signal GKA and the enable signal EN remain low, therefore the output signals QG1 and QG2 remain low.

[0112] When time point t02 arrives, the clock signal GKA changes from low to high. At this time, transistor M3 is turned on, so as the potential of input terminal 53 increases, the potential of output terminal 58 (the potential of output signal QG1) also increases. Simultaneously, the potential of the first internal node N1 also increases via capacitor C11. As a result, a large voltage is applied to the control terminal of transistor M3, and the potential of output signal QG1 rises to a level sufficient to turn on the write control transistor T1 at the connection destination of output terminal 58. Additionally, when time point t02 arrives, the enable signal EN changes from low to high. At this time, transistor M6 is turned on, so as the potential of input terminal 55 increases, the potential of output terminal 59 (the potential of output signal QG2) also increases. Simultaneously, the potential of the second internal node N2 also increases via capacitor C12 (the second internal node N2 becomes a boost state). As a result, a large voltage is applied to the control terminal of transistor M6, and the potential of the output signal QG2 rises to a level sufficient to turn on the monitoring control transistor T3 at the connection destination of the output terminal 59.

[0113] When the time point becomes t03, the enable signal EN changes from high to low. Consequently, as the potential of input terminal 55 decreases, the potential of output terminal 59 (the potential of output signal QG2) also decreases. When the potential of output terminal 59 decreases, the potential of the second internal node N2 also decreases via capacitor C12.

[0114] When the time point becomes t04, the clock signal GKA changes from a high level to a low level. Consequently, as the potential of input terminal 53 decreases, the potential of output terminal 58 (the potential of output signal QG1) also decreases. When the potential of output terminal 58 decreases, the potential of the first internal node N1 also decreases via capacitor C11.

[0115] When the time point becomes t05, the enable signal EN changes from low to high. Consequently, similar to time point t02, the potential of the second internal node N2 and the potential of the output terminal 59 (the potential of the output signal QG2) increase.

[0116] When the time point becomes t06, the enable signal EN changes from high to low. Consequently, as the potential of input terminal 55 decreases, the potential of output terminal 59 (the potential of output signal QG2) also decreases. Simultaneously, the potential of the second internal node N2 also decreases via capacitor C12.

[0117] When the time point becomes t07, the clock signal GKA changes from low to high. Consequently, similar to time point t02, the potential of the first internal node N1 and the potential of the output terminal 58 (the potential of the output signal QG1) increase. Furthermore, during the period from time point t07 to time point t08, the enable signal EN remains low, therefore the potential of the second internal node N2 does not increase.

[0118] At time t08, the clock signal GKA changes from high to low. Consequently, as the potential of input terminal 53 decreases, the potential of output terminal 58 (the potential of output signal QG1) also decreases. Simultaneously, the potential of the first internal node N1 also decreases via capacitor C11. Additionally, at time t08, the reset signal RG changes from low to high. This turns on transistor M2. As a result, the potentials of the first internal node N1 and the second internal node N2 become low. Furthermore, at time t08, the clock signal GKB changes from low to high. This turns on transistors M4 and M7. Consequently, the potential of output terminal 58 (the potential of output signal QG1) becomes low, and even with noise, the potential of output terminal 59 (the potential of output signal QG2) is pulled down to a low level.

[0119] When the time point changes to t09, the control signal MON changes from high level to low level. As a result, transistor M5 becomes cut off.

[0120] As shown above, in the pixel circuit 110 of the i-th row, during the periods t02 to t04 and t07 to t08, the write control transistor T1 is turned on, and during the periods t02 to t03 and t05 to t06, the monitoring control transistor T3 is turned on. Thus, monitoring processing of the pixel circuit 110 of the i-th row is performed.

[0121] <4. Transmit Driver>

[0122] <4.1 Structure of a Shift Register>

[0123] The detailed configuration of the transmit driver 220 in this embodiment is described below. Furthermore, the configuration described herein is an example and is not limited thereto. Similar to the gate driver 210, the transmit driver 220 includes a shift register comprising multiple stages (at least n unit circuits).

[0124] Figure 9 This is a block diagram showing the configuration of a five-stage shift register. Here, we focus on the unit circuits 22(i-2) to 22(i+2) of stages (i-2) to (i+2). This shift register is provided with an LED start pulse signal and LED clock signals ECK1 to ECK4 as control signals ECTL. Furthermore, the LED start pulse signal is provided as a set signal SE to the unit circuit 22(1) of stage 1. Figure 9 Omitted in .

[0125] Each unit circuit 22 includes: an input terminal for receiving clock signals EKA, EKB, EKC, EKD, SE, and RE respectively; and an output terminal for outputting output signals QE1 and QE2 respectively.

[0126] For unit circuit 22(i-2), it is provided with light-emitting control clock signal ECK3 as clock signal EKA, ECK1 as clock signal EKB, ECK4 as clock signal EKC, and ECK2 as clock signal EKD. For unit circuit 22(i-1), it is provided with light-emitting control clock signal ECK4 as clock signal EKA, ECK2 as clock signal EKB, ECK1 as clock signal EKC, and ECK3 as clock signal EKD. For unit circuit 22(i), it is provided with light-emitting control clock signal ECK1 as clock signal EKA, ECK3 as clock signal EKB, ECK2 as clock signal EKC, and ECK4 as clock signal EKD. For unit circuit 22(i+1), it is provided with light-emitting control clock signal ECK2 as clock signal EKA, light-emitting control clock signal ECK4 as clock signal EKB, light-emitting control clock signal ECK3 as clock signal EKC, and light-emitting control clock signal ECK1 as clock signal EKD. This configuration is repeated every four levels. Furthermore, each unit circuit 22 at each level is provided with the output signal QE1 from the previous unit circuit 22 as a set signal SE, and the output signal QE1 from the next unit circuit 22 as a reset signal RE. The output signal QE1 from each unit circuit 22 is provided to the previous unit circuit 22 as a reset signal RE, and to the next unit circuit 22 as a set signal SE. The output signal QE2 from each unit circuit 22 is provided to the corresponding light-emitting control line EM as a light-emitting control signal. Additionally, as... Figure 5 As shown, the light emission control line EM is connected to the control terminal of the light emission control transistor T4 in the pixel circuit 110.

[0127] <4.2 Composition of a Unit Circuit>

[0128] Figure 10 This is a circuit diagram showing the configuration of unit circuit 22. For example... Figure 10 As shown, the unit circuit 22 includes 10 transistors M11 to M20 and 2 capacitors C21 and C22. In addition to the input terminals connected to the first reference potential line and the input terminals connected to the power supply line provided with a high-level potential VDD (hereinafter referred to as the "second reference potential line"), the unit circuit 22 also has 6 input terminals 61 to 66 and 2 output terminals 68 and 69. Figure 10In the figure, the input terminal for receiving the set signal SE is labeled with reference numeral 61, the input terminal for receiving the reset signal RE is labeled with reference numeral 62, the input terminal for receiving the clock signal EKD is labeled with reference numeral 63, the input terminal for receiving the clock signal EKC is labeled with reference numeral 64, the input terminal for receiving the clock signal EKA is labeled with reference numeral 65, the input terminal for receiving the clock signal EKB is labeled with reference numeral 66, the output terminal for outputting the output signal QE1 is labeled with reference numeral 68, and the output terminal for outputting the output signal QE2 is labeled with reference numeral 69.

[0129] The second conducting terminal of transistor M11, the first conducting terminal of transistor M12, the control terminal of transistor M13, the control terminal of transistor M16, the control terminal of transistor M19, and one end of capacitor C21 are interconnected. This interconnected area (wiring) is called the "first control node." The first control node is labeled with reference numeral VD. The second conducting terminal of transistor M15, the first conducting terminal of transistor M16, the control terminal of transistor M17, and one end of capacitor C22 are interconnected. This interconnected area (wiring) is called the "second control node." The second control node is labeled with reference numeral VE. The control terminal of transistor M14, the second conducting terminal of transistor M17, the first conducting terminal of transistor M18, the control terminal of transistor M20, and the other end of capacitor C22 are interconnected. This interconnected area (wiring) is called the "third control node." The third control node is labeled with reference numeral VR.

[0130] Furthermore, the unit circuit 22 includes a set circuit 221, a reset circuit 222, and a buffer circuit 223. The set circuit 221 includes transistors M11 to M14 and a capacitor C21. The reset circuit 222 includes transistors M15 to M18 and a capacitor C22. The buffer circuit 223 includes transistors M19 and M20.

[0131] For transistor M11, its control terminal is connected to input terminal 63, its first conducting terminal is connected to input terminal 61, and its second conducting terminal is connected to the first control node VD. For transistor M12, its control terminal is connected to input terminal 64, its first conducting terminal is connected to the first control node VD, and its second conducting terminal is connected to input terminal 62. For transistor M13, its control terminal is connected to the first control node VD, its first conducting terminal is connected to input terminal 65, and its second conducting terminal is connected to output terminal 68. For transistor M14, its control terminal is connected to the third control node VR, its first conducting terminal is connected to output terminal 68, and its second conducting terminal is connected to the first reference potential line. For transistor M15, its control terminal is connected to input terminal 66, its first conducting terminal is connected to the second reference potential line, and its second conducting terminal is connected to the second control node VE. For transistor M16, its control terminal is connected to the first control node VD, its first conducting terminal is connected to the second control node VE, and its second conducting terminal is connected to input terminal 66. For transistor M17, its control terminal is connected to the second control node VE, its first conducting terminal is connected to the input terminal 65, and its second conducting terminal is connected to the third control node VR. For transistor M18, its control terminal is connected to the input terminal 66, its first conducting terminal is connected to the third control node VR, and its second conducting terminal is connected to the first reference potential line. For transistor M19, its control terminal is connected to the first control node VD, its first conducting terminal is connected to the second reference potential line, and its second conducting terminal is connected to the output terminal 69. For transistor M20, its control terminal is connected to the third control node VR, its first conducting terminal is connected to the output terminal 69, and its second conducting terminal is connected to the first reference potential line. For capacitor C21, one end is connected to the first control node VD, and the other end is connected to the output terminal 68. For capacitor C22, one end is connected to the second control node VE, and the other end is connected to the third control node VR.

[0132] <4.3 Operation of a Unit Circuit>

[0133] Reference Figure 11 Let's explain the operation of the unit circuit 22(i) of the i-th stage. Immediately before time point t11, the potentials of the first control node VD and the third control node VR are low, while the potential of the second control node VE is high (pre-charge state).

[0134] At time t11, the clock signal EKD changes from low to high. This turns transistor M11 on. Also at time t11, the set signal SE changes from low to high. This charges capacitor C21. Consequently, the potential of the first control node VD increases (the first control node VD enters a pre-charge state), and transistors M13, M16, and M19 turn on. Although transistor M13 turns on as described above, the clock signal EKA remains low during time t11 to time t12, therefore the potential of output terminal 68 (the potential of output signal QE1) remains low. Furthermore, the first on terminal of transistor M19 is provided with a high potential VDD, therefore at time t11, transistor M19 turns on, thereby increasing the potential of output terminal 69 (the potential of output signal QE2).

[0135] like Figure 10 As shown, the first conducting terminal of transistor M15 is provided with a high-level potential VDD, the second conducting terminal of transistor M16 is provided with a clock signal EKB, and the second conducting terminal of transistor M18 is provided with a low-level potential VSS. Here, during the period from time point t11 ​​to time point t12, the clock signal EKB is high, and as described above, the first control node VD is in a pre-charge state. Accordingly, during this period, the potential of the second control node VE remains high (pre-charge state), and the potential of the third control node VR remains low.

[0136] When the time point t12 arrives, the clock signal EKA changes from low to high. At this time, transistor M13 is in the conducting state, so as the potential of input terminal 65 increases, the potential of output terminal 68 (the potential of output signal QE1) also increases. Simultaneously, the potential of the first control node VD also increases via capacitor C21 (the first control node VD enters a boost state). As a result, a large voltage is applied to the control terminal of transistor M13, and the potential of output terminal 68 (the potential of output signal QE1) rises sufficiently. Additionally, a large voltage is also applied to the control terminal of transistor M19, thus the potential of output terminal 69 (the potential of output signal QE2) rises sufficiently.

[0137] Additionally, at time t12, the clock signal EKB changes from high to low. At this time, transistor M16 is turned on. Consequently, the potential of the second control node VE becomes low, and transistor M17 becomes off. Thus, because transistor M17 is off, even if the clock signal EKA changes from low to high at time t12, the potential of the third control node VR will remain low.

[0138] During the period from time point t13 to time point t14, the periods when the reset signal RE is high and the clock signal EKC is high alternately repeated with the periods when the set signal SE is high and the clock signal EKD is high. Therefore, the potential of the first control node VD remains high. The potential of the first control node VD fluctuates synchronously with the clock signal EKA. That is, the first control node VD alternately repeats the pre-charge state and the boost state. Therefore, the potential of the output terminal 68 (the potential of the output signal QE1) alternates between high and low levels synchronously with the clock signal EKA. Since the first conducting terminal of transistor M19 is provided with a high-level potential VDD, the potential of the output terminal 69 (the potential of the output signal QE2) is maintained at a sufficiently high level.

[0139] Furthermore, during the period from time point t13 to time point t14, as described above, the potential of the first control node VD remains high. Therefore, during the period when the clock signal EKB is high, the potential of the second control node VE becomes high (pre-charge state), and during the period when the clock signal EKB is low, the potential of the second control node VE becomes low. Thus, transistor M17 alternately repeats the on and off states. Here, during the period when the potential of the second control node VE is high, the clock signal EKA remains low. Therefore, during the period from time point t13 to time point t14, the second control node VE does not enter the boost state, and the potential of the third control node VR remains low.

[0140] At time t14, the clock signal EKD changes from low to high, but the set signal SE remains low. Therefore, the potential of the first control node VD becomes low. Consequently, transistors M13, M16, and M19 become off. Since transistor M16 is off, the potential of the second control node VE remains high (pre-charge state). At this time, the clock signal EKA is low, so the potential of the third control node VR is maintained low. Therefore, transistor M20 remains off, and the potential of output terminal 69 (the potential of output signal QE2) remains sufficiently high.

[0141] When the time point t15 arrives, the clock signal EKA changes from low to high. At this time, transistor M17 is turned on, and since capacitor C22 exists between the control terminal and the second on terminal of transistor M17, the second control node VE becomes a boost state due to the increase in the potential of input terminal 65. Consequently, the potential of the third control node VR rises sufficiently, and transistors M14 and M20 become on. Because transistor M14 is on, even if noise is generated, the potential of output terminal 68 (the potential of output signal QE1) will be pulled down to a low level. In addition, because transistor M20 is on, the potential of output terminal 69 (the potential of output signal QE2) becomes low.

[0142] During the period from time point t16 to time point t17, the potential of the first control node VD remains low, thus transistor M16 remains in the off state. Therefore, the potential of the second control node VE fluctuates synchronously with the clock signal EKA. That is, the second control node VE alternately repeats the pre-charge state and the boost state. Therefore, the potential of the third control node VR alternately repeats the high level and the low level synchronously with the clock signal EKA. In addition, during this period, transistors M13 and M19 remain in the off state, therefore, the potential of output terminal 68 (the potential of output signal QE1) and the potential of output terminal 69 (the potential of output signal QE2) remain low.

[0143] <5. Control of the current monitoring unit during integration>

[0144] Next, refer to Figure 1 The control of the current monitoring unit 320 during the integration period P14 described above will be explained. As mentioned above, the light emission control clock signals ECK1 to ECK4 used to generate the light emission control signal EM also undergo level changes during the integration period P14. Here, the timing at which the level of at least one of these light emission control clock signals ECK1 to ECK4 changes is defined as "edge timing". From Figure 1 As can be seen, in this embodiment, the integration period P14 includes multiple edge timings. Furthermore, during the integration period P14, the display control circuit 40 changes the control signal S1 from a high level to a low level immediately before each edge timing, and immediately after each edge timing, changes the control signal S1 from a low level to a high level. Therefore, during the integration period P14, immediately before each edge timing (that is, just before each edge timing), switch 324 (refer to...) Figure 5The switch 324 becomes open immediately after each edge timing (just after each edge timing). Thus, during the integration period, when P14 is at each edge timing, switch 324 is open, thereby electrically cutting off the data signal line SL and the integrating circuit 35, which are the current (measured current) flow paths corresponding to the characteristics of the driving transistor T2. Therefore, during the integration period, when P14 is at each edge timing, the current flowing into the integrating circuit 35 corresponding to the characteristics of the driving transistor T2 is stopped. Therefore, during the integration period, when P14 is at each edge timing, the integration operation of the integrating circuit 35 stops.

[0145] <6. Monitoring and Processing>

[0146] Next, refer to Figure 12 The operation of the pixel circuit 110 and the current monitoring unit 320 during monitoring processing will be explained. Here, it is assumed that the i-th row is the monitoring row, and the pixel circuit 110 in the j-th column of the i-th row and the current monitoring unit 320 corresponding to the j-th column will be observed. Furthermore, the case where TFT characteristics are detected through monitoring processing will be discussed. Figure 8 The various time points in the text and Figure 12 The correspondence between the periods is shown below.

[0147] Time point t01: The start time of period P10

[0148] Time point t02: The start time of period P11

[0149] Time point t03: The start time of period P12

[0150] Time point t04: The end time of period P12

[0151] Time point t05: The start time of period P13

[0152] Time point t06: The end time of period P14

[0153] Time point t07: The start time of period P16

[0154] Time point t08: The end time of period P16

[0155] Time point t09: The midpoint of time point P17 during the period

[0156] During period P10, data potential Vd(i-1) for image display is written in row (i-1). Immediately before the end of period P10, the scan signal GL(i) and the monitoring control signal ML(i) are low. Therefore, the write control transistor T1 and the monitoring control transistor T3 are off. Also, immediately before the end of period P10, the light emission control signal EM(i) is on. Therefore, the light emission control transistor T4 is on, and the organic EL element L1 is supplied with drive current. Furthermore, immediately before the end of period P10, control signals S2 and S1 are high, and control signal S0 is low. Therefore, switches 323 and 324 are on, and switch 325 is off. At this time, the data signal line SL(j) is electrically connected to the internal data line Sin(j).

[0157] When the period changes to P11, the light emission control signal EM(i) changes from high to low. This turns off the light emission control transistor T4, stopping the supply of drive current to the organic EL element L1. Additionally, when the period changes to P11, the scan signal GL(i) and the monitoring control signal ML(i) change from low to high. This turns on the write control transistor T1 and the monitoring control transistor T3. During P11, in these states, the initialization potential Vpc, which initializes the state of the pixel circuit 110, is applied to the data signal line SL(j). This initializes the state of capacitor C and the potential of node 111. Furthermore, the timing of the light emission control signal EM(i) changing from high to low does not necessarily have to be exactly the same as the timing of the scan signal GL(i) and the monitoring control signal ML(i) changing from low to high.

[0158] When the period P12 is reached, the monitoring control signal ML(i) changes from high to low. This turns the monitoring control transistor T3 off. In this state, the characteristic detection potential Vr_TFT is applied to the data signal line SL(j). The characteristic detection potential Vr_TFT is set to a level that allows current to flow in the driving transistor T2 but not in the organic EL element L1. That is, during period P12, the driving transistor T2 is on.

[0159] When the period P13 is reached, the scan signal GL(i) changes from high to low, and the monitoring control signal ML(i) changes from low to high. As a result, the write control transistor T1 becomes off, and the monitoring control transistor T3 becomes on. In this state, the current measurement potential Vm_TFT is applied to the data signal line SL(j). Consequently, the current flowing through the drive transistor T2 flows to the current monitoring unit 320 via the monitoring control transistor T3 and the data signal line SL(j). At this time, the control signal S2 is high, so the switch 323 is on, and no charge accumulates in the capacitor 322. Furthermore, the period P13 is set to a length sufficient to stabilize the current (measured current) flowing through the data signal line SL(j).

[0160] When the period becomes P14 (integration period), the control signal S2 changes from high to low. As a result, switch 323 becomes open, and the current is integrated over time through operational amplifier 301 and capacitor 322. However, as described above, the timing (edge ​​timing) of the change in the levels of the light-emitting control clock signals ECK1 to ECK4 (see reference...) Figure 1 When control signal S1 goes low, switch 324 (refer to...) Figure 5 The switch 324 is in the off state. When switch 324 is in the off state, the time integration of the current stops. Therefore, the time integration of the current occurs during the period P14 (integration period) when switch 324 is in the on state (during which control signal S1 is high). As shown above, during period P14 (integration period), the output voltage of operational amplifier 301 becomes the voltage corresponding to the current flowing through data signal line SL(j).

[0161] When the time interval P15 is reached, control signal S1 changes from high to low, and control signal S0 changes from low to high. As a result, switch 324 becomes open, and switch 325 becomes on. Since switch 324 is open, the data signal line SL(j) and the internal data line Sin(j) are electrically disconnected. In this state, the output voltage of operational amplifier 301 (monitoring data MOa) is converted into monitoring data MOd as digital data by A / D converter 31. Thus, the detection of the TFT characteristics of the i-th row ends. Furthermore, the AD-converted monitoring data Mod is used for digital video signal correction.

[0162] Subsequently, during period P16, the light emission control signal EM(i) changes from low to high. This turns on the light emission control transistor T4. Additionally, during period P16, control signals S2 and S1 change from low to high, and control signal S0 changes from high to low. This turns on switches 323 and 324, and off switch 325. Furthermore, during period P16, the scan signal GL(i) changes from low to high. This turns on the write control transistor T1. Under these conditions, the data potential Vd(i) for image display is applied to the data signal line SL(j), and writing based on this data potential Vd(i) is performed in the pixel circuit 110 of the i-th row and j-th column. This causes the organic EL element L1 to emit light.

[0163] When the period P17 arrives, the scan signal GL(i) changes from high to low. As a result, the write control transistor T1 becomes off. Furthermore, during period P17, a data potential Vd(i+1) for image display is written in row (i+1). In periods following period P17, in the pixel circuit 110 of row i and column j, the organic EL element L1 emits light based on the write operation during period P16.

[0164] In this embodiment, monitoring processing for detecting TFT characteristics is performed as described above. Furthermore, period P12 corresponds to the writing period for measurement, and period P14 (integration period) corresponds to the current measurement period.

[0165] Furthermore, when detecting OLED characteristics through monitoring, the light emission control signals applied to the multiple light emission control lines EM(1) to EM(n) are maintained at a high level. This is because, in order to detect OLED characteristics, current needs to flow through the organic EL element L1, and the light emission control transistor T4 must be kept in the on state.

[0166] <7. Effects>

[0167] According to this embodiment, during the edge timing of the integration period P14 (timing when the level of at least one of the light-emitting control clock signals ECK1 to ECK4 changes), the switch 324 in the current monitoring unit 320 is turned off, thereby electrically cutting off the data signal line SL(j) and the internal data line Sin(j), and thus stopping the flow of current into the integrating circuit 35 corresponding to the characteristics of the driving transistor. Therefore, as Figure 13As shown, the actual time integration of the current corresponding to the characteristics of the driving transistor is performed during the integration period P14, a period in which a stable current flows without being affected by coupling noise (current stabilization period) P14s. Therefore, even if coupling noise is generated during the integration period P14 due to the presence of parasitic capacitance between the non-monitored row light emission control line EM and the data signal line SL, the current corresponding to the characteristics of the driving transistor T2 can be detected with good accuracy. As shown above, according to this embodiment, in an organic EL display device with external compensation function, the reduction in compensation accuracy caused by coupling noise generated on the data signal line SL can be prevented.

[0168] <8. Variations>

[0169] In the above embodiments, the data signal lines SL(1) to SL(m) are used not only for transmitting data signals for image display, but also as signal lines for allowing current to flow through the drive transistor T2 or the organic EL element L1 during monitoring processing. However, it is not limited to this, such as Figure 14 As shown, a signal line (hereinafter referred to as the "current monitoring line") MCL can also be provided independently of the data signal lines SL(1) to SL(m) to allow a current corresponding to the characteristics of the driving transistor T2 or the organic EL element L1 to flow during monitoring processing.

[0170] Figure 14 This is a circuit diagram showing a portion of the pixel circuit 110 and the source driver 30 in this modified example. Similar to the first embodiment, the pixel circuit 110 includes one organic EL element L1, four transistors T1 to T4 (write control transistor T1, drive transistor T2, monitoring control transistor T3, and light-emitting control transistor T4), and one capacitor (capacitive element) C. However, the second on terminal of the monitoring control transistor T3 is connected to the current monitoring line MCL(j).

[0171] For source driver 30, such as Figure 14 As shown, the circuit consists of a data signal line driver 310 and a current monitoring unit 320. The data signal line driver 310 includes an operational amplifier 311 and a D / A converter 316. The current monitoring unit 320 includes a D / A converter 326, an operational amplifier 321, a capacitor 322, and three switches (switches 323, 324, and 325). An integrating circuit 35 is formed by the operational amplifier 321, the capacitor 322, and the switch 323. Furthermore, Figure 14 The operational amplifier 321 and D / A converter 326 in the middle are respectively equivalent to Figure 5The operational amplifier 301 and the D / A converter 306 are included. The operation of the current monitoring unit 320 is the same as in the first embodiment, so a description is omitted. However, in this modified example, the current monitoring unit 320 measures the current flowing through the current monitoring line MCL.

[0172] Even with the configuration described above, where the current monitoring line MCL is set independently of the data signal line SL, the same effect as the above-described embodiment can be obtained.

[0173] <9. Others>

[0174] In the above embodiments (including variations), an organic EL display device was described as an example of a display device having a pixel circuit including a display element driven by current, but it is not limited thereto. For example, the present invention can also be applied to an inorganic EL display device having a pixel circuit including an inorganic light-emitting diode, or a QLED (Quantum dot Light Emitting Diode) display device having a pixel circuit including a quantum dot light-emitting diode, etc.

[0175] Explanation of reference numerals in the attached figures

[0176] 10… Display Department

[0177] 20… Scan drive

[0178] 30…Source Driver

[0179] 31…A / D Converter

[0180] 32…Correction and calculation unit

[0181] 33…Correction Data Storage Department

[0182] 35…Integrating circuit

[0183] 40… Display control circuit

[0184] 110…pixel circuit

[0185] 210… Gate Driver

[0186] 220… Transmission Driver

[0187] 310…Data Signal Line Driver Section

[0188] 320… Current Monitoring Unit

[0189] GL, GL(1)~GL(n)… scan signal lines

[0190] ML, ML(1)~ML(n)… Monitoring and control lines

[0191] EM, EM(1)~EM(m)…Light emission control lines

[0192] SL, SL(1)~SL(m)… data signal lines

[0193] L1…Organic EL element

[0194] T1…Write control transistor

[0195] T2…Drive transistor

[0196] T3…Monitoring and control transistor

[0197] T4…Light-emitting control transistor.

Claims

1. A display device having a pixel circuit, the pixel circuit including a display element driven by a current and a drive transistor for controlling the drive current of the display element, the display device having a function of performing monitoring processing, the monitoring processing being a series of processes for measuring a current flowing through the pixel circuit corresponding to the characteristics of the drive transistor outside the pixel circuit, the display device being characterized in that it comprises: The display unit includes: multiple data signal lines; multiple scan signal lines; and multiple light emission control lines, which are configured to correspond one-to-one with the multiple scan signal lines and cross the multiple data signal lines. The data signal line driving circuit applies data signals to the aforementioned multiple data signal lines; A scan signal line driving circuit that applies scan signals to the aforementioned plurality of scan signal lines; and The light-emitting control line driving circuit applies light-emitting control signals to the plurality of light-emitting control lines, and includes a shift register comprising multiple unit circuits corresponding to the plurality of light-emitting control lines in a one-to-one manner. The pixel circuit described above is provided at each intersection of the plurality of data signal lines and the plurality of scan signal lines. The aforementioned data signal line driving circuit includes an integrating circuit for measuring the current corresponding to the characteristics of the aforementioned driving transistor. The aforementioned display device includes a switch disposed between a current flow path corresponding to the characteristics of the aforementioned driving transistor and the aforementioned integrating circuit. The aforementioned shift register, based on multiple light-emitting control clock signals, generates light-emitting control signals to be applied to each light-emitting control line while transmitting the light-emitting control start pulse signal from the first-stage unit circuit to the last-stage unit circuit. The monitoring period for performing the above monitoring process includes: a measurement writing period for writing a data signal that causes a current corresponding to the characteristics of the driving transistor to flow into the pixel circuit; and a current measurement period for measuring the current corresponding to the characteristics of the driving transistor by the integrating circuit. During the aforementioned current measurement, at the edge timing when the level of at least one of the aforementioned multiple light-emitting control clock signals changes, the inflow of current into the aforementioned integrating circuit, corresponding to the characteristics of the aforementioned driving transistor, is stopped.

2. The display device according to claim 1, characterized in that, During the aforementioned edge timing during the current measurement period, the switch is in the open state, thereby electrically cutting off the current flow path corresponding to the characteristics of the driving transistor and the integrating circuit.

3. The display device according to claim 2, characterized in that, The aforementioned current measurement period includes multiple edge timings as described above. During the aforementioned current measurement, the switch is in the off state just before the timing of each edge is reached, and the switch is in the on state just after the timing of each edge is reached.

4. The display device according to claim 3, characterized in that, The system includes a control circuit that controls the operation of the aforementioned data signal line driving circuit, the aforementioned scan signal line driving circuit, and the aforementioned light emission control line driving circuit. The aforementioned multiple light-emitting control clock signals and the aforementioned light-emitting control start pulse signals are output from the aforementioned control circuit. The opening / closing of the aforementioned switch is controlled based on the switch control signal output from the aforementioned control circuit. If the aforementioned switch control signal is at level 1, the aforementioned switch is in the ON state; and if the aforementioned switch control signal is at level 2, the aforementioned switch is in the OFF state. During the current measurement, the control circuit changes the switch control signal from the first level to the second level just before the timing of each edge, and changes the switch control signal from the second level back to the first level just after the timing of each edge.

5. The display device according to any one of claims 1 to 4, characterized in that, The aforementioned data signal lines are also used as signal lines for the flow of current corresponding to the characteristics of the aforementioned drive transistors during the aforementioned monitoring process. During the aforementioned current measurement, the integrator circuit measures the current flowing through the corresponding data signal line.

6. The display device according to claim 5, characterized in that, The aforementioned display unit includes multiple monitoring and control lines that correspond one-to-one with the aforementioned multiple scan signal lines. The aforementioned scan signal line drive circuit applies monitoring and control signals to the aforementioned multiple monitoring and control lines.

7. The display device according to claim 6, characterized in that, The aforementioned pixel circuit includes: The aforementioned display element has a first terminal and a second terminal; The aforementioned driving transistor has a control terminal, a first conducting terminal, and a second conducting terminal; A write control transistor has: a control terminal connected to a corresponding scan signal line; a first conduction terminal connected to a corresponding data signal line; and a second conduction terminal connected to the control terminal of the aforementioned drive transistor. A monitoring and control transistor has: a control terminal connected to a corresponding monitoring and control line; and a first conduction terminal connected to the second conduction terminal of the aforementioned driving transistor. And the second conducting terminal, which is connected to the corresponding data signal line; A light-emitting control transistor has: a control terminal connected to a corresponding light-emitting control line; and a first conduction terminal connected to the second conduction terminal of the aforementioned driving transistor. and a second conductive terminal, which is connected to the first terminal of the aforementioned display element; and A capacitor element, one end of which is connected to the control terminal of the driving transistor in order to maintain the potential of the control terminal of the driving transistor.

8. The display device according to any one of claims 1 to 4, characterized in that, The aforementioned display unit also has multiple current monitoring lines, which are configured to correspond one-to-one with the multiple data signal lines and intersect with the multiple light emission control lines. The aforementioned multiple current monitoring lines are used as signal lines for transmitting currents corresponding to the characteristics of the aforementioned driving transistors during the aforementioned monitoring process. During the aforementioned current measurement, the integrator circuit measures the current flowing through the corresponding current monitoring line.

9. The display device according to claim 8, characterized in that, The aforementioned display unit includes multiple monitoring and control lines that correspond one-to-one with the aforementioned multiple scan signal lines. The aforementioned scan signal line drive circuit applies monitoring and control signals to the aforementioned multiple monitoring and control lines.

10. The display device according to claim 9, characterized in that, The aforementioned pixel circuit includes: The aforementioned display element has a first terminal and a second terminal; The aforementioned driving transistor has a control terminal, a first conducting terminal, and a second conducting terminal; A write control transistor has: a control terminal connected to a corresponding scan signal line; a first conduction terminal connected to a corresponding data signal line; and a second conduction terminal connected to the control terminal of the aforementioned drive transistor. A monitoring and control transistor has: a control terminal connected to a corresponding monitoring and control line; and a first conduction terminal connected to the second conduction terminal of the aforementioned driving transistor. And the second conducting terminal, which is connected to the corresponding current monitoring line; A light-emitting control transistor has: a control terminal connected to a corresponding light-emitting control line; and a first conduction terminal connected to the second conduction terminal of the aforementioned driving transistor. and a second conductive terminal, which is connected to the first terminal of the aforementioned display element; and A capacitor element, one end of which is connected to the control terminal of the driving transistor in order to maintain the potential of the control terminal of the driving transistor.

11. The display device according to claim 7 or 10, characterized in that, The aforementioned light emission control line driving circuit applies the aforementioned light emission control signal to the aforementioned plurality of light emission control lines, such that the light emission control transistors in the pixel circuits contained in the row of the object being monitored remain in the off state throughout the entire monitoring period.

12. A driving method for a display device, the display device having a pixel circuit, the pixel circuit including a display element driven by a current and a driving transistor for controlling the driving current of the display element, the display device having a function of performing monitoring processing, the monitoring processing being a series of processes for measuring a current flowing through the pixel circuit corresponding to the characteristics of the driving transistor outside the pixel circuit, the driving method for the display device being characterized in that... The above-mentioned display device includes: The display unit includes: multiple data signal lines; multiple scan signal lines; and multiple light emission control lines, which are configured to correspond one-to-one with the multiple scan signal lines and cross the multiple data signal lines. The data signal line driving circuit applies data signals to the aforementioned multiple data signal lines; The scan signal line driving circuit applies the scan signal to the aforementioned multiple scan signal lines; as well as The light-emitting control line driving circuit applies light-emitting control signals to the plurality of light-emitting control lines, and includes a shift register comprising multiple unit circuits corresponding to the plurality of light-emitting control lines in a one-to-one manner. The pixel circuit described above is provided at each intersection of the plurality of data signal lines and the plurality of scan signal lines. The aforementioned data signal line driving circuit includes an integrating circuit for measuring the current corresponding to the characteristics of the aforementioned driving transistor. The aforementioned display device includes a switch disposed between a current flow path corresponding to the characteristics of the aforementioned driving transistor and the aforementioned integrating circuit. The aforementioned shift register, based on multiple light-emitting control clock signals, generates light-emitting control signals to be applied to each light-emitting control line while transmitting the light-emitting control start pulse signal from the first-stage unit circuit to the last-stage unit circuit. The monitoring period for performing the above monitoring process includes: a measurement writing period for writing a data signal that causes a current corresponding to the characteristics of the driving transistor to flow into the pixel circuit; and a current measurement period for measuring the current corresponding to the characteristics of the driving transistor by the integrating circuit. The above driving method includes: The integration stop step stops the flow of current into the integration circuit corresponding to the characteristics of the aforementioned driving transistor; as well as The integration recovery step restores the current flowing into the integration circuit corresponding to the characteristics of the aforementioned driving transistor. During the current measurement, the integration stop step is performed just before the edge timing when the level of at least one of the plurality of light emission control clock signals changes, and the integration recovery step is performed just after the edge timing.

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