Phase synchronization circuit, transceiver circuit, and semiconductor integrated circuit

Abstract

The present application relates to a phase synchronization circuit, a transceiver circuit, and a semiconductor integrated circuit. The phase synchronization circuit has an oscillation circuit (203) including a variable current generation section (222) that generates a variable current corresponding to a control voltage and a fixed current generation section (221) that generates a fixed current corresponding to a correction code, and generates an output clock signal of a frequency corresponding to a total current amount of the variable current and the fixed current, a feedback circuit (204) that generates a feedback clock signal based on the output clock signal, a control voltage generation circuit (202) that, in a normal operation mode, generates the control voltage based on the feedback clock signal and a reference clock signal so that the frequency of the output clock signal becomes a desired frequency, and a correction code generation circuit (201) that, in a correction mode, generates the correction code based on the feedback clock signal and the reference clock signal, and the control voltage generation circuit outputs a fixed control voltage in the correction mode.

Description

Technical Field

[0001] This invention relates to phase synchronization circuits, transceiver circuits, and semiconductor integrated circuits. Background Technology

[0002] Patent Document 1 discloses a voltage-controlled oscillator having multiple inverting differential amplifiers. The multiple inverting differential amplifiers are connected in series, and the current corresponding to the constant voltage used to apply the bias frequency and the current corresponding to the control voltage used to control the oscillation frequency are added together to oscillate at a frequency corresponding to the added current.

[0003] Patent Document 2 discloses a VCO circuit comprising a ring oscillator, a control current generation unit, and a constant current generation unit. For the ring oscillator, an odd number of inverters are connected in a ring. The control current generation unit generates a control current obtained by voltage-to-current conversion of the input control voltage and supplies this control current to the ring oscillator as a power supply current. The constant current generation unit generates a constant current and supplies this constant current to the ring oscillator as a power supply current superimposed on the control current.

[0004] Patent document 3 discloses a DLL circuit comprising a delay circuit for generating a delayed clock, a phase comparison circuit for outputting a phase difference signal between the delayed clock and the input clock, and a charge pump circuit for outputting a phase difference voltage corresponding to the phase difference signal. A low-pass filter circuit removes high-frequency components from the output of the charge pump circuit. The delay control circuit comprises a first voltage-to-current conversion circuit that converts the output voltage of the low-pass filter circuit into current, and a second voltage-to-current conversion circuit that converts a reference voltage into current. The arithmetic circuit subtracts the reference current output from the second voltage-to-current conversion circuit from the phase difference current output from the first voltage-to-current conversion circuit, and outputs a current obtained by adding the subtracted current to a bias current. The current-to-voltage conversion circuit converts the current output from the arithmetic circuit into a voltage, and outputs a control voltage composed of this voltage to the delay circuit.

[0005] Patent document 4 discloses a phase-locked loop (PLL) circuit comprising a phase detector, a loop filter, and a voltage-controlled oscillator. The phase detector generates a control signal representing the frequency difference between the PLL input signal and the output signal. The loop filter generates a first voltage signal and a second voltage signal in response to the control signal. The voltage-controlled oscillator includes a dynamic voltage gain control circuit. The voltage-controlled oscillator changes the frequency of the output signal based on the first voltage signal and the second voltage signal. The dynamic voltage gain control circuit supplies a bias signal based on the voltage swing of the first voltage signal.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2010-273386

[0007] Patent Document 2: Japanese Patent Application Publication No. 2012-191275

[0008] Patent Document 3: Japanese Patent Application Publication No. 2010-239483

[0009] Patent Document 4: US Patent No. 7,786,771

[0010] A voltage-controlled oscillator adds a current (variable current) corresponding to the control voltage to a bias current (fixed current) and oscillates at a frequency corresponding to the added current. However, a problem exists where the bias current varies due to manufacturing or usage conditions, causing the oscillation frequency to change as a result of this variation. Summary of the Invention

[0011] The purpose of this invention is to generate an output clock signal with a frequency corresponding to the total current amount of the variable current and the fixed current by suppressing the variation of the fixed current caused by the variation of the fixed current, based on suppressing the variation of the oscillation frequency caused by the variation of the fixed current.

[0012] The phase synchronization circuit includes: an oscillation circuit comprising a variable current generating unit that generates a variable current corresponding to a control voltage and a fixed current generating unit that generates a fixed current corresponding to a correction code, the oscillation circuit generating an output clock signal with a frequency corresponding to the sum of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generating circuit that, in a normal operating mode, generates the control voltage based on the feedback clock signal and a reference clock signal to make the frequency of the output clock signal a desired frequency; and a correction code generating circuit that, in a correction mode, generates the correction code based on the feedback clock signal and the reference clock signal, in which the control voltage generating circuit outputs a fixed control voltage and the correction code generating circuit adjusts the correction code to make the frequency of the feedback clock signal and the frequency of the reference clock signal a desired relationship.

[0013] By suppressing variations in the fixed current caused by manufacturing or usage conditions, it is possible to generate an output clock signal with a frequency corresponding to the sum of the variable and fixed currents, while suppressing variations in the oscillation frequency caused by the variations in the fixed current. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating a structural example of the semiconductor integrated circuit of this embodiment.

[0015] Figure 2This is a diagram illustrating an example of the structure of a PLL circuit.

[0016] Figure 3 It is a graph showing the relationship between the correction code and the frequency of the output clock signal.

[0017] Figure 4 It is a graph showing the relationship between the control voltage and the frequency of the output clock signal.

[0018] Figure 5 This is a circuit diagram illustrating an example of the structure of a voltage-controlled oscillator.

[0019] Figure 6 This is a circuit diagram illustrating a structural example of a fixed current generating unit.

[0020] Figure 7 This is a circuit diagram showing another structural example of a fixed current generating unit.

[0021] Figure 8 This is a circuit diagram showing another example of the structure of a fixed current generating unit.

[0022] Figure 9 This is a circuit diagram illustrating an example of the structure of a charge pump circuit and a loop filter.

[0023] Figure 10 This is a block diagram illustrating an example of the structure of a frequency comparator.

[0024] Figure 11 This is a diagram used to illustrate the adjustment method of the correction code.

[0025] Figure 12 This is a flowchart illustrating the processing method of a frequency comparator. Detailed Implementation

[0026] Figure 1 This is a block diagram illustrating a structural example of the semiconductor integrated circuit 100 according to this embodiment. The semiconductor integrated circuit 100 has an internal circuit 101 and a transceiver circuit 102. The transceiver circuit 102 has a phase-locked loop circuit (PLL circuit) 111, a transmitting circuit 112, and a receiving circuit 113.

[0027] Internal circuit 101 sends data to transmitting circuit 112, receives data from receiving circuit 113, and outputs mode signal MD, power-off signal PD, and reference clock signal RCLK to PLL circuit 111. Mode signal MD is 1 in calibration mode and 0 in normal operation mode.

[0028] PLL circuit 111 is a phase synchronization circuit that receives the mode signal MD, the power-off signal PD, and the reference clock signal RCLK, and generates the output clock signal OCLK. PLL circuit 111 can generate a high-precision output clock signal OCLK. Transmitting circuit 112 uses the output clock signal OCLK to transmit a transmit signal based on the aforementioned transmit data. Receiving circuit 113 uses the output clock signal OCLK to receive a receive signal and outputs the received data to internal circuit 101. The output clock signal OCLK can be a single-ended signal or a differential signal.

[0029] With the increasing speed of data transmission in the transmitting circuit 112 and data reception in the receiving circuit 113, the output clock signal OCLK generated by the PLL circuit 111 needs to balance high frequency and low jitter.

[0030] Figure 2 It is shown Figure 1 The diagram shows an example of the structure of PLL circuit 111. PLL circuit 111 accepts reference clock signal RCLK, power-off signal PD, and mode signal MD, and outputs output clock signal OCLK.

[0031] PLL circuit 111 includes a frequency comparator 201, a control voltage generation circuit 202, a voltage controlled oscillator (VCO) 203, and a frequency divider 204. Control voltage generation circuit 202 includes a phase frequency detector (PFD) 211, a charge pump circuit 212, and a loop filter (LPF) 213. Voltage controlled oscillator 203 is an oscillation circuit with a fixed current generation section 221, a variable current generation section 222, and multiple buffers 223 to 226.

[0032] The fixed current generation unit 221 generates a fixed current with a current amount corresponding to the correction code, and controls the buffers 223 to 226 so that the current corresponding to the fixed current flows through each of the buffers 223 to 226.

[0033] The variable current generating unit 222 generates a variable current corresponding to the current amount of the control voltage Vc, and controls the buffers 223 to 226 so that the current corresponding to the variable current flows through each of the buffers 223 to 226.

[0034] Buffers 223 to 226 each have differential signal input terminals Ip and In, and differential signal output terminals Op and On. The output terminals Op and On of the first-stage buffer 223 are connected to the input terminals Ip and In of the next-stage buffer 224. The output terminals Op and On of buffer 224 are connected to the input terminals Ip and In of the next-stage buffer 225. The output terminals Op and On of buffer 225 are connected to the input terminals Ip and In of the final-stage buffer 226. The output terminals Op and On of the final-stage buffer 226 are connected to the input terminals In and Ip of the first-stage buffer 223.

[0035] Buffers 223-226 generate an output clock signal OCLK that is a frequency differential between the variable current generated by the variable current generation unit 222 and the fixed current generated by the fixed current generation unit 221. For example... Figure 4 As shown, the lower the control voltage Vc, the larger the variable current generated by the variable current generation unit 222, the greater the total current of the variable current and the fixed current, and the higher the frequency of the output clock signal OCLK.

[0036] Frequency divider 204 is a feedback circuit that generates a feedback clock signal FBCLK based on the single-ended output clock signal OCLK. Specifically, when the mode signal MD is 0 and the system is in normal operation mode, frequency divider 204 generates and outputs the feedback clock signal FBCLK by dividing the output clock signal OCLK by a first division ratio. Furthermore, when the mode signal MD is 1 and the system is in correction mode, frequency divider 204 generates and outputs the feedback clock signal FBCLK by dividing the output clock signal OCLK by a second division ratio, which is different from the first division ratio. For example, frequency divider 204 can have two frequency dividers, one with a first division ratio and the other with a second division ratio, and can be configured to select either of these frequency dividers based on the mode signal MD.

[0037] When the mode signal MD is 0 and the system is in normal operating mode, the control voltage generation circuit 202 generates a control voltage Vc based on the feedback clock signal FBCLK and the reference clock signal RCLK to make the frequency of the output clock signal OCLK the desired frequency. Specifically, for example, in normal operating mode, the control voltage generation circuit 202 adjusts the control voltage Vc to reduce the phase difference between the feedback clock signal FBCLK and the reference clock signal RCLK. Furthermore, the control voltage generation circuit 202 stops based on the power-off signal PD.

[0038] In addition, when the mode signal MD is 1 and it is in correction mode, the control voltage generation circuit 202 outputs a fixed control voltage Vc.

[0039] Phase-frequency detector 211 compares the phase of the feedback clock signal FBCLK with the phase of the reference clock signal RCLK. When the phase of the feedback clock signal FBCLK lags behind the phase of the reference clock signal RCLK, phase-frequency detector 211 outputs a falling high-level pulse signal DN to increase the frequency of both the output clock signal OCLK and the feedback clock signal FBCLK. Figure 9 The charge pump circuit 212. Additionally, when the phase of the feedback clock signal FBCLK leads the phase of the reference clock signal RCLK, the phase frequency detector 211 outputs a rising low-level pulse signal XUP to reduce the frequency of both the output clock signal OCLK and the feedback clock signal FBCLK. Figure 9 The charge pump circuit 212.

[0040] When the mode signal MD is 0 (normal operating mode) and the power-off signal PD is 0, the charge pump circuit 212 reduces the control voltage Vc when a falling signal DN with a high-level pulse is input, and increases the control voltage Vc when a rising signal XUP with a low-level pulse is input.

[0041] Furthermore, when the mode signal MD is 1 (correction mode) and the power-off signal PD is 0, the charge pump circuit 212 outputs a fixed control voltage Vc. Additionally, the charge pump circuit 212 stops when the power-off signal PD is 1.

[0042] The loop filter 213 outputs the control voltage Vc to the variable current generation unit 222. At this time, the loop filter 213 slows down the fluctuation of the control voltage Vc to suppress extreme frequency variations. The loop filter 213 is, for example, a low-pass filter that reduces the high-frequency components of the control voltage Vc.

[0043] The frequency comparator 201 is a correction code generation circuit. When the mode signal MD is 1 (correction mode), it generates a correction code CD based on the feedback clock signal FBCLK and the reference clock signal RCLK. When the mode signal MD is 1 (correction mode), the frequency comparator 201 adjusts the correction code CD to make the frequency of the feedback clock signal FBCLK and the frequency of the reference clock signal RCLK have a desired relationship. Specifically, for example, when the mode signal MD is 1 (correction mode), the frequency comparator 201 adjusts the correction code CD to reduce the difference between the frequency of the feedback clock signal FBCLK and the frequency of the reference clock signal RCLK. For example, when the mode signal MD is 1 (correction mode), the frequency comparator 201 maintains a correction code CD where the difference between the frequency of the feedback clock signal FBCLK and the frequency of the reference clock signal RCLK is equal to or less than a desired minimum value. Furthermore, when the mode signal MD is 0 (normal operation mode), the frequency comparator 201 outputs the maintained correction code CD to the fixed current generation unit 221.

[0044] Figure 3 This is a graph showing the relationship between the correction code CD and the frequency f of the output clock signal OCLK. The larger the correction code CD, the greater the current generated by the fixed current generation unit 221, and the higher the frequency of the output clock signal OCLK. The frequency f of the output clock signal OCLK increases monotonically relative to the correction code CD. Alternatively, the frequency f of the output clock signal OCLK can also decrease monotonically relative to the correction code CD.

[0045] Figure 4 This is a graph showing the relationship between the control voltage Vc and the frequency f of the output clock signal OCLK when the mode signal MD is 0 (normal operating mode). Frequency characteristic 401 is... Figure 2 The frequency characteristics of PLL circuit 111. Frequency characteristic 402 is for... Figure 2 The frequency comparator 201 and the fixed current generation unit 221 are removed from the PLL circuit 111, and the frequency characteristics are adjusted so that the maximum value of the oscillation frequency is the same as that of the circuit before removal.

[0046] When the control voltage Vc is higher than a specified voltage, the frequency f of the output clock signal OCLK is the base frequency f0. The base frequency f0 is determined by the fixed current generated by the fixed current generation unit 221 based on the correction code CD. Furthermore, the frequency divider 204 can divide the output clock signal OCLK with different division ratios in normal operating mode and correction mode. The frequency divider 204 can control the base frequency f0 according to the division ratio in correction mode.

[0047] Furthermore, compared to frequency characteristic 402, frequency characteristic 401 shows a smaller slope of frequency f of the output clock signal OCLK relative to the control voltage Vc. This slope is determined by the ratio of the fixed current generated by the fixed current generation unit 221 to the variable current generated by the variable current generation unit 222.

[0048] Because the frequency characteristic 402 has a large slope, the frequency f of the output clock signal OCLK changes significantly due to the variation of the control voltage Vc, resulting in increased jitter of the output clock signal OCLK.

[0049] In contrast, due to the smaller slope of frequency characteristic 401, the frequency f of the output clock signal OCLK is less affected by changes in the control voltage Vc, thus reducing jitter in the output clock signal OCLK. The PLL circuit 111 can generate a high-frequency output clock signal OCLK while reducing the slope of frequency characteristic 401.

[0050] However, since the fundamental frequency f0 varies due to manufacturing or usage conditions, it is difficult to stabilize the frequency characteristic 401. Therefore, the PLL circuit 111, by providing the frequency comparator 201, suppresses the situation where the fundamental frequency f0 varies due to manufacturing or usage conditions because the fixed current generated by the fixed current generation unit 221 varies. Thus, the PLL circuit 111 reduces the variation in the fundamental frequency f0, thereby obtaining a stable frequency characteristic 401.

[0051] Figure 5 It is shown Figure 2 The circuit diagram of a voltage-controlled oscillator 203 is shown as an example. Figure 5 The diagram shows only the structure of buffer 223 out of buffers 223 to 226, but buffers 224 to 226 also have the same structure as buffer 223.

[0052] The voltage-controlled oscillator 203 includes a fixed current generation unit 221, a variable current generation unit 222, and buffers 223 to 226. The fixed current generation unit 221 includes a p-channel field-effect transistor 501, current sources 502 and 503, and an n-channel field-effect transistor 504.

[0053] The source of p-channel MOSFET 501 is connected to the power supply potential node, and the gate is connected to the drain. Current source 502 is connected between the drain of p-channel MOSFET 501 and the reference potential node, and controls the current flowing through p-channel MOSFET 501 according to the correction code CD. The reference potential node is, for example, ground. The gate of p-channel MOSFET 501 is connected to the gates of p-channel MOSFETs 521 and 524, forming a current mirror.

[0054] The source of the n-channel field-effect transistor 504 is connected to a reference potential node, and the gate is connected to the drain. A current source 503 is connected between the drain of the n-channel field-effect transistor 504 and the power supply potential node, and controls the current flowing through the n-channel field-effect transistor 504 according to a correction code CD. The gate of the n-channel field-effect transistor 504 is connected to the n-channel field-effect transistor 527, forming a current mirror.

[0055] The fixed current generation unit 221 causes a fixed current of the amount corresponding to the correction code CD to flow through the p-channel field-effect transistor 501 and the n-channel field-effect transistor 504.

[0056] The variable current generation unit 222 includes a p-channel field-effect transistor 511 and an n-channel field-effect transistor 512. The source of the p-channel field-effect transistor 511 is connected to the power supply potential node, the gate is connected to the control voltage Vc node, and the drain is connected to the drain of the n-channel field-effect transistor 512. The gate of the n-channel field-effect transistor 512 is connected to the drain, and the source is connected to the reference potential node. The lower the control voltage Vc, the larger the current flows through both the p-channel field-effect transistor 511 and the n-channel field-effect transistor 512.

[0057] The gate of p-channel field-effect transistor 511 is connected to the gates of p-channel field-effect transistors 522 and 523, forming a current mirror. The gate of n-channel field-effect transistor 512 is connected to the gate of n-channel field-effect transistor 528, forming a current mirror.

[0058] The variable current generation unit 222 causes a variable current corresponding to the control voltage Vc to flow through the n-channel field-effect transistor 512.

[0059] Buffer 223 includes p-channel field-effect transistors 521-524 and n-channel field-effect transistors 525-528. The source of p-channel field-effect transistor 521 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 501, and its drain is connected to the output terminal On. The source of p-channel field-effect transistor 522 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 511, and its drain is connected to the output terminal On. The source of p-channel field-effect transistor 523 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 511, and its drain is connected to the output terminal Op. The source of p-channel field-effect transistor 524 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 501, and its drain is connected to the output terminal Op.

[0060] P-channel field-effect transistors 521 and 524 flow with the same or proportional current as that flowing through p-channel field-effect transistor 501. P-channel field-effect transistors 522 and 523 flow with the same or proportional current as that flowing through p-channel field-effect transistor 511.

[0061] The drain of n-channel field-effect transistor 525 is connected to the output terminal On, the gate is connected to the input terminal Ip, and the source is connected to node N1. The drain of n-channel field-effect transistor 526 is connected to the output terminal Op, the gate is connected to the input terminal In, and the source is connected to node N1. n-channel field-effect transistors 525 and 526 form a differential pair.

[0062] The drain of n-channel field-effect transistor 527 is connected to node N1, the gate is connected to the gate of n-channel field-effect transistor 504, and the source is connected to the reference potential node. The drain of n-channel field-effect transistor 528 is connected to node N1, the gate is connected to the gate of n-channel field-effect transistor 512, and the source is connected to the reference potential node.

[0063] The n-channel field-effect transistor 527 carries the same or a proportional current as the current flowing through the n-channel field-effect transistor 504. The n-channel field-effect transistor 528 carries the same or a proportional current as the current flowing through the n-channel field-effect transistor 512.

[0064] Buffers 223-226 receive differential signals at input terminals Ip and In, respectively, and output differential signals from output terminals Op and On. Buffers 223-226 generate an output clock signal OCLK with a frequency corresponding to the total current flowing through the variable current generation unit 222 and the fixed current flowing through the fixed current generation unit 221. The higher the total current, the higher the frequency of the output clock signal OCLK.

[0065] Figure 6 It is shown Figure 5 A circuit diagram illustrating an example of the structure of the fixed current generating unit 221. The fixed current generating unit 221 includes resistors 601-606, n-channel field-effect transistors 504, 607-609, inverters 610-612, and p-channel field-effect transistors 501, 613-615. The correction code CD includes correction codes CD0-CDx.

[0066] The source of the p-channel field-effect transistor 501 is connected to the power supply potential node, and the gate is connected to the power supply potential node. Figure 5 The gate and drain of the p-channel field-effect transistors 521 and 524 are connected to the gate.

[0067] Resistor 601 is connected between the drain of p-channel field-effect transistor 501 and the drain of n-channel field-effect transistor 607. Resistor 602 is connected between the drain of p-channel field-effect transistor 501 and the drain of n-channel field-effect transistor 608. Resistor 603 is connected between the drain of p-channel field-effect transistor 501 and the drain of n-channel field-effect transistor 609.

[0068] The gate of n-channel field-effect transistor 607 is connected to the node of correction code CD0, and the source is connected to the reference potential node. The gate of n-channel field-effect transistor 608 is connected to the node of correction code CD1, and the source is connected to the reference potential node. The gate of n-channel field-effect transistor 609 is connected to the node of correction code CDx, and the source is connected to the reference potential node.

[0069] Inverter 610 outputs the logic inverted signal of correction code CD0 to the gate of p-channel field-effect transistor 613. Inverter 611 outputs the logic inverted signal of correction code CD1 to the gate of p-channel field-effect transistor 614. Inverter 612 outputs the logic inverted signal of correction code CDx to the gate of p-channel field-effect transistor 615.

[0070] The sources of p-channel field-effect transistors 613-615 are connected to the power supply potential node. Resistor 604 is connected between the drain of p-channel field-effect transistor 613 and the drain of n-channel field-effect transistor 504. Resistor 605 is connected between the drain of p-channel field-effect transistor 614 and the drain of n-channel field-effect transistor 504. Resistor 606 is connected between the drain of p-channel field-effect transistor 615 and the drain of n-channel field-effect transistor 504.

[0071] The gate of the n-channel field-effect transistor 504 is connected to the drain, and the source is connected to the reference potential node. Additionally, the gate of the n-channel field-effect transistor 504 is connected to... Figure 5 The gate of the n-channel field-effect transistor 527.

[0072] Figure 7 It is shown Figure 5 A circuit diagram of another structural example of the fixed current generation unit 221. The fixed current generation unit 221 includes current sources 701 and 702, n-channel field-effect transistors 504, 703 to 709, inverters 710 to 712, and p-channel field-effect transistors 501, 713 to 719. The correction code CD has correction codes CD0 to CDx.

[0073] The source of the p-channel field-effect transistor 501 is connected to the power supply potential node, and the gate is connected to the power supply potential node. Figure 5 The gate and drain of the p-channel field-effect transistors 521 and 524 are connected to the gate.

[0074] Current source 701 is connected between the power supply potential node and the drain of n-channel field-effect transistor 706. The gate of n-channel field-effect transistor 706 is connected to the drain, and the source is connected to the reference potential node.

[0075] The drain of n-channel field-effect transistor 703 is connected to the drain of p-channel field-effect transistor 501, its gate is connected to the node of correction code CD0, and its source is connected to the drain of n-channel field-effect transistor 707. The gate of n-channel field-effect transistor 707 is connected to the gate of n-channel field-effect transistor 706, and its source is connected to the reference potential node.

[0076] The drain of n-channel field-effect transistor 704 is connected to the drain of p-channel field-effect transistor 501, its gate is connected to the node of correction code CD1, and its source is connected to the drain of n-channel field-effect transistor 708. The gate of n-channel field-effect transistor 708 is connected to the gate of n-channel field-effect transistor 706, and its source is connected to the reference potential node.

[0077] The drain of n-channel field-effect transistor 705 is connected to the drain of p-channel field-effect transistor 501, its gate is connected to the node of correction code CDx, and its source is connected to the drain of n-channel field-effect transistor 709. The gate of n-channel field-effect transistor 709 is connected to the gate of n-channel field-effect transistor 706, and its source is connected to the reference potential node.

[0078] The source of the p-channel field-effect transistor 713 is connected to the power supply potential node, and the gate is connected to the drain. A current source 702 is connected between the drain of the p-channel field-effect transistor 713 and the reference potential node.

[0079] The source of p-channel field-effect transistor 714 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 713, and its drain is connected to the source of p-channel field-effect transistor 717. Inverter 710 outputs the logic inversion signal of correction code CD0 to the gate of p-channel field-effect transistor 717. The drain of p-channel field-effect transistor 717 is connected to the drain of n-channel field-effect transistor 504.

[0080] The source of p-channel field-effect transistor 715 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 713, and its drain is connected to the source of p-channel field-effect transistor 718. Inverter 711 outputs the logic inversion signal of correction code CD1 to the gate of p-channel field-effect transistor 718. The drain of p-channel field-effect transistor 718 is connected to the drain of n-channel field-effect transistor 504.

[0081] The source of p-channel field-effect transistor 716 is connected to the power supply potential node, its gate is connected to the gate of p-channel field-effect transistor 713, and its drain is connected to the source of p-channel field-effect transistor 719. Inverter 712 outputs the logic inversion signal of correction code CDx to the gate of p-channel field-effect transistor 719. The drain of p-channel field-effect transistor 719 is connected to the drain of n-channel field-effect transistor 504.

[0082] The gate of the n-channel field-effect transistor 504 is connected to the drain, and the source is connected to the reference potential node. Additionally, the gate of the n-channel field-effect transistor 504 is connected to... Figure 5 The gate of the n-channel field-effect transistor 527.

[0083] Figure 8 It is shown Figure 5 A circuit diagram of another structural example of the fixed current generating unit 221. The fixed current generating unit 221 includes p-channel field-effect transistors 501 and 801, resistors 802 to 804, and n-channel field-effect transistors 504, 805 to 807. The correction code CD includes correction codes CD0 to CDx.

[0084] The source of the p-channel field-effect transistor 501 is connected to the power supply potential node, and the gate is connected to the power supply potential node. Figure 5 The gates and drains of the p-channel field-effect transistors 521 and 524 are connected to the drain of the n-channel field-effect transistor 504.

[0085] The drain of the n-channel field-effect transistor 504 is connected to the gate, and the gate is connected to... Figure 5 The gate and source of the n-channel field-effect transistor 527 are connected to the reference potential node.

[0086] The source of p-channel field-effect transistor 801 is connected to the power supply potential node, the gate is connected to the gate of p-channel field-effect transistor 501, and the drain is connected to the gate.

[0087] Resistor 802 is connected between the drain of p-channel field-effect transistor 801 and the drain of n-channel field-effect transistor 805. The gate of n-channel field-effect transistor 805 is connected to the node of correction code CD0, and the source is connected to the reference potential node.

[0088] Resistor 803 is connected between the drain of p-channel field-effect transistor 801 and the drain of n-channel field-effect transistor 806. The gate of n-channel field-effect transistor 806 is connected to the node of correction code CD1, and the source is connected to the reference potential node.

[0089] Resistor 804 is connected between the drain of p-channel field-effect transistor 801 and the drain of n-channel field-effect transistor 807. The gate of n-channel field-effect transistor 807 is connected to the node of correction code CDx, and the source is connected to the reference potential node.

[0090] Figure 9 It is shown Figure 2 The circuit diagram shows an example of the structure of the charge pump circuit 212 and the loop filter 213. The charge pump circuit 212 includes a charge pump section 901, a fixed voltage generation section 902, inverters 903 to 905, and logic AND (OR) circuits 906 and 907.

[0091] The charge pump section 901 includes a current source 911, p-channel field-effect transistors 912-916, and n-channel field-effect transistors 917-922. The fixed voltage generation section 902 includes a p-channel field-effect transistor 931, resistors 932 and 933, and an n-channel field-effect transistor 934.

[0092] For the mode signal MD, 1 represents the correction mode and 0 represents the normal operation mode. For the power-off signal PD, 1 represents the power-off mode and 0 represents the operation mode.

[0093] Inverter 903 outputs the logic inverted signal of mode signal MD. Logic AND circuit 906 outputs the logic AND signal of inverter 903 with the power-off signal PD. Inverter 904 outputs the logic inverted signal of the output of logic AND circuit 906.

[0094] The logic AND circuit 907 outputs the mode signal MD and the power-off signal PD. The inverter 905 outputs the logic AND circuit 907's output signal, which is the inverted logic AND signal.

[0095] Current source 911 is connected between the power supply potential node and the drain of n-channel field-effect transistor 918. The source of n-channel field-effect transistor 918 is connected to the reference potential node. The drain of n-channel field-effect transistor 919 is connected to the gate of n-channel field-effect transistor 918, the gate is connected to the output terminal of logic AND circuit 907, and the source is connected to the reference potential node.

[0096] The source of p-channel field-effect transistor 912 is connected to the drain of n-channel field-effect transistor 918, and its gate is connected to the output terminal of logic AND circuit 907. The drain of p-channel field-effect transistor 912 is connected to the drain of n-channel field-effect transistor 918, its gate is connected to the output terminal of inverter 905, and its source is connected to the gate of n-channel field-effect transistor 918.

[0097] The source of the p-channel field-effect transistor 914 is connected to the power supply potential node, and the gate is connected to the drain. The drain of the n-channel field-effect transistor 920 is connected to the drain of the p-channel field-effect transistor 914, the gate is connected to the gate of the n-channel field-effect transistor 918, and the source is connected to the reference potential node.

[0098] The source of the p-channel field-effect transistor 913 is connected to the power supply potential node, the gate is connected to the output terminal of the inverter 905, and the drain is connected to the gate of the p-channel field-effect transistor 914.

[0099] The source of p-channel field-effect transistor 915 is connected to the power supply potential node, the gate is connected to the gate of p-channel field-effect transistor 914, and the drain is connected to the source of p-channel field-effect transistor 916. The gate of p-channel field-effect transistor 916 is connected to the node of the rising signal XUP, and the drain is connected to node N2.

[0100] The drain of n-channel field-effect transistor 921 is connected to node N2, the gate is connected to the node of the falling signal DN, and the source is connected to the drain of n-channel field-effect transistor 922. The gate of n-channel field-effect transistor 922 is connected to the gate of n-channel field-effect transistor 918, and the source is connected to the reference potential node.

[0101] The source of p-channel MOSFET 931 is connected to the power supply node, and its gate is connected to the output terminal of logic AND circuit 906. Resistor 932 is connected between the drain of p-channel MOSFET 931 and node N2. Resistor 933 is connected between node N2 and the drain of n-channel MOSFET 934. The gate of n-channel MOSFET 934 is connected to the output terminal of inverter 904, and its source is connected to the reference node.

[0102] Loop filter 213 includes resistor 941 and capacitors 942 and 943, designed to slow down fluctuations in the control voltage Vc of node N2 by suppressing extreme frequency variations. Loop filter 213 is, for example, a low-pass filter that reduces the high-frequency components of the control voltage Vc of node N2. A series connection of resistor 941 and capacitor 942 is established between node N2 and a reference potential node. Capacitor 943 is also connected between node N2 and the reference potential node.

[0103] First, let's explain the case where the power-off signal PD is 1 (power-off mode). P-channel MOSFET 912 and n-channel MOSFET 917 are in the off state. N-channel MOSFET 919 is in the on state, while n-channel MOSFETs 918, 920, and 922 are in the off state. P-channel MOSFET 913 is in the on state, while p-channel MOSFETs 914 and 915 are in the off state. P-channel MOSFET 931 and n-channel MOSFET 934 are in the off state. Therefore, no current flows through the charge pump circuit 212, thus reducing power consumption.

[0104] Next, the case where the power-off signal PD is 0 and the mode signal MD is 0 (normal operating mode) will be explained. P-channel MOSFET 912 and n-channel MOSFET 917 are in the ON state. n-channel MOSFET 919 is in the OFF state. P-channel MOSFET 913 is in the OFF state. P-channel MOSFET 931 and n-channel MOSFET 934 are in the OFF state.

[0105] When the phase of the feedback clock signal FBCLK leads the phase of the reference clock signal RCLK, the rising signal XUP becomes a low-level pulse, and the p-channel MOSFET 916 turns on. Then, capacitor 943 is charged, the control voltage Vc of node N2 rises, the frequency of the output clock signal OCLK decreases, and the phase of the feedback clock signal FBCLK lags.

[0106] Furthermore, when the phase of the feedback clock signal FBCLK lags behind the phase of the reference clock signal RCLK, the falling signal DN becomes a high-level pulse, and the n-channel MOSFET 921 becomes active. Then, capacitor 943 discharges, the control voltage Vc at node N2 decreases, the frequency of the output clock signal OCLK increases, and the phase of the feedback clock signal FBCLK leads.

[0107] Furthermore, when the phase of the feedback clock signal FBCLK is the same as the phase of the reference clock signal RCLK, the rising signal XUP becomes high, the falling signal DN becomes low, and the p-channel MOSFET 916 and n-channel MOSFET 921 become off. The control voltage Vc of node N2 is maintained, the frequency of the output clock signal OCLK is maintained, and the phase of the feedback clock signal FBCLK is maintained.

[0108] As described above, the charge pump circuit 212 adjusts the control voltage Vc to reduce the phase difference between the feedback clock signal FBCLK and the reference clock signal RCLK.

[0109] Next, the case where the power-off signal PD is 0 and the mode signal MD is 1 (correction mode) will be explained. P-channel MOSFET 912 and n-channel MOSFET 917 are in the off state. n-channel MOSFET 919 is in the on state, while n-channel MOSFETs 918, 920, and 922 are in the off state. P-channel MOSFET 913 is in the on state, while p-channel MOSFETs 914 and 915 are in the off state. P-channel MOSFET 931 and n-channel MOSFET 934 are in the on state. The fixed voltage generation unit 902 outputs a fixed control voltage Vc through the voltage division of resistors 932 and 933. Alternatively, the fixed voltage generation unit 902 can also output a power supply potential as the fixed control voltage Vc. The charge pump unit 901 stops flowing without current.

[0110] Figure 10 It is shown Figure 2 A block diagram illustrating the structure of a frequency comparator 201 is provided. The frequency comparator 201 includes counters 1001-1003 and a controller 1004. When the mode signal MD changes from 0 to 1, counters 1001-1003 and the controller 1004 are reset. Counter 1001 begins counting during the measurement period. The controller 1004 outputs a correction code CD for the initial value. Counter 1002 begins counting the number of pulses of the reference clock signal RCLK. Counter 1003 begins counting the number of pulses of the feedback clock signal FBCLK.

[0111] When the measurement period has elapsed, counter 1001 outputs an update signal to controller 1004. Then, controller 1004 compares the number of clock cycles of the reference clock signal RCLK during the measurement period, counted by counter 1002, with the number of clock cycles of the feedback clock signal FBCLK during the measurement period, counted by counter 1003.

[0112] For example, such as Figure 3 As shown, the case where the larger the correction code CD is, the more the fixed current generation unit 221 increases the amount of fixed current, and the higher the frequency of the output clock signal OCLK will be explained. For example... Figure 11As shown, when the number of pulses in the feedback clock signal FBCLK during the measurement period is less than the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 increases the correction code CD by one level, thereby increasing the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK. Conversely, when the number of pulses in the feedback clock signal FBCLK during the measurement period is greater than the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 decreases the correction code CD by one level, thereby decreasing the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK. Finally, when the number of pulses in the feedback clock signal FBCLK during the measurement period is the same as the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 maintains the correction code CD, thus maintaining the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK.

[0113] Subsequently, if the difference between the number of pulses of the feedback clock signal FBCLK during the measurement period and the number of pulses of the reference clock signal RCLK during the measurement period exceeds the desired minimum value, the controller 1004 outputs a reset signal RST to the counters 1001 to 1003, resetting the counters 1001 to 1003. Then, after the reset, the counters 1001 to 1003 and the controller 1004 repeat the above process.

[0114] If the difference between the number of pulses of the feedback clock signal FBCLK and the number of pulses of the reference clock signal RCLK during the measurement period is equal to or less than the desired minimum value, the controller 1004 holds the correction code CD, ends the calibration mode, and moves to the normal operation mode. In the normal operation mode, the controller 1004 outputs the held correction code CD to the fixed current generation unit 221.

[0115] As described above, the controller 1004 is an adjustment unit that adjusts the correction code CD in calibration mode to reduce the difference between the number of pulses (frequency) of the feedback clock signal FBCLK and the number of pulses (frequency) of the reference clock signal RCLK.

[0116] Figure 12 It is shown Figure 10 A flowchart illustrating the processing method of the frequency comparator 201. The frequency comparator 201 performs operations, for example, when the power supply to the PLL circuit 111 is turned on, or at certain time intervals. Figure 12 The processing.

[0117] In step S1201, the internal circuit 101 changes the mode signal MD from 0 to 1, shifting it to the correction mode.

[0118] Next, in step S1202, controller 1004 resets counters 1001-1003 and controller 1004. Controller 10045 outputs the correction code CD of the initial value. Counter 1001 begins counting for a certain period.

[0119] Next, in step S1203, counter 1002 counts the number of pulses of the reference clock signal RCLK within a certain period. Counter 1003 counts the number of pulses of the feedback clock signal FBCLK within a certain period.

[0120] Next, in step S1204, the controller 1004 compares the number of pulses of the reference clock signal RCLK within a certain period with the number of pulses of the feedback clock signal FBCLK within the same period. If the number of pulses of the feedback clock signal FBCLK within the same period is less than the number of pulses of the reference clock signal RCLK, the controller 1004 proceeds to step S1205. If the number of pulses of the feedback clock signal FBCLK within the same period is greater than the number of pulses of the reference clock signal RCLK, the controller 1004 proceeds to step S1206. If the number of pulses of the feedback clock signal FBCLK within the same period is the same as the number of pulses of the reference clock signal RCLK, the controller 1004 proceeds to step S1207.

[0121] In step S1205, the controller 1004 increases the correction code CD by one level, and proceeds to step S1208.

[0122] In step S1206, the controller 1004 reduces the correction code CD by one level and proceeds to step S1208.

[0123] In step S1207, the controller 1004 maintains the current correction code CD and proceeds to step S1208.

[0124] In step S1208, if the controller 1004 changes from increasing to decreasing the correction code CD, or from decreasing to increasing the correction code CD, it proceeds to step S1210. Alternatively, if the direction of the increase or decrease of the correction code CD remains unchanged (i.e., if the correction code CD changes but does not change from increasing to decreasing, or vice versa), the controller 1004 proceeds to step S1209.

[0125] In step S1209, the controller 1004 resets the counters 1001 to 1003 and returns to step S1203 to repeat the above process.

[0126] In step S1210, the controller 1004 holds the correction code CD. The internal circuit 101 changes the mode signal MD from 0 to 1, shifting to the normal operating mode. In the normal operating mode, the controller 1004 outputs the held correction code CD to the fixed current generation unit 221.

[0127] Next, we will explain the case where a larger correction code CD results in a smaller amount of fixed current generated by the fixed current generation unit 221, thus lowering the frequency of the output clock signal OCLK. When the number of pulses in the feedback clock signal FBCLK during the measurement period is less than the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 decreases the correction code CD by one level, increasing the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK. Conversely, when the number of pulses in the feedback clock signal FBCLK during the measurement period is greater than the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 increases the correction code CD by one level, decreasing the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK. Finally, when the number of pulses in the feedback clock signal FBCLK during the measurement period is the same as the number of pulses in the reference clock signal RCLK during the measurement period, the controller 1004 maintains the correction code CD, thus maintaining the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK.

[0128] Subsequently, if the difference between the number of pulses of the feedback clock signal FBCLK during the measurement period and the number of pulses of the reference clock signal RCLK during the measurement period is greater than the desired minimum value, the controller 1004 outputs a reset signal RST to counters 1001 to 10035 to reset counters 1001 to 1003. Then, after the reset, counters 1001 to 1003 and the controller 1004 repeat the above process.

[0129] If the difference between the number of pulses of the feedback clock signal FBCLK and the number of pulses of the reference clock signal RCLK during the measurement period is equal to or less than the desired minimum value, the controller 1004 holds the correction code CD, ends the calibration mode, and moves to the normal operation mode. In the normal operation mode, the controller 1004 outputs the held correction code CD to the fixed current generation unit 221.

[0130] For example, the controller 1004 maintains the correction code CD and the frequencies of the output clock signal OCLK and the feedback clock signal FBCLK when the correction code CD remains unchanged, changes from an increase in the correction code CD to a decrease in the correction code CD, or changes from a decrease in the correction code CD to an increase in the correction code CD.

[0131] As described above, frequency comparator 201 adjusts the correction code CD to reduce the difference between the frequency of the feedback clock signal FBCLK and the frequency of the reference clock signal RCLK. Since the fixed current generation unit 221 generates a fixed current based on this correction code CD, it can suppress fluctuations in the fixed current caused by manufacturing or usage conditions. Since buffers 223-226 generate an output clock signal OCLK with a frequency corresponding to the sum of the variable current from the variable current generation unit 222 and the fixed current from the fixed current generation unit 221, they can... Figure 4 The frequency characteristics of 401 are stable. The voltage-controlled oscillator 203 reduces... Figure 4 The frequency response slope of 401 reduces the jitter of the output clock signal OCLK.

[0132] Furthermore, the above embodiments are merely illustrative examples of implementing the present invention and are not intended to limit the scope of the invention. That is, the present invention can be implemented in various ways without departing from its technical concept or its main features.

[0133] By suppressing variations in the fixed current caused by manufacturing or usage conditions, it is possible to generate an output clock signal with a frequency corresponding to the sum of the variable and fixed currents, while suppressing variations in the oscillation frequency caused by the variations in the fixed current.

Claims

1. A phase synchronization circuit, comprising: an oscillation circuit including a variable current generating section that generates a variable current of an amount of current corresponding to a control voltage, and a fixed current generating section that generates a fixed current of an amount of current corresponding to a correction code, the oscillation circuit generating an output clock signal of a frequency corresponding to a total amount of current of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generating circuit that generates the control voltage based on the feedback clock signal and a reference clock signal in a normal operation mode so that a frequency of the output clock signal becomes a desired frequency; and a correction code generating circuit that generates the correction code based on the feedback clock signal and the reference clock signal in a correction mode, wherein in the correction mode, the control voltage generating circuit outputs a fixed control voltage, and the correction code generating circuit adjusts the correction code so that a frequency of the feedback clock signal and a frequency of the reference clock signal become a desired relationship, wherein the correction code generating circuit includes: a first counter that counts a number of pulses of the feedback clock signal; a second counter that counts a number of pulses of the reference clock signal; and an adjustment section that adjusts the correction code so that a difference between the number of pulses of the feedback clock signal and the number of pulses of the reference clock signal becomes smaller.

2. The phase synchronization circuit according to claim 1, wherein the feedback circuit is a frequency divider that generates the feedback clock signal by frequency-dividing the output clock signal.

3. The phase synchronization circuit according to claim 2, wherein in the normal operation mode, the frequency divider generates the feedback clock signal by frequency-dividing the output clock signal at a first frequency division ratio, and in the correction mode, the frequency divider generates the feedback clock signal by frequency-dividing the output clock signal at a second frequency division ratio different from the first frequency division ratio.

4. The phase synchronization circuit according to any one of claims 1 to 3, wherein in the normal operation mode, the control voltage generating circuit adjusts the control voltage so that a difference between a phase of the feedback clock signal and a phase of the reference clock signal becomes smaller.

5. The phase synchronization circuit according to claim 1, wherein the control voltage generating circuit has a loop filter that makes a variation of the control voltage slow.

6. The phase synchronization circuit according to claim 1, wherein in the correction mode, the correction code generating circuit adjusts the correction code so that a difference between the frequency of the feedback clock signal and the frequency of the reference clock signal becomes smaller.

7. The phase synchronization circuit according to claim 1, wherein the greater the correction code is, the more the fixed current generating section increases the amount of current of the fixed current. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The adjustment section increases the correction code when the number of pulses of the feedback clock signal is less than the number of pulses of the reference clock signal, and decreases the correction code when the number of pulses of the feedback clock signal is more than the number of pulses of the reference clock signal.

8. The phase synchronization circuit according to claim 1, wherein The greater the correction code, the smaller the fixed current generation section decreases the amount of the fixed current, The adjustment section increases the correction code when the number of pulses of the feedback clock signal is less than the number of pulses of the reference clock signal, and decreases the correction code when the number of pulses of the feedback clock signal is more than the number of pulses of the reference clock signal.

9. The phase synchronization circuit according to claim 7 or 8, wherein For the adjustment section, In the correction mode, the correction code is maintained when the correction code changes from an increase to a decrease, or when the correction code changes from a decrease to an increase, In the normal operation mode, the maintained correction code is output to the fixed current generation section.

10. The phase synchronization circuit according to claim 1, wherein The oscillation circuit has a plurality of buffers that generate an output clock signal at a frequency corresponding to the sum of the amounts of the variable current and the fixed current.

11. The phase synchronization circuit according to claim 10, wherein The plurality of buffers respectively receive differential signals and output differential signals.

12. A transceiver circuit having: a phase synchronization circuit that generates an output clock signal; a transmission circuit which transmits a transmission signal using the output clock signal; and and a reception circuit that receives a reception signal using the output clock signal, The phase synchronization circuit has: an oscillation circuit that includes a variable current generation section that generates a variable current corresponding to an amount of current corresponding to a control voltage, and a fixed current generation section that generates a fixed current corresponding to an amount of current corresponding to a correction code, the oscillation circuit generating the output clock signal at a frequency corresponding to the sum of the amounts of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that, in a normal operation mode, generates the control voltage based on the feedback clock signal and a reference clock signal so that the frequency of the output clock signal becomes a desired frequency; and a correction code generation circuit that, in a correction mode, generates the correction code based on the feedback clock signal and the reference clock signal, In the correction mode, the control voltage generation circuit outputs a fixed control voltage, and the correction code generation circuit adjusts the correction code so that the frequency of the feedback clock signal and the frequency of the reference clock signal become a desired relationship, The correction code generation circuit has: a first counter that counts the number of pulses of the feedback clock signal; a second counter that counts the number of pulses of the reference clock signal; and an adjustment section that adjusts the correction code so that the difference between the number of pulses of the feedback clock signal and the number of pulses of the reference clock signal becomes smaller.

13. A semiconductor integrated circuit, comprising: a transceiver circuit; and an internal circuit that transmits transmission data to the transceiver circuit and receives reception data from the transceiver circuit, the transceiver circuit having: a phase synchronization circuit that generates an output clock signal; and a transmission circuit that transmits a transmission signal based on the transmission data using the output clock signal; and a reception circuit that receives a reception signal using the output clock signal and outputs reception data to the internal circuit, the phase synchronization circuit having: an oscillation circuit that includes a variable current generation section that generates a variable current of an amount of current corresponding to a control voltage and a fixed current generation section that generates a fixed current of an amount of current corresponding to a correction code, and that generates the output clock signal of a frequency corresponding to a total amount of current of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage based on the feedback clock signal and a reference clock signal in a normal operation mode so that the frequency of the output clock signal becomes a desired frequency; and a correction code generation circuit that generates the correction code based on the feedback clock signal and the reference clock signal in a correction mode, in the correction mode, the control voltage generation circuit outputs a fixed control voltage, and the correction code generation circuit adjusts the correction code so that the frequency of the feedback clock signal and the frequency of the reference clock signal become a desired relationship, the correction code generation circuit having: a first counter that counts the number of pulses of the feedback clock signal; a second counter that counts the number of pulses of the reference clock signal; and an adjustment section that adjusts the correction code so that the difference between the number of pulses of the feedback clock signal and the number of pulses of the reference clock signal becomes smaller. ​ ​

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