Semiconductor memory device

Abstract

The semiconductor storage device of one embodiment of the present application can uniformize a program voltage regardless of the number of planes, and thus can shorten a write time. The semiconductor storage device of one embodiment has a plurality of planes including a memory cell array including a plurality of memory cells, a word line, and a bit line; a voltage generation circuit that supplies a program voltage to a selected word line to be written during programming, and that applies a first intermediate voltage to an adjacent word line adjacent to the selected word line during the first half of the programming period and then applies a second intermediate voltage higher than the first intermediate voltage during the second half of the programming period; a discharge circuit provided on a path between the voltage generation circuit and the selected word line, which flows a discharge current from the selected word line during a period corresponding to the period during which the second intermediate voltage is applied to the adjacent word line; and a control circuit that sets a discharge characteristic of the discharge circuit in accordance with the number of planes from which the program voltage is simultaneously supplied by the voltage generation circuit.

Description

[0001] Related Applications

[0002] This application claims priority to Japanese Patent Application No. 2021-45259 (filed on March 18, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] In recent years, semiconductor memory devices such as NAND (Not And) memory have sought to achieve 3D construction due to the requirements of miniaturization and large capacity. Not only are there cases where the memory cell transistors are set as SLC (Single Level Cell) that can store 1 bit (2-value) of data, but there are also cases where they are constructed as MLC (Multi-Level Cell) that can store 2 bits (4-value), TLC (Triple Level Cell) that can store 3 bits (8-value), or QLC (Quad Level Cell) that can store 4 bits (16-value).

[0005] In such semiconductor memory devices, a configuration is sometimes adopted in which multiple physically independent planes are arranged within the memory chip.

[0006] If write operations are performed on multiple planes simultaneously, the write speed may vary depending on the number of planes operating at the same time. Summary of the Invention

[0007] One embodiment of the present invention provides a semiconductor memory device that can uniformize the programming voltage regardless of the number of planes operating simultaneously, thereby shortening the write time.

[0008] One embodiment of a semiconductor memory device includes: a plurality of planes comprising a memory cell array, the memory cell array comprising a plurality of memory cells, word lines connected to the gates of the plurality of memory cells, and bit lines electrically connected to one end of the plurality of memory cells via select gate transistors respectively connected to one end of the plurality of memory cells; a voltage generating circuit capable of generating a voltage supplied to one or more of the memory cell arrays in each of the plurality of planes, and supplying a programming voltage to the select word line to be written during programming, and simultaneously applying a first intermediate voltage to adjacent word lines adjacent to the select word line during the first half of the programming period, and applying a second intermediate voltage higher than the first intermediate voltage during the second half of the programming period; a discharge circuit disposed on the path between the voltage generating circuit and the select word line, and flowing a discharge current from the select word line during a period corresponding to the period during which the second intermediate voltage is applied to the adjacent word line; and a control circuit that sets the discharge characteristics of the discharge circuit according to the number of planes from which the programming voltage is simultaneously supplied from the voltage generating circuit. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a configuration example of a memory system related to the first embodiment.

[0010] Figure 2 This is a block diagram illustrating a configuration example of the non-volatile memory of the first embodiment.

[0011] Figure 3 It means Figure 2 A block diagram illustrating a specific example of the multiple planes within the structure.

[0012] Figure 4A This is a diagram showing the equivalent circuit of a block of a 3D constructed NAND memory cell array 23.

[0013] Figure 4B This is a diagram illustrating an example of the structure of a block of a 3D NAND memory cell array 23.

[0014] Figure 5 It is a graph showing the potential changes of each wire during the write operation (programming operation).

[0015] Figure 6 This is a graph representing the threshold voltage distribution of the memory cell array.

[0016] Figure 7 This is an explanatory diagram showing the standard write sequence for write operations.

[0017] Figure 8 It indicates composition Figure 2 or Figure 3A block diagram illustrating an example of the specific configuration of the VPGM generation circuit 40 in the voltage generation circuit 28.

[0018] Figure 9 It means Figure 8 The circuit diagram shows an example of the specific configuration of the charge pump circuit 41 in the circuit.

[0019] Figure 10 It is a graph with time on the horizontal axis and voltage on the vertical axis, used to illustrate the floating potential of the programming voltage VPGM.

[0020] Figure 11 This is a circuit diagram illustrating an example of the specific configuration of the voltage generating circuit 28, which includes the discharge circuit 50, and the MUX switch 29.

[0021] Figure 12 This is a block diagram illustrating an example of the specific configuration of TS30 and line decoder 25.

[0022] Figure 13 This is an explanatory diagram used to illustrate the discharge action during VPASS_SHIFT.

[0023] Figure 14 This is a block diagram illustrating a configuration example of the non-volatile memory in the second embodiment.

[0024] Figure 15 It means Figure 14 A block diagram illustrating a specific example of the multiple planes within the structure.

[0025] Figure 16 This is a block diagram illustrating the third embodiment of the present invention.

[0026] Figure 17 This is an explanatory diagram used to illustrate the effects of the first embodiment. Detailed Implementation

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0028] (First Embodiment)

[0029] This embodiment controls the programming voltage supplied to each plane in accordance with the control of VPASS_SHIFT described later. Regardless of the number of planes operating simultaneously, it aims to uniformize the supplied programming voltage, thereby shortening the write time.

[0030] (The structure of a memory system)

[0031] Figure 1This is a block diagram illustrating an example configuration of a memory system related to an implementation embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a portable terminal.

[0032] Non-volatile memory 2 is a semiconductor storage device that stores data non-volatilely, such as a NAND flash memory. In this embodiment, non-volatile memory 2 is described as a NAND flash memory having a storage cell transistor capable of storing 4 bits per transistor, that is, a 4-bit / cell (QLC: Quad Level Cell) NAND flash memory, but it is not limited thereto. Non-volatile memory 2 is 3-dimensional.

[0033] The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Furthermore, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0034] The host interface 13 outputs requests received from the host, user data (i.e., write data), etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0035] The memory interface 15 controls, based on instructions from the processor 12, the processes of writing user data, etc., to the non-volatile memory 2 and reading user data, etc., from the non-volatile memory 2.

[0036] Processor 12 provides unified control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from the host via host interface 13, processor 12 performs control according to the request. For example, upon a request from the host, processor 12 instructs memory interface 15 to write user data and parity checks to non-volatile memory 2. Furthermore, upon a request from the host, processor 12 instructs memory interface 15 to read user data and parity checks from non-volatile memory 2.

[0037] Processor 12 determines the storage area (hereinafter referred to as memory area) on non-volatile memory 2 based on the user data accumulated in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory area for data written in units of pages, i.e., page data. In this specification, user data stored in one page of non-volatile memory 2 is defined as cell data. Cell data is encoded and stored as codewords in non-volatile memory 2, for example.

[0038] Furthermore, encoding is not mandatory. The memory controller 1 can also store the cell data in non-volatile memory 2 without encoding, but... Figure 1 In the example shown, the encoding configuration is used as an example. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Furthermore, a codeword can be generated based on one cell data, or a codeword can be generated based on segmented data of segmented cell data. Alternatively, a codeword can be generated using multiple cell data.

[0039] Processor 12 determines the memory region of the non-volatile memory 2 to be written to based on the data in each cell. It allocates physical addresses to the memory regions of the non-volatile memory 2. Processor 12 manages the memory regions of the cells to be written using these physical addresses. Processor 12 instructs memory interface 15 to write user data to the non-volatile memory 2 using the physical addresses of the determined memory regions. Processor 12 manages the mapping between logical addresses (logical addresses managed by the host) and physical addresses of user data. When processor 12 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address, instructs memory interface 15 to read the user data.

[0040] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Furthermore, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0041] RAM 11 temporarily stores user data received from the host until it is stored in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 until it is sent to the host. RAM 11 is, for example, general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0042] Figure 1The diagram shows an example configuration where the memory controller 1 includes both an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Furthermore, the ECC circuit 14 can also be integrated into the non-volatile memory 2.

[0043] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and sends the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0044] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 sends the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0045] (A rough outline of the structure of a non-volatile memory)

[0046] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. Furthermore, Figure 3 It means Figure 2 A block diagram illustrating a specific example of the multiple planes within the structure.

[0047] The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a register 26, a sequence generator 27, a voltage generation circuit 28, a MUX switch 29, input / output pad groups 32, logic control pad groups 34, power input terminal groups 35, and multiple planes PB0, PB1, ... (hereinafter, without distinguishing between these planes PB0, PB1, ..., they are referred to as planes PB). Furthermore... Figure 2 In the example shown, the number of planes in plane PB is 4, but the number of planes in non-volatile memory 2 is not limited to this. For example, the number of planes in non-volatile memory 2 can also be 2, 3, 8, 16, etc.

[0048] In order to transmit and receive signals containing data with the memory controller 1, the input / output pad group 32 has multiple terminals (pads) corresponding to the signal DQ<7:0> and the data strobe signals DQS and / DQS.

[0049] In order to transmit and receive various signals with the memory controller 1, the logic control pad group 34 has multiple terminals (pads) corresponding to the chip start signal / CE, instruction latch start signal CLE, address latch start signal ALE, write start signal / WE, read start signal RE, / RE, write protection signal / WP and signal R / B.

[0050] The / CE signal selects non-volatile memory 2. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The / WE signal enables writing. The RE and / RE signals enable reading. The / WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). Memory controller 1 can determine the status of non-volatile memory 2 by receiving the R / B signal.

[0051] To supply various operating power sources to the non-volatile memory 2 from an external source, the power input terminal group 35 has multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage typically applied externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, for example, a voltage of 12V.

[0052] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0053] The logic control circuit 21 receives external control signals (e.g., latch start signal / CE, instruction latch start signal CLE, address latch start signal ALE, write start signal / WE, read start signal RE, / RE, and write protect signal / WP) from the memory controller 1 via the NAND bus. The " / " in the signal name indicates active low. Furthermore, the logic control circuit 21 sends a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0054] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the non-volatile memory 2. Register 26 is constructed, for example, from SRAM.

[0055] The sequence generator 27, which serves as the control circuit, receives instructions from the register 26 and controls the non-volatile memory 2 in sequence based on the instructions.

[0056] The voltage generation circuit 28 receives a power supply voltage from outside the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltage to the memory cell array 23, sense amplifier 24, and row decoder 25 within the planar PB via the MUX switch 29.

[0057] Each plane PB has a memory cell array 23. The memory cell array 23 has multiple blocks. Each block BLK has multiple memory cell transistors (memory cells). In order to control the voltage applied to the memory cell transistors, multiple bit lines, multiple word lines, and source lines are provided in the memory cell array 23.

[0058] (Block structure of a memory cell array)

[0059] Figure 4A This is a diagram showing the equivalent circuit of the block BLK of the NAND memory cell array 23, which is a 3D structure of the non-volatile memory 2 in this embodiment. Figure 4A This represents one block BLK among the multiple blocks constituting the storage cell array 23. The other blocks in the storage cell array also have the same... Figure 4A The same structure. Furthermore, this embodiment can also be applied to 2D memory cell arrays.

[0060] As shown in the figure, block BLK contains, for example, four string cells (SU0 to SU3). Furthermore, each string cell SU contains multiple NAND strings NS. Here, each NAND string NS contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. However, the number of memory cell transistors MT in each NAND string NS is eight, but not limited to eight; it could also be, for example, 32, 48, 64, or 96. Select gate transistors ST1 and ST2 are represented as one transistor in the circuit, but their construction can be the same as the memory cell transistors. Furthermore, for example, to improve cutoff characteristics, multiple select gate transistors can be used as select gate transistors ST1 and ST2. Additionally, dummy cell transistors can be placed between the memory cell transistors MT and the select gate transistors ST1 and ST2.

[0061] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to the select gate transistor ST2.

[0062] The gates of the select gate transistors ST1 for each of the serial cells SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3 (hereinafter, without distinction, they are referred to as select gate lines SGD). On the other hand, the gates of the select gate transistors ST2 are connected to the same select gate line SGS among multiple serial cells SU within the same block BLK. Furthermore, the gates of the memory cell transistors MT0 to MT7 within the same block BLK are respectively connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate lines SGS are connected together among multiple serial cells SU0 to SU3 within the same block BLK, while the select gate line SGD is independent of each serial cell SU0 to SU3, even within the same block BLK.

[0063] The gates of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi located in the same row within block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS may be simply referred to as "string".

[0064] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST or other memory cell transistor MT contained in the NAND string NS. As described above, the data of the memory cell transistor MTs within the same block BLK is erased uniformly. On the other hand, data reading and writing are performed in memory cell group MG units (or page units). In this specification, multiple memory cell transistors MTs connected to one word line WLi and belonging to one string unit SU are defined as a memory cell group MG. In this embodiment, the non-volatile memory 2 is a QLC NAND memory capable of storing 4 bits (16 values) of data. Therefore, one memory cell group MG can store 4 pages of data. The 4 bits that can be stored by each memory cell transistor MT correspond to the 4 pages respectively.

[0065] Figure 4B This is a diagram illustrating an example of the block BLK configuration of the NAND memory cell array 23, which is a 3D structure of the non-volatile memory 2 in this embodiment. Figure 4B This represents one block BLK among the multiple blocks constituting the storage cell array 23. The other blocks in the storage cell array also have the same... Figure 4B Same composition.

[0066] More specifically, Figure 4B This is a partial cross-sectional view of the block BLK of the NAND memory cell array 23 of the non-volatile memory 2 in this embodiment. (See attached image.) Figure 4BAs shown, transistors, such as those contained in peripheral circuits like the sense amplifier 24 or the row decoder 25, are formed on the semiconductor substrate 601, and memory cell transistors, contained in the memory cell array 23, are formed on top of it. In the following description, the two directions orthogonal to the surface of the semiconductor substrate 601 are designated as the x-direction and the y-direction, and the direction perpendicular to the surface of the semiconductor substrate 601 is designated as the z-direction.

[0067] Figure 4B The p-type or n-type well regions formed on the upper surface of the semiconductor substrate 601, the impurity diffusion regions formed in each well region, and the element separation regions that insulate between the well regions are not shown in the diagram. A conductor GC is disposed on the semiconductor substrate 601 as a gate insulating film (not shown). Furthermore, multiple contacts 661 are provided in multiple impurity diffusion regions (not shown) of the semiconductor substrate 601, sandwiching the conductor GC. Multiple conductors 641, which are wiring patterns, are connected to each of the multiple contacts 661. For example, the conductor GC functions as the gate electrode of a transistor, and the conductors 641 function as the source electrode or drain electrode of a transistor.

[0068] For example, a contact 662 is provided on conductor 641, and conductor 642, which serves as a wiring pattern, is connected to contact 662. A contact 663 is provided on conductor 642, and conductor 643, which serves as a wiring pattern, is connected to contact 663. The wiring layers on which conductors 641, 642, and 643 are provided are referred to as wiring layers D0, D1, and D2, respectively. Wiring layers D0, D1, and D2 are provided in the lower part of the non-volatile memory 2. Furthermore, the wiring layers provided in the lower part of the non-volatile memory 2 are not limited to three layers. It may consist of two or fewer wiring layers, or it may consist of four or more wiring layers.

[0069] Above conductor 643, conductor 644 is disposed with a dielectric, such as an interlayer insulating film (not shown). Conductor 644 is formed into a plate shape, for example, parallel to the xy plane, and functions as a source line SL. Above conductor 644, conductors 645 to 654 are sequentially deposited in the z direction, for example with an interlayer insulating film (not shown).

[0070] Conductors 645 to 654 are each formed as, for example, a plate parallel to the xy plane. For example, conductor 645 functions as the select gate line SGS, conductors 646 to 653 function as word lines WL0 to WL7 respectively, and conductor 654 functions as the select gate line SGD.

[0071] A columnar memory pillar 634 is provided in such a way that it contacts each of the conductors 645-654. The memory pillar 634 includes, for example, a centrally located conductor pillar 638; a channel insulating film 637 formed on the outside of the conductor pillar 638; a charge accumulation film 636 formed on the outside of the channel insulating film 637; and a block insulating film 635 formed on the outside of the charge accumulation film 636. The portions of the memory pillar 634 that intersect with each of the conductors 646-654 function as memory cell transistors (MTs). Furthermore, the portions of the memory pillar 634 that intersect with each of the conductors 645 and 654 function as select transistors (STs).

[0072] Above the upper surface of the memory cylinder 634, a conductor 655 is disposed on an interlayer insulating film (not shown). The conductor 655 is formed as a line extending in the x-direction and functions as a bit line BL. A plurality of conductors 655 are arranged at open intervals in the y-direction. The conductors 655 are electrically connected to the conductor cylinder 638 in one memory cylinder 634 corresponding to each string cell SU via contact plugs CP.

[0073] Specifically, in each string unit SU, for example, a contact plug CP is provided on the conductive post 638 within each memory hole 634, and a conductor 645 is provided on the contact plug CP. Furthermore, not limited to this configuration, for example, the conductive post 638 and the conductor 645 may be further connected via multiple contacts or wiring.

[0074] Above the layer where the conductor 655 is disposed, an interlayer insulating film (not shown) is provided with a conductor 656. Above the layer where the conductor 656 is disposed, an interlayer insulating film (not shown) is provided with a conductor 657.

[0075] Conductors 656 and 657 function as wiring, for example, to connect the wiring disposed in the memory cell array 23 to the wiring of the peripheral circuitry disposed in the lower layer of the memory cell array 23. The layers on which conductors 655, 656, and 657 are disposed are referred to as wiring layers M0, M1, and M2, respectively.

[0076] Figure 3 The planes PB0 to PB3 shown are identical in configuration. Each plane PB has a memory cell array 23, a sense amplifier 24, a row decoder 25, and a plane decoder (hereinafter referred to as TS) 30.

[0077] The row decoder 25 receives the row address from the register 26 and decodes the row address. Based on the decoded row address, the row decoder 25 performs word line selection. Furthermore, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0078] The sense amplifier 24 receives the column address from the register 26 and decodes the column address. The sense amplifier 24 has a group of sense amplifier units 24A connected to each bit line, which selects any bit line based on the decoded column address. Furthermore, during data readout, the sense amplifier unit group 24A detects and amplifies the data read from the memory cell transistor to the bit line. Additionally, during data writeout, the sense amplifier unit group 24A transmits the written data to the bit line.

[0079] The sensing amplifier 24 has a data register 24B. When data is read out, the data register 24B temporarily stores the data detected by the sensing amplifier group 24A and serially transmits it to the input / output circuit 22. Furthermore, when data is written, the data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits the data to the sensing amplifier unit group 24A. The data register 24B is composed of SRAM or the like.

[0080] The voltage generation circuit 28 generates the voltages used for writing and reading from the memory cell array 23, the sense amplifier 24, and the row decoder 25. In other words, the voltage generation circuit 28 generates various voltages required for writing, reading, and erasing, and outputs these voltages to the MUX switch 29. The MUX switch 29 switches which wiring is supplied with the various voltages generated by the voltage generation circuit 28 according to the writing and reading sequence.

[0081] (Write action)

[0082] The process of writing data to a memory cell MT generally includes programming and verification. Programming involves injecting electrons into the charge accumulation film to raise the threshold voltage of the memory cell MT (or maintaining the threshold voltage by disabling electron injection).

[0083] Figure 5 This is a diagram showing the potential changes of each wire during the write operation (programming operation). Voltage generation circuit 28 generates... Figure 5 The various voltages shown, the MUX switch 29 is controlled by the sequence generator 27, will Figure 5 The various voltages shown are assigned to each wiring.

[0084] Programming operations are performed according to the programming voltages and bit line voltages applied to the word lines and bit lines. For example... Figure 5 As shown, the character line is not aligned ( Figure 5 The block BLK for which the programming voltage VPGM is applied (selected WL, non-selected WL) is the non-selected BLK that is not the object to be written. Figure 5(Next paragraph). Furthermore, since the bit line voltage is applied to the memory cell transistor MT by turning on the select gate transistor ST1 connected to the bit line BL, the string cells SU in the block BLK (select block BLK) that are not subject to the select gate line SGD are non-selected SUs that are not intended for writing. Figure 5 (Middle section). Also, regarding the non-selection of SU when choosing BLK ( Figure 5 Alternatively, before applying the programming voltage VPGM, the select gate line SGD can be set to, for example, 5V, to turn on the select gate transistor ST1.

[0085] Regarding the block BLK (select BLK) of the written object, the string unit SU (select SU) of the written object (select SU) Figure 5 (Upper section), before applying the programming voltage VPGM, such as Figure 5 As shown on the left side of the upper section, the select gate line SGD is set to, for example, 5V, turning on the select gate transistor ST1. Furthermore, during programming, the select gate line SGS is, for example, 0V. Therefore, the select gate transistor ST2 is in the off state. On the other hand, applying... Figure 5 When the programming voltage VPGM is shown on the right side of the upper section, the select gate line SGD is set to, for example, 2.5V. Therefore, the on / off state of the select gate transistor ST1 is determined by the bit line voltage connected to the bit line BL of the select gate transistor ST1.

[0086] As described above, the sense amplifier 24 transmits data to each bit line BL. For the bit line BL given a "0" data, a ground voltage Vss of, for example, 0V is applied as the bit line voltage Vbl_L. For the bit line BL given a "1" data, a write inhibit voltage Vinhibit (e.g., 2.5V) is applied as the bit line voltage Vbl_H. Therefore, when the programming voltage VPGM is applied, the select gate transistor ST1 connected to the bit line BL given a "0" data is turned on, and the select gate transistor ST1 connected to the bit line BL given a "0" data is turned off. The memory cell transistor MT connected to the turned-off select gate transistor ST1 is disabled from writing.

[0087] The memory cell transistor MT connected to the select gate transistor ST1, which is in the ON state, injects electrons into the charge accumulation film according to the voltage applied to the word line WL. The memory cell transistor MT connected to the word line WL (non-select WL), where the word line voltage VPASS is applied, is in the ON state regardless of the threshold voltage, but does not inject electrons into the charge accumulation film. On the other hand, the memory cell transistor MT connected to the word line WL (select WL), where the word line voltage VPGM is applied, injects electrons into the charge accumulation film according to the programming voltage VPGM.

[0088] In other words, the row decoder 25 selects any word line WL in the select block BLK, applies a programming voltage VPGM to the selected word line (select WL), and applies a first intermediate voltage, namely voltage VPASS, to the other word lines (non-selected word lines) WL. The programming voltage VPGM is a high voltage used to inject electrons into the charge accumulation film through tunneling, and VPGM > VPASS. The row decoder 25 controls the voltage of the word line WL, and the sense amplifier 24 supplies data to each word line BL, thereby performing the writing operation (programming operation) on each memory cell transistor MT of the memory cell array 23.

[0089] (VPASS_SHIFT)

[0090] However, to suppress the decrease in the programming voltage VPGM applied to the channel, sometimes during the latter half of the programming voltage application period, the voltage VPASS applied to the non-select word line adjacent to the select word line (hereinafter referred to as the adjacent word line) is increased to the second intermediate voltage, namely VPASS_SHIFT. By changing the voltage of the adjacent word line from VPASS to VPASS_SHIFT, for example, increasing the programming voltage VPGM of the select word line, programming efficiency is improved, while the channel potential of the NAND string NS to which the non-write target memory cell transistor MT belongs is increased, thereby suppressing interference.

[0091] Furthermore, the channels of non-select SUs are floating. Therefore, when a high voltage VPGM is applied to the select word line, the channel potential of the non-select SU also rises, so normally no writing is performed on the memory cell transistor MT of the non-select SU. However, if the channel voltage of the non-select SU drops due to charge leakage, there is a concern that the application of the programming voltage VPGM might also result in erroneous writing to the memory cell transistor MT of the non-select SU. Therefore, by increasing the voltage of the adjacent word line from VPASS to the voltage VPASS_SHIFT, the channel voltage of the non-select SU is increased, preventing writing to the memory cell transistor MT of the non-select SU. In other words, VPASS_SHIFT also has the function of preventing interference (erroneous writing caused by unintentional rise in threshold voltage).

[0092] (Threshold voltage distribution)

[0093] When writing multi-valued data to a memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to the value corresponding to the data value. If a programming voltage VPGM and a bit line voltage Vbl are applied to the memory cell transistor MT, electrons are injected into the charge accumulation film of the memory cell transistor MT, and the threshold voltage rises. By increasing the programming voltage VPGM, the amount of electron injection can be increased, thus raising the threshold voltage of the memory cell transistor MT. However, due to variations in the memory cell transistor MT, even when the same programming voltage VPGM is applied, the amount of electron injection in each memory cell transistor MT is different. The temporarily injected electrons are retained until an erase operation is performed. Therefore, to ensure that the threshold voltage set for each memory cell transistor MT falls within the allowable threshold voltage range, the programming voltage VPGM is gradually increased, and multiple programming and verification operations (loops) are performed. The verification operation is a read operation performed as part of the write operation.

[0094] Figure 6 This is a graph representing the threshold voltage distribution of the memory cell array. Figure 6 The diagram illustrates an example of the threshold voltage distribution in a 4-bit / cell non-volatile memory 2. In the non-volatile memory 2, the threshold voltage of the memory cell MT is set based on the data values ​​of the multi-value data stored in the memory cell MT. Since the amount of charge injected into the charge accumulation film (charge storage region) is random, as shown... Figure 6 As shown, the threshold voltage of each memory cell MT also exhibits a statistical distribution.

[0095] Figure 6 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of storage cells (cells). This represents the 16 mountain-shaped threshold voltage distributions corresponding to the 16 states (states Er, S1 to S15) that correspond to the 4-bit 16-value. Figure 6 In the example, by setting the threshold voltage of the storage cell MT to any one of the 16 threshold distributions corresponding to the 16 states, 16-value data (4-bit data) can be stored in the storage cell MT.

[0096] The threshold voltage Vth is Figure 6 The threshold voltage distribution below voltage Vr1 corresponds to state Er; the threshold voltage distribution above voltage Vth but below voltage Vr2 corresponds to state S1; the threshold voltage distribution below voltage Vth but below voltage Vr2 corresponds to state S2; and the threshold voltage distribution below voltage Vth but below voltage Vr4 corresponds to state S3. Similarly, as follows... Figure 6 As shown, the distribution of each threshold voltage corresponds to states S4 to S15.

[0097] In other words, the state represents the threshold voltage Vth of each memory cell MT. In the case of a 4-bit 16-value system, the threshold voltage Vth of each memory cell MT is set to any one of the 16 threshold voltage distributions corresponding to the 16 states Er and S1 to S15. Voltages Vr1 to Vr15 are reference voltages that form the boundaries of each of the 16 threshold voltage distributions. Furthermore, during the verification process, voltages Vr1 to Vr15 are applied as verification voltages to the word line WL and read out. The target memory cell MT is then disconnected, and it is determined that the threshold voltage corresponding to the state has been reached.

[0098] Figure 7 This is an explanatory diagram showing the standard write sequence for write operations. Figure 7 The horizontal axis represents time, and the vertical axis represents voltage, indicating the change in the programming voltage VPGM, the timing of programming actions, and the timing of verification actions during a write operation based on the standard write sequence.

[0099] Figure 7 This indicates the writing order of planes PB1 to PB3. Figure 7 The slash represents the change in the programming voltage VPGM during writing. In other words, Figure 7 This example illustrates the write sequence for 19 cycles of writing, where the programming voltage VPGM changes 19 times. The write sequence for each plane PB is synchronized.

[0100] like Figure 7 As shown, in the standard write sequence, the programming voltage VPGM applied to the select word line WL is increased sequentially in each loop. Furthermore, in each loop, a verification operation is performed on at least one state to determine whether the threshold voltage Vth of each memory cell MT in the write result has reached a value higher than the verification voltage. Figure 7 In the example, the program ultimately loops a maximum of 19 times, performing 19 programming actions and 42 verification actions.

[0101] (Voltage generation circuit)

[0102] Figure 8 It indicates composition Figure 2 or Figure 3 A block diagram illustrating an example of the specific configuration of the VPGM generation circuit 40 within the voltage generation circuit 28. Figure 9 It means Figure 8 The circuit diagram shows an example of the specific configuration of the charge pump circuit 41 in the circuit.

[0103] The block control circuit 42 generates a clock signal CLK and its inverted signal, / CLK. The clock control circuit 42 supplies the complementary clock signals CLK and / CLK to the charge pump circuit 41. The charge pump circuit 41 uses the clock signals CLK and / CLK supplied from the clock control circuit 42 to generate a specific voltage VOUT.

[0104] like Figure 9 As shown, the charge pump circuit 41 includes n+1 NMOS transistors NM1, NM2, ..., NMn, NMn+1 and n capacitors C1 to Cn. Furthermore, the number n of the NMOS transistors and capacitors in the charge pump circuit 41 can be appropriately set.

[0105] NMOS transistors NM1 through NMn+1 are connected as diodes, functioning as diodes. The current paths of NMOS transistors NM1 through NMn+1 are connected in series sequentially. One end of capacitors C1 through Cn is electrically connected to one end of the current path output side of NMOS transistors NM1 through NMn. The other end of capacitors C1, C3, C5, ... is supplied with the clock signal CLK, and the other end of capacitors C2, C4, C6, ... is supplied with the clock signal / CLK.

[0106] A voltage VSUP (e.g., power supply voltage VDD) is supplied to one end of the current path input side of NMOS transistor NM1. Furthermore, capacitors C1 to Cn are repeatedly charged and discharged using clock signals CLK and / CLK, for example, with an amplitude equal to the power supply voltage VDD, thereby boosting the input voltage VSUP and sequentially transmitting it to the next stage. As a result, an output voltage VOUT greater than VSUP is generated on the current path output side of transistor NMn+1.

[0107] The charge pump circuit 41 can generate different voltage levels at each stage of the diode-connected NMOS transistor. The voltage generation circuit 28 generates the various voltages required for writing and reading from the output of the charge pump circuit 41.

[0108] Figure 8 In the diagram, VPGM generation circuit 40, which uses the output of charge pump circuit 41 to generate the programming voltage VPGM, is represented among the circuits constituting voltage generation circuit 28. The output VOUT of charge pump circuit 41 is supplied as voltage VGMMH to output circuit 43. Output circuit 43 connects two PMOS transistors PM1 and PM2, connected in series via current paths, between the power supply line supplying voltage VGMMH and output node N. The source and gate of transistor PM1 are connected to the power supply line. The source and gate of type I transistor PM2 are connected to the drain of transistor PM1, and the drain is connected to output node N.

[0109] Between the output node N and the reference potential point, the current path of NMOS transistor NM11, resistor R1, variable resistor R2, and the current path of NMOS transistor NM12 are connected in series. The connection point of resistors R1 and R2 is connected to one input terminal of comparator 44. A reference voltage VREF is applied to the other input terminal of comparator 44. During the period when the voltage at the connection point of resistors R1 and R2 is higher than the reference voltage VREF, comparator 44 outputs a stop signal to clock control circuit 42. During the period when clock control circuit 42 outputs the stop signal from comparator 44, it stops generating clock signals CLK and / CLK. Transistors NM11 and NM12, resistors R1 and R2, and comparator 44 constitute a limiting circuit.

[0110] Transistors PM1 and PM2 are both diode-connected. The voltage VPGMH supplied to the output circuit 43 reduces the threshold voltage of transistors PM1 and PM2 by a certain amount, appearing at the output node N. By setting a voltage VPGMH that is higher than the threshold voltage of transistors PM1 and PM2 by a certain amount compared to the programming voltage VPGM, the programming voltage VPGM can be generated from the output node N.

[0111] Transistors NM11 and NM12 are turned on when a control signal (not shown) is supplied from sequence generator 27, enabling the limiting circuit to function. During the on-time of transistors NM11 and NM12, the voltage at output node N is divided by resistors R1 and R2. The voltage at the junction of resistors R1 and R2 is compared with a reference voltage VREF in comparator 44. The reference voltage VREF is set to the voltage at the junction of resistors R1 and R2 when the voltage at output node N is the specified programming voltage VPGM. Therefore, if the voltage at the output node exceeds the specified programming voltage VPGM, the voltage at the junction of resistors R1 and R2 is higher than the reference voltage VREF, and a stop signal is generated from comparator 44. Based on the stop signal, clock control circuit 42 stops generating clock signals CLK and / CLK. As a result, the output voltage of charge pump circuit 41 decreases, suppressing the voltage rise at output node N, and maintaining the voltage at output node N at the specified programming voltage VPGM.

[0112] (Floating potential)

[0113] However, to suppress increased power consumption, resistors R1 and R2 are set to sufficiently large values ​​to reduce the current flowing from output node N to the reference potential. Therefore, in multi-plane operations involving multiple planes, a floating potential is generated in the programming voltage VPGM, resulting in longer write times.

[0114] Figure 10 It is a graph with time on the horizontal axis and voltage on the vertical axis, used to illustrate the floating potential of the programming voltage VPGM.Figure 10 It means Figure 2 In the configuration shown, the waveforms (thin solid lines) of the voltage applied to the selection word line (WLn) during single-plane programming and the waveforms (thick solid lines) of the voltage applied to the selection word line (WLn) during four-plane programming are illustrated. The thin solid lines largely overlap with the thick solid lines, except for the portion enclosed by the dashed box. Furthermore, the waveforms (dashed lines) of the voltage applied to adjacent word lines (WLn±1) are approximately the same in both the single-plane and four-plane programming scenarios.

[0115] like Figure 10 As shown by the dashed line, in adjacent word lines (WLn±1), VPASS is converted to VPASS_SHIFT. By increasing the voltage applied to VPASS_SHIFT, as shown by the thick solid line, the programming voltage VPGM for selecting the word line increases.

[0116] When the programming voltage VPGM exceeds the expected voltage by using VPASS_SHIFT, the limiting circuit of the VPGM generation circuit 40 operates during programming operations targeting a single plane. A small amount of discharge is performed from the selection word line of the single plane through TS30, MUX switch 29, and the output node N of the VPGM generation circuit 40 in the voltage generation circuit 28 to the reference potential point. As a result, the potential of the selection word line (WLn) is stabilized at the programming voltage VPGM.

[0117] In contrast, in the case of multi-plane operation, after the programming voltage VPGM of the select word line (WLn) increases through the VPASS of the adjacent word lines (WLn±1) by rising to PVASS_SHIFT, even if the programming voltage VPGM exceeds the originally set voltage value, as mentioned above, the discharge amount of the limiting circuit in the VPGM generation circuit 40 is relatively small. Therefore, even if the selection word lines from the four planes PB0 to PB3 discharge through each TS30, through the output node N of the VPGM generation circuit 40 in the MUX switch 29 and voltage generation circuit 28, the discharge amount is still relatively small. Figure 10 As shown by the thin solid line, the voltage of the select word line (WLn) cannot be sufficiently reduced to the programming voltage VPGM. As a result, the following occurs: Figure 10 The floating potential is indicated by the area enclosed by the dashed box. Furthermore, the state of the floating potential varies depending on the number of simultaneously operating planes.

[0118] In other words, the programming voltage VPGM varies depending on the number of planes operating simultaneously, causing deviations that affect the number of program loops. Thus, in the case of multiple planes operating simultaneously, this results in a longer write time.

[0119] (constitute)

[0120] Therefore, in this embodiment, by setting up a discharge circuit to reduce the programming voltage VPGM, and controlling the discharge circuit according to VPASS_SHIFT, the uniformity of the programming voltage VPGM is sought regardless of the number of planes operating simultaneously.

[0121] Figure 11 This is a circuit diagram illustrating an example of the specific configuration of the voltage generating circuit 28, which includes the discharge circuit 50, and the MUX switch 29. Figure 11 This only refers to the VPGM generation circuit 40, VPASS generation circuit 45, and VPASS2 generation circuit 46 in the circuits constituting the voltage generation circuit 28, and the circuits constituting the MUX switch 29 that are related to... Figure 11 The circuit portion corresponding to the voltage generation circuit 28 shown.

[0122] In voltage generation circuit 28, in addition to VPGM generation circuit 40, VPASS generation circuit 45 and VPASS2 generation circuit 46 are also configured. VPASS generation circuit 45 and VPASS2 generation circuit 46 have the same configuration as VPGM generation circuit 40, and generate voltage VPASS and voltage VPASS_SHIFT respectively.

[0123] MUX switch 29 has multiple switches T01-T03, T11-T13, ..., T71-T73, all composed of transistors. The programming voltage VPGM from VPGM generation circuit 40 is supplied to switches T01, T11, ..., T71; the voltage VPASS from VPASS generation circuit 45 is supplied to switches T02, T12, ..., T72; and the voltage VPSS_SHIFT from VPASS2 generation circuit 46 is supplied to switches T03, T13, ..., T73. Switches T01-T03, T11-T13, ..., and T71-T73 are respectively connected to signal lines CG0, CG1, ..., CG7.

[0124] Switches T01~T03, switches T11~T13, ... and switches T71~T73 are controlled by timing generator 27, which supplies programming voltages VPGM, VPASS, and VPASS_SHIFT to signal lines CG0~CG7.

[0125] In this embodiment, the wiring connecting the VPGM generation circuit 40 to switches T01, T11, ..., T71, i.e., the wiring connected to the output node N, is connected to the discharge circuit 50. The discharge circuit 50 consists of a variable resistor R3 connected in series between the output node N and the reference potential point and an NMOS transistor NM13. The drain of transistor NM13 is connected to the variable resistor R3, and the source is connected to the reference potential point. A control signal from the timing generator 27 (not shown) is input to the gate. Transistor NM13 is controlled to be turned on and off by the timing generator 27. For example, transistor NM13 can also be set to be turned on during the period when VPASS_SHIFT is applied to the adjacent word line (hereinafter referred to as the VPASS_SHIFT period).

[0126] In this embodiment, the resistance value of the variable resistor R3 is also controlled by the timing generator 27. The timing generator 27 changes the resistance value of the variable resistor R3 according to, for example, the number of simultaneously operating planes. For example, the more simultaneously operating planes there are, the smaller the resistance value of the variable resistor R3 is made by the timing generator 27; the fewer simultaneously operating planes there are, the larger the resistance value of the variable resistor R3 is made. Thus, when the number of simultaneously operating planes is large, the discharge current of the discharge circuit 50 is increased, suppressing the floating potential of the programming voltage VPGM; when the number of simultaneously operating planes is small, the discharge current of the discharge circuit 50 is reduced, suppressing power consumption.

[0127] in addition, Figure 11 The example shown depicts a discharge circuit 50 composed of a variable resistor R3 and a transistor NM13. However, it can also be configured as a series circuit with multiple resistors and switches connected in parallel between the output node N and the reference potential point. The resistance values ​​of these parallel resistors are set to different resistance values ​​corresponding to the number of simultaneously operating planes. In this case, by selectively turning on the switches using the timing generator 27, resistors with different resistance values ​​can be selectively connected between the output node N and the reference potential point. Alternatively, the timing generator 27 can also be configured to vary the number of resistors with the same or different resistance values ​​connected between the output node N and the reference potential point, depending on the number of simultaneously operating planes.

[0128] in addition, Figure 11 The example shown is that the discharge circuit 50 is set in the voltage generation circuit 28, but the discharge circuit 50 can also be set on any path from the output node N of the VPGM generation circuit 40 to the input terminal of the TS30.

[0129] Figure 12 This is a block diagram illustrating an example of the specific configuration of TS30 and line decoder 25, and explaining the wiring path from voltage generation circuit 28 to word lines.

[0130] As described above, the voltage generation circuit 28 generates various voltages, including those required for programming and reading operations of the memory cell transistor MT. Specifically, the voltage generation circuit 28 includes circuits supplying voltage to signal lines SG0-SG4 (not shown), and the VPGM generation circuit 40, VPASS generation circuit 45, and VPASS2 generation circuit 46 supplying voltage to signal lines CG0-CG7 respectively. The various voltages from the voltage generation circuit 28 are then supplied to the MUX switch 29.

[0131] Figure 12 In the middle, the MUX switch 29 has a structure composed of... Figure 11 Multiple switch circuits 29B are formed by switches T01~T03, switches T11~T13, ..., switches T71~T73. The switch circuits 29B are supplied with voltages from the voltage generation circuit 28 to the word lines WL0~WL7, and output these voltages to the signal lines CG0~CG7 according to the control of the sequence generator 27.

[0132] Furthermore, the MUX switch 29 has switch circuits 29A and 29C with the same configuration as switch circuit 29B. Switch circuit 29A receives a voltage from voltage generation circuit 28 supplied to the select gate line SGS, and outputs the voltage to the SGS signal line under the control of sequence generator 27. Switch circuit 29C receives a voltage from voltage generation circuit 28 supplied to the select gate lines SGD0 to SGD3, and outputs these voltages to signal lines SG0 to SG3 under the control of sequence generator 27.

[0133] These signal lines SG0-SG4 and CG0-CG7 are connected to the signal lines SG0-SG4 and CG0-CG7 on each plane PB through each plane decoder (TS) 30 constituting the plane decoder group 31. Each TS 30 is composed of a transmission control circuit 30A and a switching circuit group 30B. The switching circuit group 30B has switches TR_PSG0-TR_PSG4 and TR_PCG0-TR_PCG7 corresponding to the signal lines SG0-SG4 and CG0-CG7, respectively. Each switch TR_PSG0-TR_PSG4 and TR_PCG0-TR_PCG7 connects the signal lines SG0-SG4 and CG0-CG7 connected to the MUX switch 29 to the signal lines SG0-SG4 and CG0-CG7 on each plane PB, respectively.

[0134] The transmission control circuit 30A of each TS30 in the planar decoder group 31 is controlled by the sequence generator 27 to generate selection signals PLNSEL for turning on the switches TR_PSG0~TR_PSG4 and TR_PCG0~TR_PCG7 of one of the switch circuit groups 30B connected in the planes PB0~PB3. As a result, the signal lines SG0~SG4 and CG0~CG7 connected to the MUX switch 29 are electrically connected to the signal lines SG0~SG4 and CG0~CG7 within one of the planes PB0~PB3.

[0135] Furthermore, signal lines SG0-SG4 and CG0-CG7 within each plane PB are branched by the row decoder 25 and connected to the wiring of each BLK block. That is, signal lines SG0-SG4 function as global drain-side select gate lines, connected via the row decoder 25 to the select gate lines SGD0-SGD3 in each BLK block as local select gate lines. Signal lines CG0-CG7 function as global word lines, connected via the row decoder 25 to the word lines WL0-WL7 in each BLK block as local word lines. Signal line SG4 functions as a global source-side select gate line, connected via the row decoder 25 to the select gate line SGS in each BLK block as a local select gate line.

[0136] The row decoder 25 has multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B corresponding to the multiple switch circuit groups 25A. Each switch circuit group 25A includes: multiple transistors TR_SG0 to TR_SG3 connected to signal lines SG0 to SG3 and select gate lines SGD0 to SGD3 respectively; multiple transistors TR_CG0 to TR_CG7 connected to signal lines CG0 to CG7 and word lines WL0 to WL7 respectively; and transistor TR_SG4 connected to signal line SG4 and select gate line SGS. Transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are high-voltage resistant transistors.

[0137] When each block decoder 25B is specified by the row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7. As a result, in the switching circuit group 25A that supplies the block selection signal BLKSEL from the block decoder 25B specified by the row decoder, since transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_SG7 are turned on, the voltage supplied from the power generation circuit 28 to the signal lines SG0 to SG4 and CG0 to CG7 is supplied to the selection gate lines SGD0 to SGD3, SGS, and word lines WL0 to WL7 of the block BLK that is to be operated.

[0138] In other words, through the voltage generation circuit 28, MUX switch 29, TS30 and row decoder 25, the programming voltage VPGM is supplied to the select word line WL, the voltage VPASS is supplied to the non-select word line WL, and the voltage VPASS and voltage VPASS_SHIFT are supplied to the adjacent word line WL.

[0139] In addition, for example, a voltage VSG_sel is supplied to the select gate line SGD (SGD_sel) of the select gate transistor ST1 connected to the string unit SU which is the object of the operation, and a voltage VSG_usel of 0V is supplied to the select gate line SGD (SGD_usel) of the select gate transistor ST1 which is not the object of the operation.

[0140] (effect)

[0141] Next, regarding the operation of this embodiment, refer to... Figure 13 Please provide an explanation. Figure 13 This is an explanatory diagram used to illustrate the discharge action during VPASS_SHIFT.

[0142] During programming, sequence generator 27 is controlled to apply programming voltage VPGM to the select word line (WLn) and voltage VPASS to the non-select word line. Furthermore, during the latter half of the VPASS_SHIFT period when the specific programming voltage VPGM is applied, sequence generator 27 executes a VPASS_SHIFT that raises the voltage VPASS of the adjacent word line (WLn±1) to the VPASS_SHIFT voltage.

[0143] Figure 13 This indicates that programming is performed only for plane PB0, and programming is not performed for other planes PB1 to PB3. A programming voltage VPGM is applied to the selection word line (WLn) of plane PB0. For adjacent word lines (WLn±1), a voltage VPASS is applied during the first half of the VPGM application period, and a voltage VPASS_SHIFT is applied during the second half of the VPASS_SHIFT period. Due to the influence of adjacent word lines (WLn±1), a floating potential is easily generated at the programming voltage VPGM during the VPASS_SHIFT application period. Figure 13 (dashed waveform).

[0144] However, in this embodiment, the timing generator 27 outputs a control signal to turn on the transistor NM13 of the discharge circuit 50 during VPASS_SHIFT. Therefore, during VPASS_SHIFT, the variable resistor R3 of the discharge circuit 50 is connected to the reference potential point. Thus, as... Figure 13As shown by the dashed arrow, current flows from the select word line (WLn) through the row decoder 25, TS30, and MUX switch 29, and then through the variable resistor R3 of the discharge circuit 50 to the reference potential point. The result is as follows: Figure 13 As shown in the waveform, the floating potential is suppressed, and the programming voltage VPGM remains at a roughly flat level. That is, even with 4-plane operation, no floating potential is generated in the programming voltage VPGM.

[0145] Furthermore, in this embodiment, the sequence generator 27 causes the resistance value of the variable resistor R3 to vary according to the number of simultaneously operating planes. As a result, the discharge current of the discharge circuit 50 varies depending on the number of simultaneously operating planes, effectively suppressing floating potentials. Thus, regardless of the number of simultaneously operating planes, the programming voltage VPGM can be uniformized in both multi-plane and single-plane operation scenarios, resulting in a shorter write time.

[0146] Furthermore, since the discharge circuit 50 of the embodiment is arranged in parallel with the output circuit 43 of the VPGM generation circuit 40 that generates the output voltage VPGMH, it is not necessary to directly increase the discharge capability of the output circuit 43 of the VPGM generation circuit 40 in order to suppress the floating potential. Therefore, the resistance values ​​of the resistors R1 and R2 included in the output circuit 43 of the VPGM generation circuit 40 can be set sufficiently large, and the increase in power consumption can be suppressed.

[0147] Figure 17 This is an explanatory diagram used to illustrate the effects of the first embodiment. Figure 17 The horizontal axis represents time, and the vertical axis represents voltage. The graph represents the change of the programming voltage VPGM of signal lines CG0 to CG7. Figure 17 In the diagram, the Before column indicates the programming voltage VPGM waveform when the discharge circuit 50 is not used, and the After column indicates the programming voltage VPGM waveform in this embodiment.

[0148] Figure 17 In the example, 1P, 2P, 3P, and 4P represent instances where the number of planes acting simultaneously is 1, 2, 3, and 4, respectively. From... Figure 17 A comparison of the Before and After columns shows that, according to the first embodiment employing the discharge circuit 50, floating potentials are uniformly suppressed at any location on the wiring, and the programming voltage VPGM during VPASS_SHIFT changes uniformly regardless of the difference in the number of simultaneously operating planes.

[0149] Thus, in this embodiment, during the VPASS_SHIFT period when the programming voltage VPGM is applied, by flowing discharge current through the discharge circuit provided in the wiring supplying the programming voltage VPGM, even in multi-plane operation, the floating potential generated in the programming voltage VPGM can be suppressed. In this case, by varying the amount of discharge current in the discharge circuit according to the number of simultaneously operating planes, uniformity of the programming voltage VPGM is achieved regardless of the number of simultaneously operating planes. As a result, the write time can be shortened.

[0150] (Example of variation)

[0151] The above description illustrates an example where the sequence generator 27 causes the resistance value of the variable resistor R3 in the discharge circuit 50 to vary according to the number of simultaneously operating planes. Furthermore, the sequence generator 27 can also cause the resistance value of the variable resistor R3 in the discharge circuit 50 to vary according to the level of the programming voltage VPGM.

[0152] Because the higher the programming voltage VPGM level, the greater the current flowing in the limiting circuit in the VPGM generation circuit 40, the lower the floating potential level. Therefore, the sequence generator 27 is controlled in the following way: the higher the programming voltage VPGM level, the higher the resistance value of the variable resistor R3, and the smaller the discharge current; the lower the programming voltage VPGM level, the smaller the resistance value of the variable resistor R3, and the greater the discharge current.

[0153] In addition, in the same way as in the first embodiment, multiple resistors can be configured between the output node N and the reference potential point, and the resistors connected between the output node N and the reference potential point can be selected by a switch.

[0154] (Second Implementation)

[0155] Figure 14 and Figure 15 Related to the second embodiment of the present invention, Figure 14 This is a block diagram illustrating a configuration example of the non-volatile memory according to the second embodiment. Furthermore, Figure 15 It means Figure 14 A block diagram illustrating a specific example of the multiple planes within the structure. Figure 14 and Figure 15 In the middle, to and Figure 2 and Figure 3 The same constituent elements are marked with the same symbol, and the explanation is omitted.

[0156] This embodiment, by providing the discharge path of the limiting circuit configured in the VPGM generation circuit 40 in each plane PB10 to PB13 (hereinafter, without distinction, referred to as plane PB1), similarly suppresses floating units, just as in the case of a single-plane configuration. In other words, in this embodiment, as... Figure 14and Figure 15 As shown, a voltage generating circuit 60 and a MUX switch 29 are constructed in each plane PB1, while planes PB1 to TS30 are omitted.

[0157] The voltage generating circuit 60 will discharge the circuit 50 from Figure 11 The voltage generating circuit 28 is omitted, but the other components are the same as those of the voltage generating circuit 28. That is to say, within the voltage generating circuit 60, the following components are configured... Figure 8 The illustrated VPGM generation circuit 40 forms a discharge path for the limiting circuit.

[0158] In addition, since the voltage generation circuit 60 and the MUX switch 29 are located in each plane PB1, the TS30 used to select the plane PB1 and supply voltage is omitted.

[0159] In this configuration, the select word line WLn of a single-plane PB1 is connected to the output node N of the VPGM generation circuit 40. As a result, the same discharge as in the single-plane configuration is performed through the limiting circuit within the VPGM generation circuit 40, suppressing floating potentials. Since the limiting circuit within the VPGM generation circuit 40 performs the same discharge in each plane PB1, uniformity of the programming voltage VPGM among the planes PB1 can be achieved.

[0160] Thus, in this embodiment, regardless of the number of planes operating simultaneously, the programming voltage VPGM can be made uniform, resulting in a shorter write time.

[0161] Alternatively, in this embodiment, the current flowing in the limiting circuit of the VPGM generation circuit 40 may be configured to vary according to the level of the programming voltage VPGM. That is, the sequence generator 27 is controlled in the following way: the higher the level of the programming voltage VPGM, the higher the resistance value of the variable resistor R2 constituting the limiting circuit, and the smaller the discharge current; the lower the level of the programming voltage VPGM, the smaller the resistance value of the variable resistor R2, and the larger the discharge current.

[0162] Therefore, in this embodiment, floating potentials can be uniformly suppressed regardless of the level of the programming voltage VPGM.

[0163] (Third Implementation)

[0164] Figure 16 This is a block diagram illustrating the third embodiment of the present invention. Figure 16 In the middle, to and Figure 2 The same components are labeled with the same symbols and their descriptions are omitted. The hardware configuration of this embodiment differs from that of the voltage generation circuit 28 in that it uses a voltage generation circuit 61 instead of a voltage generation circuit 28. Figure 2The difference lies in the implementation method. This method aims to homogenize the programming voltage VPGM by varying the level of the voltage VPASS_SHIFT according to the number of simultaneously operating planes.

[0165] Voltage generating circuit 61 discharges circuit 50 from Figure 11 The voltage generating circuit 28 is omitted, but its other configuration is the same as that of the voltage generating circuit 28. Furthermore, the voltage generating circuit 61 includes... Figure 8 The illustrated charge pump circuit 41 and clock control circuit 42 Figure 11 The illustrated VPASS generation circuit 45 and VPASS2 generation circuit 46. The voltage generation circuit 61 can change the level of the voltage VPASS_SHIFT from the VPASS2 generation circuit 46 by switching the clock signal CLK from the clock control circuit 42, the clock number of / CLK, the number of stages of the charge pump circuit 41, etc., based on the control signal from the sequence generator 27.

[0166] In this embodiment, the sequence generator 27 controls the voltage generation circuit 61 to change the level of the voltage VPASS_SHIFT according to the number of simultaneously operating planes. For example, in the sequence generator 27, the more simultaneously operating planes there are, the lower the level of the voltage VPASS_SHIFT becomes, and the fewer simultaneously operating planes there are, the higher the level of the voltage VPASS_SHIFT becomes. Thus, when the number of simultaneously operating planes is large, the increase in the programming voltage VPGM is suppressed, and the generation of floating potential is suppressed; when the number of simultaneously operating planes is small, the increase in the programming voltage VPGM is increased, and the decrease in the programming voltage VPGM is suppressed.

[0167] Furthermore, in this embodiment, the sequence generator 27 can also vary the level of the voltage VPASS_SHIFT according to the level of the programming voltage VPGM. For example, in the sequence generator 27, the higher the level of the programming voltage VPGM, the higher the level of the voltage VPASS_SHIFT, suppressing the decrease of the programming voltage VPGM; the lower the level of the programming voltage VPGM, the lower the level of the voltage VPASS_SHIFT, suppressing the generation of the floating potential of the programming voltage VPGM.

[0168] Thus, in this embodiment, similar to the first embodiment, regardless of the number of simultaneously operating planes, the floating potential generated in the programming voltage VPGM can be suppressed, thereby uniformizing the programming voltage VPGM. As a result, the write time can be shortened.

[0169] This invention is not limited to the described embodiments, and various changes can be made during the implementation phase without departing from its spirit. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, if even if several constituent elements are deleted from all the constituent elements shown in the embodiments, the problem described in the Problem to be Solved section can be solved, and the effects described in the Effects section can be obtained, then the configuration after deleting the constituent elements can be extracted as an invention.

[0170] [Symbol Explanation]

[0171] 1. Memory controller

[0172] 2. Non-volatile memory

[0173] 11 RAM

[0174] 12 processors

[0175] 13. Host Interface

[0176] 14 ECC Circuit

[0177] 15 Memory Interface

[0178] 16 Internal Bus

[0179] 21 Logic Control Circuit

[0180] 22 Input / Output Circuit

[0181] 23-cell storage array

[0182] 24 Sensing Amplifier

[0183] 25-line decoder

[0184] 26 Registers

[0185] 27 Sequence Generator

[0186] 28 Voltage Generation Circuit

[0187] 29 MUX Switch

[0188] 30 TS

[0189] 41 Charge Pump Circuit

[0190] 42 Clock control circuit

[0191] 40 VPGM generation circuit

[0192] 45 VPASS generation circuit

[0193] 46 VPASS2 generation circuit

[0194] 50 Discharge Circuit

[0195] R3 Variable resistor

[0196] NM13 transistor.

Claims

1. A semiconductor memory device comprising: a plurality of planes including a memory cell array, the memory cell array comprising a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one end of the plurality of memory cells via select gate transistors respectively connected to one end of the plurality of memory cells; The voltage generation circuit is capable of generating voltages to one or more of the memory cell arrays contained in each of the plurality of planes, and during programming, it supplies programming voltage to the select word line of the write target, and simultaneously applies a first intermediate voltage to the adjacent word line adjacent to the select word line during the first half of the programming period, and then applies a second intermediate voltage higher than the first intermediate voltage in the second half of the programming period. A discharge circuit, disposed on the path between the voltage generating circuit and the select word line, allows a discharge current to flow from the select word line during a period corresponding to the period during which the second intermediate voltage is applied to the adjacent word line; and The control circuit sets the discharge characteristics of the discharge circuit based on the number of planes simultaneously supplied with the programming voltage from the voltage generation circuit.

2. The semiconductor memory device according to claim 1, wherein the control circuit sets the discharge characteristics of the discharge circuit according to the level of the programming voltage.

3. A semiconductor memory device comprising: a plurality of planes including a memory cell array, the memory cell array comprising a plurality of memory cells, word lines connected to the gates of the plurality of memory cells, and bit lines electrically connected to one end of the plurality of memory cells via select gate transistors respectively connected to one end of the plurality of memory cells; A voltage generation circuit, disposed on the plurality of planes, generates a voltage supplied to the memory cell array and has a limiting circuit that restricts the programming voltage supplied to the select word line of the write target to a predetermined value. During programming, a programming voltage is supplied to the select word line, and simultaneously, for adjacent word lines adjacent to the select word line, a first intermediate voltage is applied in the first half of the programming period, followed by a second intermediate voltage higher than the first intermediate voltage in the second half. The control circuit sets the amount of current flowing in the limiting circuit based on the level of the programming voltage.

4. A semiconductor memory device comprising: a plurality of planes including a memory cell array, the memory cell array comprising a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one end of the plurality of memory cells via select gate transistors respectively connected to one end of the plurality of memory cells; A voltage generation circuit is capable of generating voltages to one or more memory cell arrays contained in each of the plurality of planes, and supplying a programming voltage to the select word line of the write target during programming, while simultaneously applying a first intermediate voltage to adjacent word lines adjacent to the select word line during the first half of the programming period, followed by applying a second intermediate voltage higher than the first intermediate voltage in the second half; and The control circuit sets the level of the second intermediate voltage based on the number of planes simultaneously supplied with the programming voltage from the voltage generation circuit.

5. The semiconductor memory device according to claim 4, wherein the control circuit sets the level of the second intermediate voltage according to the level of the programming voltage.

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