Method, device, equipment and storage medium for processing check pins of memory

Abstract

The present application relates to a method, device, equipment and storage medium for processing the check pins of a memory. The method can be applied to the application scenarios of cloud technology and vehicle-mounted terminals, including: receiving the first data signal and sampling pulse signal returned by each check pin in the target memory based on the first data read instruction; time-shifting each first data signal respectively through a delay circuit so that the target level value in each first data signal after the time shift is aligned with the sampling pulse signal, and obtaining a first delay parameter; when receiving the second data signal returned by each check pin in the target memory, time-shifting the target data signal in each second data signal respectively through a delay circuit so that the target level value in each second data signal after the time shift is aligned, and obtaining a second delay parameter; based on the first delay parameter and the second delay parameter, determining the sampling delay parameter of the check pin. The use of this method can ensure the correctness of sampling data signals based on sampling pulse signals.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for processing a check pin of a memory. Background Art

[0002] High Bandwidth Memory (HBM) is a new type of high-speed, high-bandwidth memory primarily used in artificial intelligence chips. The transmission lines of HBM read data signals are susceptible to malfunctions due to factors such as chip processing, operating voltage, ambient temperature, and crosstalk between signals. This can lead to errors in the transmitted read data signals, necessitating detection of read data signal errors.

[0003] Traditional detection methods mainly transmit the read data signal together with the parity check PAR (Parity Check) signal of the read data signal and the sampling pulse signal of the read data signal, so that the receiver can obtain verification information based on the sampling pulse signal sampling parity check signal, and then verify whether the read data signal is transmitted incorrectly based on the verification information.

[0004] However, the parity signal is also affected by the chip process, operating voltage, ambient temperature and crosstalk between signals, causing the parity signal and the sampling pulse signal to be offset. When the receiver samples the parity signal based on the sampling pulse signal, a sampling error may occur, resulting in incorrect verification information, which in turn leads to an incorrect verification result for the data signal. Summary of the Invention

[0005] Based on this, it is necessary to provide a method, device, equipment and storage medium for processing the check pin of a memory that can improve the sampling accuracy of the parity check signal to address the above technical problems.

[0006] In a first aspect, the present application provides a method for processing a check pin of a memory. The method comprises:

[0007] Sending a first data read instruction to the target memory;

[0008] receiving a first data signal and a sampling pulse signal returned by each check pin in the target memory;

[0009] Time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter;

[0010] When receiving the second data signals returned by the check pins in the target memory, the target data signals in the second data signals are time-shifted by the delay circuit so that the target level values ​​in the second data signals are aligned after the time shift, thereby obtaining a second delay parameter;

[0011] A sampling delay parameter of the verification pin is determined based on the first delay parameter and the second delay parameter.

[0012] In a second aspect, the present application further provides a memory check pin processing device. The device comprises:

[0013] An instruction sending module, configured to send a first data read instruction to a target memory;

[0014] A signal receiving module, configured to receive a first data signal and a sampling pulse signal returned by each check pin in the target memory;

[0015] a signal time-shift module, configured to time-shift each of the first data signals using a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; and, upon receiving a second data signal returned by each of the check pins in the target memory, time-shift each of the target data signals in each of the second data signals using the delay circuit so that the target level values ​​in each of the second data signals after the time shift are aligned, thereby obtaining a second delay parameter;

[0016] The delay determination module determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0017] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are performed:

[0018] Sending a first data read instruction to the target memory;

[0019] receiving a first data signal and a sampling pulse signal returned by each check pin in the target memory;

[0020] Time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter;

[0021] When receiving the second data signals returned by the check pins in the target memory, the target data signals in the second data signals are time-shifted by the delay circuit so that the target level values ​​in the second data signals are aligned after the time shift, thereby obtaining a second delay parameter;

[0022] A sampling delay parameter of the verification pin is determined based on the first delay parameter and the second delay parameter.

[0023] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0024] Sending a first data read instruction to the target memory;

[0025] receiving a first data signal and a sampling pulse signal returned by each check pin in the target memory;

[0026] Time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter;

[0027] When receiving the second data signals returned by the check pins in the target memory, the target data signals in the second data signals are time-shifted by the delay circuit so that the target level values ​​in the second data signals are aligned after the time shift, thereby obtaining a second delay parameter;

[0028] A sampling delay parameter of the verification pin is determined based on the first delay parameter and the second delay parameter.

[0029] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the following steps:

[0030] Sending a first data read instruction to the target memory;

[0031] receiving a first data signal and a sampling pulse signal returned by each check pin in the target memory;

[0032] Time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter;

[0033] When receiving the second data signals returned by the check pins in the target memory, the target data signals in the second data signals are time-shifted by the delay circuit so that the target level values ​​in the second data signals are aligned after the time shift, thereby obtaining a second delay parameter;

[0034] A sampling delay parameter of the verification pin is determined based on the first delay parameter and the second delay parameter.

[0035] The above-mentioned memory check pin processing method, apparatus, computer equipment, storage medium and computer program product are configured to send a first data read instruction to a target memory; receive a first data signal and a sampling pulse signal returned by each check pin in the target memory; time-shift each first data signal using a delay circuit so that a target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; when receiving a second data signal returned by each check pin in the target memory, time-shift each target data signal in each second data signal using a delay circuit so that a target level value in each second data signal after the time shift is aligned, thereby obtaining a second delay parameter; and determine a sampling delay parameter for the check pin based on the first delay parameter and the second delay parameter. Thus, after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, thereby ensuring the accuracy of the parity check signal when sampling based on the sampling pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 FIG2 is an application environment diagram of a method for processing a check pin of a memory according to an embodiment;

[0037] Figure 2 A schematic diagram of a read instruction in one embodiment;

[0038] Figure 3 A schematic diagram of reading data in one embodiment;

[0039] Figure 4 A schematic diagram of reading data in another embodiment;

[0040] Figure 5 A schematic diagram of reading data in another embodiment;

[0041] Figure 6 A schematic diagram of reading data in another embodiment;

[0042] Figure 7 A schematic diagram of a data signal and a sampling pulse signal in one embodiment;

[0043] Figure 81 is a flow chart of a method for processing a check pin of a memory according to an embodiment;

[0044] Figure 9 is a functional diagram of mode register bit MR7 in one embodiment;

[0045] Figure 10 A schematic diagram of a MISR circuit in one embodiment;

[0046] Figure 11 is a functional diagram of the mode register bit MR0 in one embodiment;

[0047] Figure 12 A schematic diagram of a read data structure in one embodiment;

[0048] Figure 13 is a schematic diagram of a delay circuit in one embodiment;

[0049] Figure 14 is a schematic diagram of a delay circuit in another embodiment;

[0050] Figure 15 A schematic diagram of a time-shift effect of a digital signal in an embodiment;

[0051] Figure 16 A schematic diagram of a time-shift effect of a digital signal in another embodiment;

[0052] Figure 17 is an architectural diagram of a check pin processing system for a memory according to one embodiment;

[0053] Figure 18 is a structural block diagram of a check pin processing device of a memory in one embodiment;

[0054] Figure 19 is a structural block diagram of a check pin processing device of a memory in another embodiment;

[0055] Figure 20 is a diagram of the internal structure of a computer device in one embodiment;

[0056] Figure 21 FIG. 4 is a diagram showing the internal structure of a computer device in another embodiment. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0058] Artificial Intelligence (AI) refers to the theories, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that seeks to understand the essence of intelligence and produce new intelligent machines that can respond in a manner similar to human intelligence. AI also studies the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making.

[0059] With the research and advancement of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common artificial intelligence chips (AI), smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned driving, autonomous driving, drones, robots, smart medical care, smart customer service, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0060] The memory check pin processing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. The memory check pin processing method can be executed by terminal 102 or server 104, or by terminal 102 and server 104 in collaboration. In some embodiments, terminal 102 and server 104 are provided with a memory controller, and the memory check pin processing method can be specifically executed by the memory controller. If the check pin processing method of the memory is executed by the terminal 102, the terminal 102 sends a first data read instruction to the target memory; receives a first data signal and a sampling pulse signal returned by each check pin in the target memory; time-shifts each first data signal through a delay circuit so that a target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; when receiving a second data signal returned by each check pin in the target memory, time-shifts the target data signal in each second data signal through a delay circuit so that a target level value in each second data signal after the time shift is aligned, thereby obtaining a second delay parameter; and determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0061] Among them, the terminal 102 can be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, intelligent voice interaction device, smart home appliance and car terminal etc. integrated with an AI chip, but is not limited thereto. The AI ​​chip can be a chip that combines an AI processor and a memory (such as a high-bandwidth memory). The memory can include a data storage area and a controller, or the controller can exist in an independent form and control the memory.

[0062] Server 104 can be an independent physical server with an integrated AI chip, or a service node in a blockchain system. The service nodes in the blockchain system form a peer-to-peer (P2P) network. The P2P protocol is an application layer protocol running on top of the Transmission Control Protocol (TCP).

[0063] In addition, server 104 can also be a server cluster composed of multiple physical servers with integrated AI chips. It can be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), as well as big data and artificial intelligence platforms.

[0064] The terminal 102 and the server 104 may be connected via Bluetooth, USB (Universal Serial Bus), or a network, and this application does not impose any limitation thereto.

[0065] Before describing the memory check pin processing method provided in the embodiment of the present application, the memory data reading process in the traditional solution is first described.

[0066] In a traditional solution, after a computer device sends a burst data read instruction to a target memory, the target memory reads the read data based on the received read instruction and returns the read data to the computer device, such as Figure 2 The figure shows a schematic diagram of a READ command sent in a traditional solution, where the burst length can be 2 or 4. Figure 3This is a schematic diagram of the read data (DQ) returned by the READ instruction. The relevant timing parameters contained in the figure are as follows: tDQSCK (min / max) refers to the minimum and maximum time range between the rising edge of RDQS_c (or the falling edge of RDQS_t) and the rising edge of CK_c (or the falling edge of CK_t); tDQSCK describes the time delay between the rising edge of RDQS and the rising edge of CK; tQSH: describes the time delay of the RDQS signal being continuously high; tQSL describes the time delay of the RDQS signal being continuously low. tLZ (min / max) describes the minimum and maximum time ranges for the read data to continuously transition from a high-impedance state to a low-impedance state; tHZ (min / max) describes the minimum and maximum time ranges for the read data to continuously transition from a low-impedance state to a high-impedance state; tDQSQ describes the time delay between the rising edge of RDQS_t (or the falling edge of RDQS_c) and the readout of DQ, DM, and DBI data; tQH describes the time delay between the rising edge of RDQS_t (or the falling edge of RDQS_c) and the stable readout of DQ, DM, and DBI data; RDQS (Read DQ Strobe) is the read data selection pulse, also known as the sampling pulse signal; DQ is the read data bus, also known as read data; DM (Data Mask) is the data mask; and DBI (Data Bus Inversion) is the data bus inversion. A burst refers to the continuous data transmission between adjacent memory cells in the same row of the target memory. The number of cycles of continuous transmission is the burst length (BL).

[0067] It should be noted that in the traditional solution, after the computer device sends a burst data read instruction to the target memory, the target memory returns the read data to the computer device based on the received read instruction, and also returns the parity data of the read data to the computer device. The parity signal corresponding to the parity data can be transmitted at the same time as the read data signal of the read data, or can be transmitted later than the read data signal of the read data. The PL (parity latency) parameter is usually used to describe the number of delay cycles of the parity signal relative to the read data signal. The PL parameter can be specifically configured from 0 to 3 clock cycles. The configuration of the PL parameter is controlled by the mode register bit MR4 (Mode Register 4) of the HBM, as shown in the following table:

[0068] Table 1

[0069]

[0070] The role of PL parameters is explained with examples, such as Figure 4As shown in the figure, the corresponding read BL (Read burst length) = 2, PL = 0, RL (Read Latency) = 7, then the read data signal will arrive at the rising edge of the clock at time T7. Since PL = 0, the parity check signal will also arrive at the rising edge of the clock at time T7; Figure 5 , the corresponding RL (Read burst length) = 2, PL = 1, RL (Read Latency) = 6, then the read data signal will arrive at the rising edge of the clock at time T6. Since PL = 1, the parity signal will also arrive at the rising edge of the clock at time T7.

[0071] From the above description, it can be seen that when the computer device sends a data read instruction to the target memory, such as Figure 6 As shown in the figure, the target memory returns a read data signal (DQ), a parity signal (PAR) for the read data signal, and a corresponding sampling pulse signal (RAQS) to the computer device. The computer device uses RDQS as the sampling signal to sample the read data signal and parity signal, thereby obtaining read data and parity data. Therefore, sampling accuracy is highest only when the sampling pulse signal and the parity signal's eye diagram center are aligned. ACT is a row activation instruction, and PRE is a precharge instruction.

[0072] The following is an example of sampling accuracy: Figure 7 As shown in the figure, CLK is used to sample Data. In the HBM read verification data scenario, CLK is the RDQS signal returned by the HBM DRAM, and Data contains the PAR data returned by the HBM DRAM. Figure 7 In A, the rising edge of CLK (i.e., the sampling edge) is located at the center of the data center. At this time, the sampling accuracy is the highest; Figure 7 B and Figure 7 In C, the center position of the Data data and the rising edge of CLK are not aligned. Figure 7 The rising edge of CLK in B drifts out of the data window of Data; Figure 7 In C, although the rising edge of CLK does not drift outside the data window of Data, the sampling edge and the setup (or release) edge of the data are too close, resulting in a setup timing (or hold timing) violation in this sampling. Figure 7 B and Figure 7 Both situations shown in C will result in sampling errors in the read data.

[0073] In one embodiment, Figure 8 As shown, a method for processing the check pin of a memory is provided, and the method is applied to Figure 1 The following steps are used as an example to illustrate the computer device (terminal or server) in the example:

[0074] S802: Send a first data read instruction to the target memory.

[0075] The target memory may be a high bandwidth memory (HBM), specifically a dynamic random access memory (HBM DRAM). The first data read instruction is used to read data from the target memory.

[0076] It should be noted that, in the embodiment of the present application, sending a first data read instruction to the target memory is to initiate a read operation to the target memory. The read operation in the embodiment of the present application is generally a burst read operation. Burst refers to a method of continuously transmitting data between adjacent storage cells in the same row of the target memory. The number of continuous transmission cycles is the burst length (Burst Lengths, abbreviated as BL).

[0077] Specifically, the computer device generates a first data read instruction and sends the first data read instruction to the target memory in the target mode. The target memory in the target mode reads the read data from the register unit of the target register based on the received data read instruction. Figure 2 Schematic diagram of the first data read instruction in an embodiment of the present application.

[0078] Among them, the target mode is one of the operating modes of the memory. The operating mode of the memory can be set specifically through the mode register. The mode register is used to define the specific operating mode of the HBM. The definition includes the selection of burst length, burst type, CAS latency, operating mode and write burst mode. The operating mode in the embodiment of the present application is specifically set by the mode register bit MR7. For details, please refer to Figure 9 The function description information of the mode register bit MR7 is shown.

[0079] In one embodiment, before the computer device sends the first data read instruction to the target memory, it also needs to configure the operation mode of the target memory. The process of configuring the operation mode of the target memory specifically includes the following steps: sending an operation mode configuration instruction to the target memory so that the target memory configures the operation mode to the target mode based on the operation mode configuration instruction; when the target memory is in the target mode, sending the first data read instruction to the target memory in the target mode.

[0080] The target mode is a data word (DWORD) read linear feedback shift register (LFSR) mode.

[0081] Specifically, after configuring the target memory to the data word read linear feedback shift register (DWORDLFSR) mode, the computer device sends a first data read instruction to the target memory in the data word read linear feedback shift register mode. The target memory in the data word read linear feedback shift register mode can read the read data based on the received first data read instruction and store the read data in the register unit of the target memory, so that the computer device can obtain the read data stored in the register unit.

[0082] In the above embodiment, the computer device sends an operation mode configuration instruction to the target memory so that the target memory configures the operation mode to the target mode based on the operation mode configuration instruction, so that the memory in the target mode can return the first data signal and the sampling pulse signal through each check pin to further determine the sampling delay parameters of the check pin.

[0083] In one embodiment, the process of configuring the target register to operate in a target mode based on an operation mode configuration instruction includes the following steps: initializing a read instruction processing circuit of the target memory; and configuring the operation mode of the read instruction processing circuit to operate in the target mode based on the operation mode configuration instruction.

[0084] The operation mode configuration instruction includes 8 bits of data, and different instructions are generated by changing the values ​​of different bits of data. The instruction processing circuit can be a multi-input shift register (MISR) circuit.

[0085] It should be noted that the multi-input shift register (MISR) circuit may include a plurality of flip-flops and a plurality of input selectors alternately coupled in series, and the plurality of input selectors may correspond to the plurality of flip-flops, respectively. Figure 10 FIG. 1 is a schematic diagram of a MISR circuit in an embodiment, which shows four flip-flops and four input selectors for storing and outputting four bits of data. Figure 10When the input control signals M0 and M1 are both 1, that is, when the input control signals M0 and M1 are both input at a logic high level, the MISR circuit corresponds to a multi-input shift register mode (MISR mode), that is, the MISR circuit can perform the function of a multi-input shift register; when the input control signal M0 is 0 and M1 is 1, that is, the input control signal M0 is input at a logic low level and M1 is input at a logic high level, the MISR circuit corresponds to a simple register mode (Register mode), that is, the MISR circuit can perform a simple register (Register) function; when the input control signal M0 is 1 and M1 is 0, that is, the input control signal M0 is input at a logic high level and M1 is input at a logic low level, the MISR circuit corresponds to a linear feedback shift register mode (LFSR mode), that is, the MISR circuit can perform the function of a linear feedback shift register (LFSR).

[0086] It is understood that when the instruction processing circuit supports 20 data bits, the corresponding MISR circuit may include 20 flip-flops and 20 input selectors to store and output 20 data bits. The 20-bit MISR circuit can be mathematically described by the following polynomial:

[0087] f(X)=X 20 +X 17 +1

[0088] When the instruction processing circuit supports 4-bit data, the corresponding MISR circuit may include 4 flip-flops and 4 input selectors to store and output 4-bit data. The 4-bit MISR circuit can be mathematically described by the following polynomial:

[0089] f(X)=X 4 +X 3 +1

[0090] Specifically, the computer device generates an initialization instruction and sends the initialization instruction to the target memory. After receiving the initialization instruction, the target memory initializes the read instruction processing circuit based on the initialization instruction. Then the computer device sends an operation mode configuration instruction to the target memory. The initialized target memory configures the operation mode of the read instruction processing circuit of the target memory to the target mode based on the operation mode configuration instruction.

[0091] For example, HBM configures the DWORD MISR circuit to DWORD read LFSR mode, which is accomplished by configuring the HBM mode register MR7. The steps for configuring HBM to DWORD read LFSR mode are as follows: First, configure the instruction value of MR7 to 8'b00000001. Figure 9Among them, OP0 is 1, indicating that the DWORD Loopback mode is enabled, OP[5:3] is 3'b000, indicating that the default value in the DWORD register is reset to 0xAAAAAh, and the remaining bits are all default values, thereby initializing the read instruction processing circuit based on the instruction of MR7; then the instruction value of MR7 is configured to be 8'b00001011, among which OP0 is 1, indicating that the DWORD Loopback mode is enabled, OP[2:1] is 2'b01, indicating that the value in the MISR register is read. Since the value is reset during the initialization process, the read value is 0xAAAAAh; OP[5:3] is 3'b001, configuring the DWORD register to read LFSR mode, and the remaining bits are all default values, thereby configuring the operation mode of the read instruction processing circuit of the target memory based on the instruction of MR7 to be DWORD read LFSR mode.

[0092] In the above embodiment, the read instruction processing circuit of the target memory is initialized; based on the operation mode configuration instruction, the operation mode of the read instruction processing circuit is configured to the target mode, so that the target memory in the target mode can return the first data signal and the sampling pulse signal through each check pin, so as to further determine the sampling delay parameters of the check pin.

[0093] S804: Receive the first data signal and sampling pulse signal returned by each verification pin in the target memory.

[0094] The first data signal is generated based on a target data bit in the read data, and the read data is data read from a register of the target memory by the target memory based on a first data read instruction.

[0095] It should be noted that the operating mode of the target memory is the target mode. In the target mode, the data output by each check pin no longer represents the check data of the read data, but returns the value of the target data bit in the read data that is closer to each pin to the corresponding check pin.

[0096] Specifically, after receiving the first data read instruction, the target memory performs a read operation based on the first data read instruction to obtain read data, and returns the value of the target data bit in the read data to the corresponding check pin, and outputs the value of the target data bit as the first data signal through the check pin.

[0097] For example, the read data and parity pins of a single channel of HBM DRAM include the following related interfaces:

[0098] Table 2

[0099] Function Data bit width Functional Description DQ 128-bit HBM DRAM read data bus DBI 16-bit Data Bus Inversion PAR 4 digits Read Parity verification data

[0100] For example, it should be noted that in DWORD read LFSR mode, the data returned by the check pin no longer truly represents the content of the check data of the read data, and is not affected by the corresponding setting of the DQ bus read parity in MR0. The functional description information of the mode register bit MR0 is as follows Figure 11 In DWORD read LFSR mode, the HBM DRAM will return the target data bit in the read data (DQ) that is closest to each parity pin to the corresponding parity pin. The following table shows the data bit of the read data actually returned by each parity (PAR) pin:

[0101] Table 3

[0102] PAR pin location Related DQ data bits PAR[0] DQ[2] PAR[1] DQ

[34] PAR[2] DQ

[66] PAR[3] DQ

[98]

[0103] In LFSR read mode, PAR[0] no longer represents the parity data for the 32-bit data DQ[31:0]. Instead, it simply returns the value of DQ[2] to PAR[0]. Similarly, the value of DQ

[34] is returned to PAR[1], the value of DQ

[66] is returned to PAR[2], and the value of DQ

[98] is returned to PAR[3]. At the same time, the PL configuration no longer takes effect, and PAR and DQ will arrive at the same time, which is the return delay when PL = 0.

[0104] refer to Figure 12 As shown in the read data structure diagram, a complete data word (DWORD) in the embodiment of the present application can be divided into four groups: DWORD0, DWORD1, DWORD2 and DWORD3, where each DWORD is further divided into Byte0, Byte1, Byte2 and Byte3, a total of 4 data units, that is, 128 bits of read data (DQ) are distributed in 16 bytes, and each Byte contains 8 bits of DQ, as shown in FIG. Figure 12 As shown in the figure, the 19th bit to the 0th bit in each byte are the falling edge data word and the rising edge data word of DBI, the falling edge data word and the rising edge data word of each bit in 8-bit DQ, the falling edge data word of DM and the rising edge data word of DBI. In other words, each byte contains a 20-bit value. When the DWORD register is reset, the value will become 0xAAAAAh. Therefore, the initial value of each check pin is shown in the following table:

[0105] Table 4

[0106] PAR pin location Related DQ data bits PAR initial value PAR[0] DQ[2] 1’b0 PAR[1] DQ

[34] 1’b0 PAR[2] DQ

[66] 1’b0 PAR[3] DQ

[98] 1’b0

[0107] It can be understood that the number of check pins is the same as the number of first data signals. For example, when there are 4 check pins, there are also 4 corresponding first data signals. For example, when the check pins are PAR[0], PAR[1], PAR[2] and PAR[3], the read data are data1, data2, data3 and data4. The first data signal returned by PAR[0] is generated based on the value of the DQ[2] data bit in data1, data2, data3 and data4 respectively. The first data signal returned by PAR[1] is generated based on the value of the DQ

[34] data bit in data1, data2, data3 and data4 respectively. The first data signal returned by PAR[2] is generated based on the value of the DQ

[66] data bit in data1, data2, data3 and data4 respectively. The first data signal returned by PAR[3] is generated based on the value of the DQ

[98] data bit in data1, data2, data3 and data4 respectively.

[0108] S806 , time-shifting each first data signal using a delay circuit so that a target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter.

[0109] Each check pin corresponds to a corresponding delay circuit, which is used to time-shift the data signal returned by the corresponding check pin. Time-shifting refers to moving the data signal in time. Specifically, this can be achieved by adjusting the time delay along the transmission path corresponding to each data signal. The time-shift direction specifically includes a first direction and a second direction, where the first direction refers to the direction of time delay, and the second direction refers to the direction of time advance.

[0110] The target level value may be the first high level of the first data signal, and the alignment of the target level value with the sampling pulse signal means that the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal. The alignment of the first high level of the first data signal with the rising edge of the sampling pulse signal may specifically be at least one of the following: the rising edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal, the falling edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal, and the eye center of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal.

[0111] The first delay parameter is the delay time that aligns the eye center of the first high level in the first data signal after time shift with the sampling pulse signal. That is, when the first data signal is time shifted according to the first delay parameter, the eye center of the first high level in the first data signal after time shift is aligned with the rising edge of the sampling pulse signal.

[0112] refer to Figure 7 , assuming Figure 7 The Data in C is the first data signal received by a certain check pin. The center of the first high-level eye diagram of the first data signal is on the left side of the rising edge of the sampling pulse signal (CLK). Then, the delay circuit corresponding to the check pin shifts the first data signal in the first direction according to the first delay parameter, thereby achieving Figure 7 The eye center of the first high level of the time-shifted first data signal shown in A is aligned with the rising edge of the sampling pulse signal (CLK).

[0113] like Figure 13 FIG. 1 is a schematic diagram of a delay circuit in an embodiment, wherein the delay circuit corresponding to each check pin includes multiple delay elements (DE), each delay element includes four inverter circuits, and each DE includes a tap interface, such as Figure 14 As shown, a step counter can be used to control the data signal to be output from a certain tap outlet, thereby achieving the purpose of time-shifting the data signal, where the time difference between two adjacent tap outlets is one time-shift step. For example, in the initial state, the first data signal of a certain check pin is connected to the i-th tap outlet of the delay circuit. In other words, in the default state, the computer device receives the first data signal from the i-th tap outlet of the delay circuit. When the first data signal needs to be time-shifted in a first direction, the first data signal can be received from the tap outlets after the i+1th tap outlet, thereby achieving the purpose of time-shifting the first data signal in the first direction. When the first data signal needs to be time-shifted in a second direction, the first data signal can be received from the tap outlets after the i-1th tap outlet, thereby achieving the purpose of time-shifting the first data signal in the second direction.

[0114] In one embodiment, S806 specifically includes the following steps: time-shifting each first data signal along a first direction through a delay circuit so that the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter; time-shifting each first data signal along a second direction through a delay circuit so that the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter; the first direction and the second direction are opposite directions; and determining the first delay parameter corresponding to each check pin based on the first time-shift parameter and the second time-shift parameter.

[0115] Regarding time shifting each first data signal along the first direction, the specific process is as follows: after obtaining the first data signal, the computer device sets the corresponding time shift length of each check pin, and returns to execute the step of sending the first data read instruction to the target memory. After receiving the first data signal returned by each check pin, the first data signal is time shifted according to the set time shift length, and it is determined whether the rising edge of the target level value in the first data signal after time shift is aligned with the sampling pulse signal. If the rising edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, the set time shift length is set. The time shift length and the first direction corresponding to each check pin are determined as the first time shift parameter corresponding to each pin; if the rising edge of the target level value in the first data signal corresponding to at least one check pin among the check pins is not aligned with the sampling pulse signal, the time shift length corresponding to the at least one check pin is reset, and the step of sending the first data read instruction to the target memory is returned to be executed until the rising edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, and the time shift length and the first direction corresponding to each check pin when aligned are determined as the first time shift parameter of the corresponding check pin.

[0116] Take one of the calibration pins as an example, refer to Figure 15 , where the data signal corresponding to phase 0 is the first data signal received by the computer device through the i-th (initial default) tap outlet of the delay circuit. That is to say, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. After receiving the first data signal, the computer device Figure 14The delay circuit shown sets the time shift direction of the check pin to the first direction and the time shift length to n time shift steps, that is, the first data signal will be received through the i+nth tap outlet, where n refers to the number of time shifts, and returns to execute the step of sending the first data read instruction to the target memory. After receiving the first data signal returned by each check pin, the first data signal is received through the i+nth tap outlet to obtain the time-shifted first data signal, and it is determined that the rising edge of the target level value of the time-shifted first data signal is aligned with the sampling pulse signal, and the time shift length and first direction corresponding to the check pin during the alignment are determined as the first time shift parameter of the check pin, as shown in FIG. Figure 15 As shown, the data signal corresponding to phase 1 is a first data signal after time shifting obtained after several times of time shifting.

[0117] Regarding time-shifting each first data signal along the second direction, the specific process is as follows: after obtaining the first data signal, the computer device sets a corresponding time shift length for each check pin and returns to the step of sending the first data read instruction to the target memory. After receiving the first data signal returned by each check pin, the computer device time-shifts the first data signal according to the set time shift length and determines whether the falling edge of the target level value in the first data signal after the time shift is aligned with the sampling pulse signal. If the falling edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, the set time shift length and second direction corresponding to each check pin are determined as the second time shift parameter corresponding to each pin. If the falling edge of the target level value in the first data signal corresponding to at least one of the check pins is not aligned with the sampling pulse signal, the time shift length corresponding to the at least one check pin is reset, and the computer device returns to the step of sending the first data read instruction to the target memory until the falling edge of the target level value in the first data signal corresponding to each check pin is aligned with the sampling pulse signal, and the time shift length and second direction corresponding to each check pin when aligned are determined as the second time shift parameter corresponding to the corresponding check pin.

[0118] Take one of the calibration pins as an example, refer to Figure 15 , where the data signal corresponding to phase 0 is the first data signal received by the computer device through the i-th (initial default) tap outlet of the delay circuit. That is to say, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. After receiving the first data signal, the computer device Figure 14The delay circuit shown sets the time shift direction of the check pin to the second direction and the time shift length to n time shift steps, that is, the first data signal is received through the in-th tap outlet, where n refers to the number of time shifts, and returns to execute the step of sending the first data read instruction to the target memory. After receiving the first data signal returned by each check pin, the first data signal is received through the in-th tap outlet to obtain the time-shifted first data signal, and it is determined that the falling edge of the target level value of the time-shifted first data signal is aligned with the sampling pulse signal, and the time shift length corresponding to the check pin during the alignment is determined as the second time shift parameter of the check pin, as shown in FIG. Figure 15 As shown, the data signal corresponding to phase 2 is a first data signal obtained after time shifting for several times.

[0119] In one embodiment, after obtaining the first time shift parameter and the second time shift parameter of any verification pin, the computer device inputs the first time shift parameter and the second time shift parameter into the following formula to determine the first delay parameter of the verification pin:

[0120]

[0121] Among them, V CNT Represents the first delay parameter, R CNT represents the first time shift parameter, L CNT represents the second time shift parameter.

[0122] In the above embodiment, the computer device time-shifts each first data signal along the first direction through the delay circuit so that the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter; time-shifts each first data signal along the second direction through the delay circuit so that the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter; the first direction and the second direction are opposite directions; based on the first time-shift parameter and the second time-shift parameter, the first delay parameter corresponding to each check pin is determined, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined first delay parameter so that the parity check signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby further determining the second delay parameter.

[0123] S808, when receiving the second data signals returned by the check pins in the target memory, time-shift the target data signals in the second data signals through the delay circuit respectively, so that the target level values ​​in the second data signals after the time shift are aligned, and obtain a second delay parameter.

[0124] In one embodiment, after the computer device time-shifts each first data signal through a delay circuit so that the target level value in each first data signal after time shifting is aligned with the sampling pulse signal, it can also send a second data read instruction to the target memory; and receive the second data signal and sampling pulse signal returned by each check pin in the target memory.

[0125] The second data read instruction may be the same as or different from the first data read instruction. The second data signal is generated based on a target data bit in the read data, and the read data is data read from a register of the target memory by the target memory based on the second data read instruction.

[0126] It should be noted that the operating mode of the target memory is the target mode. In the target mode, the data output by each check pin no longer represents the check data of the read data, but returns the value of the target data bit in the read data that is closer to each pin to the corresponding check pin.

[0127] Specifically, after receiving the second data read instruction, the target memory performs a read operation based on the second data read instruction to obtain read data, and returns the value of the target data bit in the read data to the corresponding check pin, and outputs the value of the target data bit as a second data signal through the check pin.

[0128] In one embodiment, after obtaining the second data signal, the computer device may also sample the second data signal that has been time-shifted based on the first delay parameter according to the sampling pulse signal to obtain fourth sampled data. The computer device time-shifts the target data signal in the second data signal through the delay circuit so that the target level values ​​in each second data signal after the time shift are aligned. The process of obtaining the second delay parameter specifically includes the following steps: if the target data bit of the target sampled data in each fourth sampled data is different from the target data bit of other fourth sampled data, determining that the target data signal in the second data signal is not aligned with the target level values ​​in the other second data signals; time-shifting the target data signal in the second data signal through the delay circuit so that the target level values ​​in each second data signal after the time shift are aligned, and obtaining the second delay parameter.

[0129] Specifically, after obtaining the second data signal, the computer device performs an initial time shift on the second data signal according to the first delay parameter through the delay circuit to obtain the second data signal after the initial time shift, and samples the second data signal after the initial time shift according to the sampling pulse signal to obtain fourth sampled data, and searches for target sampled data in which the target data bit of each fourth sampled data is different from the target data bit of other fourth sampled data, determines that the second data signal after the initial time shift corresponding to the target sampled data is not aligned with the second data signals in other initial data signals, and performs a correction time shift on the target data signal in the second data signal after the initial time shift through the delay circuit to align the target level values ​​in each second data signal after the time shift; and determines the time shift length of the target data signal in the correction time shift process as the second delay parameter.

[0130] It should be noted that after the computer device performs an initial time shift on the second data signal corresponding to each check pin according to the first delay parameter through the delay circuit, the center of the eye diagram of the target level value of the second data signal after the initial time shift corresponds to the rising edge of the sampling pulse signal, but the rising edge of the corresponding sampling pulse signal can be a rising edge within the same clock cycle or a rising edge within a different cycle, such as Figure 16 As shown in A, the second data signals corresponding to the four PAR pins PAR[0] to PAR[3] are respectively obtained after the second data signals are initially time-shifted according to the first delay parameters corresponding to the respective PAR pins. Figure 16 The results shown in B are from Figure 16 As can be seen from B, the eye diagram center of the target level value of the second data signal after the initial time shift of PAR[0], PAR[1] and PAR[3] is aligned with the rising edge of the second clock cycle, and the eye diagram center of the target level value of the second data signal after the initial time shift of PAR[2] is aligned with the rising edge of the third clock cycle. After sampling the second data signal after the initial time shift of each PAR[0], PAR[1] and PAR[3] to obtain the fourth sampling data, the target data bit of PAR[0], PAR[1] and PAR[3] is all bit 1, PAR[2] is aligned with the rising edge of the third clock cycle. If the target data bit of the fourth sampling data of PAR[2] is the 2nd bit, the fourth sampling data of PAR[2] is determined to be the target sampling data, and the initial time-shifted second data signal corresponding to the fourth sampling data of PAR[2] is determined to be the target second data signal, then the initial time-shifted second data signal of PAR[2] is corrected and time-shifted by a delay circuit until the target level value in the corrected time-shifted second data signal of PAR[2] is aligned with the target level value of the initial time-shifted second data signal of PAR[0], PAR[1] and PAR[3] (e.g. Figure 16C), and the time shift length and direction of the corrected time shift corresponding to the second data signal after the corrected time shift of PAR[2] are determined as the second delay parameter of PAR[2]. For PAR[0], PAR[1], and PAR[3] that have not undergone the corrected time shift, their second delay parameters can be determined to be 0.

[0131] In one embodiment, after obtaining the second data signal, the computer device performs an initial time shift on the second data signal according to a first delay parameter through a delay circuit to obtain the second data signal after the initial time shift, and samples the second data signal after the initial time shift according to a sampling pulse signal to obtain fourth sampled data. If the target data bits of the respective fourth sampled data are the same, it is determined that the target level values ​​of the second data signals after the initial time shift corresponding to the respective fourth sampled data are aligned, and the second delay parameter corresponding to each check pin is determined to be 0.

[0132] In the above embodiment, the computer device obtains fourth sampled data by sampling each second data signal that has been time-shifted based on the first delay parameter according to the sampling pulse signal; and because the target data bit of the target sampled data in the fourth sampled data is different from the target data bits of the other fourth sampled data, it is determined that the target data signal in the second data signal is not aligned with the target level values ​​in the other second data signals; and the target data signal in the second data signal is time-shifted by the delay circuit so that the target level values ​​in the second data signals after the time shift are aligned to obtain the second delay parameter, thereby determining the sampling delay parameter of each check pin based on the second delay parameter. After subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, thereby ensuring the accuracy of the parity check signal when sampling based on the sampling pulse signal.

[0133] S810 : Determine a sampling delay parameter of a verification pin based on a first delay parameter and a second delay parameter.

[0134] Specifically, after obtaining the first delay parameter and the second delay parameter corresponding to each check pin, the computer device calculates the sum of the corresponding first delay parameter and the second delay parameter, and determines the obtained sum as the sampling delay parameter of the corresponding check pin, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter, so that the time-shifted parity check signal is aligned with the sampling pulse signal, thereby ensuring the correctness of the parity check signal when sampling based on the sampling pulse signal.

[0135] In the above embodiment, the computer device sends a first data read instruction to the target memory; receives the first data signal and sampling pulse signal returned by each check pin in the target memory; time-shifts each first data signal through a delay circuit so that the target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; when receiving the second data signal returned by each check pin in the target memory, time-shifts the target data signal in each second data signal through a delay circuit so that the target level value in each second data signal after the time shift is aligned, thereby obtaining a second delay parameter; based on the first delay parameter and the second delay parameter, determines the sampling delay parameter of the check pin, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, thereby ensuring the accuracy of sampling the parity check signal based on the sampling pulse signal.

[0136] In one embodiment, after obtaining a first data signal, a computer device samples the first data signal according to a sampling pulse signal to obtain first sampled data. The computer device time-shifts each first data signal along a first direction through a delay circuit so that a rising edge of a target level value in each first data signal after the time shift is aligned with a rising edge of the sampling pulse signal. The process of obtaining a first time shift parameter specifically includes the following steps: time-shifting each first data signal along a first direction through a delay circuit; sampling the first data signal time-shifted along the first direction according to the sampling pulse signal to obtain second sampled data; when a value of a target data bit in each second sampled data is the same as a target value corresponding to a target data bit in the first sampled data, determining that a rising edge of a target level value in each first data signal after the time shift is aligned with a rising edge of the sampling pulse signal; and determining a time shift length corresponding to each second sampled data as a first time shift parameter.

[0137] It should be noted that after the computer device obtains the first data signal, it samples the first data signal according to the sampling pulse signal to obtain the first sampled data. The value of the data bit corresponding to the target level value of the first data signal in the obtained first sampled data should be 1. When the rising edge of the target level value in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, that is, when the rising edge of the first high level in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, the value of the corresponding bit data bit obtained by sampling the time-shifted first data signal based on the sampling pulse signal should be 0, as shown in FIG. Figure 15As shown, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. When the first data signal is sampled according to the sampling pulse signal, the value of the first bit in the obtained first sampled data should be 1; the data signal corresponding to phase 1 is the first data signal after time-shifting. When the first data signal after time-shifting is sampled according to the sampling pulse signal, the value of the first bit in the obtained first sampled data should be 0.

[0138] Based on this, in an embodiment of the present application, the data bit corresponding to the target level value of the first data signal in the first sampled data is determined as the target data bit, and the target value corresponding to the target data bit in the first sampled data is set to 0.

[0139] Specifically, after obtaining each first data signal, the computer device samples the first data signal at the rising edge of the sampling pulse signal to obtain each first sampled data, and returns to execute the step of sending the first data read instruction to the target memory, time-shifts each first data signal along the first direction through the delay circuit to obtain each time-shifted first data signal, and samples each time-shifted first data signal at the rising edge of the sampling pulse signal to obtain each second sampled data, and determines whether the value of the target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data. When the value of the target data bit in the second sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the rising edge of the target level value in each time-shifted first data signal is aligned with the rising edge of the sampling pulse signal, and the time shift length and first direction of the time-shifted first data signal corresponding to the second sampled data are determined as the first time shift parameter.

[0140] For example, the target data in the first sampled data obtained by sampling the first data signal of a certain check pin is the second bit, the value of the second bit is 1, and the corresponding target value is 0. Then, after sampling the time-shifted first data signal obtained by time-shifting along the first direction to obtain second sampled data, the value of the second bit in the second sampled data is obtained. If the value of the second bit in the second sampled data is 0, it is determined that the rising edge of the target level value of the time-shifted first data signal obtained by time-shifting along the first direction is aligned with the rising edge of the sampling pulse signal, and the time shift length of the time-shifted first data signal along the first direction and the first direction are determined as the first time shift parameter.

[0141] In the above embodiment, the computer device samples a first data signal according to a sampling pulse signal to obtain first sampled data; time-shifts each first data signal in a first direction using a delay circuit; samples the first data signal time-shifted in the first direction according to the sampling pulse signal to obtain second sampled data; when the value of a target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, aligning the rising edge of the target level value in each first data signal after the time shift with the rising edge of the sampling pulse signal; determining the time shift length corresponding to each second sampled data as a first time shift parameter, and then determining a sampling delay parameter of a check pin based on the first time shift parameter. Subsequently, after receiving the data signal returned by each check pin, i.e., after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter to align the time-shifted parity check signal with the sampling pulse signal, thereby ensuring the accuracy of the parity check signal when sampling based on the sampling pulse signal.

[0142] In one embodiment, when there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the step of sending the first data read instruction to the target memory is returned to execute until the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and the time shift length corresponding to each second sampling data is determined as the first time shift parameter.

[0143] Specifically, the computer device samples each time-shifted first data signal along the first direction at the rising edge of the sampling pulse signal to obtain each second sampled data, and determines whether the value of the target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data. When the value of the target data bit in at least one second sampled data is different from the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the rising edge of the target level value in each time-shifted first data signal corresponding to the at least one second sampled data is not aligned with the rising edge of the sampling pulse signal, and the computer device returns to execute the step of sending the first data read instruction to the target memory until the rising edge of the target level value in each time-shifted first data signal obtained is aligned with the rising edge of the sampling pulse signal, and the time shift length and first direction corresponding to each time-shifted first data signal during the alignment are determined as the first time shift parameter.

[0144] For example, in the first sampled data obtained by sampling the first data signal of a check pin, the target data is the second bit, the value of the second bit is 1, and the corresponding target value is 0. Then, after sampling the time-shifted first data signal obtained by time-shifting along the first direction to obtain second sampled data, the value of the second bit of the second sampled data is obtained. If the value of the second bit of the second sampled data is 1, that is, the value of the second bit of the second sampled data is 1 and is different from the target value 0, it is determined that the rising edge of the target level value of the time-shifted first data signal obtained by time-shifting along the first direction is not aligned with the rising edge of the sampling pulse signal. The process returns to executing the step of sending the first data read instruction to the target memory until the rising edge of the target level value of each time-shifted first data signal is aligned with the rising edge of the sampling pulse signal. The time shift length and first direction corresponding to each time-shifted first data signal during the alignment are determined as the first time shift parameter.

[0145] In the above embodiment, when there is second sampled data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampled data, the computer device returns to the step of sending the first data read instruction to the target memory until the rising edge of the target level value in each first data signal obtained after the time shift is aligned with the rising edge of the sampling pulse signal; the time shift length corresponding to each second sampled data is determined as the first time shift parameter, and then the sampling delay parameter of the check pin can be determined based on the first time shift parameter, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter, so that the parity check signal after the time shift is aligned with the sampling pulse signal, thereby ensuring the correctness of the parity check signal when sampling based on the sampling pulse signal.

[0146] In one embodiment, after obtaining the first data signal, the computer device samples the first data signal according to the sampling pulse signal to obtain first sampled data. The computer device time-shifts each of the first data signals along the second direction through the delay circuit so that the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal. The process of obtaining the second time shift parameter specifically includes the following steps: time-shifting each of the first data signals along the second direction through the delay circuit; sampling the first data signal along the second direction according to the sampling pulse signal to obtain third sampled data; when the value of the target data bit in each of the third sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal; and determining the time shift length corresponding to each of the third sampled data as the second time shift parameter.

[0147] It should be noted that after the computer device obtains the first data signal, it samples the first data signal according to the sampling pulse signal to obtain the first sampled data. The value of the data bit corresponding to the target level value of the first data signal in the obtained first sampled data should be 1. When the falling edge of the target level value in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, that is, when the first high-level falling edge in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, the value of the corresponding bit data bit obtained by sampling the time-shifted first data signal based on the sampling pulse signal should be 0, as shown in FIG. Figure 15 As shown, the data signal corresponding to phase 0 is the first data signal that has not been time-shifted. When the first data signal is sampled according to the sampling pulse signal, the value of the first bit in the obtained first sampled data should be 1; the data signal corresponding to phase 2 is the first data signal after time-shifting. When the first data signal after time-shifting is sampled according to the sampling pulse signal, the value of the first bit in the obtained first sampled data should be 0.

[0148] Based on this, in an embodiment of the present application, the data bit corresponding to the target level value of the first data signal in the first sampled data is determined as the target data bit, and the target value corresponding to the target data bit in the first sampled data is set to 0.

[0149] Specifically, after obtaining each first data signal, the computer device samples the first data signal at the rising edge of the sampling pulse signal to obtain each first sampled data, and returns to execute the step of sending the first data read instruction to the target memory, time-shifts each first data signal along the second direction through the delay circuit to obtain each time-shifted first data signal, and samples each time-shifted first data signal at the rising edge of the sampling pulse signal to obtain each third sampled data. When the value of the target data bit in the third sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the rising edge of the target level value in each time-shifted first data signal is aligned with the rising edge of the sampling pulse signal, and the time shift length and second direction of the time-shifted first data signal corresponding to the third sampled data are determined as the second time shift parameter.

[0150] For example, the target data in the first sampled data obtained by sampling the first data signal of a certain check pin is the second bit, the value of the second bit is 1, and the corresponding target value is 0. Then, after sampling the time-shifted first data signal obtained by time-shifting along the second direction to obtain third sampled data, the value of the second bit in the third sampled data is obtained. If the value of the second bit in the third sampled data is 0, it is determined that the falling edge of the target level value of the time-shifted first data signal obtained by time-shifting along the second direction is aligned with the rising edge of the sampling pulse signal, and the time shift length of the time-shifted first data signal along the second direction and the second direction are determined as the second time shift parameter.

[0151] In the above embodiment, the computer device samples a first data signal according to a sampling pulse signal to obtain first sampled data; time-shifts each first data signal in a second direction using a delay circuit; samples the first data signal in the second direction according to the sampling pulse signal to obtain third sampled data; when the value of a target data bit in each third sampled data is the same as the target value corresponding to the target data bit in the first sampled data, aligning the falling edge of the target level value in each first data signal after the time shift with the rising edge of the sampling pulse signal; determining the time shift length corresponding to each third sampled data as a second time shift parameter, and then determining a sampling delay parameter of a check pin based on the second time shift parameter. Subsequently, after receiving the data signal returned by each check pin, i.e., after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter to align the time-shifted parity check signal with the sampling pulse signal, thereby ensuring the accuracy of the parity check signal when sampling based on the sampling pulse signal.

[0152] In one embodiment, when there is third sampling data whose target data bit value is different from the target value corresponding to the target data bit in the first sampling data, the step of sending the first data read instruction to the target memory is returned to execute until the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and the time shift length corresponding to each third sampling data is determined as the second time shift parameter.

[0153] Specifically, the computer device samples each time-shifted first data signal along the second direction based on the rising edge of the sampling pulse signal to obtain each third sampled data, and determines whether the value of the target data bit in each third sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data. When the value of the target data bit in at least one third sampled data is different from the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the falling edge of the target level value in each time-shifted first data signal corresponding to the at least one third sampled data is not aligned with the rising edge of the sampling pulse signal, and the computer device returns to execute the step of sending the first data read instruction to the target memory until the falling edge of the target level value in each time-shifted first data signal obtained is aligned with the rising edge of the sampling pulse signal, and the time shift length and first direction corresponding to each time-shifted first data signal during the alignment are determined as the second time shift parameter.

[0154] For example, in the first sampled data obtained by sampling the first data signal of a check pin, the target data is the second bit, the value of the second bit is 1, and the corresponding target value is 0. Then, after sampling the time-shifted first data signal obtained by time-shifting along the first direction to obtain third sampled data, the value of the second bit of the third sampled data is obtained. If the value of the second bit of the third sampled data is 1, that is, the value of the second bit of the third sampled data is different from the target value 0, it is determined that the falling edge of the target level value of the time-shifted first data signal obtained by time-shifting along the first direction is not aligned with the rising edge of the sampling pulse signal. The process returns to executing the step of sending the first data read instruction to the target memory until the falling edge of the target level value of each time-shifted first data signal is aligned with the rising edge of the sampling pulse signal. The time shift length and first direction corresponding to each time-shifted first data signal during the alignment are determined as the second time shift parameter.

[0155] In the above embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the computer device returns to the step of sending the first data read instruction to the target memory until the falling edge of the target level value in each first data signal obtained after the time shift is aligned with the rising edge of the sampling pulse signal; the time shift length corresponding to each third sampling data is determined as the second time shift parameter, and then the sampling delay parameter of the check pin can be determined based on the second time shift parameter, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter to align the time-shifted parity check signal with the sampling pulse signal, thereby ensuring the correctness of the parity check signal when sampling based on the sampling pulse signal.

[0156] The present application also provides an application scenario, which uses a method for processing the check pin of a memory. Figure 17 As shown in the system architecture diagram, the application of the memory check pin processing method in this application scenario is as follows:

[0157] Step 1: Set the HBM DRAM operation mode to target mode.

[0158] Specifically, the mode configuration unit of the HBM host sends an operation mode configuration instruction to the HBM DRAM, so that the HBM DRAM is configured to the DWORD read LFSR mode based on the operation mode configuration instruction.

[0159] Step 2: Send a read command to HBM DRAM

[0160] Specifically, the HBM host sends a read instruction to the HBM DRAM through the instruction sending unit. The HBM DRAM parses the received read instruction and inputs the parsing result into the DWORD MISR circuit. The DWORD MISR circuit outputs the read data and returns the target data bits in the read data to the HBM host through the read PAR sending unit.

[0161] Step 3: Receive the read PAR data returned by each PAR pin

[0162] Specifically, the read PAR data signal and the sampling pulse signal (RDQS) returned by each PAR pin are received respectively.

[0163] Step 4: Per PAR training

[0164] Specifically, the read PAR training unit determines whether the eye center of the first high level of each PAR data signal is aligned with the rising edge of the sampling pulse signal (RDQS). If they are aligned, step five is executed. If the eye center of the first high level of at least one read PAR data signal is not aligned with the rising edge of the sampling pulse signal (RDQS), the delay on the PAR path corresponding to the at least one read PAR data signal is adjusted by the read PAR path delay control circuit, and the process returns to step two and step three. After receiving each read PAR data signal, the corresponding read PAR data signal is time-shifted according to the determined delay to determine The eye centers of the first high levels of the time-shifted PAR data signals are aligned with the rising edge of the sampling pulse signal (RDQS). If so, step five is executed. If the eye center of the first high level of at least one time-shifted PAR data signal is not aligned with the rising edge of the sampling pulse signal (RDQS), the delay on the PAR path corresponding to the at least one time-shifted PAR data signal is adjusted using the PAR path delay control circuit. The process then returns to steps two and three until the eye centers of the first high levels of all time-shifted PAR data signals are aligned with the rising edge of the sampling pulse signal (RDQS). The delay corresponding to each PAR pin during the alignment is determined as the first delay parameter.

[0165] For example, as shown in FIG15 , the initial state of the data signal of a PAR pin is phase 0. The data signal of the read PAR in the phase 0 state is sampled based on the pulse signal, and the value of the second bit in the sampled data is 1.

[0166] By continuously increasing the circuit delay corresponding to the PAR pin through the Step Counter, the data signal of the PAR pin will eventually reach the Phase 1 state. The data signal of the PAR read in the Phase 1 state is sampled, and the value of the second bit in the sampled data is 0. At this time, the value of the Step Counter is recorded as R_CNT, which is the first delay parameter of the PAR pin.

[0167] By adjusting the Step Counter to continuously reduce the circuit delay corresponding to the PAR pin, the data signal of the PAR pin eventually reaches the Phase 2 state. The data signal of the PAR read in the Phase 2 state is sampled, and the value of the second bit in the sampled data is 0. At this time, the value of the Step Counter is recorded as L_CNT, which is the second delay parameter of the PAR pin.

[0168] Then, it is concluded that when the circuit delay of the PAR pin is (R_CNT+L_CNT) / 2, the PAR data signal output by the delay circuit of the PAR pin can be aligned with the rising edge of the sampling pulse clock.

[0169] Step 5: Per slice training

[0170] Returning to step 2 and step 3, performing an initial time shift on the read PAR data signal returned by each PAR pin according to the first delay parameter determined in step 4 to obtain an initially time-shifted read PAR data signal. The read PAR training unit determines whether the first high levels of the initially time-shifted read PAR data signals are aligned. If the first high level of at least one initially time-shifted read PAR data signal is not aligned with the first high levels of other initially time-shifted read PAR data signals, the read PAR path delay control circuit adjusts the delay on the PAR path corresponding to the at least one read PAR data signal. Returning to step 2 and step 3, after receiving each read PAR data signal, the first delay parameter is determined according to the determined first delay parameter. Time-shifting a read PAR data signal corresponding to the time-shifted read PAR data signal, time-shifting the other read PAR data signals according to the determined first delay parameter, and determining whether first high levels of the time-shifted read PAR data signals are aligned. If the first high level of at least one time-shifted read PAR data signal is not aligned with the first high levels of other time-shifted read PAR data signals, adjusting the delay on the PAR path corresponding to the at least one read PAR data signal by a read PAR path delay control circuit, and returning to step 2 and step 3 until the first high levels of the time-shifted read PAR data signals are aligned, and determining the delay of each time-shifted read PAR data signal during the alignment as the second delay parameter.

[0171] For example, after receiving the initial time-shifted read PAR data signal through the delay circuit of each PAR pin at this stage, each initial time-shifted read PAR data signal is sampled according to the sampling pulse to obtain each sampled data. If the first "1" data bit in each sampled data is the same, it is determined that the first high level of each initial time-shifted read PAR data signal has been aligned; if the first "1" data bit in at least one sampled data is different from the first "1" data bit in other sampled data (such as Figure 16B), it is determined that the first high level of at least one read PAR data signal after the initial time shift is not aligned with the first high levels of other read PAR data signals after the initial time shift, the delay on the PAR path corresponding to the at least one read PAR data signal is adjusted by the read PAR path delay control circuit, and the process returns to step 2 and step 3 until the first high levels of the read PAR data signals after the time shift are aligned (as shown in FIG. Figure 16 C), and the delay of each time-shifted read PAR data signal during alignment determined in this stage is determined as the second delay parameter.

[0172] The following technical effects can be achieved by using the above memory check pin processing method:

[0173] 1. The mechanism of this application can be used to train the read PAR pins before the HBM chip is brought up for initial operation. This ensures that when the HBM chip is initially operating, if back-end timing does not converge or HBM chip production failures cause sampling errors in the chip's read PAR path, the PAR data returned by the HBM DRAM is accurate, thereby ensuring that the HBM host will not make errors in the read data verification process.

[0174] 2. When the HBM chip detects significant PVT (Process, Voltage, and Temperature) drift, the software configures the chip to train the PAR read pin to ensure that the chip does not cause data transmission errors in the chip's PAR read path due to PVT drift;

[0175] 3. The periodic PAR reading training mechanism included in the hardware can be used to regularly train the HBM chip to ensure that the chip does not have PAR reading sampling errors during operation;

[0176] 4. Since this application supports software-configured single-step PAR read training, software can also be used to configure PAR read training for the entire chip. Since the software can complete this action when the system is not busy, it can ensure that the PAR read pin does not have sampling errors while maintaining the efficiency of the entire system.

[0177] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0178] Based on the same inventive concept, embodiments of the present application also provide a memory check pin processing device for implementing the aforementioned memory check pin processing method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of the one or more memory check pin processing device embodiments provided below can be found in the limitations of the memory check pin processing method described above and will not be further elaborated here.

[0179] In one embodiment, Figure 18 As shown, a memory check pin processing device is provided, comprising: an instruction sending module 1802, a signal receiving module 1804, a signal time shift module 1806 and a delay determination module 1808, wherein:

[0180] The instruction sending module 1802 is configured to send a first data read instruction to the target memory.

[0181] The signal receiving module 1804 is configured to receive the first data signal and the sampling pulse signal returned by each check pin in the target memory.

[0182] The signal time-shift module 1806 is used to time-shift each first data signal through a delay circuit so that the target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; and when receiving the second data signal returned by each check pin in the target memory, time-shift the target data signal in each second data signal through a delay circuit so that the target level value in each second data signal after the time shift is aligned, thereby obtaining a second delay parameter.

[0183] The delay determination module 1808 determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0184] In the above embodiment, a first data read instruction is sent to the target memory; a first data signal and a sampling pulse signal returned by each check pin in the target memory are received; each first data signal is time-shifted by a delay circuit so that the target level value in each first data signal after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; when a second data signal returned by each check pin in the target memory is received, the target data signal in each second data signal is time-shifted by a delay circuit so that the target level value in each second data signal after the time shift is aligned, thereby obtaining a second delay parameter; based on the first delay parameter and the second delay parameter, the sampling delay parameter of the check pin is determined, so that after subsequently receiving the data signal returned by each check pin, that is, after receiving the parity check signal, the parity check signal can be time-shifted according to the determined sampling delay parameter so that the parity check signal after the time shift is aligned with the sampling pulse signal, thereby ensuring the correctness of sampling the parity check signal based on the sampling pulse signal.

[0185] In one embodiment, Figure 19 As shown, the device also includes: a mode configuration module 1810, wherein: the mode configuration module 1810 is used to send an operation mode configuration instruction to the target memory so that the target memory configures the operation mode to the target mode based on the operation mode configuration instruction; the instruction sending module 1802 is also used to: send a first data read instruction to the target memory in the target mode.

[0186] In one embodiment, the mode configuration module 1810 is further configured to: initialize the read instruction processing circuit of the target memory; and configure the operation mode of the read instruction processing circuit to the target mode based on the operation mode configuration instruction.

[0187] In one embodiment, the first data signal is generated based on a target data bit in the read data; the read data is data read from a register of the target memory by the target memory based on a first data read instruction.

[0188] In one embodiment, the signal time-shift module 1806 is further used to: time-shift each first data signal along a first direction through a delay circuit so that the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter; time-shift each first data signal along a second direction through a delay circuit so that the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter; the first direction and the second direction are opposite directions; and based on the first time-shift parameter and the second time-shift parameter, determine the first delay parameter corresponding to each check pin.

[0189] In one embodiment, the signal time-shift module 1806 is further used to: sample the first data signal according to the sampling pulse signal to obtain first sampled data; time-shift each first data signal along the first direction through a delay circuit; sample the first data signal time-shifted along the first direction according to the sampling pulse signal to obtain second sampled data; when the value of the target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determine that the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and determine the time shift length corresponding to each second sampled data as the first time shift parameter.

[0190] In one embodiment, the signal time-shift module 1806 is further used to: when there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, return to the step of sending the first data read instruction to the target memory through the instruction sending module 1802 until the rising edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and determine the time shift length corresponding to each second sampling data as the first time shift parameter.

[0191] In one embodiment, the signal time-shift module 1806 is further used to: sample the first data signal according to the sampling pulse signal to obtain first sampled data; time-shift each first data signal along the second direction through a delay circuit; sample the first data signal along the second direction according to the sampling pulse signal to obtain third sampled data; when the value of the target data bit in each third sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determine that the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and determine the time shift length corresponding to each third sampled data as the second time shift parameter.

[0192] In one embodiment, the signal time-shift module 1806 is further used to: when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, return to the step of sending the first data read instruction to the target memory through the instruction sending module 1802 until the falling edge of the target level value in each first data signal after the time shift is aligned with the rising edge of the sampling pulse signal; and determine the time shift length corresponding to each third sampling data as the second time shift parameter.

[0193] In one embodiment, after time-shifting each first data signal through a delay circuit so that the target level value in each first data signal after time shifting is aligned with the sampling pulse signal, the instruction sending module 1802 is further used to: send a second data read instruction to the target memory; the signal receiving module 1804 is further used to: receive the second data signal and sampling pulse signal returned by each check pin in the target memory.

[0194] In one embodiment, the signal time-shift module 1806 is further used to: sample each second data signal after time-shifting based on the first delay parameter according to the sampling pulse signal to obtain fourth sampled data; if the target data bit of the target sampled data in each fourth sampled data is different from the target data bit of other fourth sampled data, determine that the target data signal in the second data signal is not aligned with the target level values ​​in the other second data signals; and time-shift the target data signal in the second data signal through the delay circuit so that the target level values ​​in each second data signal after the time shift are aligned to obtain the second delay parameter.

[0195] Each module in the aforementioned memory check pin processing device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a computer device's memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0196] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 20 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store parity data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for processing the check pin of the memory is implemented.

[0197] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 21As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface, the display unit and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a memory check pin processing method is implemented. The display unit of the computer device is used to form a visually visible image, and can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse, etc.

[0198] Those skilled in the art will understand that Figure 20 or Figure 21 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0199] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0200] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0201] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0202] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0203] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0204] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0205] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for processing a memory check pin, characterized in that: The method comprises: Sending a first data read instruction to the target memory; receiving a first data signal and a sampling pulse signal returned by each check pin in the target memory; Time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; Sending a second data read instruction to the target memory; receiving a second data signal and a sampling pulse signal returned by each check pin in the target memory; performing an initial time shift on the second data signal according to the first delay parameter via the delay circuit to obtain a second data signal after the initial time shift; sampling the second data signal after the initial time shift according to the sampling pulse signal to obtain fourth sampled data; if a target data bit of a target sampled data in each of the fourth sampled data is different from a target data bit of another fourth sampled data, determining that a target data signal in the second data signal is not aligned with target level values ​​in the other second data signals; performing time shift on the target data signal in the second data signal via the delay circuit so that the target level values ​​in the second data signals after the time shift are aligned to obtain a second delay parameter; Determining a sampling delay parameter of the verification pin based on the first delay parameter and the second delay parameter; Among them, the operating mode of the target memory is the target mode, and the signal output by the check pin of the target memory in the target mode is the value of the corresponding data bit in the read data; the read data is the data obtained by performing a read operation based on a data read instruction; the target level value is the first high level in the signal output by the check pin, and the target data bit is the data bit corresponding to the first high level.

2. The method according to claim 1, characterized in that The method further comprises: Sending an operation mode configuration instruction to the target memory, so that the target memory configures its operation mode to a target mode based on the operation mode configuration instruction; The sending of the first data read instruction to the target memory includes: A first data read instruction is sent to the target memory in the target mode.

3. The method according to claim 2, characterized in that Configuring the operation mode to the target mode based on the operation mode configuration instruction includes: Initializing a read instruction processing circuit of the target memory; Based on the operation mode configuration instruction, the operation mode of the read instruction processing circuit is configured to be the target mode.

4. The method according to claim 1, wherein The step of time-shifting each of the first data signals by a delay circuit so that a target level value in each of the first data signals after the time shift is aligned with the sampling pulse signal to obtain a first delay parameter includes: Time-shifting each of the first data signals along a first direction by the delay circuit so that a rising edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter; time-shifting each of the first data signals along a second direction by the delay circuit so that a falling edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter; the first direction and the second direction are opposite directions; Based on the first time shift parameter and the second time shift parameter, a first delay parameter corresponding to each of the check pins is determined.

5. The method according to claim 4, characterized in that The method further comprises: sampling the first data signal according to the sampling pulse signal to obtain first sampled data; The first data signals are time-shifted in a first direction by the delay circuit so that a rising edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal to obtain a first time-shift parameter, including: Time-shift each of the first data signals along a first direction respectively by the delay circuit; sampling the first data signal time-shifted along the first direction according to the sampling pulse signal to obtain second sampled data; When the value of the target data bit in each of the second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each second sampling data is determined as a first time shift parameter.

6. The method according to claim 5, characterized in that The method further comprises: When there is second sampled data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampled data, returning to the step of sending the first data read instruction to the target memory until the rising edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each second sampling data is determined as a first time shift parameter.

7. The method according to claim 4, characterized in that The method further comprises: sampling the first data signal according to the sampling pulse signal to obtain first sampled data; The method of time-shifting each of the first data signals along the second direction by the delay circuit so that the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal to obtain a second time-shift parameter includes: Time-shift each of the first data signals along a second direction respectively by the delay circuit; sampling the first data signal along the second direction according to the sampling pulse signal to obtain third sampled data; When the value of the target data bit in each of the third sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the falling edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each of the third sampling data is determined as a second time shift parameter.

8. The method according to claim 7, characterized in that The method further comprises: When there is the third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, returning to the step of sending the first data read instruction to the target memory until the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each of the third sampling data is determined as a second time shift parameter.

9. A memory check pin processing device, characterized in that: The device comprises: An instruction sending module, configured to send a first data read instruction to a target memory; A signal receiving module, configured to receive a first data signal and a sampling pulse signal returned by each check pin in the target memory; a signal time-shift module, configured to time-shift each of the first data signals through a delay circuit so that a target level value in each of the first data signals after time-shifting is aligned with the sampling pulse signal, thereby obtaining a first delay parameter; The instruction sending module is further configured to send a second data read instruction to the target memory; The signal receiving module is further configured to receive the second data signal and the sampling pulse signal returned by each check pin in the target memory; The signal time-shifting module is further configured to perform an initial time shift on the second data signal according to the first time delay parameter via the delay circuit to obtain a second data signal after the initial time shift; sample the second data signal after the initial time shift according to the sampling pulse signal to obtain fourth sampled data; if a target data bit of a target sampled data in each of the fourth sampled data is different from a target data bit of other fourth sampled data, determine that a target data signal in the second data signal is not aligned with target level values ​​in other second data signals; and time-shift the target data signal in each of the second data signals via the delay circuit so that the target level values ​​in the second data signals after the time shift are aligned to obtain a second delay parameter; a delay determination module, which determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter; Among them, the operating mode of the target memory is the target mode, and the signal output by the check pin of the target memory in the target mode is the value of the corresponding data bit in the read data; the read data is the data obtained by performing a read operation based on a data read instruction; the target level value is the first high level in the signal output by the check pin, and the target data bit is the data bit corresponding to the first high level.

10. The device according to claim 9, characterized in that The device further comprises: a mode configuration module, configured to send an operation mode configuration instruction to the target memory, so that the target memory configures its operation mode to a target mode based on the operation mode configuration instruction; The instruction sending module is further used for: A first data read instruction is sent to the target memory in the target mode.

11. The device according to claim 10, characterized in that The mode configuration module is also used for: Initializing a read instruction processing circuit of the target memory; Based on the operation mode configuration instruction, the operation mode of the read instruction processing circuit is configured to be the target mode.

12. The device according to claim 9, characterized in that The signal time shift module is also used for: Time-shifting each of the first data signals along a first direction by the delay circuit so that a rising edge of a target level value in each of the first data signals after the time shift is aligned with a rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter; Time-shift each of the first data signals along the second direction by the delay circuit, so that the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter; The first direction and the second direction are opposite directions; Based on the first time shift parameter and the second time shift parameter, a first delay parameter corresponding to each of the check pins is determined.

13. The device according to claim 12, characterized in that The signal time shift module is also used for: sampling the first data signal according to the sampling pulse signal to obtain first sampled data; Time-shift each of the first data signals along a first direction respectively by the delay circuit; sampling the first data signal time-shifted along the first direction according to the sampling pulse signal to obtain second sampled data; When the value of the target data bit in each of the second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each second sampling data is determined as a first time shift parameter.

14. The device according to claim 13, characterized in that The signal time shift module is also used for: When there is second sampled data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampled data, returning to the step of executing the first data read instruction to the target memory by the instruction sending module until the rising edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each second sampling data is determined as a first time shift parameter.

15. The device according to claim 12, characterized in that The signal time shift module is also used for: sampling the first data signal according to the sampling pulse signal to obtain first sampled data; Time-shift each of the first data signals along a second direction respectively by the delay circuit; sampling the first data signal along the second direction according to the sampling pulse signal to obtain third sampled data; When the value of the target data bit in each of the third sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the falling edge of the target level value in each of the first data signals after time shifting is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each of the third sampling data is determined as a second time shift parameter.

16. The device according to claim 15, characterized in that The signal time shift module is also used for: When there is the third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, returning to the step of sending the first data read instruction to the target memory until the falling edge of the target level value in each of the first data signals after the time shift is aligned with the rising edge of the sampling pulse signal; The time shift length corresponding to each of the third sampling data is determined as a second time shift parameter.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

Images