Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, on which a channel structure is formed, including one or more channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and a dummy gate structure spanning the channel structure is further formed on the substrate; performing a first grooving process on the channel structure between adjacent dummy gate structures to form a trench penetrating the channel structure, the first grooving process including one or more sub-grooving processes, and the sub-grooving processes correspond to the channel stacks one by one, and the steps of the sub-grooving process include: removing the channel stack between adjacent dummy gate structures to form a first groove; removing a part of the width of the sacrificial layer exposed on the sidewall of the first groove to form a first inner wall groove communicating with the first groove; forming a first inner wall in the first inner wall groove; after completing the first grooving process, forming a source / drain doping layer in the trench. The size of each first inner wall is adjustable, which is beneficial to meeting different performance requirements for the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has also been continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and drain of the device also decreases, so the control ability of the gate structure over the channel becomes worse, and it becomes more and more difficult to pinch off the channel with the gate voltage, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better meet the requirements of device size scaling, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as Gate-all-around (GAA) transistors. In a Gate-all-around metal gate transistor, the gate surrounds the region where the channel is located from all sides. Compared with planar transistors, the Gate-all-around metal gate transistor has a stronger gate control ability over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a channel structure is formed, the channel structure includes one or more channel stacks, the channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer, a dummy gate structure spanning the channel structure is further formed on the substrate, and the dummy gate structure covers a part of the sidewalls and a part of the top of the channel structure; performing a first grooving process on the channel structure between adjacent dummy gate structures to form a groove penetrating the channel structure, the first grooving process includes one or more sub-grooving processes, and the sub-grooving processes correspond to the channel stacks one by one, wherein the steps of the sub-grooving process include: removing the channel stack between adjacent dummy gate structures to form a first groove; removing a part of the width of the sacrificial layer exposed on the sidewall of the first groove along a direction perpendicular to the sidewall of the dummy gate structure to form a first inner wall groove communicating with the first groove, and the sidewall of the first inner wall groove is recessed inward relative to the sidewall of the first groove; forming a first inner wall in the first inner wall groove; after completing the first grooving process, forming a source / drain doping layer in the groove.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the forming method provided by the embodiment of the present invention, a first grooving process is performed on the channel structure between adjacent pseudo-gate structures to form a groove penetrating the channel structure. The first grooving process includes one or more sub-grooving processes, and the sub-grooving processes correspond one-to-one to the channel stack. Wherein, the steps of the sub-grooving process include: removing the channel stack between adjacent pseudo-gate structures to form a first groove, and removing a partial width of the sacrificial layer exposed on the side wall of the first groove along a direction perpendicular to the side wall of the pseudo-gate structure to form a first inner wall groove communicating with the first groove. The side wall of the first inner wall groove is recessed inward relative to the side wall of the first groove, and a first inner wall is formed in the first inner wall groove. In the embodiment of the present invention, the first grooving process includes one or more sub-grooving processes, so each sub-grooving process is independent, and the sub-grooving processes correspond one-to-one to the channel stack. Therefore, during each sub-grooving process, first inner wall grooves of different sizes can be formed according to actual requirements, so as to form first inner walls of different sizes. That is to say, the size of each first inner wall is adjustable. Moreover, in the steps of each sub-grooving process, after the first inner wall groove is formed, the next sub-grooving process is carried out. Compared with the solution of forming all the first inner wall grooves and then forming the inner walls simultaneously, in the embodiment of the present invention, during the subsequent sub-grooving process, the formed first inner wall can protect the first inner wall groove where it is located. And compared with the solution of using a protective gas in the etching process for protection, the uniformity of the first inner wall is better, ensuring the protective effect of the first inner wall. Therefore, it is beneficial to reduce the probability that the subsequent sub-grooving process affects the size of the already formed first inner wall, and is beneficial to forming first inner wall grooves with more precise morphology and size. In summary, by performing one or more sub-grooving processes to independently control the size of each first inner wall groove, it is beneficial to meet different performance requirements of the semiconductor structure and at the same time beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 5 are schematic structural diagrams corresponding to each step in a forming method of a semiconductor structure;

[0009] Figures 6 to 17 are schematic structural diagrams corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present invention;

[0010] Figures 18 to 21 are schematic structural diagrams corresponding to each step in another embodiment of the forming method of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] Currently, the performance of semiconductor structures needs to be improved. The reason for the need to improve its performance is analyzed in combination with a forming method of a semiconductor structure.

[0012] Figures 1 to 5 It is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] Reference Figure 1 , a substrate 10 is provided, a channel structure 20 is formed on the substrate 10, a compensation layer 30 is formed on the channel structure 20, the channel structure 20 includes one or more channel stacks 21, wherein the channel stack 21 includes a sacrificial layer 22 and a channel layer 23 located on the sacrificial layer 22, a dummy gate structure 40 spanning the channel structure 20 and the compensation layer 30 is further formed on the substrate 10, and the dummy gate structure 40 covers a part of the sidewall and a part of the top of the channel structure 20.

[0014] Reference Figure 2 , the compensation layer 30 and the channel structure 20 between adjacent dummy gate structures 40 are removed to form a trench 26 penetrating the channel structure 20.

[0015] Reference Figure 3 , along a direction perpendicular to the sidewall of the dummy gate structure 40, a part of the width of the sacrificial layer 22 and the compensation layer 30 exposed on the sidewall of the trench 26 is removed to form an inner wall groove 28 communicating with the trench 26.

[0016] Reference Figure 4 , an inner wall 25 is formed in the inner wall groove 28.

[0017] Reference Figure 5 , a source / drain doping layer 50 is formed in the trench 26; after the source / drain doping layer 50 is formed, the dummy gate structure 40 is removed to expose the sacrificial layer 22; the exposed sacrificial layer 22 is removed, and a metal gate structure 60 covering the channel layer 23 is formed at the positions of the dummy gate structure 40 and the sacrificial layer 22.

[0018] After the trench 26 is formed, if all the inner wall grooves 28 are formed uniformly and then the inner wall 25 is formed simultaneously, it is difficult to form the inner wall grooves 28 of different sizes according to actual requirements, and thus it is difficult to form the inner walls 25 of different sizes. That is to say, the sizes of the inner walls 25 are difficult to be adjusted independently. Moreover, during the process of forming the subsequent inner wall grooves 28, it is difficult to accurately control the size and morphology of the formed inner wall grooves 28 by using a protective gas in the etching process, and at the same time, it also results in poor uniformity of the inner walls formed in the inner wall grooves 28, thereby making it difficult to improve the performance of the semiconductor structure.

[0019] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a channel structure is formed, the channel structure includes one or more channel stacks, each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer, a dummy gate structure spanning the channel structure is further formed on the substrate, and the dummy gate structure covers a part of the sidewalls and a part of the top of the channel structure; performing a first grooving process on the channel structure between adjacent dummy gate structures to form a groove penetrating the channel structure, the first grooving process includes one or more sub-grooving processes, and the sub-grooving processes correspond to the channel stacks one by one, wherein the steps of the sub-grooving process include: removing the channel stack between adjacent dummy gate structures to form a first groove; removing a part of the width of the sacrificial layer exposed on the sidewall of the first groove along a direction perpendicular to the sidewall of the dummy gate structure to form a first inner wall groove communicating with the first groove, and the sidewall of the first inner wall groove is recessed inward relative to the sidewall of the first groove; forming a first inner wall in the first inner wall groove; after completing the first grooving process, forming a source / drain doping layer in the groove.

[0020] In the formation method provided by the embodiments of the present invention, a first grooving process is performed on the channel structure between adjacent pseudo-gate structures to form a groove penetrating the channel structure. The first grooving process includes one or more sub-grooving processes, and the sub-grooving processes correspond one-to-one with the channel stacks. Wherein, the steps of the sub-grooving process include: removing the channel stack between adjacent pseudo-gate structures to form a first groove, and removing a part of the width of the sacrificial layer exposed on the side wall of the first groove along the direction perpendicular to the side wall of the pseudo-gate structure to form a first inner wall groove communicating with the first groove. The side wall of the first inner wall groove is recessed inward relative to the side wall of the first groove, and a first inner wall is formed in the first inner wall groove; in the embodiments of the present invention, the first grooving process includes one or more sub-grooving processes, then each sub-grooving process is independent, and the sub-grooving processes correspond one-to-one with the channel stacks. Therefore, during each sub-grooving process, first inner wall grooves of different sizes can be formed according to actual needs, so as to form first inner walls of different sizes. That is to say, the size of each first inner wall is adjustable. Moreover, in the steps of each sub-grooving process, after the first inner wall groove is formed, the next sub-grooving process is carried out. Compared with the scheme of forming all the first inner wall grooves and then forming the inner walls simultaneously, in the embodiments of the present invention, when the subsequent sub-grooving process is carried out, the formed first inner wall can protect the first inner wall groove where it is located. And compared with the scheme of using a protective gas in the etching process for protection, the uniformity of the first inner wall is better, ensuring the protective effect of the first inner wall, which is beneficial to reducing the probability that the subsequent sub-grooving process affects the size of the formed first inner wall, and is beneficial to forming first inner wall grooves with more accurate topography and size. In summary, by performing one or more sub-grooving processes to independently control the size of each first inner wall groove, it is beneficial to meet different performance requirements of the semiconductor structure and is also beneficial to improving the performance of the semiconductor structure.

[0021] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0022] Figures 6 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of the formation method of the semiconductor structure of the present invention.

[0023] Reference Figure 6, a substrate 100 is provided, on which a channel structure 200 is formed. The channel structure 200 includes one or more channel stacks 210, and each channel stack 210 includes a sacrificial layer 220 and a channel layer 230 located on the sacrificial layer 220. A dummy gate structure 400 spanning the channel structure 200 is also formed on the substrate 100, and the dummy gate structure 400 covers a part of the sidewalls and a part of the top of the channel structure 200.

[0024] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure includes a gate-all-around (GAA) transistor. The gate-all-around transistor includes a nanosheet FET or a nanowire FET.

[0025] The substrate 100 includes a substrate (not labeled).

[0026] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0027] It should be noted that the substrate 100 may further include: fins (not labeled), located on the substrate.

[0028] The channel structure 200 is used to form the channel layer 230, and the channel layer 230 is used as the channel of the semiconductor structure. The sacrificial layer 220 is used to provide a process basis for the subsequent suspension of the channel layer 230 and also to occupy the spatial position for the device gate structure formed subsequently. In the subsequent manufacturing process, the sacrificial layer 220 is removed, so that the channel layer 230 is suspended, and a device gate structure is formed between the channel layer 230 and the substrate 100 and between adjacent channel layers 230.

[0029] The top and sidewalls of the channel layer 230 covered by the device gate structure are used as the channel. In this embodiment, the top, bottom, and sidewalls of the channel layer 230 can all be used as the channel, increasing the area of the channel layer 230 used as the channel, thereby increasing the operating current of the semiconductor structure.

[0030] In this embodiment, the material of the channel layer 230 includes silicon. In other embodiments, the material of the channel layer can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide.

[0031] It should be noted that, in this embodiment, the materials of the channel layer 230 and the substrate 100 are the same. In other embodiments, the materials of the channel layer and the substrate may also be different.

[0032] In this embodiment, the material of the sacrificial layer 220 includes silicon germanide.

[0033] The silicon germanide and silicon can form a large etching selectivity, which is beneficial to the subsequent removal of the sacrificial layer 220 and reduces the damage to the channel layer 230.

[0034] In other embodiments, according to the material of the channel layer, a suitable material with an etching selectivity to the channel layer can be selected to reduce the damage to the channel layer when removing the sacrificial layer subsequently.

[0035] In this embodiment, in the step of providing the substrate 100, a compensation layer 300 is further formed on the channel structure 200, and the dummy gate structure 400 covers a part of the sidewall and a part of the top of the compensation layer 300.

[0036] The compensation layer 300 is used to occupy a spatial position for increasing the height of the device gate structure formed subsequently.

[0037] In this embodiment, the material of the compensation layer 300 is the same as the material of the sacrificial layer 220, which is beneficial to simplifying the forming process. And since a part of the compensation layer 300 and the sacrificial layer 220 need to be removed subsequently, it is beneficial to remove the compensation layer 300 and the sacrificial layer 220 in the same step and simplify the removal process.

[0038] Specifically, the material of the compensation layer 300 includes silicon germanide.

[0039] The silicon germanide and silicon can form a large etching selectivity, which is beneficial to the subsequent removal of the compensation layer 300 and reduces the damage to the channel layer 230.

[0040] In this embodiment, in the step of providing the substrate 100, an isolation layer 110 is further formed between the substrate 100 and the channel structure 200. Specifically, the isolation layer 110 is located between the channel structure 200 and the fin.

[0041] In this embodiment, the isolation layer 110 is used to insulate the channel structure 200 from the substrate 100, thereby achieving the effect of suppressing leakage.

[0042] The material of the isolation layer 110 is an insulating material. As an example, the material of the isolation layer 110 is silicon oxide.

[0043] In this embodiment, in the step of providing the substrate 100, a spacer layer 410 is further formed on the sidewalls of the dummy gate structure 400, and the spacer layer 410 also covers the top of the channel structure 200.

[0044] The spacer layer 410 is used to protect the sidewalls of the gate structure after the device gate structure is formed subsequently.

[0045] The spacer layer 410 can be a single-layer structure or a stacked-layer structure, and the material of the spacer layer 410 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the spacer layer 410 is a single-layer structure, and the material of the spacer layer 410 is silicon nitride.

[0046] In this embodiment, in the step of forming the spacer layer 410, the spacer layer 410 conformally covers the dummy gate structure 400 and the channel structure 200.

[0047] The dummy gate structure 400 is used to occupy a spatial position for the subsequent formation of the device gate structure.

[0048] Specifically, the dummy gate structure 400 is a stacked-layer structure, including a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) covering the dummy gate oxide layer.

[0049] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0050] With reference to Figures 7 to 13 a first grooving process is performed on the channel structure 200 between adjacent dummy gate structures 400 to form a trench 260 penetrating through the channel structure 200. The first grooving process includes one or more sub-grooving processes, and the sub-grooving processes correspond one-to-one to the channel stack 210. Wherein, the steps of the sub-grooving process include: removing the channel stack 210 between adjacent dummy gate structures 400 to form a first groove 270; removing a partial width of the sacrificial layer 220 exposed on the sidewalls of the first groove 270 along a direction perpendicular to the sidewalls of the dummy gate structure 400 to form a first inner sidewall groove 280 communicating with the first groove 270, and the sidewalls of the first inner sidewall groove 280 are recessed inward relative to the sidewalls of the first groove 270; forming a first inner sidewall 250 in the first inner sidewall groove 280.

[0051] In an embodiment of the present invention, the first grooving process includes one or more sub - grooving processes. Each sub - grooving process is independent, and the sub - grooving process corresponds one - to - one with the channel stack 210. Therefore, during each sub - grooving process, first inner wall grooves 280 of different sizes can be formed according to actual requirements, thereby forming first inner walls 250 of different sizes. That is to say, the size of each first inner wall 250 is adjustable. Moreover, in each step of the sub - grooving process, after the first inner wall groove 280 is formed, the next sub - grooving process is carried out. Compared with the scheme of forming all the first inner wall grooves and then forming the inner walls simultaneously, in the subsequent sub - grooving process of the embodiment of the present invention, the formed first inner wall 250 can protect the corresponding first inner wall groove 280. And compared with the scheme of using a protective gas in the etching process for protection, the uniformity of the first inner wall 250 is better, ensuring the protective effect of the first inner wall 250. Thus, it is beneficial to reduce the probability that the subsequent sub - grooving process affects the size of the already formed first inner wall 250, and is beneficial to forming first inner wall grooves 280 with more accurate topography and size. In summary, by performing one or more sub - grooving processes, it is beneficial to meet different performance requirements of the semiconductor structure and improve the performance of the semiconductor structure at the same time.

[0052] In this embodiment, during the sub - grooving process, the first groove 270, the first inner wall groove 280, and the first inner wall 250 are formed in the same device.

[0053] Forming the first groove 270, the first inner wall groove 280, and the first inner wall 250 in the same device simplifies the process operation flow, improves the process efficiency, saves the process cost, and is beneficial for the formed first inner wall 250 to protect the corresponding first inner wall groove 280.

[0054] Therefore, the device has both etching and deposition functions, and the deposition process is added to the etching process, so that etching and deposition are completed in the same process.

[0055] The following describes the steps of the sub - grooving process in detail with reference to the accompanying drawings.

[0056] With reference to Figures 7 to 11 , the channel stack 210 between adjacent pseudo - gate structures 400 is removed to form the first groove 270.

[0057] The first groove 270 is used to expose the sacrificial layer 220, preparing for removing a part of the width of the sacrificial layer 220.

[0058] In addition, a plurality of vertically connected first grooves 270 are used to form a trench 260, thereby providing a spatial position for the subsequent formation of the source-drain doping layer. Herein, the vertical direction refers to the height direction of the channel structure 200.

[0059] In this embodiment, during the sub-grooving process, the channel stack 210 between adjacent pseudo-gate structures 400 is removed by a dry etching process.

[0060] Since the dry etching process has the characteristic of anisotropic etching, when removing the channel stack 210 between adjacent pseudo-gate structures 400, it is beneficial to reduce the damage to the channel stack 210 on the sidewalls of the first groove 270. Moreover, the dry etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first groove 270.

[0061] Reference Figure 9 , a part of the width of the sacrificial layer 220 exposed on the sidewall of the first groove 270 is removed along the direction perpendicular to the sidewall of the pseudo-gate structure 400, forming a first inner wall groove 280 communicating with the first groove 270. The sidewall of the first inner wall groove 280 is recessed inward relative to the sidewall of the first groove 270.

[0062] The first inner wall groove 280 is used to provide a spatial position for forming the first inner wall 250.

[0063] In this embodiment, during the sub-grooving process, an isotropic dry etching process is used to remove a part of the width of the sacrificial layer 220 exposed on the sidewall of the first groove 270.

[0064] The isotropic dry etching process has a high lateral etching rate, which can perform better lateral etching to remove a part of the width of the sacrificial layer 220 exposed on the sidewall of the first groove 270. Moreover, compared with the wet etching process, the dry etching process can better control the process parameters, has a higher process controllability, and is easy to obtain a more accurate pattern transfer.

[0065] Moreover, by using the dry etching process, it is convenient to form the first groove 270, the first inner wall groove 280, and the first inner wall 250 in the same device.

[0066] Combined with reference Figure 10 and Figure 11 , a first inner wall 250 is formed in the first inner wall groove 280.

[0067] The first inner wall 250 is used to isolate the device gate structure and the source-drain doping layer after the subsequent formation of the device gate structure and the source-drain doping layer, so as to reduce the parasitic capacitance between the device gate structure and the source-drain doping layer.

[0068] The material of the first inner wall 250 is an insulating material. In this embodiment, the material of the first inner wall 250 includes silicon oxide.

[0069] The silicon oxide can play a good isolation role, and by using silicon oxide, it is beneficial to be compatible with the processes of forming the first inner wall groove 280 and the first inner wall 250 in the same device.

[0070] In other embodiments, according to process requirements, the first inner wall groove and the first inner wall can also be formed in different devices respectively. Correspondingly, other suitable materials can also be selected for the material of the first inner wall.

[0071] Specifically, referring to Figure 10 , in the process of the sub-grooving treatment, the steps of forming the first inner wall 250 in the first inner wall groove 280 include: forming a first inner wall material layer 240 in the first groove 270 and the first inner wall groove 280.

[0072] The first inner wall material layer 240 is used to form the first inner wall 250.

[0073] The material of the first inner wall material layer 240 includes silicon oxide, which is beneficial to directly form the first inner wall 250.

[0074] In this embodiment, in the step of forming the first inner wall material layer 240, the first inner wall material layer 240 conformally covers the bottom of the first groove 270 and each surface of the first inner wall groove 280.

[0075] The first inner wall material layer 240 conformally covers the bottom of the first groove 270 and each surface of the first inner wall groove 280, that is, the first inner wall material layer 240 fills the first groove 270 and the first inner wall groove 280 located in the sacrificial layer 220. As the material of the first inner wall material layer 240 is continuously deposited, it is beneficial to fill the first inner wall groove 280 completely, reducing the probability of void defects in the formed first inner wall 250.

[0076] As an example, the first inner wall material layer 240 also fills the first groove 270 completely.

[0077] In this embodiment, the atomic layer deposition process is used to form the first inner wall material layer 240.

[0078] The thickness uniformity of the first inner wall material layer 240 formed by the atomic layer deposition process is good, and it has good step coverage ability, enabling the first inner wall material layer 240 to conformally cover the bottom of the first groove 270 and the surfaces of the first inner wall groove 280 well until the first inner wall groove 280 is filled, thereby improving the formation quality of the subsequent first inner wall 250.

[0079] In this embodiment, the equipment used for the sub-grooving process has the function of realizing atomic layer deposition. Therefore, by adopting the atomic layer deposition process, the first groove 270, the first inner wall groove 280, and the first inner wall 250 are formed in the same equipment.

[0080] Reference Figure 11 , the first inner wall material layer 240 located in the first groove 270 is removed, and the first inner wall material layer 240 located in the first inner wall groove 280 is retained as the first inner wall 250.

[0081] The first inner wall material layer 240 located in the first groove 270 is removed to expose the channel stack 210 at the bottom of the first groove 270, for preparing for the next sub-grooving process.

[0082] In this embodiment, the first inner wall material layer 240 located in the first groove 270 is removed by a dry etching process.

[0083] The dry etching process has the characteristic of anisotropic etching. When removing the first inner wall material layer 240 located in the first groove 270, it is beneficial to reduce the damage to the first inner wall 250 located in the first inner wall groove 280, and the dry etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first inner wall 250.

[0084] It should be noted that Figures 9 to 11 only the process of forming one first inner wall 250 is shown, that is, the process of performing one sub-grooving process. To form multiple first inner walls 250, only need to continue to repeat Figures 9 to 11 the steps after forming the first inner wall 250. Reference Figure 12 , Figure 12 shows the first inner wall 250 formed after all sub-grooving processes are completed, that is, after the first grooving process is completed.

[0085] Reference Figure 13The step of forming the trench 260 that penetrates the channel structure 200 further includes: after completing the first grooving process, performing a second grooving process on the isolation layer 110 exposed in the first groove 270, removing a partial thickness of the isolation layer 110 exposed in the first groove 270, so that the bottom of the trench 260 extends into the isolation layer 110.

[0086] In the step of forming the trench 260 that penetrates the channel structure 200, the first grooving process is sequentially performed on the channel structure 200 between adjacent pseudo-gate structures 400, and the second grooving process is performed on the isolation layer 110, removing a partial thickness of the isolation layer 110 exposed in the first groove 270, further ensuring that the trench 260 completely penetrates the channel structure 200. At the same time, the remaining isolation layer 110 is also used to isolate the source-drain doping layer formed in the trench 260 from the substrate 100 subsequently.

[0087] Specifically, the remaining isolation layer 110 is used to isolate the source-drain doping layer formed in the trench 260 from the fin in the substrate 100 subsequently.

[0088] In this embodiment, in the same device, the first grooving process and the second grooving process are sequentially performed, simplifying the process operation flow, improving the process efficiency, and saving the process cost.

[0089] Wherein, the device has the functions of etching and deposition at the same time. Therefore, the first grooving process and the second grooving process can be sequentially performed in the same device.

[0090] In this embodiment, a dry etching process is used for the second grooving process.

[0091] The dry etching process has the characteristic of anisotropic etching. Then, when removing a partial thickness of the isolation layer 110 exposed in the first groove 270, it is beneficial to reduce the damage to the isolation layer 110, the substrate 100, and the first inner sidewall 250 located on the sidewall of the trench 260. Moreover, the dry etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the trench 260.

[0092] Combined with reference Figure 7 and Figure 8 The step of forming the trench 260 that penetrates the channel structure 200 further includes: before performing the first grooving process, performing a third grooving process on the compensation layer 300 between adjacent pseudo-gate structures 400, removing the compensation layer 300 between adjacent pseudo-gate structures 400, and exposing the top of the channel structure 200.

[0093] The compensation layer 300 between the adjacent dummy gate structures 400 is removed to expose the top of the channel structure 200 in preparation for the first trenching process.

[0094] In this embodiment, the third grooving process and the second grooving process are performed sequentially in the same device.

[0095] In the same device, the third slotting process and the second slotting process are performed sequentially, which simplifies the process operation flow, improves the process efficiency, and saves the process cost.

[0096] Specifically, in this embodiment, the steps of the third groove processing include: removing the compensation layer 300 between adjacent pseudo gate structures 400 to form a second groove 310; removing the partial width of the compensation layer 300 exposed on the side wall of the second groove 310 to form a second inner wall groove 320 connected to the second groove 310, and the side wall of the second inner wall groove 320 is recessed inward relative to the side wall of the second groove 310; forming a first inner wall 250 in the second inner wall groove 320.

[0097] The first inner sidewall 250 is formed in the second inner sidewall groove 320 to enhance the isolation effect of the device gate structure and the source-drain doping layer after the device gate structure and the source-drain doping layer are subsequently formed.

[0098] In this embodiment, the compensation layer 300 between adjacent dummy gate structures 400 is removed by dry etching, which is beneficial to reduce damage to the compensation layer 300 located on the sidewall of the second groove 310, thereby facilitating the size control of the subsequent formation of the second inner sidewall groove 320.

[0099] In this embodiment, an isotropic dry etching process is used to remove the partial width of the compensation layer 300 exposed by the side wall of the second groove 310. The isotropic dry etching process has a high lateral etching rate and can better perform lateral etching to remove the partial width of the compensation layer 320 exposed by the side wall of the second groove 310. The isotropic dry etching process can better control the process parameters and obtain more accurate graphic conversion.

[0100] The description of forming the second inner sidewall groove 320 can be combined with reference to the corresponding description of forming the first inner sidewall, which will not be repeated here.

[0101] In this embodiment, during the third grooving process, the steps of forming the first inner wall 250 in the second inner wall groove 320 include: forming a first inner wall material layer (not shown) in the second groove 310 and the second inner wall groove 320; removing the first inner wall material layer located in the second groove 310, and retaining the first inner wall material layer located in the second inner wall groove 320 as the first inner wall 250.

[0102] In this embodiment, the first inner wall material layer 240 is formed by atomic layer deposition process, and the first inner wall material layer 240 located in the second groove 310 is removed by dry etching process. The method of forming the first inner wall 250 in the second inner wall groove 320 is similar to the method of forming the first inner wall 250 in the first inner wall groove 280 described above, and will not be elaborated here.

[0103] Continue to refer to Figure 7 , in this embodiment, before the first grooving process, it further includes: removing the sidewall layer 410 on the top of the channel structure 200 between adjacent pseudo-gate structures 400.

[0104] Specifically, before the third grooving process, the sidewall layer 410 on the top of the channel structure 200 between adjacent pseudo-gate structures 400 is removed.

[0105] After forming the sidewall layer 410, the sidewall layer 410 on the top of the channel structure 200 between adjacent pseudo-gate structures 400 is removed to prepare for the third grooving process and the first grooving process. At the same time, the sidewall layer 410 on the top of the pseudo-gate structure 400 is also removed to expose the top of the pseudo-gate structure 400, which is used to prepare for the subsequent removal of the pseudo-gate structure.

[0106] Refer to Figure 14 , after completing the first grooving process, a source / drain doping layer 500 is formed in the trench 260.

[0107] The source / drain doping layer 500 is used as the source region or drain region of the transistor, and the doping type of the source / drain doping layer 500 is the same as the channel conduction type of the corresponding transistor.

[0108] Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doping layer 500 are N-type ions, and the N-type ions include P ions, As ions or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source / drain doping layer 500 are P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0109] In this embodiment, a source-drain doping layer 500 is formed in the trench 260 through an epitaxial growth process.

[0110] Reference Figure 15 , after forming the source-drain doping layer 500, it further includes: forming an interlayer dielectric layer 700 on the substrate 100 to cover the sidewalls of the dummy gate structure 400 and the channel structure 200, and the top of the dummy gate structure 400 is exposed by the interlayer dielectric layer 700.

[0111] The interlayer dielectric layer 700 is used to isolate adjacent devices, and the interlayer dielectric layer 700 also provides a platform basis for forming a gate opening by removing the dummy gate structure 400 subsequently.

[0112] The material of the interlayer dielectric layer 700 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride.

[0113] In this embodiment, after forming the interlayer dielectric layer 700, it further includes: removing the dummy gate structure 400 and forming a gate opening 510 in the interlayer dielectric layer 700.

[0114] The gate opening 510 provides a spatial position for forming a device gate structure subsequently.

[0115] Reference Figure 16 , removing the sacrificial layer 220 exposed by the gate opening 510 to form a through groove 520 communicating with the gate opening 510.

[0116] The through groove 520 provides a spatial position for forming a device gate structure subsequently, and the top, bottom, and sidewalls of the channel layer 230 are exposed by the through groove 520, so that the device gate structure formed subsequently surrounds and covers the channel layer 230.

[0117] Reference Figure 17 , forming a device gate structure 600 in the gate opening 510 and the through groove 520, and the device gate structure 600 covers the channel layer 230.

[0118] The device gate structure 600 is used to control the opening or closing of the channel of the transistor.

[0119] Since the device gate structure 600 covers the channel layer 230, the top, bottom, and sidewalls of the channel layer 230 can all serve as channels, increasing the area of the channel layer 230 used as a channel, thereby increasing the working current of the semiconductor structure.

[0120] In this embodiment, the device gate structure 600 is a metal gate structure.

[0121] In this embodiment, the metal gate structure includes a high-k gate dielectric layer (not labeled), a work function layer (not labeled) located on the high-k gate dielectric layer, and a gate electrode layer (not labeled) located on the work function layer.

[0122] The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0123] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0124] The gate electrode layer is used to lead out the electrical property of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Au, Pt, Ni, Ti, or W.

[0125] In some other embodiments, according to process requirements, the device gate structure can also be a polysilicon gate structure.

[0126] Figures 18 to 21 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0127] The same parts of this embodiment and the previous embodiment will not be described in detail here. The difference between this embodiment and the previous embodiment is that the first inner sidewall 251 is removed, and a second inner sidewall 252 is formed in the first inner sidewall groove 281.

[0128] Combined with reference to Figures 18 to 21 , after completing the first grooving process and before forming a source / drain doping layer (not shown) in the trench 261, it further includes: removing the first inner sidewall 251 to expose the first inner sidewall groove 281; after removing the first inner sidewall 251, forming a second inner sidewall 252 in the first inner sidewall groove 281.

[0129] According to actual requirements, it is necessary to form the second inner sidewall 252 of the required material (for example, a material with a relatively small dielectric constant). However, part of the material (for example, a material with a relatively small dielectric constant) is difficult to be used in the first grooving process. Therefore, the first inner sidewall 251 compatible with the process of the first grooving process can be formed first to occupy the space position for forming the second inner sidewall 252.

[0130] Moreover, by forming the first inner sidewall 251 to be removed first, a material with a higher etching resistance can be selected to ensure the protective effect of the first inner sidewall 251 on the first inner sidewall groove 281.

[0131] In addition, the formed second inner sidewall 252 has not experienced the etching process in the first grooving process, and the probability of damage to the second inner sidewall 252 is greatly reduced, and its quality and performance are correspondingly guaranteed.

[0132] It should be noted that as Figure 18 shown, since the first inner sidewall 251 needs to be removed, when the first inner sidewall 251 is formed, the first inner sidewall material layer (not shown) conformally covers the bottom of the first groove (not shown) and each surface of the first inner sidewall groove 281. Correspondingly, the first inner sidewall 251 conformally covers each surface of the first inner sidewall groove 281, and the first inner sidewall 251 does not completely fill the first inner sidewall groove.

[0133] Specifically, the thickness of the first inner sidewall 251 satisfies that the thickness of the first inner sidewall 251 is sufficient to protect the first inner sidewall groove.

[0134] Among them, compared with the scheme in which the first inner sidewall material layer completely fills the first groove and the first inner sidewall groove (that is, the first inner sidewall completely fills the first inner sidewall groove), in this embodiment, the thickness of the first inner sidewall 251 is smaller, thereby reducing the difficulty of removing the first inner sidewall 251.

[0135] In addition, since the first inner sidewall 251 is formed on each surface of the first inner sidewall groove 281 in a conformal coverage manner, its thickness uniformity is better. Even if the first inner sidewall 251 does not completely fill the first inner sidewall groove 281, the protective effect of the first inner sidewall 251 on the first inner sidewall groove 281 can still be guaranteed.

[0136] In other embodiments, the first inner sidewall can also completely fill the first inner sidewall groove.

[0137] In this embodiment, a wet etching process is used to remove the first inner sidewall 251.

[0138] The wet etching process has an isotropic characteristic, which is beneficial to completely removing the first inner sidewall 251. At the same time, the wet etching process has good etching selectivity, which is beneficial to reducing the damage to other film layers when removing the first inner sidewall 251.

[0139] As an example, the material of the first inner sidewall 251 is silicon oxide, and a diluted hydrofluoric acid solution is correspondingly used to remove the first inner sidewall 251.

[0140] In this embodiment, in the step of forming the second inner sidewall 252 in the first inner sidewall groove 281, the dielectric constant of the material of the second inner sidewall 252 is less than the dielectric constant of the material of the first inner sidewall 251. The low-k dielectric material has a relatively low dielectric constant, thereby further reducing the parasitic capacitance between the device gate structure and the source-drain doping layer.

[0141] In this embodiment, the material of the second inner sidewall 252 includes a low-k dielectric material, where the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9.

[0142] Specifically, with reference to Figure 19 and Figure 20 , the step of forming the second inner sidewall 252 in the first inner sidewall groove 281 includes: after removing the first inner sidewall 251, forming a second inner sidewall material layer 242 in the trench 261 and the first inner sidewall groove 281.

[0143] The second inner sidewall material layer 242 is used to form the second inner sidewall 252.

[0144] The material of the second inner sidewall material layer 242 includes a low-k dielectric material, which is beneficial to directly forming the second inner sidewall 252.

[0145] In this embodiment, in the step of forming the second inner sidewall material layer 242, the second inner sidewall material layer 242 conformally covers the bottom and sidewalls of the trench 261 and each surface of the first inner sidewall groove 281.

[0146] The second inner sidewall material layer 242 conformally covers the bottom and sidewalls of the trench 261 and each surface of the first inner sidewall groove 281, that is, the second inner sidewall material layer 242 fills the trench 261 and the first inner sidewall groove 281. As the material of the second inner sidewall material layer 242 is continuously deposited, it is beneficial to fill the first inner sidewall groove 281 completely, reducing the probability of void defects in the formed second inner sidewall 252.

[0147] As an example, the second inner sidewall material layer 242 also fills the trench 261 completely.

[0148] In this embodiment, the second inner sidewall material layer 242 is formed by an atomic layer deposition process.

[0149] The second inner sidewall material layer 242 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the second inner sidewall material layer 242 can conformally cover the bottom and sidewalls of the trench 261 and the surfaces of the first inner sidewall groove 281 well until the first inner sidewall groove 280 is filled, thereby improving the formation quality of the subsequent first inner sidewall 250.

[0150] Reference Figure 20 , the second inner sidewall material layer 242 located in the trench 261 is removed, and the second inner sidewall material layer 242 located in the first inner sidewall groove 281 is retained as the second inner sidewall 252.

[0151] The second inner sidewall material layer 242 located in the trench 261 is removed to expose the trench 261, which is used to prepare for the subsequent formation of the source-drain doping layer.

[0152] In this embodiment, the second inner sidewall material layer 242 located in the trench 261 is removed by a dry etching process.

[0153] The dry etching process has the characteristics of anisotropic etching. When removing the second inner sidewall material layer 242 located in the trench 261, it is beneficial to reduce the damage to the sidewall film layer of the trench 261, and the dry etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the trench 261.

[0154] It should be noted that the specific description of the process for forming the second inner sidewall 252 is similar to the process for forming the first inner sidewall 251 in the foregoing embodiment, and can be combined with the corresponding description in the foregoing embodiment, which will not be elaborated here.

[0155] For the specific description of the forming method described in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, which will not be elaborated here.

[0156] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, on which a channel structure is formed. The channel structure includes a plurality of channel stacks, and each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer. A dummy gate structure spanning the channel structure is also formed on the substrate, and the dummy gate structure covers a part of the sidewalls and a part of the top of the channel structure. Performing a first grooving process on the channel structure between adjacent dummy gate structures to form a groove penetrating the channel structure. The first grooving process includes multiple sub-grooving processes, and the sub-grooving processes correspond one by one to the channel stacks. Wherein, the steps of the sub-grooving process include: removing the channel stack between adjacent dummy gate structures to form a first groove; removing a part of the width of the sacrificial layer exposed on the sidewall of the first groove along a direction perpendicular to the sidewall of the dummy gate structure to form a first inner wall groove communicating with the first groove, and the sidewall of the first inner wall groove is recessed inward relative to the sidewall of the first groove; forming a first inner wall in the first inner wall groove. After completing the first grooving process, a source / drain doping layer is formed in the groove.

2. The method for forming a semiconductor structure according to claim 1, wherein, During the sub-grooving process, the first groove, the first inner wall groove, and the first inner wall are formed in the same device.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the sub-grooving process, the step of forming the first inner wall in the first inner wall groove includes: forming a first inner wall material layer in the first groove and the first inner wall groove. Removing the first inner wall material layer located in the first groove, and retaining the first inner wall material layer located in the first inner wall groove as the first inner wall.

4. The method for forming a semiconductor structure according to claim 3, wherein, In the step of forming the first inner wall material layer, the first inner wall material layer conformally covers the bottom of the first groove and each surface of the first inner wall groove.

5. The method for forming a semiconductor structure according to claim 1, wherein After completing the first grooving process and before forming the source / drain doping layer in the groove, it further includes: removing the first inner wall to expose the first inner wall groove; after removing the first inner wall, forming a second inner wall in the first inner wall groove.

6. The method for forming a semiconductor structure as described in claim 5, wherein, In the step of forming the second inner wall in the first inner wall groove, the dielectric constant of the second inner wall material is less than the dielectric constant of the first inner wall material.

7. The method for forming a semiconductor structure according to claim 5, wherein, The step of forming the second inner wall in the first inner wall groove includes: after removing the first inner wall, forming a second inner wall material layer in the groove and the first inner wall groove. Removing the second inner wall material layer located in the groove, and retaining the second inner wall material layer located in the first inner wall groove as the second inner wall.

8. The method for forming a semiconductor structure as claimed in claim 1, wherein, In the step of providing the substrate, a sidewall layer is further formed on the sidewall of the dummy gate structure, and the sidewall layer also covers the top of the channel structure. Before performing the first grooving process, it further includes: removing the sidewall layer on the top of the channel structure between adjacent dummy gate structures.

9. The method for forming a semiconductor structure according to claim 1, wherein, In the step of providing the substrate, an isolation layer is further formed between the substrate and the channel structure. The step of forming a groove penetrating the channel structure further includes: after completing the first grooving process, performing a second grooving process on the isolation layer exposed by the first groove to remove a part of the thickness of the isolation layer exposed by the first groove.

10. The method for forming a semiconductor structure according to claim 9, wherein, In the same device, the first grooving process and the second grooving process are sequentially performed.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of providing the substrate, a compensation layer is further formed on the channel structure, and the dummy gate structure covers part of the sidewalls and part of the top of the compensation layer; The step of forming a trench penetrating the channel structure further includes: before performing the first grooving process, performing a third grooving process on the compensation layer between adjacent dummy gate structures to remove the compensation layer between adjacent dummy gate structures and expose the top of the channel structure.

12. The method for forming a semiconductor structure according to claim 11, wherein, In the same device, the third grooving process and the second grooving process are sequentially performed.

13. The method for forming a semiconductor structure according to claim 11, wherein The step of the third grooving process includes: removing the compensation layer between adjacent dummy gate structures to form a second groove; removing a part of the width of the compensation layer exposed on the sidewall of the second groove to form a second inner wall groove communicating with the second groove, and the sidewall of the second inner wall groove is recessed inward relative to the sidewall of the second groove; forming a first inner wall in the second inner wall groove.

14. The method for forming a semiconductor structure as described in claim 1, wherein, During the sub-grooving process, the trench stack between adjacent dummy gate structures is removed by a dry etching process.

15. The method for forming a semiconductor structure according to claim 1, wherein, During the sub-grooving process, an isotropic dry etching process is used to remove a part of the width of the sacrificial layer exposed on the sidewall of the first groove.

16. The method for forming a semiconductor structure according to claim 3, wherein, The first inner wall material layer is formed by an atomic layer deposition process.

17. The method for forming a semiconductor structure according to claim 7, wherein, The second inner wall material layer is formed by an atomic layer deposition process.

18. The method for forming a semiconductor structure according to claim 3, wherein, The first inner wall material layer located in the first groove is removed by a dry etching process.

19. The method for forming a semiconductor structure according to claim 7, wherein The second inner wall material layer located in the trench is removed by a dry etching process.

20. The method for forming a semiconductor structure according to claim 5, wherein, The first inner wall is removed by a wet etching process.

21. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first inner wall includes silicon oxide.

22. The method for forming a semiconductor structure according to claim 5, wherein, The material of the second inner wall includes a low-k dielectric material.

23. The method for forming a semiconductor structure according to claim 1, wherein, The material of the channel layer includes silicon, and the material of the sacrificial layer includes silicon germanide.

24. The method for forming a semiconductor structure according to claim 11, wherein, The material of the compensation layer is the same as the material of the sacrificial layer.

25. The method for forming a semiconductor structure according to claim 1, wherein, After forming the source / drain doping layer, it further includes: forming an interlayer dielectric layer covering the sidewalls of the dummy gate structure and the channel structure on the substrate, and the interlayer dielectric layer exposes the top of the dummy gate structure; Removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; Removing the sacrificial layer exposed in the gate opening to form a through groove communicating with the gate opening; Forming a device gate structure in the gate opening and the through groove, and the device gate structure covers the channel layer.

26. The method for forming a semiconductor structure as described in claim 25, wherein, The device gate structure includes a metal gate structure.

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