Integrated circuit package and method of forming the same

Abstract

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connection and a second die connection on a top side of the interposer and a first dielectric layer covering at least one sidewall of the first die connection and at least one sidewall of the second die connection. The first die is coupled to the first die connection and the first dielectric layer, and the second die connection is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connection and attaching a second die to the interposer, the second die coupled to the second die connection. Embodiments of the present application also relate to integrated circuit packages.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit packages and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced sustained rapid growth due to advancements in integrated circuits (ICs), driven by continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, these improvements in integration density stem from iterative reductions in the size of the smallest component, allowing more components to be integrated into a given area.

[0003] These integration improvements are inherently two-dimensional because the integrated components occupy an area on the surface of the semiconductor wafer. The increasing density of integrated circuits and the corresponding reduction in area have often exceeded the capability to directly bond integrated circuit chips to the substrate. Interposers have been used to redistribute the ball contact area from the chip area to a larger area within the interposer. Furthermore, interposers allow for three-dimensional packages that include multiple chips. Other packages have also been developed to incorporate three-dimensional aspects. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming an integrated circuit package, comprising: attaching a logic die to the top side of an interposer, the interposer including a first die connector and a second die connector located on the top side of the interposer, and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector, the logic die being coupled to the first die connector and the first dielectric layer, the second die connector being exposed by the logic die; recessing the first dielectric layer, the recess exposing the at least one sidewall of the second die connector; and attaching a memory device to the top side of the interposer, the memory device being coupled to the second die connector.

[0005] Other embodiments of this application provide a method for forming an integrated circuit package, comprising: placing a processor device on an interposer; forming a metal-to-metal bond between a first die connector of the processor device and a second die connector of the interposer, and forming a dielectric-to-dielectric bond between a first dielectric layer of the processor device and a second dielectric layer of the processor; exposing a sidewall of a third die connector by removing a top portion of the second dielectric layer exposed by the processor device; mounting a memory device on the interposer, the mounting of the memory device comprising reflowing a first conductive connector on the third die connector to cover the top surface of the third die connector and the exposed sidewall; and forming an underfill between the memory device and the interposer.

[0006] Some embodiments of this application provide an integrated circuit package, including: an interposer comprising: a first dielectric layer; a first die connector having sidewalls covered by the first dielectric layer; a second die connector having a top portion extending over the first dielectric layer, the top surface of the second die connector being coplanar with the top surface of the first die connector; a logic device located on the interposer, the logic device including a third die connector being coupled to the first die connector by metal-to-metal bonding; and a memory device located on the interposer, the memory device being coupled to the interposer by conductive connectors covering the top portion of the second die connector. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of an integrated circuit device according to some embodiments.

[0009] Figures 2A to 2F This is a cross-sectional view of an intermediate step during the process of forming a memory cube, according to some embodiments.

[0010] Figures 3A to 3D This is a cross-sectional view of an intermediate step during the process of forming an HBM device according to some embodiments.

[0011] Figures 4 to 11C This is a cross-sectional view of an intermediate step during the process of forming an integrated circuit package, according to some embodiments.

[0012] Figures 12 to 14C This is a cross-sectional view of an intermediate step during the process of forming an integrated circuit package, according to some other embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] According to some embodiments, two devices (such as, for example, a logic die and a memory device) are bonded to an interposer. After the logic die is bonded to bonding pads in a dielectric layer on the interposer, the remaining exposed portion of the dielectric layer is recessed to expose a larger proportion of the surface area of ​​the bonding pads extending from the recessed dielectric layer. This provides a larger bonding area for the memory device to be subsequently bonded to the interposer using, for example, flip-chip bonding, thereby enhancing bonding strength and increasing the gap between the interposer and the memory device. This increased gap provides a larger process window for the underfill material filling the space between the memory device and the interposer, thereby improving bonding reliability. A cover layer, such as, for example, an electroless nickel / electroless palladium (ENEP) layer, can be formed over the exposed surface area of ​​the bonding pads, which reduces the amount of intermetallic compound (IMC) formed in the solder joint between the memory device and the interposer.

[0016] Figure 1This is a cross-sectional view of an integrated circuit device 10 according to some embodiments. The integrated circuit device 10 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) cell, a static random access memory (SRAM) cell, etc.), a power management die (e.g., a power management integrated circuit (PMIC) cell, a radio frequency (RF)) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or combinations thereof. The integrated circuit device 10 is formed in a wafer (not shown) that includes different device regions. In some embodiments, multiple wafers are stacked to form a wafer stack, which is subsequently diced to form multiple die stacks. In some embodiments, a wafer is diced to form multiple integrated circuit devices 10, which are subsequently stacked to form multiple die stacks. The integrated circuit device 10 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit device 10 may include a semiconductor substrate 12, an interconnect structure 14, a conductive via 16, a die connector 22, and a dielectric layer 24.

[0017] Semiconductor substrate 12 may be an active layer such as doped or undoped silicon, or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 12 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Semiconductor substrate 12 has an active surface (e.g., on...). Figure 1 The surface facing upwards (often referred to as the front); and the non-active surface (e.g., in...). Figure 1 The surface facing down (the middle side), sometimes referred to as the back side.

[0018] Devices may be formed on the active surface of the semiconductor substrate 12. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Passive surfaces may not contain devices. An interlayer dielectric (ILD) is located above the active surface of the semiconductor substrate 12. The ILD surrounds and may cover the devices. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG).

[0019] Interconnect structure 14 is located above the active surface of semiconductor substrate 12. Interconnect structure 14 interconnects devices at the active surface of semiconductor substrate 12 to form an integrated circuit. Interconnect structure 14 may be formed, for example, by metallization patterning in a dielectric layer. Metallization patterning includes metal lines and vias formed in one or more dielectric layers. The metallization patterning of interconnect structure 14 is electrically coupled to devices at the active surface of semiconductor substrate 12.

[0020] Conductive vias 16 are formed extending into interconnect structures 14 and / or semiconductor substrates 12. The conductive vias 16 are electrically coupled to the metallization pattern of the interconnect structures 14. As an example of forming the conductive vias 16, grooves can be formed in the interconnect structures 14 and / or semiconductor substrates 12 by means of, for example, etching, milling, laser technology, or combinations thereof. A thin dielectric material can be formed in the grooves, such as by using oxidation technology. A barrier layer 18 can be conformally deposited in the openings by means of methods such as CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or similar methods. The barrier layer 18 can be formed of oxides, nitrides, or oxynitrides, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, etc. A conductive material 20 can be deposited over the barrier layer 18 and in the openings. The conductive material 20 can be formed by electrochemical plating processes, CVD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material 20 and barrier layer 18 are removed from the surface of interconnect structure 14 and / or semiconductor substrate 12 by, for example, chemical mechanical polishing (CMP). The remaining portion of barrier layer 18 and conductive material 20 forms conductive via 16.

[0021] In the illustrated embodiment, the conductive via 16 is not exposed on the back side of the integrated circuit device 10. Instead, the conductive via 16 is buried in the semiconductor substrate 12. As will be discussed in more detail below, the conductive via 16 will be exposed on the back side of the integrated circuit device 10 in a subsequent process. After exposure, the conductive via 16 may be referred to as a through-silicon via or through-substrate via (TSV).

[0022] Die connector 22 is located on the front side of integrated circuit device 10. Die connector 22 can be a conductive pillar, pad, etc., used for external connection. Die connector 22 is in and / or above interconnect structure 14. Die connector 22 can be formed of metal such as copper, titanium, aluminum, or combinations thereof, and can be formed by, for example, plating.

[0023] A dielectric layer 24 is located on the front side of the integrated circuit device 10. The dielectric layer 24 is located in and / or on the interconnect structure 14. The dielectric layer 24 laterally seals the die connector 22, and the dielectric layer 24 shares a common end with the sidewall of the integrated circuit device 10 laterally (within process variations). The dielectric layer 24 can be an oxide such as silicon oxide, PSG, BSG, BPSG, etc.; a nitride such as silicon nitride; a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer; or a combination thereof. The dielectric layer 24 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the dielectric layer 24 is formed after the die connector 22, and the die connector 22 may be buried such that the top surface of the dielectric layer 24 is above the top surface of the die connector 22. In some embodiments, the die connector 22 is formed after the dielectric layer 24, such as by a damascene process, such as single damascene, dual damascene, etc. After formation, the die connector 22 and dielectric layer 24 can be planarized using, for example, CMP processes, etch-back processes, or combinations thereof. After planarization, the top surface of the die connector 22 is coplanar with the top surface of the dielectric layer 24 (within process variations) and exposed on the front side of the integrated circuit device 10. In another embodiment, the die connector 22 is formed after the dielectric layer 24, such as by plating, and is a raised connector (e.g., microbumps) such that the top surface of the die connector 22 extends above the top surface of the dielectric layer 24.

[0024] Figures 2A to 2F This is a cross-sectional view of an intermediate step during the process of forming the memory cube 50 according to some embodiments. This will be discussed in more detail below. Figures 2A to 2F The diagram illustrates a process for forming a memory cube 50 by stacking multiple wafers, including first integrated circuit devices, on a carrier substrate 52. Each of the first integrated circuit devices may have the same characteristics as those referenced above. Figure 1 The integrated circuit device 10 discussed has a similar structure and may be a memory device in embodiments. Wafers are shown stacked in a device region 52A of a carrier substrate 52 to form a memory cube 50; however, it should be understood that the carrier substrate 52 may have any number of device regions, and the memory cube 50 may be formed in each device region. The memory cube 50 is formed in a top-down (or reverse) manner by wafer-on-wafer (WoW) stacking, wherein a wafer is provided for the top layer of the memory cube 50, and wafer cubes 50 for the bottom layer of the memory are subsequently stacked on top of the top wafer. The wafer stack is divided to form multiple memory cubes 50. The memory cubes 50 are tested after formation to reduce or prevent subsequent processing of known bad memory cubes 50.

[0025] Subsequently, the memory cube 50 can be used to form a high-bandwidth memory (HBM) device. Specifically, as will be discussed in more detail below, the memory cube 50 can be further stacked on a second integrated circuit device to form an HBM device. The second integrated circuit device may have the same features as referenced above. Figure 1 The integrated circuit device 10 discussed has a similar structure and may be a logic device in the embodiments.

[0026] exist Figure 2A In this process, a carrier substrate 52 is provided, and a release layer 54 is formed on the carrier substrate 52. The carrier substrate 52 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 52 can be a wafer, so that multiple memory cubes 50 can be formed simultaneously on the carrier substrate 52.

[0027] Release layer 54 may be formed of a polymer-based material that can be removed from the above structure along with the carrier substrate 52, to be formed in subsequent steps. In some embodiments, release layer 54 is an epoxy-based thermally release material that loses its adhesive properties upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 54 may be a UV adhesive that loses its adhesive properties upon exposure to UV light. Release layer 54 may be dispensed and cured in liquid form, may be a laminated film laminated onto the carrier substrate 52, or may be the like. The top surface of release layer 54 may be horizontal and may have a high degree of flatness.

[0028] Wafer 56A is stacked on carrier substrate 52. Wafer 56A includes multiple integrated circuit devices, such as memory device 10A in device region 52A. Memory device 10A will be diced in a subsequent process to be included in memory cube 50. Memory device 10A includes semiconductor substrate 12A, interconnect structure 14A, conductive via 16A, and dielectric layer 24A, but die connectors in dielectric layer 24A are not included in this processing step. Wafer 56A is stacked face-down on carrier substrate 52 such that the main surface of dielectric layer 24A faces / contacts carrier substrate 52. As will be discussed in more detail below, memory cube 50 is attached to another integrated circuit device after dicing. Reflowable connectors are used to connect memory cube 50 to another integrated circuit device. In some embodiments, die connectors may be formed in dielectric layer 24A (see below). Figure 2E Die connectors are formed after wafer stacking is completed to prevent damage to the die connectors during the wafer stacking process.

[0029] exist Figure 2BIn this process, wafer 56A is thinned. Thinning can be performed using CMP processes, polishing processes, etch-back processes, or combinations thereof, and is performed on the non-active surface of semiconductor substrate 12A. Thinning exposes conductive via 16A. After thinning, the surface of conductive via 16A is coplanar with the non-active surface of semiconductor substrate 12A (within the process variation). Thus, conductive via 16A is exposed on the back side of memory device 10A.

[0030] exist Figure 2C In this configuration, wafer 56B is stacked above carrier substrate 52. Specifically, the front side of wafer 56B is attached to the back side of wafer 56A. Wafer 56B includes multiple integrated circuit devices, such as memory device 10B in device region 52A. Memory device 10B will be diced in subsequent processing to be included in memory cube 50. Memory device 10B includes semiconductor substrate 12B, interconnect structure 14B, conductive via 16B, die connector 22B, and dielectric layer 24B.

[0031] Wafer 56A and wafer 56B are bonded back-to-back, for example, by hybrid bonding in a back-to-back manner, such that the back side of wafer 56A is bonded to the front side of wafer 56B. Specifically, a dielectric-to-dielectric bond and a metal-to-metal bond are formed between wafers 56A and 56B. In the illustrated embodiment, a dielectric layer 58 and a die connector 60 are formed on the back side of wafer 56A and used for hybrid bonding.

[0032] A dielectric layer 58 is formed on the back side of wafer 56A, such as on semiconductor substrate 12A. The dielectric layer 58 shares lateral ends with the sidewalls of integrated circuit device 10 (subject to process variations). The dielectric layer 58 can be an oxide such as silicon oxide, PSG, BSG, BPSG, etc.; a nitride such as silicon nitride; a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer; or combinations thereof. The dielectric layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments (discussed in more detail below), the semiconductor substrate 12A is recessed before the dielectric layer 58 is formed, such that the dielectric layer 58 surrounds the conductive via 16A.

[0033] A die connector 60 is formed on the back side of wafer 56A and is in physical contact with conductive via 16A. The die connector 60 can be a conductive pillar, pad, etc., used for external connection. The die connector 60 can be formed of a metal such as copper or aluminum and can be formed by, for example, plating. The die connector 60 is electrically connected to the integrated circuit of memory device 10A through conductive via 16A. After formation, the dielectric layer 58 and the die connector 60 are planarized using processes such as CMP, etch-back, or combinations thereof. After planarization, the top surface of the die connector 60 is coplanar with the top surface of the dielectric layer 58 (within process variations) and exposed on the back side of wafer 56A.

[0034] Dielectric layer 58 is bonded to dielectric layer 24B via dielectric-to-dielectric bonding without the use of any adhesive material (e.g., die bonding film), and die connector 60 is bonded to die connector 22B via metal-to-metal bonding without the use of any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press wafer 56B against wafer 56A. Pre-bonding is performed at a low temperature, such as room temperature, or a temperature in the range of 15°C to 30°C, and after pre-bonding, dielectric layer 24B and dielectric layer 58 are bonded to each other. Bond strength is then increased in a subsequent annealing step, wherein dielectric layer 24B and dielectric layer 58 are annealed at a high temperature, such as a temperature in the range of 140°C to 280°C. After annealing, a bond is formed between dielectric layer 24B and dielectric layer 58, such as a fusion bond. For example, the bond may be a covalent bond between the material of dielectric layer 58 and the material of dielectric layer 24B. Die connectors 22B and 60 are connected to each other in a one-to-one correspondence. Die connectors 22B and 60 may be in physical contact after pre-bonding, or they may expand during annealing to form physical contact. Furthermore, during annealing, the material of die connector 22B mixes with the material of die connector 60 (e.g., copper), thereby also forming a metal-to-metal bond. Therefore, the bond formed between wafers 56A and 56B is a hybrid bond, which includes both dielectric-to-dielectric bonding and metal-to-metal bonding.

[0035] In another embodiment, die connector 60 is omitted. Dielectric layer 58 is bonded to dielectric layer 24B by dielectric-to-dielectric bonding without the use of any adhesive material (e.g., die adhesive film), and conductive via 16A is bonded to die connector 22B by metal-to-metal bonding without the use of any eutectic material (e.g., solder).

[0036] In another embodiment, dielectric layer 58 and die connector 60 are omitted. Semiconductor substrate 12A can be bonded to dielectric layer 24B via dielectric-to-dielectric bonding without the use of any adhesive material (e.g., die bonding film), and conductive via 16A can be bonded to die connector 22B via metal-to-metal bonding without the use of any eutectic material (e.g., solder). For example, oxides such as native oxides, thermal oxides, etc., can be formed on the non-active surface of semiconductor substrate 12A, and these oxides can be used for dielectric-to-dielectric bonding.

[0037] exist Figure 2D The above steps are repeated so that wafers 56C, 56D, 56E, 56F, 56G, and 56H are stacked on top of carrier substrate 52. Wafers 56C, 56D, 56E, 56F, 56G, and 56H each include multiple integrated circuit devices, such as memory devices 10C, 10D, 10E, 10F, 10G, and 10H respectively included in device region 52A. Memory devices 10C, 10D, 10E, 10F, 10G, and 10H will be diced in subsequent processing to be included in memory cube 50. Each of wafers 56C, 56D, 56E, 56F, 56G, and 56H is directly bonded to wafers 56B, 56C, 56D, 56E, 56F, and 56G respectively via hybrid bonding in a back-to-face manner. The final stacked wafers, such as wafer 56H, may not be thinned, so that the conductive vias 16H of wafer 56H remain electrically insulated.

[0038] exist Figure 2E In this process, carrier substrate peeling is performed to separate (or “de-adhere”) the carrier substrate 52 from the wafer stack (e.g., wafer 56A). According to some embodiments, de-adhesion involves projecting light, such as laser or UV light, onto a release layer 54, causing the release layer 54 to decompose under the heat of the light, and thus removing the carrier substrate 52. Removing the carrier substrate 52 exposes the main surface of the upper memory device (e.g., memory device 10A) of the memory cube 50. The wafer stack is then flipped over and placed over an adhesive tape (not shown).

[0039] Then, for example, on the front side of wafer 56A, a die connector 22A for the top layer of memory cube 50 is formed. The die connector 22A is used to subsequently connect the memory cube to another device, such as wafer 102 (see below). Figure 3C The core connector 22A can be made as described above regarding... Figure 2CThe die connector 60 is made of a similar material and formed using a similar method. The die connector 60 is electrically connected to the integrated circuit of the memory device 10A via a conductive via 16A. After formation, the dielectric layer 24A and the die connector 22A are planarized using processes such as CMP, etch-back, or combinations thereof. After planarization, the top surface of the die connector 22A is coplanar with the top surface of the dielectric layer 24A (within process variations) and is exposed on the front side of the wafer 56A.

[0040] exist Figure 2F In this process, a partitioning process is performed along a scribing line between, for example, device region 52A and an adjacent device region. Partitioning can be performed by sawing, laser cutting, etc. The partitioning process can be performed before or after the formation of die connector 22A. Partitioning separates device region 52A from adjacent device regions. The resulting partitioned memory cube 50 originates from device region 52A. The memory devices of memory cube 50 share a common end laterally after partitioning (within process variations).

[0041] It should be understood that the memory cube 50 may include any number of layers. In the illustrated embodiment, the memory cube 50 includes eight layers. In another embodiment, the memory cube 50 includes more or fewer than eight layers, such as two layers, four layers, sixteen layers, thirty-two layers, etc.

[0042] After the formation of memory cube 50 is completed (e.g., after forming die connector 22A and dividing memory cube 50), the resulting memory cube 50 is tested using probe 62. Probe 62 is physically and electrically connected to die connector 22A. Die connector 22A is used to test memory cube 50 so that only memory cubes known to be in good condition are used for further processing. Testing may include testing the functionality of memory devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H, or may include tests for known open or short circuits that can be anticipated based on the design of the memory devices. During testing, all memory devices in memory cube 50 may be tested in a daisy-chain manner.

[0043] Figures 3A to 3D This is a cross-sectional view of intermediate steps during the process of forming the HBM device 100 according to some embodiments. These will be discussed in more detail below. Figures 3A to 3D This is illustrated by using a second integrated circuit device (e.g., logic device 10L, see...) Figure 3A The process of stacking memory cubes 50 on a wafer 102 to form HBM device 100 is described. The second integrated circuit device is a bare die that can be formed in wafer 102. An HBM device 100 is shown formed in a device region 102A of wafer 102, but it should be understood that wafer 102 can have any number of device regions, and an HBM device 100 can be formed in each device region.

[0044] exist Figure 3A In the process, wafer 102 is obtained. Wafer 102 includes logic devices 10L in device region 102A. Logic devices 10L will be diced in subsequent processing to be included in HBM device 100. Logic devices 10L may be interface devices, buffer devices, controller devices, etc., for memory devices in memory cube 50. In some embodiments, logic devices 10L provide input / output (I / O) interfaces for HBM device 100. Logic devices 10L include a semiconductor substrate 12L, interconnect structures 14L, conductive vias 16L, die connectors 22L, and a dielectric layer 24L.

[0045] Die connector 22L is used for connection to other devices, such as devices in an integrated circuit package that can realize HBM device 100. In some embodiments, die connector 22L is a conductive bump suitable for use with reflowable connectors, such as microbumps extending through dielectric layer 24L. Die connector 22L may have substantially vertical sidewalls (within process variations). In the illustrated embodiment, die connector 22L is formed as a metallized pattern extending through dielectric layer 24L to couple interconnect structure 14L. As an example of forming die connector 22L, an opening is formed in dielectric layer 24L, and a seed layer is formed over dielectric layer 24L and in the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is then formed on the seed layer and patterned thereon. Photoresist can be formed by spin coating or similar methods and exposed to light for patterning. The pattern of the photoresist corresponds to the die connector 22L. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, nickel, titanium, tungsten, aluminum, etc. The photoresist and portions of the seed layer where no conductive material has been formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. After removing the photoresist, the exposed portions of the seed layer are removed by an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the die connector 22L.

[0046] exist Figure 3BIn this process, wafer 102 is thinned. Thinning can be performed using CMP processes, polishing processes, etch-back processes, or combinations thereof, and is performed on the non-active surface of semiconductor substrate 12L. Thinning exposes conductive vias 16L. After thinning, the surface of conductive via 16L is coplanar with the non-active surface of semiconductor substrate 12L (within process variations). Thus, conductive via 16L is exposed on the back side of logic device 10L.

[0047] Then, a dielectric layer 104 is formed on top of wafer 102, for example, on the back side of logic device 10L. Dielectric layer 104 may be formed by [the following text is incomplete and requires further context: "about..."] Figure 2C The dielectric layer 58 is made of a similar material and formed using a similar method. A die connector 106 extending through the dielectric layer 104 is then formed. The die connector 106 may be made of a material similar to that described above. Figure 2E The die connector 22A described is made of a similar material and formed by a similar method. For example, the die connector 106 may be a conductive pillar, pad, etc., suitable for metal-to-metal bonding without the use of any eutectic material (e.g., solder). The die connector 106 is physically connected to the conductive via 16L and electrically connected to the integrated circuit of the logic device 10L through the conductive via 16L.

[0048] exist Figure 3C In this configuration, the memory cube 50 is attached to the wafer 102, for example, to the back side of the logic device 10L. The wafer 102 and memory cube 50 are back-to-back bonded, for example, by a hybrid bonding method, such that the back side of the wafer 102 is bonded to the front side of the memory cube 50. Specifically, a dielectric-to-dielectric bond is formed between the dielectric layer 104 of the wafer 102 and the dielectric layer 24A of the memory cube 50, and a metal-to-metal bond is formed between the die connector 106 of the wafer 102 and the die connector 22A of the memory cube 50. The hybrid bonding of the wafer 102 and memory cube 50 can be used in conjunction with the methods described above for... Figure 2C The hybrid bonding of wafers 56A and 56B is performed using a similar method to that described.

[0049] exist Figure 3DIn this process, a sealant 112 is formed on and around the various components. After formation, the sealant 112 seals the memory cube 50 and contacts the top surface of the dielectric layer 104 and each memory element of the memory cube 50. The sealant 112 can be a molding compound, epoxy resin, etc. The sealant 112 can be applied by compression molding, transfer molding, etc., and can be formed over the wafer 102 such that the memory cube 50 is buried or covered. The sealant 112 can be applied in liquid or semi-liquid form and then subsequently cured. Optionally, a planarization process is performed on the sealant 112 to expose the memory cube 50. After the planarization process, the top surface of the memory cube 50 is coplanar with the top surface of the sealant 112 (within process variations). The planarization process can be, for example, chemical mechanical polishing (CMP), grinding, etc. In some embodiments, planarization may be omitted, for example if the memory cube 50 is already exposed.

[0050] A dicing process is then performed along the scribing area (e.g., around device area 102A). Dividing can be performed by sawing, laser cutting, etc. The dicing process separates device area 102A (including logic device 10L) from adjacent device areas to form HBM device 100 including logic device 10L. The diced logic device 10L has a larger width than each memory device in memory cube 50. After dicing, logic device 10L shares a common end with sealant 112 laterally (within process variations).

[0051] Conductive connectors 114 are formed on die connectors 22L. Conductive connectors 114 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse die connection (C4) bumps, microbumps, bumps formed by electroless nickel plating, electroless palladium immersion gold plating (ENEPIG), etc. Conductive connectors 114 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 114 are first formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, solder placement, etc. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, conductive connectors 114 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal overlay is formed on the top of the metal pillar. The metallic overlay may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process. The conductive connector 114 may be formed before or after the dicing process. The conductive connector 114 will be used for external connections (discussed further below).

[0052] Provide such as Figure 3DThe exemplary electronic device (HBM device 100) shown is for illustrative purposes only to further explain the application of the disclosed embodiments and is not intended to limit the disclosed embodiments in any way. Subsequently, the HBM device 100 is used to form an integrated circuit package. Specifically, as will be discussed in more detail below, the HBM device 100 is packaged in a three-dimensional integrated circuit (3DIC) package such as a system-in-package (SiP). Examples of 3DIC packages include chip-on-wafer (CoW) packages, chip-on-substrate (CoWoS) packages, integrated fan-out (InFO) packages, etc., although it should be understood that the embodiments can be applied to other 3DIC packages.

[0053] Figures 4 to 11C This is a cross-sectional view of an intermediate step during the process of forming an integrated circuit package, according to some embodiments. This will be discussed in more detail below. Figures 4 to 10 This illustrates the packaging of the HBM device 100 into an integrated circuit package 300, such as a CoW package (see...). Figure 9 The process is as follows: The integrated circuit package 300 is then mounted onto the package substrate 400 (see...). Figure 11A This is used to form another package, such as a CoWoS package. The integrated circuit package 300 is formed by stacking the HBM device 100 and a third integrated circuit device on wafer 302. The third integrated circuit device may have the same characteristics as referenced above. Figure 1 The integrated circuit device 10 discussed has a similar structure and may be a logic device or a processor device in the embodiments. An integrated circuit package is shown to be formed in a packaging region 302A of wafer 302, but it should be understood that wafer 302 may have any number of device regions and HBM devices 100 may be stacked in each device region.

[0054] exist Figure 4 In the process, wafer 302 is obtained. Wafer 302 includes an interposer 304 in a packaging region 302A. Interposer 304 will be diced in subsequent processing to be included in an integrated circuit package 300. Interposer 304 includes a semiconductor substrate 306, interconnect structure 308, conductive via 310, dielectric layer 311, and die connector 312, which may be similar to those referenced above. Figure 1 The semiconductor substrate 12, interconnect structure 14, conductive via 16, dielectric layer 24, and die connector 22 of the integrated circuit device 10 discussed differ in that the semiconductor substrate 306 may not contain active / passive devices. The die connector 312 can be a metal such as copper, titanium, aluminum, or a combination thereof. The die connector 312 may have a pitch P1 in the range of 1 μm to 10 μm, which allows for mixed-pitch bonding with subsequently attached logic devices of fine pitch (see below). Figure 5A ).

[0055] exist Figure 5A In this process, logic dies such as processor devices 10P are attached to the front side of wafer 302, for example, to interconnect structure 308 of interposer layer 304. Figure 5B As shown Figure 5A The view shown is of area 500. The processor device 10P may be a processing unit, such as a CPU, GPU, SoC, etc. In some embodiments, the processor device 10P includes a semiconductor substrate 12P, a conductive component 20P, an interconnect structure 14P on the front side of the semiconductor substrate 12P, conductive pads 18P, conductive vias 22P, a dielectric layer 24P, and die connectors 26P. In some embodiments, the processor device 10P does not contain a TSV. The conductive component 20P may be, for example, a conductive line connected to logic circuitry in the semiconductor substrate 12P or other top metal component. The conductive pads 18P may be, for example, aluminum pads on the conductive component 20P, which may be used for external connections via the interconnect structure 14P or for connection to probes 62 (see above). Figure 2F This is used for testing to determine whether the processor device 10P is a known good die. Conductive vias 22P in the interconnect structure 14P can connect conductive pads 18P to die connectors 26P. In some embodiments, multilayer conductive vias and / or conductive lines can connect conductive pads 18P to die connectors 26P via the interconnect structure 14P. The dielectric layer 24P may be composed of [missing information - likely related to dielectric structure 14P]. Figure 1 The dielectric layer 24 is made of a similar material and formed using a similar method. The die connector 26P can be made of the same material as described above. Figure 1 The described core connector 22 is made of similar materials (such as copper, titanium, aluminum, or combinations thereof) and formed by similar methods.

[0056] Processor device 10P is bonded face-to-face to interposer 304, for example, by hybrid bonding in a face-to-face direct bonding manner, such that the front side of processor device 10P is bonded to the front side of interposer 304. Specifically, a dielectric-to-dielectric bond is formed between dielectric layer 24P and dielectric layer 311, and a metal-to-metal bond is formed between die connector 26L and die connector 312. Hybrid bonding can be achieved through the above-mentioned... Figure 2C The bonding of wafers 56A and 56B described herein is performed in a similar manner. The metal-to-metal bonding between die connector 26L and die connector 312 can be a Cu-Cu bonding, Ti-Ti bonding, Al-Al bonding, Cu-Ti bonding, Cu-Al bonding, Ti-Al bonding, or a combination thereof.

[0057] Figure 5C An embodiment is shown in which conductive via 22P is formed directly on conductive component 20P. Conductive pad 18P can be coupled to other conductive components 20P and can be used to connect to probe 62 (see above) during the test process. Figure 2F To determine whether the processor device 10P was a known good die 14P before the interconnect structure was formed.

[0058] exist Figure 6A In this process, the exposed portion of dielectric layer 311 is recessed using a self-aligned process, employing the attached processor device 10P as a mask for recessing dielectric layer 311. Recessing dielectric layer 311 exposes a larger surface area of ​​die connector 312 not attached to processor device 10P and widens the interposer layer 304 to subsequently attached memory devices (such as HBM device 100, see below). Figure 7A and Figure 7B The gap between the dielectric layer 304 and the HBM device 100 provides a sufficient process window for forming solder joints and underfill, thereby enhancing the bonding strength between the dielectric layer 304 and the HBM device 100. As an example of recessing, plasma etching can be used, for instance, to recess the dielectric layer 311. This ion etching utilizes plasma from one or more etchants, including CH4, CF4, CH2F2, CHF3, O2, HBr, Cl2, NF3, N2, He, or combinations thereof. However, other removal methods can be used optionally, in combination, or sequentially, such as wet etching using etchants such as HF or H2, dry etching using etchants such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning. The recessing process is self-aligned by using the processor device 10P to cover the portion of the dielectric layer 311 intended for bonding with the processor device 10P.

[0059] Figure 6B As shown Figure 6A The diagram shows a view of area 1000, illustrating the recessed dielectric layer 311 and die connector 312. In some embodiments, the die connector 312 has a height H1 ranging from 5 μm to 10 μm, and the dielectric layer 311 is recessed to a height H2 ranging from 5 μm to 10 μm below the top surface of the die connector 312. A height H2 ranging from 5 μm to 10 μm may facilitate the exposure of a portion of the sidewalls of the die connector 312 to improve the bonding strength between the interposer 304 and the subsequently attached HBM device 100. A height H2 less than 5 μm may not adequately expose the sidewalls of the die connector 312, resulting in poor bonding strength between the interposer 304 and the subsequently attached HBM device 100. A height H2 greater than 10 μm may result in excessive die connector 312 above the dielectric layer 311, thereby increasing the likelihood of the die connector 312 separating from the interposer 304.

[0060] A ratio of H1 to H2 between 1 and 3 may facilitate the exposure of a certain proportion of the sidewalls of the die connector 312, thereby improving the bonding strength between the interposer 304 and the subsequently attached HBM device 100. A ratio of H1 to H2 less than 1 may result in an excessively large proportion of the die connector 312 being located above the dielectric layer 311, thereby increasing the likelihood of separation between the die connector 312 and the interposer 304. A ratio of H1 to H2 greater than 3 may expose too small a proportion of the sidewalls of the die connector 312, resulting in poor bonding strength between the interposer 304 and the subsequently attached HBM device 100.

[0061] exist Figure 7A and Figure 7B In this process, HBM device 100 is attached to wafer 302, for example, to interconnect structure 308 of interposer 304. HBM device 100 can be attached to die connector 312 of wafer 302 by reflowing conductive connector 114 using a flip-chip bonding process. In some embodiments, the reflowed conductive connector 114 covers the top surface and sidewalls of die connector 312 and is in physical contact with the top surface of dielectric layer 311. The dielectric layer 311 is recessed (see above). Figure 6A and Figure 6B This allows the conductive connector 114 to cover a larger surface area of ​​the die connector 312, which can increase the bonding strength. In some embodiments, such as Figure 7C As shown, a corresponding portion of the lower sidewall of the die connector 312 is exposed between the corresponding bottom surface of the conductive connector 114 and the top surface of the dielectric layer 311.

[0062] exist Figure 8 In this configuration, underfill 316 can be formed between wafer 302 and HBM device 100, simultaneously surrounding conductive connector 114. Underfill 316 reduces stress and protects the reflow junction of reflowable connector 114. Dielectric layer 311 is recessed (see above). Figure 6A and Figure 6B This allows for a larger gap between the HBM device 100 and the interposer 304, which improves the filling process of the underfill 316 and increases bonding strength. The underfill 316 can be formed after the HBM device 100 is attached using a capillary flow process, or it can be formed before the HBM device 100 is attached using a suitable deposition method. The material of the underfill 316 can be liquid epoxy resin, deformable gel, silicone rubber, or a combination thereof. However, any suitable material can be used for the underfill 316.

[0063] exist Figure 9 In this process, sealant 318 is then formed on and around the various components. After formation, sealant 318 seals the HBM device 100 and the processor device 10P and comes into contact with the underfill 316. Sealant 318 may be formed by [the following process / method / approach]... Figure 3D The sealant 112 described is a similar material and is formed by a similar method. Optionally, a planarization process is performed on the sealant 318 to expose the HBM device 100 and / or the processor device 10P. The structure is then flipped over and placed over an adhesive tape (not shown).

[0064] exist Figure 10 In this process, wafer 302 is thinned. Thinning can be performed using CMP processes, polishing processes, etch-back processes, or combinations thereof, and is performed on the non-active surfaces of wafer 302. Thinning exposes conductive vias 310. After thinning, the surface of the conductive vias 310 is coplanar with the non-active surfaces of wafer 302 (within process variations). Thus, the conductive vias 310 are exposed on the back side of the interposer 304.

[0065] After the conductive via 310 is exposed, an external connector 314 is formed on the non-active surface of the wafer 302 and connected to the conductive via 310. The external connector 314 may be configured with respect to... Figure 3A The described die connector 22L is made of a similar material and formed by a similar method. A conductive connector 320 is formed on the outer connector 314. The conductive connector 320 may be made of a material similar to that described above. Figure 3D The conductive connector 114 described is made of a similar material and formed by a similar method.

[0066] Next, a dicing process is performed by sawing along a scribe line 301 between, for example, package region 302A and an adjacent package region such as, for example, package region 302B. The sawing divides package region 302A and the adjacent package region such as, for example, package region 302B. The resulting diced integrated circuit packages 300 are derived from package region 302A and package region 302B, respectively.

[0067] exist Figure 11A In this process, conductive connector 320 is used to connect components such as those from package region 302A (see above). Figure 10An integrated circuit package 300 is mounted to a package substrate 400. The package substrate 400 includes a substrate core 402 and bonding pads 404 above the substrate core 402. The substrate core 402 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof may also be used. Furthermore, the substrate core 402 may be an SOI substrate. Typically, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an optional embodiment, the substrate core 402 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative materials for the core material include bismaleimide triazine BT resin or alternatively other PCB materials or films. Deposited films such as ABF or other laminates may be used for the substrate core 402.

[0068] The substrate core 402 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to meet the structural and functional requirements of the design for device stacking. Any suitable method can be used to form the devices.

[0069] The substrate core 402 may further include a metallization layer and vias (not shown), wherein bonding pads 404 are physically and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed over active and passive devices and is designed to connect the respective devices to form a functional circuit. The metallization layer may be formed of alternating layers of dielectric (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and the metallization layer may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 402 substantially does not contain active and passive devices.

[0070] In some embodiments, conductive connector 320 is reflowed to attach external connector 314 to bonding pad 404. Conductive connector 320 electrically couples and / or physically couples the package substrate 400 (including the metallization layer in the substrate core 402) to the integrated circuit package 300. In some embodiments, solder resist is formed on the substrate core 402. Conductive connector 320 may be disposed in openings in the solder resist for electrical and mechanical coupling to bonding pad 404. Solder resist may be used to protect areas of the substrate core 402 from external damage.

[0071] In some embodiments, underfill 406 may be formed between the integrated circuit package 300 and the package substrate 400 and surround the conductive connector 320 to reduce stress and protect the connector from reflow occurring on the conductive connector 320. Underfill 406 may be formed by a capillary flow process after the integrated circuit package 300 is attached, or by a suitable deposition method before the integrated circuit package 300 is attached. The conductive connectors 320 may have an epoxy flux (not shown) formed thereon before reflow, wherein at least some of the epoxy resin portions of the epoxy flux are retained after the integrated circuit package 300 is attached to the package substrate 400. This retained epoxy resin portion may serve as underfill 406.

[0072] In some embodiments, passive devices (e.g., surface mount devices (SMDs, not shown) may also be attached to the integrated circuit package 300 (e.g., external connector 314) or the package substrate 400 (e.g., bonding pad 404). For example, the passive device may be bonded to the same surface of the integrated circuit package 300 or the package substrate 400 along with the conductive connector 320. The passive device may be attached to the integrated circuit package 300 before the integrated circuit package 300 is mounted on the package substrate 400, or may be attached to the package substrate 400 before or after the integrated circuit package 300 is mounted on the package substrate 400.

[0073] Figure 11B The following are examples illustrating some embodiments: Figure 11A The view shown is of region 1000. A bottom filler 316 is disposed between dielectric layer 24L and dielectric layer 311. A conductive connector 114 is coupled to the bottom surface of die connector 22L opposite to dielectric layer 24L and covers the top surface and sidewalls of die connector 312. The bottom filler 316 may cover the sidewalls of conductive connector 114 and die connector 22L. In some embodiments, the bottom filler 316 covers a portion of the bottom surface of die connector 22L. In some embodiments, such as... Figure 11C As shown, the corresponding portion of the lower sidewall of the core connector 312 is covered by the bottom filler 316.

[0074] Figures 12 to 14C This is a cross-sectional view of an intermediate step during the process of forming the integrated circuit package 350. In this embodiment, the integrated circuit package 350 is similar to the reference above. Figures 7A to 11A The described integrated circuit package 300, wherein the same reference numerals indicate the same components formed using the same process. Embodiments of integrated circuit package 350 and their manufacture may differ from embodiments of integrated circuit package 300 and their manufacture; for example, die connector 312 for mounting HBM device 100 on interposer 304 is covered by cover layer 324.

[0075] Figure 12 Showing something similar to the one above Figure 6A In one embodiment shown, a cover layer 324 is formed on the exposed surface of the die connector 312. The cover layer 324 reduces the burden on the interposer 304 and the subsequently attached HBM device 100 (see below). Figure 13A The amount of intermetallic compound (IMC) formed in the solder joints (such as conductive connector 114) between the components can reduce resistance and improve device performance. The capping layer 324 can be formed using an electroless plating (E-Less) process. As examples, the electroless plating process may include electroless nickel / electroless palladium (ENEP), electroless nickel / electroless palladium / immersion gold (ENEPIG), immersion gold, or other processes. Other electroless plating processes may also be used to form the capping layer 324.

[0076] exist Figure 13A In this process, HBM device 100 is attached to wafer 302, for example, to interconnect structure 308 of interposer 304. Figure 13B The following are examples illustrating some embodiments: Figure 13A The diagram shows a view of region 1002. The HBM device 100 can be attached to the die connector 312 of wafer 302 by using a flip-chip bonding process with a reflow conductive connector 114. In some embodiments, the reflow conductive connector 114 covers the capping layer 324 on the top surface and sidewalls of the die connector 312 and is in physical contact with the top surface of the dielectric layer 311. In some embodiments, such as Figure 13C As shown, a corresponding portion of the cover layer 324 is exposed between the corresponding bottom surface of the conductive connector 114 and the top surface of the dielectric layer 311.

[0077] Figure 14A This illustrates an integrated circuit package 350 mounted on a package substrate 400 using conductive connectors 320. The use of conductive connectors 320 is described in relation to... Figures 8 to 11A The integrated circuit package 350 can be made using a similar method to the described integrated circuit package 300. Figure 13A and Figure 13B The structure shown is formed. Figure 14B The following are examples illustrating some embodiments: Figure 14A The view shown is of region 1002. A bottom filler 316 is disposed between dielectric layer 24L and dielectric layer 311. A conductive connector 114 is coupled to the bottom surface of die connector 22L opposite to dielectric layer 24L and covers cover layer 324. The bottom filler 316 may cover the sidewalls of conductive connector 114 and die connector 22L. In some embodiments, the bottom filler 316 covers a portion of the bottom surface of die connector 22L. In some embodiments, such as... Figure 14CAs shown, the corresponding portion of the cover layer 324 located between the corresponding bottom surface of the conductive connector 114 and the top surface of the dielectric layer 311 is covered by the bottom filler 316.

[0078] The embodiments offer advantages. A logic die is bonded to a dielectric layer on an interposer. The remaining exposed portion of the dielectric layer is then recessed, exposing the sidewalls of the bonding pads extending from the interposer and providing a larger bonding area for subsequently bonded memory devices. This increased surface area of ​​the bonding pads increases bonding strength and widens the gap between the memory device and the interposer. This increases bonding reliability by providing a larger process window for the underfill between the memory device and the interposer. In some embodiments, a capping layer is formed on the top surface and sidewalls of the bonding pads to reduce the amount of intermetallic compound (IMC) formed in the solder joint between the memory device and the interposer.

[0079] According to an embodiment, the method includes: attaching a logic die to a top side of an interposer, the interposer including a first die connector and a second die connector located on the top side of the interposer, and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector, the logic die being coupled to the first die connector and the first dielectric layer, the second die connector being exposed by the logic die; recessing the first dielectric layer, the recess exposing the at least one sidewall of the second die connector; and attaching a memory device to the top side of the interposer, the memory device being coupled to the second die connector. In an embodiment, the method further includes forming an underfill in a gap between the memory device and the interposer. In an embodiment, the method further includes forming a capping layer on the top surface and sidewall of the second die connector. In an embodiment, forming the capping layer includes an electroless nickel / electroless palladium plating process. In one embodiment, the method further includes: sealing the memory device and the logic die with a sealant; and bonding the interposer to a package substrate, the interposer being located between the package substrate and the sealant. In another embodiment, the logic die includes a third die connector and a second dielectric layer, wherein attaching the logic die to the top side of the interposer includes a metal-to-metal bond between the first die connector and the third die, and a dielectric-to-dielectric bond between the first dielectric layer and the second dielectric layer. In yet another embodiment, attaching the memory device to the top side of the interposer includes flip-chip bonding.

[0080] According to another embodiment, the method includes: placing a processor device on an interposer; forming a metal-to-metal bond between a first die connector of the processor device and a second die connector of the interposer, and forming a dielectric-to-dielectric bond between a first dielectric layer of the processor device and a second dielectric layer of the processor; exposing a sidewall of a third die connector by removing a top portion of the second dielectric layer exposed by the processor device; mounting a memory device on the interposer, the mounting of the memory device including reflowing a first conductive connector on the third die connector to cover the top surface and exposed sidewall of the third die connector; and forming an underfill between the memory device and the interposer. In an embodiment, the method further includes: sealing the processor device and the memory device with a sealant; forming a plurality of second conductive connectors located on the interposer opposite to the sealant; and dividing the processor device, the memory device, and a portion of the interposer to form an integrated circuit package. In an embodiment, the method further includes forming a capping layer on the exposed top surface and sidewall of the third die connector, the capping layer comprising nickel or palladium. In one embodiment, the third die connector has a first height, and removing the top portion of the second dielectric layer exposes a portion of the third die connector having a second height, wherein the ratio of the first height to the second height is between 1 and 3. In another embodiment, the second height is between 5 μm and 10 μm. In another embodiment, the metal-to-metal bond is a Cu-Cu bond. In another embodiment, the metal-to-metal bond is a Ti-Ti bond or an Al-Al bond. In yet another embodiment, the metal-to-metal bond is a Cu-Ti bond, a Cu-Al bond, or a Ti-Al bond.

[0081] According to another embodiment, an integrated circuit package includes: an interposer comprising: a first dielectric layer; a first die connector, the sidewalls of which are covered by the first dielectric layer; a second die connector, the top portion of which extends over the first dielectric layer, the top surface of which is coplanar with the top surface of the first die connector; a logic device located on the interposer, the logic device including a third die connector joined to the first die connector by metal-to-metal bonding; and a memory device located on the interposer, the memory device coupled to the interposer by conductive connectors covering the top portion of the second die connector. In an embodiment, the integrated circuit package further includes a cover layer located above the top portion of the second die connector, the conductive connectors covering the cover layer. In an embodiment, the cover layer comprises nickel or palladium. In an embodiment, the integrated circuit package further includes an underfill disposed between the interposer and the memory device. In one embodiment, the first dielectric layer includes: a first portion, the first portion being bonded to a second dielectric layer of the logic device; and a second portion, the second portion being 5 μm to 10 μm lower in height than the first portion.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming an integrated circuit package, comprising: A logic die is attached to the top side of an interposer layer, the interposer layer including a first die connector and a second die connector located on the top side of the interposer layer, and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector, the logic die being coupled to the first die connector and the first dielectric layer, and the second die connector being exposed by the logic die. The first dielectric layer is recessed, and the recess exposes at least one sidewall of the second die connector; as well as The storage device is attached to the top side of the interposer layer, and a conductive connector of the storage device is coupled to the second die connector, wherein the conductive connector covers the top surface and a portion of the sidewall of the second die connector, and another portion of the sidewall of the second die connector is exposed.

2. The method of claim 1, further comprising forming a bottom filler in the gap between the storage device and the interlayer.

3. The method according to claim 1, further comprising forming a covering layer on the top surface and sidewall of the second core connector.

4. The method according to claim 3, wherein, The formation of the coating layer includes a chemical nickel plating / chemical palladium plating process.

5. The method according to claim 1, further comprising: The memory device and the logic die are sealed with a sealant; as well as The interposer is bonded to the encapsulation substrate, the interposer being located between the encapsulation substrate and the sealant.

6. The method according to claim 1, wherein, The logic die includes a third die connector and a second dielectric layer, wherein attaching the logic die to the top side of the interposer layer includes a metal-to-metal connection between the first die connector and the third die, and a dielectric-to-dielectric connection between the first dielectric layer and the second dielectric layer.

7. The method according to claim 1, wherein, Attaching the storage device to the top side of the interposer includes flip-chip bonding.

8. A method for forming an integrated circuit package, comprising: Place the processor device in the interposer layer; A metal-to-metal bond is formed between the first die connector of the processor device and the second die connector of the interposer layer, and a dielectric-to-dielectric bond is formed between the first dielectric layer of the processor device and the second dielectric layer of the processor. The sidewalls of the third die connector are exposed by removing the top portion of the second dielectric layer exposed by the processor device; Mounting the storage device on the interposer layer, wherein mounting the storage device includes refluxing a first conductive connector on the third die connector to cover the top surface of the third die connector and a portion of the exposed sidewall, and exposing another portion of the sidewall of the third die connector; as well as An underfill is formed between the storage device and the interlayer.

9. The method according to claim 8, further comprising: The processor device and the memory device are sealed with a sealant; A plurality of second conductive connectors are formed on the intermediary layer opposite to the sealant; as well as The processor device, the memory device, and a portion of the interposer layer are separated to form an integrated circuit package.

10. The method of claim 8, further comprising forming a cover layer on the exposed top surface and sidewalls of the third die connector, the cover layer comprising nickel or palladium.

11. The method according to claim 8, wherein, The third die connector has a first height, the top portion of the second dielectric layer is removed to expose a portion of the third die connector having a second height, and the ratio of the first height to the second height is in the range of 1 to 3.

12. The method according to claim 11, wherein, The second height is in the range of 0.45 μm to 5 μm.

13. The method according to claim 8, wherein, The metal-to-metal bond is a Cu-Cu bond.

14. The method according to claim 8, wherein, The metal-to-metal bonding is either a Ti-Ti bonding or an Al-Al bonding.

15. The method according to claim 8, wherein, The metal-to-metal bonding is Cu-Ti bonding, Cu-Al bonding, or Ti-Al bonding.

16. An integrated circuit package, comprising: Intermediary layer, the intermediary layer comprising: First dielectric layer; A first die connector, wherein the sidewall of the first die connector is covered by the first dielectric layer; and The second die connector has a top portion that extends above the first dielectric layer, and the top surface of the second die connector is coplanar with the top surface of the first die connector. A logic device, located on the interposer layer, includes a third die connector, the third die connector being coupled to the first die connector via a metal-to-metal connection; and A storage device is located on the interposer layer and is coupled to the interposer layer by a conductive connector that covers the top portion and a portion of the sidewall of the second die connector, and exposes another portion of the sidewall of the second die connector.

17. The integrated circuit package of claim 16, further comprising a cover layer located above the top portion of the second die connector, the conductive connector covering the cover layer.

18. The integrated circuit package according to claim 17, wherein, The coating layer comprises nickel or palladium.

19. The integrated circuit package of claim 16, further comprising an underfill material disposed between the interposer and the memory device.

20. The integrated circuit package according to claim 16, wherein, The first dielectric layer includes: A first portion, the first portion being bonded to a second dielectric layer of the logic device; and The second part is at a height that is 5 μm to 10 μm lower than the first part.

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