Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate comprising an NMOS region and a PMOS region; forming discrete channel structures on the substrates of the NMOS and PMOS regions, the channel structures comprising one or more stacked channel layers, each channel layer comprising a sacrificial layer and a channel layer located on the sacrificial layer, wherein the aspect ratio of the channel layer in the NMOS region is smaller than that in the PMOS region, and the channel structure comprises a channel region along its extension direction; removing the sacrificial layer of the channel region; after removing the sacrificial layer of the channel region, forming a gate dielectric layer surrounding the channel layer in the channel region; and forming a gate structure spanning the channel layer and surrounding the gate dielectric layer. In the NMOS region, by making the aspect ratio of the channel layer smaller, the width of the channel layer is increased, thereby increasing the operating current of the NMOS. In the PMOS region, by making the aspect ratio of the channel layer larger, the height of the channel layer is increased, thereby increasing the operating current of the PMOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including an NMOS region and a PMOS region, wherein the NMOS region is used to form an NMOS transistor and the PMOS region is used to form a PMOS transistor; a channel layer structure, respectively suspended on the substrate of the NMOS region and the PMOS region, the channel layer structure comprising one or more channel layers spaced apart, wherein the aspect ratio of the channel layer in the NMOS region is smaller than the aspect ratio of the channel layer in the PMOS region; a gate dielectric layer located in the NMOS region and the PMOS region, and surrounding and covering a portion of the top and a portion of the sidewalls of the channel layer; and a gate structure located on the substrate and spanning the channel layer structure, the gate structure surrounding and covering the gate dielectric layer.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including an NMOS region and a PMOS region, wherein the NMOS region is used to form an NMOS transistor and the PMOS region is used to form a PMOS transistor; forming discrete channel structures on the substrate of the NMOS region and the PMOS region, the channel structures including one or more stacked channel layers, each of the channel layers including a sacrificial layer and a channel layer located on the sacrificial layer, wherein the aspect ratio of the channel layer in the NMOS region is smaller than the aspect ratio of the channel layer in the PMOS region, and the channel structure including a channel region along the extension direction of the channel structure; removing the sacrificial layer of the channel region; after removing the sacrificial layer of the channel region, forming a gate dielectric layer surrounding and covering the channel layer in the channel region; and forming a gate structure across the channel layer on the substrate, the gate structure surrounding and covering the gate dielectric layer.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a semiconductor structure including a channel layer structure suspended on substrates of an NMOS region and a PMOS region, respectively. The channel layer structure includes one or more spaced-apart channel layers, wherein the aspect ratio of the channel layer in the NMOS region is smaller than that in the PMOS region. A gate dielectric layer is located in the NMOS and PMOS regions and surrounds and covers a portion of the top and sidewalls of the channel layer. A gate structure is located on the substrate and spans the channel structure, surrounding and covering the gate dielectric layer. In this semiconductor structure, since the top, bottom, and sidewalls of the channel layer covered by the gate structure serve as channels, and due to the physical phenomena arising from the combination of crystal orientation and crystal planes, in an NMOS, charge carriers in the channel layer... The mobility at the top and bottom of the channel layer is greater than that at the sidewalls of the channel layer. In PMOS, the mobility of charge carriers at the sidewalls of the channel layer is greater than that at the top and bottom of the channel layer. Therefore, in the NMOS region, by making the aspect ratio of the channel layer smaller, the width of the channel layer can be increased, and the top and bottom dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the NMOS. In the PMOS region, by making the aspect ratio of the channel layer larger, the height of the channel layer can be increased, and the sidewall dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the PMOS. In summary, the scheme described in the embodiments of the present invention can easily meet the performance requirements of both NMOS and PMOS, thereby improving the performance of the semiconductor structure.

[0009] In the formation method provided by this embodiment of the invention, discrete channel structures are formed on the substrates of the NMOS and PMOS regions. Each channel structure includes one or more stacked channel layers, each including a sacrificial layer and a channel layer located on the sacrificial layer. The aspect ratio of the channel layer in the NMOS region is smaller than that in the PMOS region. Along the extension direction of the channel structure, the channel structure includes a channel region. The sacrificial layer of the channel region is removed. After removing the sacrificial layer, a gate dielectric layer surrounding and covering the channel layer is formed in the channel region. A gate structure spanning the channel layer structure is formed on the substrate, surrounding and covering the gate dielectric layer. In the semiconductor structure, since the top, bottom, and sidewalls of the channel layer covered by the gate structure are used as channels, and since the crystal orientation... The physical phenomena arising from the interaction with crystal planes result in the following: In NMOS, the mobility of charge carriers at the top and bottom of the channel layer is greater than their mobility on the sidewalls of the channel layer; in PMOS, the mobility of charge carriers on the sidewalls of the channel layer is greater than their mobility at the top and bottom of the channel layer. Therefore, in the NMOS region, by making the aspect ratio of the channel layer smaller, the width of the channel layer can be increased, and the top and bottom dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the NMOS. In the PMOS region, by making the aspect ratio of the channel layer larger, the height of the channel layer can be increased, and the sidewall dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the PMOS. In summary, the solution described in the embodiments of the present invention can easily meet the performance requirements of both NMOS and PMOS, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure.

[0011] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figures 16 to 17 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0014] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0015] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, including a PMOS region 10P for forming a PMOS transistor and an NMOS region 10N for forming an NMOS transistor; a channel layer structure 24 is formed on the substrate 10 of the NMOS region 10N and the PMOS region 10P and is suspended on the substrate 10 and is discrete, the channel layer structure 24 including one or more channel layers 21 spaced apart; a gate structure 70 is formed on the substrate 10 across the channel layer structure 24, the gate structure 70 surrounds each of the channel layers 21 and covers part of the top and part of the sidewalls of the channel layer structure 24.

[0017] Currently, when forming the channel layer structure 24, the width W of the channel layer 21 in the NMOS region 10N and the PMOS region 10P are equal, and the height H of the channel layer 21 in the NMOS region 10N and the PMOS region 10P are also equal. Since the top, bottom, and sidewalls of the channel layer 21, which are covered by the gate structure 70, are used as channels, and the size of the channel affects the performance of the transistor, in the prior art, the size of the channel layer 21 is difficult to simultaneously meet the performance requirements of NMOS and PMOS.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including an NMOS region and a PMOS region, wherein the NMOS region is used to form an NMOS transistor and the PMOS region is used to form a PMOS transistor; forming discrete channel structures on the substrate of the NMOS region and the PMOS region, the channel structures including one or more stacked channel layers, each of the channel layers including a sacrificial layer and a channel layer located on the sacrificial layer, wherein the aspect ratio of the channel layer in the NMOS region is smaller than the aspect ratio of the channel layer in the PMOS region, and the channel structure including a channel region along the extension direction of the channel structure; removing the sacrificial layer of the channel region; and after removing the sacrificial layer of the channel region, forming a gate structure surrounding and covering the channel layer in the channel region.

[0019] In the formation method provided by this embodiment of the invention, discrete channel structures are formed on the substrates of the NMOS region and the PMOS region. Each channel structure includes one or more stacked channel layers, each including a sacrificial layer and a channel layer located on the sacrificial layer. The aspect ratio of the channel layer in the NMOS region is smaller than that in the PMOS region. Along the extension direction of the channel structure, the channel structure includes a channel region. The sacrificial layer of the channel region is removed. After removing the sacrificial layer, a gate structure is formed surrounding and covering the channel layer in the channel region. In the semiconductor structure, since the top, bottom, and sidewalls of the channel layer covered by the gate structure are used as channels, and due to the physical phenomena generated by the combination of crystal orientation and crystal plane, in NMOS... The mobility of charge carriers at the top and bottom of the channel layer is greater than their mobility on the sidewalls of the channel layer. In PMOS, the mobility of charge carriers on the sidewalls of the channel layer is greater than their mobility at the top and bottom of the channel layer. Therefore, in the NMOS region, by making the aspect ratio of the channel layer smaller, the width of the channel layer can be increased, and the top and bottom dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the NMOS. In PMOS, by making the aspect ratio of the channel layer larger, the height of the channel layer can be increased, and the sidewall dimensions of the channel layer can be increased accordingly, which is beneficial to increasing the operating current of the PMOS. In summary, the solution described in the embodiments of the present invention can easily meet the performance requirements of both NMOS and PMOS, thereby improving the performance of the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0022] The semiconductor structure includes: a substrate 101, comprising an NMOS region 101N and a PMOS region 101P, wherein the NMOS region 101N is used to form an NMOS transistor and the PMOS region 101P is used to form a PMOS transistor; a channel layer structure 241, respectively suspended on the substrate 101 of the NMOS region 101N and the PMOS region 101P, wherein the channel layer structure 241 includes one or more channel layers 211 spaced apart, wherein the aspect ratio H / W of the channel layer 211 in the NMOS region 101N is smaller than the aspect ratio H / W of the channel layer 211 in the PMOS region 101P; a gate dielectric layer 711, located in the NMOS region 101N and the PMOS region 101P, and surrounding and covering a portion of the top and a portion of the sidewalls of the channel layer 211; and a gate structure 701, located on the substrate 101 and spanning the channel layer structure 241, wherein the gate structure 701 surrounds and covers the gate dielectric layer 711.

[0023] The aspect ratio H / W of the channel layer 211 refers to the ratio of the height H to the width W of the channel layer 211.

[0024] In a semiconductor structure, the top, bottom, and sidewalls of the channel layer 211, covered by the gate structure 701, serve as channels. Furthermore, due to physical phenomena arising from crystal orientation and crystal plane bonding, in NMOS, the carrier mobility at the top and bottom of the channel layer 211 is greater than its mobility at the sidewalls of the channel layer 211; in PMOS, the carrier mobility at the sidewalls of the channel layer 211 is greater than its mobility at the top and bottom of the channel layer 211. Therefore, in the NMOS region 101N, by making the aspect ratio H / W of the channel layer 211 smaller, it is easier to increase the... The width W of the channel layer 211 is increased accordingly, thereby increasing the top and bottom dimensions of the channel layer 211, which is beneficial to increasing the operating current of the NMOS. In the PMOS region 101P, by making the aspect ratio H / W of the channel layer 211 larger, the height H of the channel layer 211 is increased, and the sidewall dimensions of the channel layer 211 are increased accordingly, which is beneficial to increasing the operating current of the PMOS. In summary, the scheme described in the embodiments of the present invention can easily meet the performance requirements of both NMOS and PMOS, thereby improving the performance of the semiconductor structure.

[0025] The substrate 101 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a gate-all-around (GAA) transistor. The GAA transistor includes nanosheet FETs and nanowire FETs.

[0026] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0027] It should be noted that the semiconductor structure may further include: a fin (not shown) located on the substrate 101; and an isolation layer (not shown) located on the substrate 101 exposed by the fin, covering the sidewalls of the fin. Correspondingly, a channel layer structure 241 is suspended on the fin. The isolation layer may be a shallow trench isolation structure.

[0028] The top, bottom, and sidewalls of the channel layer 211, which are covered by the gate structure 701, are used as channels. In this embodiment, the channel layer structure 241 is suspended on the substrate 101 of the NMOS and PMOS regions. The channel layer structure 241 includes one or more channel layers 211 spaced apart. The top, bottom, and sidewalls of the channel layer 211 can all serve as channels. Therefore, the channel layer structure 241 increases the area used as a channel, thereby increasing the operating current of the semiconductor structure.

[0029] As an example, the number of channel layers 211 is multiple, and the multiple channel layers 211 are arranged at intervals along the normal direction of the surface of the substrate 101.

[0030] In this embodiment, the height H of the channel layer 211 in the NMOS region 101N is less than the height H of the channel layer 211 in the PMOS region 101P, thereby making the aspect ratio H / W of the channel layer 211 in the NMOS region 101N less than the aspect ratio H / W of the channel layer 211 in the PMOS region 101P.

[0031] Since the top, bottom, and sidewalls of the channel layer 211, which are covered by the gate structure 701, are used as channels, in PMOS, the mobility of charge carriers on the sidewalls of the channel layer 211 is greater than their mobility on the top of the channel layer 211. By making the height H of the channel layer 211 in the NMOS region 101N smaller than the height H of the channel layer 211 in the PMOS region 101P, the sidewall size of the channel layer 211 in the PMOS region 101P is increased, which is beneficial to increasing the operating current of the PMOS.

[0032] Correspondingly, given that the height H of the channel layer 211 in the PMOS region 101P meets the performance requirements of the PMOS, it is easy to adjust the width W of the channel layer 211 to meet the performance requirements of the NMOS. In the NMOS, the carrier mobility at the top of the channel layer 211 is greater than its mobility on the sidewalls of the channel layer 211. Therefore, in the NMOS region 101N, increasing the width W of the channel layer 211 correspondingly increases the top dimension of the channel layer 211, thereby facilitating an increase in the operating current of the NMOS.

[0033] As an example, the width W of the channel layer 211 in the NMOS region 101N is greater than the width W of the channel layer 211 in the PMOS region 101P. In an NMOS, the mobility of charge carriers at the top of the channel layer 211 is greater than their mobility on the sidewalls of the channel layer 211. Increasing the top dimension of the channel layer 211 in the NMOS region 101N is beneficial for increasing the operating current of the NMOS.

[0034] In this embodiment, according to the performance requirements of the transistor, the dimensions of the channel layer 211 can also meet the following conditions: the width W of the channel layer 211 in the NMOS region 101N is equal to the width W of the channel layer 211 in the PMOS region 101P, and the height H of the channel layer 211 in the NMOS region 101N is less than the height H of the channel layer 211 in the PMOS region 101P.

[0035] Since the top, bottom, and sidewalls of the channel layer 211, covered by the gate structure 701, are used as channels, in NMOS, the mobility of charge carriers at the top of the channel layer 211 is greater than their mobility at the sidewalls of the channel layer 211; in PMOS, the mobility of charge carriers at the sidewalls of the channel layer 211 is greater than their mobility at the top of the channel layer 211. The width W of the channel layer 211 in the NMOS region 101N is equal to the width W of the channel layer 211 in the PMOS region 101P. If the height H of the channel layer 211 is less than the height H of the channel layer 211 in the PMOS region 101P, then for the NMOS region 101N, the top dimension of the channel layer 211 is increased in a targeted manner compared to the sidewall dimension of the channel layer 211, which is beneficial to increasing the operating current of the NMOS. Similarly, for the PMOS region 101P, the sidewall dimension of the channel layer 211 is increased in a targeted manner compared to the top dimension of the channel layer 211, which is beneficial to increasing the operating current of the PMOS.

[0036] In other embodiments, depending on the performance requirements of the transistor, the width of the channel layer in the NMOS region may be greater than the width of the channel layer in the PMOS region, and the height of the channel layer in the NMOS region may be less than the height of the channel layer in the PMOS region. Specifically, by intentionally increasing the width and height of the channel layer in the NMOS region, the performance requirements of both NMOS and PMOS can be met simultaneously.

[0037] In the NMOS region 101N, the aspect ratio H / W of the channel layer 211 cannot be too large or too small. Since the top, bottom, and sidewalls of the channel layer 211, covered by the gate structure 701, serve as the channel, in NMOS, the carrier mobility at the top and bottom of the channel layer 211 is greater than its mobility at the sidewalls. If the aspect ratio H / W of the channel layer 211 is too large, the height H of the channel layer 211 will be too large and the width W too small, resulting in excessively small top and bottom dimensions of the channel layer 211. This makes it difficult to increase the operating current of the NMOS and improve the performance of the semiconductor structure. Conversely, if the aspect ratio H / W of the channel layer 211 is too small, the height H will be too small and the width W too large, making the channel layer 211 too thin. This increases the manufacturing difficulty and the risk of breakage, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the aspect ratio H / W of the channel layer 211 in the NMOS region 101N is 1:6 to 1:1.

[0038] In the PMOS region 101P, the aspect ratio H / W of the channel layer 211 cannot be too large or too small. If the aspect ratio H / W of the channel layer 211 is too large, the height H of the channel layer 211 will be too large and the width W will be too small, making the channel layer 211 too narrow, increasing the difficulty of forming the channel layer 211 and affecting the performance of the semiconductor structure. Since the top, bottom, and sidewalls of the channel layer 211 covered by the gate structure 701 are used as channels, in PMOS, the mobility of charge carriers on the sidewalls of the channel layer 211 is greater than their mobility on the top of the channel layer 211. If the aspect ratio H / W of the channel layer 211 is too small, the height H of the channel layer 211 will be too small and the width W will be too large, resulting in the sidewall size of the channel layer 211 being too small, making it difficult to increase the operating current of the PMOS and improve the performance of the semiconductor structure. Therefore, in this embodiment, in the PMOS region 101P, the aspect ratio H / W of the channel layer 211 is 1:3 to 3:1.

[0039] In this embodiment, the number of channel layers 211 in the NMOS region 101N is equal to the number of channel layers 211 in the PMOS region 101P.

[0040] The number of channel layers 211 in the NMOS region 101N is equal to the number of channel layers 211 in the PMOS region 101P. This is beneficial because the channel layers 211 in the NMOS region 101N and the PMOS region 101P are formed in the same step during the formation of the channel layers 211, which simplifies the process flow and improves process efficiency.

[0041] In this embodiment, the number of trench layers 211 is 1 to 5. The number of trench layers 211 cannot be too large; if the number of trench layers 211 is too large, it greatly increases the difficulty of forming the trench layers 211 and easily leads to unnecessary process waste. Therefore, in this embodiment, the number of trench layers 211 is 1 to 5.

[0042] In this embodiment, on the vertical plane of the extension direction of the channel layer 211, the shape of the channel layer 211 includes a rectangle or a trapezoid, that is, the sidewall of the channel layer is perpendicular to the substrate surface or has an angle with it.

[0043] The morphology of the channel layer 211 includes a rectangle or a trapezoid, which makes the morphology of the channel layer 211 easy to form in the process. Moreover, the rectangle or trapezoid is a quadrilateral, which can better expose the top and sidewalls of the channel layer 211 and make contact with the gate structure 701.

[0044] In this embodiment, the material of the channel layer 211 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. In this embodiment, the material of the channel layer 211 is silicon.

[0045] It should be noted that in this embodiment, the channel layer 211 and the substrate 101 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0046] In this embodiment, the gate structure 701 spans the channel layer structure 241 and surrounds and covers a portion of the top, a portion of the bottom, and a portion of the sidewalls of the channel layer 211, thereby increasing the area of ​​the channel layer structure 211 used as a channel and thus increasing the operating current of the semiconductor structure.

[0047] In this embodiment, the semiconductor structure further includes a gate dielectric layer 711, located in the NMOS region 101N and the PMOS region 101P, and surrounding and covering a portion of the top and a portion of the sidewalls of the channel layer 211.

[0048] The gate dielectric layer 711 is made of one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 711 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0049] In this embodiment, the gate structure 701 is a device gate structure used to control the opening or closing of the transistor channel.

[0050] In this embodiment, the gate structure 701 includes a metal gate structure.

[0051] In this embodiment, the metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0052] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0053] The gate electrode layer is used to draw out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0054] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0055] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0056] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0057] refer to Figure 3 A substrate 100 is provided, including an NMOS region 100N and a PMOS region 100P, wherein the NMOS region 100N is used to form an NMOS transistor and the PMOS region 100P is used to form a PMOS transistor.

[0058] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a gate-all-around (GAA) transistor. The GAA transistor includes nanosheet FETs and nanowire FETs.

[0059] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0060] Reference Figures 3 to 14 Discrete channel structures 250 are formed on the substrate 100 of the NMOS region 101N and the PMOS region 101P. The channel structure 250 includes one or more stacked channel layers 200. Each channel layer 200 includes a sacrificial layer 220 and a channel layer 210 located on the sacrificial layer 220. The aspect ratio H / W of the channel layer 210 in the NMOS region 101N is smaller than the aspect ratio H / W of the channel layer 210 in the PMOS region 101P. Along the extension direction of the channel structure 250, the channel structure 250 includes a channel region.

[0061] In semiconductor structures, the top, bottom, and sidewalls of the channel layer 210, covered by the gate structure, serve as channels. Due to physical phenomena arising from crystal orientation and crystal plane bonding, in NMOS, the carrier mobility at the top and bottom of the channel layer 210 is greater than its mobility at the sidewalls; in PMOS, the carrier mobility at the sidewalls is greater than its mobility at the top and bottom. Therefore, in the NMOS region 101N, by making the aspect ratio H / W of the channel layer 210 smaller, it is easier to increase the... The width W of the channel layer 210 is increased accordingly, thereby increasing the top and bottom dimensions of the channel layer 210, which is beneficial to increasing the operating current of the NMOS. In the PMOS region 101P, by making the aspect ratio H / W of the channel layer 210 larger, the height H of the channel layer 210 is increased, and the sidewall dimensions of the channel layer 210 are increased accordingly, which is beneficial to increasing the operating current of the PMOS. In summary, the solution described in the embodiments of the present invention can easily meet the performance requirements of both NMOS and PMOS, thereby improving the performance of the semiconductor structure.

[0062] The channel structure 250 is used to form the channel layer 210, which serves as a channel for the semiconductor structure. The sacrificial layer 220 provides a process basis for the subsequent floating arrangement of the channel layer 210 and also occupies space for the subsequently formed gate structure. In subsequent processes, the sacrificial layer 220 is removed, leaving the channel layer 210 floating. A gate structure is then formed between the channel layer 210 and the substrate 100, and between adjacent channel layers 210.

[0063] The top, bottom, and sidewalls of the channel layer 210 covered by the gate structure are used as channels. In this embodiment, the top, bottom, and sidewalls of the channel layer 210 can all serve as channels, increasing the area of ​​the channel layer 210 used as channels, thereby increasing the operating current of the semiconductor structure.

[0064] Reference Figure 14 , Figure 14 This is a top view of any channel structure 250, which includes a channel region 250a along its extending direction. The channel layer 210 of the channel region 250a is used as a channel for a transistor.

[0065] In this embodiment, depending on the performance requirements of the transistor, the material of the channel layer 210 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. In this embodiment, the material of the channel layer 210 is silicon.

[0066] It should be noted that in this embodiment, the channel layer 210 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0067] The materials of the sacrificial layer 220 and the channel layer 210 have an etching selectivity ratio, which facilitates the subsequent removal of the sacrificial layer 220 and reduces damage to the channel layer 210. Specifically, the material of the sacrificial layer 220 includes silicon, germanium, or silicon germanide.

[0068] In this embodiment, the channel layer 210 is made of silicon; therefore, the sacrificial layer 220 is made of silicon germanide. The silicon germanide and silicon can achieve a large etching selectivity ratio.

[0069] It should be noted that the semiconductor structure may further include: a fin (not shown) located on the substrate 100; and an isolation layer (not shown) located on the substrate 100 where the fin is exposed, and covering the sidewalls of the fin. Correspondingly, a channel structure 250 is located on the isolation layer. The isolation layer may be a shallow trench isolation structure.

[0070] In this embodiment, during the step of forming the channel structure 250, the height H of the channel layer 210 in the NMOS region 100N is less than the height H of the channel layer 210 in the PMOS region 100P, thereby making the aspect ratio H / W of the channel layer 210 in the NMOS region 100N less than the aspect ratio H / W of the channel layer 210 in the PMOS region 100P.

[0071] Since the top, bottom, and sidewalls of the channel layer 210, which are covered by the gate structure, are used as channels, in a PMOS, the mobility of charge carriers on the sidewalls of the channel layer 210 is greater than their mobility on the top of the channel layer 210. By making the height H of the channel layer 210 in the NMOS region 100N smaller than the height H of the channel layer 210 in the PMOS region 100P, the sidewall size of the channel layer 210 in the PMOS region 100P is increased, which is beneficial to increasing the operating current of the PMOS.

[0072] Correspondingly, when the height H of the channel layer 210 in the PMOS region 100P meets the performance requirements of the PMOS, it is easy to adjust the width W of the channel layer 210 to meet the performance requirements of the NMOS. In the NMOS, the carrier mobility at the top and bottom of the channel layer 210 is greater than its mobility on the sidewalls of the channel layer 210. Therefore, in the NMOS region 100N, by increasing the width W of the channel layer 210, the top and bottom dimensions of the channel layer 210 can be increased accordingly, thereby facilitating an increase in the operating current of the NMOS.

[0073] As an example, the width W of the channel layer 210 in the NMOS region 100N is greater than the width W of the channel layer 210 in the PMOS region 100P. In an NMOS, the mobility of charge carriers at the top and bottom of the channel layer 210 is greater than their mobility on the sidewalls of the channel layer 210. Increasing the top and bottom dimensions of the channel layer 210 in the NMOS region 100N facilitates an increase in the operating current of the NMOS.

[0074] In this embodiment, according to the performance requirements of the transistor, the dimensions of the channel layer 210 can also meet the following conditions: the width W of the channel layer 210 in the NMOS region 100N is equal to the width W of the channel layer 210 in the PMOS region 100P, and the height H of the channel layer 210 in the NMOS region 100N is less than the height H of the channel layer 210 in the PMOS region 100P.

[0075] Since the top, bottom, and sidewalls of the channel layer 210, covered by the gate structure, are used as channels, in NMOS, the carrier mobility at the top of the channel layer 210 is greater than its mobility at the sidewalls of the channel layer 210. In PMOS, the carrier mobility at the sidewalls of the channel layer 210 is greater than its mobility at the top of the channel layer 210. The width W of the channel layer 210 in the NMOS region 100N is equal to the width W of the channel layer 210 in the PMOS region 100P. If the height H of layer 210 is less than the height H of channel layer 210 in PMOS region 100P, then for NMOS region 100N, the top dimension of channel layer 210 is increased in a targeted manner compared to the sidewall dimension of channel layer 210, which is beneficial to increasing the operating current of NMOS. Similarly, for PMOS region 100P, the sidewall dimension of channel layer 210 is increased in a targeted manner compared to the top dimension of channel layer 210, which is beneficial to increasing the operating current of PMOS.

[0076] In other embodiments, depending on the performance requirements of the transistor, the width of the channel layer in the NMOS region may be greater than the width of the channel layer in the PMOS region, and the height of the channel layer in the NMOS region may be less than the height of the channel layer in the PMOS region. Specifically, by intentionally increasing the width and height of the channel layer in the NMOS region, the performance requirements of both NMOS and PMOS can be met simultaneously.

[0077] In the NMOS region 100N, the aspect ratio H / W of the channel layer 210 cannot be too large or too small. Since the top, bottom, and sidewalls of the channel layer 210, covered by the gate structure, serve as the channel, in NMOS, the carrier mobility at the top of the channel layer 210 is greater than its mobility at the sidewalls. If the aspect ratio H / W of the channel layer 210 is too large, the height H of the channel layer 210 will be too large and the width W too small, resulting in an excessively small top dimension of the channel layer 210. This makes it difficult to increase the operating current of the NMOS and improve the performance of the semiconductor structure. Conversely, if the aspect ratio H / W of the channel layer 210 is too small, the height H will be too small and the width W too large, making the channel layer 210 too thin. This increases the manufacturing difficulty and the risk of breakage, affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the NMOS region 100N, the aspect ratio H / W of the channel layer 210 is 1:6 to 1:1.

[0078] In the PMOS region 100P, the aspect ratio H / W of the channel layer 210 cannot be too large or too small. If the aspect ratio H / W of the channel layer 210 is too large, the height H of the channel layer 210 will be too large and the width W too small, making the channel layer 210 too narrow, increasing the difficulty of forming the channel layer 210 and affecting the performance of the semiconductor structure. Since the top, bottom, and sidewalls of the channel layer 210 covered by the gate structure are used as channels, in PMOS, the mobility of charge carriers on the sidewalls of the channel layer 210 is greater than their mobility on the top of the channel layer 210. If the aspect ratio H / W of the channel layer 210 is too small, the height H of the channel layer 210 will be too small and the width W too large, resulting in the sidewall size of the channel layer 210 being too small, making it difficult to increase the operating current of the PMOS and improve the performance of the semiconductor structure. Therefore, in this embodiment, in the PMOS region 100P, the aspect ratio H / W of the channel layer 210 is 1:3 to 3:1.

[0079] In this embodiment, the number of channel layers 210 in the NMOS region 100N is equal to the number of channel layers 210 in the PMOS region 100P.

[0080] The number of channel layers 210 in the NMOS region 100N is equal to the number of channel layers 210 in the PMOS region 100P. This is beneficial because the channel layers 210 in the NMOS region 100N and the PMOS region 100P are formed in the same step during the formation of the channel layers 210, which simplifies the process flow and improves process efficiency.

[0081] In this embodiment, the number of trench layers 210 is 1 to 5. The number of trench layers 210 cannot be too large; if the number of trench layers 210 is too large, it greatly increases the difficulty of forming the trench layers 210 and easily leads to unnecessary process waste. Therefore, in this embodiment, the number of trench layers 210 is 1 to 5.

[0082] Specifically, in conjunction with reference Figures 3 to 5 The step of forming the channel structure 250 includes: forming a channel structure material layer (not shown) on the substrate 100, including one or more stacked channel material stacks 130, each of the channel material stacks 130 including a sacrificial material layer 120 and a channel material layer 110 located on the sacrificial material layer 120, wherein the height H1 of the channel material layer 110 of the NMOS region 100N is less than the height H2 of the channel material layer of the PMOS region 100P.

[0083] The channel structure material layer is used to form the channel structure 250, the channel material stack 130 is used to form the channel stack 200, the sacrificial material layer 120 is used to form the sacrificial layer 220, and the channel material layer 110 is used to form the channel layer 210. The height H1 of the channel material layer 110 in the NMOS region 100N is less than the height H2 of the channel material layer in the PMOS region 100P, which is beneficial to the fact that the height H of the channel layer 210 in the NMOS region 100N is less than the height H of the channel layer 210 in the PMOS region 100N formed subsequently.

[0084] In this embodiment, the material of the channel material layer 110 includes silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In this embodiment, the material of the channel material layer 110 is silicon, which is used to directly form the channel layer 210 in the subsequent process.

[0085] In this embodiment, the material of the sacrificial material layer 120 includes silicon germanide, which is used to directly form the sacrificial layer 220 in the future.

[0086] In this embodiment, one or more film formation processes are performed to form a channel structure material layer on the substrate 100. The number of film formation processes is equal to the number of channel material stacks 130. Each film formation process corresponds one-to-one with a channel material stack 130, that is, each film formation process is used to form a channel material stack 130 in the NMOS region 100N and PMOS region 100P in the normal direction of the surface of the substrate 100.

[0087] Each of the channel material stacks 130 includes a sacrificial material layer 120 and a channel material layer 110 located on the sacrificial material layer 120. Therefore, by performing one or more film formation processes, the height H1 of the channel material layer 110 of each channel material stack 130 in the NMOS region 100N is adjusted so that the height H1 of the channel material layer 110 of the NMOS region 100N is less than the height H2 of the channel material layer of the PMOS region 100P.

[0088] The one or more film formation processes are used to define the film height of the channel material layer 110 of the NMOS region 100N and PMOS region 100P.

[0089] Reference Figure 3 and Figure 4 The film formation process includes: forming a sacrificial material layer 120 and an initial channel material layer 140 covering the sacrificial material layer 120 on the substrate 100; thinning the initial channel material layer 140 in the NMOS region 100N to form the channel material layer 110.

[0090] Thinning the initial channel material layer 140 in the NMOS region 100N reduces the height H1 of the channel material layer 110 formed in the NMOS region 100N, achieving the effect that the height H1 of the channel material layer 110 in the NMOS region 100N is less than the height H2 of the channel material layer in the PMOS region 100P, thereby making the height H of the channel layer 210 formed in the NMOS region 100N less than the height H of the channel layer 210 in the PMOS region 100N.

[0091] Specifically, refer to Figure 3 During the film formation process, the step of thinning the initial channel material layer 140 in the NMOS region 100N includes: forming a protective layer 230 on the initial channel material layer 140 of the PMOS region 100P, wherein the protective layer 230 exposes the initial channel material layer 140 of the NMOS region 100N.

[0092] The protective layer 230 is used to cover the initial channel material layer 140 of the PMOS region 100P, thereby reducing the damage to the initial channel material layer 140 of the PMOS region 100P caused by the process of thinning the initial channel material layer 140 in the NMOS region 100N.

[0093] The protective layer 230 includes photoresist, which can effectively cover the initial channel material layer 140 of the PMOS region 100P.

[0094] refer to Figure 4 The initial channel material layer 140, with a portion of its thickness removed from the protective layer 230, is used to form a channel material layer 110, achieving the effect that the height H1 of the channel material layer 110 in the NMOS region 100N is less than the height H2 of the channel material layer in the PMOS region 100P.

[0095] In this embodiment, after removing the portion of the initial channel material layer 140 exposed by the protective layer 230, the protective layer 230 is removed to prepare for subsequent stacking of the channel material stack 130 or the formation of a mask layer.

[0096] In this embodiment, the sacrificial material layer 120 and the initial channel material layer 140 are formed using atomic layer deposition (ALD).

[0097] The sacrificial material layer 120 and the initial channel material layer 140 formed by the atomic layer deposition process have good thickness uniformity. After one film formation process, a step morphology is easily generated between the NMOS region 100N and the PMOS region 100P. The atomic layer deposition process has good step coverage capability. Therefore, the atomic layer deposition process is beneficial to form a stacked channel material stack 130 after each film formation process.

[0098] In this embodiment, the step of thinning the initial channel material layer 140 in the NMOS region 100N includes: using a dry etching process to etch away a portion of the thickness of the initial channel material layer 140 in the NMOS region 100N.

[0099] The dry etching process has anisotropic etching characteristics. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the initial channel material layer 140 in the PMOS region 100P. At the same time, the dry etching process has high controllability of etching effect, so it can better control the thickness of the initial channel material layer 140 after removing part of the thickness, thus meeting the process requirements.

[0100] It should be noted that, Figure 3 and Figure 4 Only the process of forming one channel material stack 130 is shown. To form multiple channel material stacks 130, simply repeat the process on the channel material stack 130 after its initial formation. Figure 3 and Figure 4 The steps are straightforward. (Refer to the original text.) Figure 5 , Figure 5 The diagram shows the trench structure material layer formed after all the film layer formation processes are completed.

[0101] Reference Figures 6 to 13 The channel structure material layer is graphically visualized to form a channel structure 250. During the graphical process, the sacrificial material layer 120 is graphically visualized as a sacrificial layer 220, and the channel material layer 110 is graphically visualized as a channel layer 210.

[0102] In this embodiment, the width W of the channel layer 210 in the NMOS region 100N is greater than or equal to the width W of the channel layer 210 in the PMOS region 100P.

[0103] By making the width W of the channel layer 210 in the NMOS region 100N greater than the width W of the channel layer 210 in the PMOS region 100P, the top and bottom dimensions of the channel layer 210 in the NMOS region 100N are increased, which is beneficial to increasing the operating current of the NMOS.

[0104] In this embodiment, a dry etching process is used to perform the patterning process.

[0105] The dry etching process has anisotropic etching characteristics. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to other film layers during the patterning process. At the same time, the dry etching process can obtain a better etching profile, thereby better controlling the width W and morphology of the trench layer 210 formed after patterning, and meeting the process requirements.

[0106] Reference Figures 6 to 12 The step of graphically representing the channel structure material layer includes: forming a mask layer 310 on the channel structure material layer of the NMOS region 100N and the PMOS region 100P, wherein the width D of the mask layer 310 in the NMOS region 100N is greater than or equal to the width D of the mask layer 310 in the PMOS region 100P.

[0107] The mask layer 310 is used as an etching mask for forming the channel structure 250.

[0108] The width D of the mask layer 310 in the NMOS region 100N can be entirely greater than the width D of the mask layer 310 in the PMOS region 100P, or it can be partially greater than the width D of the mask layer 310 in the PMOS region 100P, partially equal to the width D of the mask layer 310 in the PMOS region 100P, or entirely equal to the width D of the mask layer 310 in the PMOS region 100P.

[0109] The width D of the mask layer 310 in the NMOS region 100N is greater than the width D of the mask layer 310 in the PMOS region 100P, so that the width W of the channel layer 210 formed in the NMOS region 100N is greater than the width W of the channel layer 210 in the PMOS region 100P, thereby increasing the operating current of the NMOS.

[0110] The width D of the mask layer 310 in the NMOS region 100N is equal to the width D of the mask layer 310 in the PMOS region 100P, which is used to make the width W of the channel layer 210 in the NMOS region 100N partially equal to the width W of the channel layer 210 in the PMOS region 100P. As mentioned above, the height H of the channel layer 210 in the NMOS region 100N is less than the height H of the channel layer 210 in the PMOS region 100P. Therefore, even if the mask layer 310 in the NMOS region 100N is partially equal to the width D of the channel layer 210 in the PMOS region 100P, the width D of the channel layer 310 in the NMOS region 100N is not equal to the width D of the channel layer 210 in the PMOS region 100P. The width D of the film layer 310 is equal to the width D of the mask layer 310 in the PMOS region 100P. Therefore, for the NMOS region 100N, the top dimension of the channel layer 210 is increased in a targeted manner compared to the sidewall dimension of the channel layer 210, which is beneficial to increasing the operating current of the NMOS. Similarly, for the PMOS region 100P, the sidewall dimension of the channel layer 210 is increased in a targeted manner compared to the top dimension of the channel layer 210, which is beneficial to increasing the operating current of the PMOS.

[0111] In this embodiment, the mask layer 310 is a non-metallic mask layer, and the material of the mask layer 310 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 310 can be a single-layer structure or a stacked structure. As an example, the material of the mask layer 310 is silicon nitride, that is, the mask layer 310 is a single-layer structure.

[0112] In this embodiment, the mask layer 310 is formed using a self-aligned quadruple patterning (SAQP) process to meet the requirement of continuously decreasing feature size.

[0113] Specifically, refer to Figure 6 and Figure 7 The method of forming the mask layer 310 includes forming a mask material layer 300, a bottom core material layer 400 and a top core material layer 500 stacked sequentially from bottom to top on the channel structure material layer.

[0114] The mask material layer 300 is used to form the mask layer 310, the bottom core material layer 400 is used to form the second core layer, and the top core material layer 500 is used to form the first core layer.

[0115] It should be noted that, as Figure 6 As shown, due to the film formation process, a step-like morphology appears on the top of the trench structure material layer at the junction of the NMOS region 100N and the PMOS region 100P. In order to facilitate the accuracy of subsequent processes, the formed mask material layer 300 covers the step and is flush with the top.

[0116] The bottom core material layer 400 is made of amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride, or silicon carbonitride. The top core material layer 500 is made of amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride, or silicon carbonitride. In this embodiment, the bottom core material layer 400 is made of amorphous silicon, and the top core material layer 500 is made of silicon nitride.

[0117] refer to Figure 8 The top core material layer 500 is graphically represented to form a discrete first core layer 510.

[0118] Subsequently, a first sidewall is formed on the sidewall of the first core layer 510, and the first core layer 510 serves as a support for the subsequent formation of the first sidewall. The line width of the first core layer 510 and the spacing between adjacent first core layers 510 are also used to define the spacing between subsequent adjacent first sidewalls.

[0119] Continue to refer to Figure 8 A first sidewall 610 is formed on the sidewall of the first core layer 510.

[0120] The first sidewall 610 is used as an etching mask for subsequent etching of the bottom core material layer 400 to form the second core layer.

[0121] In this embodiment, the step of forming the first sidewall 610 includes: forming a first sidewall material layer (not shown) that conformally covers the top and sidewalls of the first core layer 510 and the top of the bottom core material layer 400; removing the first sidewall material layer located at the top of the first core layer 510 and the top of the bottom core material layer 400; and retaining the first sidewall material layer located at the sidewall of the first core layer 510 as the first sidewall 610.

[0122] In this embodiment, the atomic layer deposition process is used to form the first sidewall material layer, which is beneficial to improve the conformal coverage of the first sidewall material layer, as well as to improve the thickness uniformity of the first sidewall material layer and reduce the difficulty of accurately controlling the thickness of the first sidewall material layer, thereby improving the linewidth uniformity of the first sidewall 610.

[0123] In this embodiment, an anisotropic dry etching process is used to remove the first sidewall material layer located on top of the first core layer 510 and the bottom core material layer 400. The anisotropic dry etching process has the characteristics of anisotropic etching, thus enabling the removal of the first sidewall material layer on top of the first core layer 510 and the bottom core material layer 400 without a mask, while simultaneously retaining the first sidewall material layer on the sidewalls of the first core layer 510.

[0124] The material of the first sidewall 610 includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first sidewall 610 is titanium oxide. Since the first core layer 510 needs to be removed while retaining the first sidewall 610, the titanium oxide material has a high etching selectivity compared to amorphous silicon, which is beneficial for the first sidewall 610 to be retained in the subsequent step of removing the first core layer 510.

[0125] refer to Figure 9 After the first sidewall 610 is formed, the first core layer 510 is removed.

[0126] In this embodiment, a wet etching process is used to remove the first core layer 510. The wet etching process has relatively low cost, simple operation steps, and can achieve a large etching selectivity.

[0127] refer to Figure 10 After removing the first core layer 510, the bottom core material layer 400 is patterned using the first sidewall 610 as a mask to form a discrete second core layer 410.

[0128] A second sidewall is subsequently formed on the sidewall of the second core layer 410, which serves to support the subsequent formation of the first sidewall. The line width of the second core layer 410 and the spacing between adjacent second core layers 410 are also used to define the spacing between subsequent adjacent second sidewalls.

[0129] In this embodiment, a second sidewall 620 is formed on the sidewall of the second core layer 410, wherein at least a portion of the second core layer 410 is in contact with the second sidewall 620 on the opposite sidewall in the NMOS region 100N.

[0130] The second sidewall 620 is used as an etching mask for the subsequent formation of the mask layer 310.

[0131] In the NMOS region 100N, the contacting second sidewall 620 is used to increase the width of the second sidewall 620, thereby increasing the width D of the formed mask layer 310; the second sidewall 620 may also include uncontacting second sidewall 620, for the portion of the width D of the mask layer 310 in the NMOS region 100N is equal to the width D of the mask layer 310 in the PMOS region 100P.

[0132] In this embodiment, the step of forming the second sidewall 620 includes: forming a second sidewall material layer (not shown) that conformally covers the top and sidewalls of the second core layer 410 and the top of the mask material layer 300; removing the second sidewall material layer located on the top of the second core layer 410 and the top of the mask material layer 300; and retaining the second sidewall material layer located on the sidewall of the second core layer 410 as the second sidewall 620.

[0133] In this embodiment, the atomic layer deposition process is used to form the second sidewall material layer, which is beneficial to improve the conformal coverage of the second sidewall material layer, as well as to improve the thickness uniformity of the second sidewall material layer and reduce the difficulty of accurately controlling the thickness of the second sidewall material layer, thereby improving the linewidth uniformity of the second sidewall 620.

[0134] In this embodiment, an anisotropic dry etching process is used to remove the second sidewall material layer located on top of the second core layer 410 and the mask material layer 300. The anisotropic dry etching process has the characteristics of anisotropic etching, thus enabling the removal of the second sidewall material layer on top of the second core layer 410 and the mask material layer 300 without a mask, while simultaneously retaining the second sidewall material layer on the sidewalls of the second core layer 410.

[0135] The material of the second sidewall 620 includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the second sidewall 620 is titanium oxide. Since the second core layer 410 needs to be removed subsequently while retaining the second sidewall 620, the titanium oxide and silicon oxide materials have significant etching selectivity, which is beneficial for the second sidewall 620 to be retained in the subsequent step of removing the second core layer 410.

[0136] It should be noted that, since at least a portion of the second core layer 410 is in contact with the second sidewalls 620 on the opposite sidewalls, in this embodiment, the contacting second sidewalls 620 are designated as first-type sidewalls, and the remaining second sidewalls 620 are designated as second-type sidewalls. Based on the interval between adjacent second core layers 410, the width of the first-type sidewalls is greater than or equal to the width of the second-type sidewalls. Specifically, when the interval between adjacent second core layers 410 is less than or equal to twice the width of the second-type sidewalls, the second sidewalls 620 on the opposite sidewalls of the second core layer 410 can be in contact.

[0137] Therefore, with the width of the second type of sidewall (i.e., the second sidewall 620 that is not in contact) as the initial size, and the width of the first type of sidewall (i.e., the second sidewall 620 that is in contact) being one to two times the initial size, the width of the mask layer 310 formed is one to two times the initial size, and the width of the channel layer 210 formed is one to two times the initial size.

[0138] As an example, after the second sidewall 620 is formed, both the first type of sidewall and the second type of sidewall are formed.

[0139] refer to Figure 11 After the second sidewall 620 is formed, the second core layer 410 is removed.

[0140] In this embodiment, a wet etching process is used to remove the second core layer 410. The wet etching process has relatively low cost, simple operation steps, and can achieve a large etching selectivity.

[0141] refer to Figure 12 After removing the second core layer 410, the mask material layer 300 is patterned using the second sidewall 620 as a mask to form a discrete mask layer 310.

[0142] The mask layer 310 is used as an etching mask for forming the channel structure 250.

[0143] Reference Figure 13 and Figure 14 Using the mask layer 310 as a mask, the channel structure material layer is patterned to form the channel structure 250.

[0144] Using the mask layer 620 as a mask helps to control the width W dimension of the formed channel structure 250.

[0145] In this embodiment, the morphology of the channel layer 210 includes a rectangle on the vertical plane of the extending direction of the channel layer 210. In other embodiments, the morphology of the channel layer can also be trapezoidal, that is, the sidewall of the channel layer is perpendicular to or has an angle with the surface of the substrate.

[0146] The morphology of the channel layer 210 includes a rectangle or a trapezoid, which makes the morphology of the channel layer 210 easy to form in the process. Moreover, the rectangle or trapezoid is a quadrilateral, which can better expose the top and sidewalls of the channel layer 210 and make contact with the gate structure.

[0147] It should be noted that during the process of patterning the channel structure material layer using an etching process to form the channel structure 250, the etching parameters can be adjusted so that the external angle between the sidewall of the channel structure 250 and the surface of the substrate 100 is an obtuse angle, thereby forming the trapezoidal morphology of the channel layer 210.

[0148] In this embodiment, the forming method further includes: removing the mask layer 310 after forming the channel structure 250.

[0149] refer to Figure 15 Remove the sacrificial layer 220 of the channel region 250a.

[0150] Removing the sacrificial layer 220 of the channel region allows the channel layer 210 to be suspended, which also provides space for the formation of the gate structure.

[0151] In this embodiment, wet etching is used to remove the sacrificial layer 220. The wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which helps to reduce damage to the channel layer 210 during the removal of the sacrificial layer 220.

[0152] In this embodiment, before removing the sacrificial layer 220 of the channel region, the forming method further includes: forming a pseudo-gate structure (not shown) on the substrate 100, the pseudo-gate structure spanning the channel structure 250 of the channel region and covering part of the top and part of the sidewalls of the channel structure 250; and removing the pseudo-gate structure.

[0153] The pseudo-gate structure occupies space for the subsequent formation of the gate structure.

[0154] In this embodiment, the step of removing the sacrificial layer 220 in the channel region includes: after removing the pseudo-gate structure, removing the sacrificial layer 220 at the location of the pseudo-gate structure.

[0155] The dummy gate structure is removed to provide space for the subsequent formation of the gate structure, and at the same time, the sacrificial layer 220 is exposed in preparation for its removal.

[0156] Continue to refer to Figure 15 After removing the sacrificial layer 220 of the channel region, a gate dielectric layer 710 is formed in the channel region 250a, surrounding and covering the channel layer 210.

[0157] The gate dielectric layer 710 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 710 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0158] Continue to refer to Figure 15 A gate structure 700 is formed on the substrate 100, spanning the channel layer 210, and the gate structure 700 surrounds and covers the gate dielectric layer 710.

[0159] In this embodiment, the gate structure 700 surrounds and covers the gate dielectric layer 710, and the gate dielectric layer 710 surrounds and covers a portion of the top, a portion of the bottom, and a portion of the sidewalls of the channel layer 210. Thus, the gate structure 700 surrounds and covers a portion of the top, a portion of the bottom, and a portion of the sidewalls of the channel layer 210, increasing the area of ​​the channel layer structure 210 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0160] In this embodiment, the gate structure 700 is a device gate structure used to control the opening or closing of the transistor channel.

[0161] In this embodiment, the gate structure 700 includes a metal gate structure.

[0162] In this embodiment, the metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0163] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0164] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0165] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0166] In this embodiment, after removing the dummy gate structure and the sacrificial layer 220 at the location of the dummy gate structure, the gate structure 700 is formed at the location of the dummy gate structure.

[0167] The position of the gate structure 700 is defined by the pseudo-gate structure and the sacrificial layer 220 at the position of the pseudo-gate structure, which is beneficial to the process accuracy of forming the gate structure.

[0168] Figures 16 to 17 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0169] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that a channel layer with a width dimension greater than twice the initial dimension and a width dimension less than one time the initial dimension is formed.

[0170] refer to Figure 16 The method of forming the mask layer 312 further includes: after removing the second core layer (not shown), forming a photoresist 632 on the mask material layer 302 of the NMOS region 102N, the photoresist 632 covering part or all of the sidewalls of the second sidewall 622 that are in contact with each other.

[0171] As can be seen from the foregoing embodiments, the width of the second sidewall 620 is one to two times the initial size. When it is necessary to form a width greater than twice the initial size, photoresist 632 is formed on the sidewalls of the second sidewall 622 that are in partial or complete contact with each other to increase the width of the second sidewall 622 that are in contact with each other, thereby increasing the width of the mask layer that is subsequently formed to meet more process requirements, thereby increasing the width of the channel layer that is subsequently formed, and further increasing the operating current of the NMOS region 102N.

[0172] Specifically, photoresist 632 is formed at the target location through the coating, exposure, and development of photoresist material. The process of forming photoresist 632 causes minimal damage to the second sidewall 622 and the mask material layer 302.

[0173] It should be noted that during the process of forming photoresist 632 on the sidewalls of the second sidewall 622 that are in partial or complete contact, the photoresist may also cover the top of the second sidewall 622 that are in partial or complete contact.

[0174] Continue to refer to Figure 16The method of forming the mask layer 312 further includes: after removing the second core layer, removing part or all of the width of the second sidewall 622 in the PMOS region 102P.

[0175] As can be seen from the foregoing embodiments, the width of the second sidewall 620 is one to two times the initial size. When it is necessary to form a width smaller than one time the initial size, part or all of the width of the second sidewall 622 is removed to reduce the width of part or all of the second sidewall 622. This reduces the width of the mask layer to be formed later, thereby meeting more process requirements and reducing the width of the channel layer to be formed later. This increases the aspect ratio of the PMOS region 102P channel layer and improves the performance of the semiconductor structure.

[0176] In this embodiment, after removing part or all of the width of the second sidewall 622, a second sidewall 622 with a reduced width is obtained (e.g., Figure 16 (As shown by the dashed coil in the middle).

[0177] In this embodiment, dry etching is used to remove part or all of the width of the second sidewall 622. The dry etching has the characteristics of anisotropic etching, which can reduce the damage to the mask material layer 302 during the etching process. At the same time, the dry etching process has high controllability of etching effect and can control the size of the width of the second sidewall 622 removed more precisely.

[0178] Specifically, a cover layer (not shown) is formed to cover the second sidewall 622 in the PMOS region 102P that does not need to be narrowed, and the NMOS region 102N, while exposing the second sidewall 622 in the PMOS region 102P that needs to be narrowed; and a portion of the width of the exposed second sidewall 622 is removed.

[0179] Reference Figure 16 and Figure 17 Using the second sidewall 622 and photoresist 632 together as a mask, the mask material layer 302 is patterned to form a discrete mask layer 312.

[0180] Using the second sidewall 622 and photoresist 632 together as a mask, the width of the mask layer 312 formed can be one to two times the initial size, less than one time the initial size, or more than two times the initial size, to meet different process requirements. At the same time, the channel layer formed subsequently can further increase the operating current and improve the performance of the semiconductor structure.

[0181] For a detailed description of the formation method described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0182] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an NMOS region and a PMOS region, wherein the NMOS region is used to form an NMOS transistor and the PMOS region is used to form a PMOS transistor; A channel layer structure is respectively suspended on the substrates of the NMOS region and the PMOS region. The channel layer structure includes one or more channel layers spaced apart. The aspect ratio of the channel layer in the NMOS region is smaller than that of the channel layer in the PMOS region. The aspect ratio refers to the ratio of the height to the width of the channel layer. The width of the channel layer in the NMOS region is greater than that in the PMOS region, and the height of the channel layer in the NMOS region is less than that in the PMOS region; or, the width of the channel layer in the NMOS region is equal to the width of the channel layer in the PMOS region, and the height of the channel layer in the NMOS region is less than that in the PMOS region. A gate dielectric layer is located in the NMOS and PMOS regions and surrounds a portion of the top and sidewalls of the channel layer. A gate structure is located on the substrate and spans the channel layer structure, the gate structure surrounding and covering the gate dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, In the NMOS region, the aspect ratio of the channel layer is 1:6 to 1:

1.

3. The semiconductor structure as described in claim 1, characterized in that, In the PMOS region, the aspect ratio of the channel layer is 1:3 to 3:

1.

4. The semiconductor structure as described in claim 1, characterized in that, The number of channel layers in the NMOS region is equal to the number of channel layers in the PMOS region.

5. The semiconductor structure as described in claim 1, characterized in that, On a plane perpendicular to the extension direction of the channel layer, the morphology of the channel layer includes rectangular or trapezoidal shapes.

6. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a metal gate structure.

7. The semiconductor structure as described in claim 1, characterized in that, The channel layer material includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

8. The semiconductor structure as described in claim 1, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

9. The semiconductor structure as described in claim 6, characterized in that, The metal gate structure includes a gate electrode layer, and the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including an NMOS region and a PMOS region, wherein the NMOS region is used to form an NMOS transistor and the PMOS region is used to form a PMOS transistor; Discrete channel structures are formed on the substrates of the NMOS and PMOS regions. The channel structures include one or more stacked channel layers, each of which includes a sacrificial layer and a channel layer located on the sacrificial layer. The aspect ratio of the channel layer in the NMOS region is smaller than that of the channel layer in the PMOS region. Along the extension direction of the channel structure, the channel structure includes a channel region. The aspect ratio of the channel layer refers to the ratio of the height to the width of the channel layer. In the step of forming the channel structure, the width of the channel layer in the NMOS region is greater than the width of the channel layer in the PMOS region, and the height of the channel layer in the NMOS region is less than the height of the channel layer in the PMOS region; or, the width of the channel layer in the NMOS region is equal to the width of the channel layer in the PMOS region, and the height of the channel layer in the NMOS region is less than the height of the channel layer in the PMOS region. Remove the sacrificial layer from the channel region; After removing the sacrificial layer in the channel region, a gate dielectric layer is formed in the channel region surrounding and covering the channel layer; A gate structure is formed on the substrate that spans the channel layer and surrounds the gate dielectric layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of forming the channel structure includes: forming a channel structure material layer on the substrate, including one or more stacked channel material stacks, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer; The channel structure material layer is patterned to form a channel structure. During the patterning process, the sacrificial material layer is patterned as a sacrificial layer, and the channel material layer is patterned as a channel layer. The width of the channel layer in the NMOS region is greater than or equal to the width of the channel layer in the PMOS region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of graphically representing the channel structure material layer includes: forming a mask layer on the channel structure material layer in the NMOS region and the PMOS region, wherein the width of the mask layer in the NMOS region is greater than or equal to the width of the mask layer in the PMOS region; Using the mask layer as a mask, the channel structure material layer is patterned; The formation method further includes removing the mask layer after forming the channel structure.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method of forming the mask layer includes: forming a mask material layer, a bottom core material layer and a top core material layer stacked sequentially from bottom to top on the channel structure material layer; The top core material layer is graphically represented to form a discrete first core layer; A first sidewall is formed on the sidewall of the first core layer; After the first sidewall is formed, the first core layer is removed; After removing the first core layer, the bottom core material layer is patterned using the first sidewall as a mask to form a discrete second core layer. A second sidewall is formed on the sidewall of the second core layer, wherein, in the NMOS region, at least a portion of the second core layer is in contact with the second sidewall on the opposite sidewall; After the second sidewall is formed, the second core layer is removed; After removing the second core layer, the mask material layer is patterned using the second sidewall as a mask to form discrete mask layers.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method of forming the mask layer further includes: after removing the second core layer, forming photoresist on the mask material layer of the NMOS region, wherein the photoresist covers part or all of the sidewalls of the second sidewalls in contact; Using the second sidewall and photoresist together as a mask, the mask material layer is patterned to form discrete mask layers.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method of forming the mask layer further includes: after removing the second core layer, removing part or all of the width of the second sidewall in the PMOS region.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of forming the channel structure includes: forming a channel structure material layer on the substrate, including one or more stacked channel material stacks, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer, wherein the height of the channel material layer in the NMOS region is less than the height of the channel material layer in the PMOS region; The channel structure material layer is graphically represented to form a channel structure, and during the graphical representation process, the sacrificial material layer is graphically represented as a sacrificial layer, and the channel material layer is graphically represented as a channel layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, One or more film formation processes are performed to form a channel structure material layer on the substrate; The film formation process includes: forming a sacrificial material layer and an initial channel material layer covering the sacrificial material layer on the substrate; thinning the initial channel material layer in the NMOS region to form the channel material layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, During the film formation process, the step of thinning the initial channel material layer in the NMOS region includes: forming a protective layer on the initial channel material layer in the PMOS region, wherein the protective layer exposes the initial channel material layer in the NMOS region; The initial channel material layer, with a portion of its thickness exposed by removing the protective layer, is removed. After removing the portion of the initial channel material layer that is exposed by the protective layer, the protective layer is removed.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, The sacrificial material layer and the initial channel material layer are formed using an atomic layer deposition process.

20. The method for forming a semiconductor structure as described in claim 17, characterized in that, The step of thinning the initial channel material in the NMOS region includes: using a dry etching process to etch away a portion of the initial channel material layer in the NMOS region.

21. The method for forming a semiconductor structure as described in claim 11 or 16, characterized in that, The patterning process is performed using a dry etching process.

22. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before removing the sacrificial layer of the channel region, the forming method further includes: forming a dummy gate structure on the substrate, the dummy gate structure spanning the channel structure of the channel region and covering a portion of the top and a portion of the sidewalls of the channel structure; and removing the dummy gate structure. The step of removing the sacrificial layer in the channel region includes: after removing the pseudo-gate structure, removing the sacrificial layer at the location of the pseudo-gate structure; After removing the pseudo-gate structure and the sacrificial layer at the location of the pseudo-gate structure, a gate dielectric layer is formed around and covering the channel layer in the channel region.

23. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming discrete channel structures on the substrate, the material of the channel layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material, and the material of the sacrificial layer includes silicon, germanium, or silicon germanide.

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