Buried word line structure and manufacturing method thereof

By setting the channel layer to connect the barrier layer with an extension in the embedded word line structure, the leakage current problem caused by the too close distance between the embedded word line and the capacitor is solved, and the effect of effectively reducing the electric field is achieved.

CN115117060BActive Publication Date: 2025-05-13WINBOND ELECTRONICS CORP
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202110285290.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-03-17
Publication Date
2025-05-13
Estimated Expiration
2041-03-17

AI Technical Summary

Technical Problem

The distance between the buried word line and the capacitor arranged on the substrate is too close, causing the electrons stored in the capacitor to be attracted by the electric field generated by the buried word line, causing leakage current to occur.

Method used

In the embedded word line structure, a channel layer is provided to connect to a barrier layer with an extension to form an isolation structure to reduce the electric field in adjacent corner areas.

Benefits of technology

It effectively reduces the electric field near the buried word line, prevents electrons in the capacitor from being attracted, and reduces or avoids the generation of leakage current.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115117060B_ABST
    Figure CN115117060B_ABST
Patent Text Reader

Abstract

The present invention provides a buried word line structure and a manufacturing method thereof. The buried word line structure comprises a first isolation structure, a buried word line, a first barrier layer, a second barrier layer, a channel layer and a second isolation structure. The first isolation structure is arranged in a substrate and has a groove. The buried word line is arranged on the bottom surface of the groove. The first barrier layer is arranged between the buried word line and the sidewall and the bottom surface of the groove. The second barrier layer covers the top surface of the buried word line and comprises a main body part and an extension part, wherein the main body part is located on the buried word line, and the extension part extends upward from the periphery of the main body part. The channel layer is arranged on the first barrier layer and the second barrier layer. The second isolation structure is arranged on the channel layer.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a buried word line structure and a manufacturing method thereof. Background Art

[0002] In order to increase the integration level of dynamic random access memory to speed up the operation speed of components and meet the needs of consumers for miniaturized electronic devices, buried wordline dynamic random access memory (buried wordline DRAM) has been developed in recent years to meet the above needs.

[0003] Generally speaking, a buried word line can be disposed in an isolation structure. However, when the buried word line is too close to a capacitor disposed on a substrate, electrons stored in the capacitor are easily attracted by the electric field generated by the buried word line, resulting in leakage current. Summary of the invention

[0004] The invention is directed to a buried word line structure, wherein the buried word line is provided with a channel layer, and the channel layer is connected to a barrier layer arranged around the buried word line.

[0005] The present invention is directed to a method for manufacturing a buried word line structure, which is used to manufacture the buried word line structure.

[0006] According to an embodiment of the present invention, a buried word line structure includes a first isolation structure, a buried word line, a first barrier layer, a second barrier layer, a channel layer and a second isolation structure. The first isolation structure is arranged in a substrate and has a groove. The buried word line is arranged on the bottom surface of the groove. The first barrier layer is arranged between the buried word line and the sidewall and the bottom surface of the groove. The second barrier layer covers the top surface of the buried word line and includes a main body portion and an extension portion, wherein the main body portion is located on the buried word line, and the extension portion extends upward from the periphery of the main body portion. The channel layer is arranged on the first barrier layer and the second barrier layer. The second isolation structure is arranged on the channel layer.

[0007] According to an embodiment of the present invention, a method for manufacturing a buried word line structure includes the following steps. First, a first isolation structure is formed in a substrate. Then, a trench is formed in the first isolation structure. Then, a first barrier layer is formed on the lower sidewall and bottom surface of the trench. Then, a buried word line is formed on the first barrier layer. Then, a second barrier layer is formed on the top surface of the buried word line, wherein the second barrier layer includes a main body portion and an extension portion, the main body portion is located on the buried word line, and the extension portion extends upward from the periphery of the main body portion. Then, a channel layer is formed on the first barrier layer and the second barrier layer. After that, a second isolation structure is formed on the channel layer.

[0008] Based on the above, in the buried word line structure of the present invention, a barrier layer having an extension portion is formed on the buried word line, and a channel layer is formed on the barrier layer having the extension portion and extends downward beside the extension portion to connect with another barrier layer formed around the buried word line. In this way, when the device is operated, the electric field in the corner area adjacent to the buried word line can be effectively reduced to prevent the electrons stored in the capacitor from being attracted by the electric field generated by the buried word line and causing the generation of leakage current.

[0009] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1G FIG. 4 is a cross-sectional diagram of a manufacturing process of a buried word line structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] Figures 1A to 1G FIG. 4 is a cross-sectional diagram of a manufacturing process of a buried word line structure according to an embodiment of the present invention.

[0012] Reference Figure 1A , providing a substrate 100. The substrate 100 may be a semiconductor substrate. In the present embodiment, the substrate 100 is, for example, a silicon substrate. Next, a first isolation structure 102 is formed in the substrate 100. The first isolation structure 102 is, for example, a shallow trench isolation (STI) structure. In the present embodiment, the material of the first isolation structure 102 is, for example, silicon nitride, but the present invention is not limited thereto. In other embodiments, the material of the first isolation structure 102 may also be silicon oxide. Thereafter, a trench 104 is formed in the first isolation structure 102. The trench 104 is used to define a region for a buried word line to be formed subsequently.

[0013] Reference Figure 1BAfter forming the trench 104, an insulating layer 106 may be formed on the sidewalls and bottom surface of the trench 104. The insulating layer 106 is used to reduce interference between multiple buried word lines formed subsequently. In the present embodiment, the insulating layer 106 is, for example, an in situ steam generation (ISSG) oxide layer, but the present invention is not limited thereto. Next, a barrier material layer 108 is formed on the insulating layer 106 and on the surface of the substrate 100. In the present embodiment, the barrier material layer 108 is, for example, a titanium nitride layer, but the present invention is not limited thereto. Then, a word line material layer 110 is formed on the substrate 100 to fill the trench 104. In the present embodiment, the word line material layer 110 is, for example, a tungsten layer, but the present invention is not limited thereto.

[0014] Reference Figure 1C , an etch-back process is performed to remove a portion of the barrier material layer 108 and a portion of the word line material layer 110 to form a buried word line 112 and a first barrier layer 114 located between the buried word line 112 and the sidewall and bottom surface of the trench 104. In detail, in the present embodiment, during the etch-back process, the barrier material layer 108 and the word line material layer 110 on the surface of the substrate 100 and on the sidewall at the upper portion of the trench 104 are removed. Next, a dielectric layer 116 is formed on the surface of the substrate 100, on the sidewall of the trench 104, on the buried word line 112, and on the first barrier layer 114. An etching selectivity ratio is required between the dielectric layer 116 and the first isolation structure 102. In the present embodiment, since the material of the first isolation structure 102 is, for example, silicon nitride, the material of the dielectric layer 116 is, for example, silicon oxide. In other embodiments, when the material of the first isolation structure 102 is, for example, silicon oxide, the material of the dielectric layer 116 is, for example, silicon nitride. In addition, in order to prevent the subsequently formed channel layer from contacting the buried word line 112, the thickness of the dielectric layer 116 must not exceed the thickness of the first barrier layer 114, which will be described in detail later.

[0015] Please refer to Figure 1D, an etch-back process is performed to remove a portion of the dielectric layer 116 to form a dielectric structure 118. In detail, in the present embodiment, during the etch-back process, the dielectric layer 116 on the surface of the substrate 100, on the sidewall at the upper portion of the trench 104, and on the buried word line 112 is removed to expose the top surface of the buried word line 112, and the dielectric layer 116 on the sidewall at the lower portion of the trench 104 is retained. The retained dielectric layer 116 forms a dielectric structure 118 on the first barrier layer 114. Since the thickness of the dielectric layer 116 does not exceed the thickness of the first barrier layer 114, the formed dielectric structure 118 is only located on the first barrier layer 114 and does not contact the buried word line 112. In addition, since there is an etching selectivity between the dielectric layer 116 and the first isolation structure 102, the first isolation structure 102 will not be damaged during the above-mentioned etch-back process.

[0016] Please refer to Figure 1E , a barrier material layer 120 is formed on the surface of the substrate 100, on the sidewalls of the trench 104, on the top surface of the buried word line 112, and on the dielectric structure 118. In the present embodiment, the barrier material layer 120 is, for example, a titanium nitride layer, but the present invention is not limited thereto. Then, a protective material layer 122 is formed on the substrate 100 to fill the trench 104. In the present embodiment, the protective material layer 122 is, for example, a spin-on coating (SOC) layer, but the present invention is not limited thereto.

[0017] Please refer to Figure 1F , the protective material layer 122 is subjected to an etch-back process to remove a portion of the protective material layer 122, so as to form a protective layer 124 on the barrier material layer 120. The protective layer 124 exposes the barrier material layer 120 at the upper portion of the trench 104. In other words, the protective layer 124 covers the barrier material layer 120 on the top surface of the buried word line 112 and on the sidewalls and a portion of the top surface of the dielectric structure 118. Then, an anisotropic etching process is performed using the protective layer 124 as an etching mask to remove the barrier material layer 120 not covered by the protective layer 124. In this way, a second barrier layer 126 is formed on the top surface of the buried word line 112. In the present embodiment, the second barrier layer 126 includes a main portion 126a, an extension portion 126b, and a horizontal portion 126c. The main portion 126a is located on the top surface of the buried word line 112, the extension portion 126b extends upward from the periphery of the main portion 126a, and the horizontal portion 126c is connected to the top of the extension portion 126b to form a second barrier layer 126 with a "U"-shaped cross section.

[0018] The cross-sectional shape of the second barrier layer 126 can be changed by controlling the thickness of the barrier material layer 120. For example, in the present embodiment, the thickness of the barrier material layer 120 is less than the width of the dielectric structure 118, so the formed second barrier layer 126 may have a horizontal portion 126c. In another embodiment, when the thickness of the barrier material layer 120 is equal to the width of the dielectric structure 118, the formed second barrier layer 126 does not have a horizontal portion 126c. In addition, the thickness of the barrier material layer 120 cannot be greater than the width of the dielectric structure 118, otherwise the second barrier layer with an extended portion cannot be formed.

[0019] Reference Figure 1G , an etching process is performed to remove the dielectric structure 108 and the protective layer 124. Then, a channel layer 128 is formed on the first barrier layer 114 and the second barrier layer 126. The method for forming the channel layer 128 is, for example, to first form a channel material layer on the substrate 100 to fill the trench 104, and then perform a back etching process to remove the channel material layer on the surface of the substrate 100 and the upper part of the trench 104. It is particularly mentioned that when the component is operated, the electric field generated by the channel layer 128 must be lower than the electric field generated by the buried word line 112, which will be further described later. Therefore, in the present embodiment, when the buried word line 112 is, for example, a tungsten layer, the channel layer 128 is, for example, a polysilicon layer, but the present invention is not limited to this. In the present embodiment, after the above-mentioned etching back process, the second barrier layer 126 is not exposed, that is, the channel layer 128 completely covers the second barrier layer 126 and contacts the first barrier layer 114 around the second barrier layer 126, but the present invention is not limited thereto. In other embodiments, after the above-mentioned etching back process, the channel layer 128 may expose a portion of the second barrier layer 126, and the channel layer 128 is still in contact with the first barrier layer 114 around the second barrier layer 126. For example, the horizontal portion 126c and a portion of the extension portion 126b of the second barrier layer 126 may be exposed. Afterwards, a second isolation structure 130 is formed on the channel layer 128 to complete the buried word line structure 10 of the present embodiment. In the present embodiment, the material of the second isolation structure 130 is, for example, silicon nitride to prevent damage to the oxide layer on the substrate 100 during processing in subsequent processes.

[0020] The following will be Figure 1G The buried word line structure of the present invention is described by taking an example.

[0021] Please refer to Figure 1GIn the buried word line structure 10, a second barrier layer 126 having an extension portion 126b is disposed on the buried word line 112, and a channel layer 128 is disposed on the second barrier layer 126 and extends downward beside the extension portion 126b to be connected to the first barrier layer 114. In this way, when the device is operated, the electric field in the corner area adjacent to the buried word line 112 can be effectively reduced, so that the electrons stored in the capacitor subsequently formed on the substrate 100 are not easily attracted by the electric field generated by the buried word line 112, thereby reducing or even avoiding the generation of leakage current.

[0022] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A buried word line structure, characterized in that: include: A first isolation structure is disposed in the substrate and has a trench; A buried word line is disposed on the bottom surface of the trench; a first barrier layer disposed between the buried word line and the sidewall and bottom surface of the trench; a second barrier layer covering the top surface of the buried word line and comprising a main body portion and an extension portion, wherein the main body portion is located on the buried word line, and the extension portion extends upward from the periphery of the main body portion; A channel layer, disposed on the first barrier layer and the second barrier layer; as well as A second isolation structure is disposed on the channel layer, The channel layer covers the second barrier layer and is in contact with the first barrier layer.

2. The buried word line structure according to claim 1, wherein: The second barrier layer further includes a horizontal portion connected to a top of the extending portion.

3. The buried word line structure according to claim 1, wherein: The invention also comprises an insulating layer which is arranged on the side wall and the bottom surface of the groove and contacts the side wall and the bottom surface of the groove.

4. The buried word line structure according to claim 1, wherein: The buried word line includes a tungsten layer.

5. The buried word line structure according to claim 1, wherein: The channel layer includes a polysilicon layer.

6. A method for manufacturing a buried word line structure, characterized in that: include: forming a first isolation structure in the substrate; forming a trench in the first isolation structure; forming a first barrier layer on the lower sidewall and bottom surface of the trench; forming a buried word line on the first barrier layer; forming a second barrier layer on the top surface of the buried word line, wherein the second barrier layer comprises a main body portion and an extension portion, the main body portion is located on the buried word line, and the extension portion extends upward from the periphery of the main body portion; forming a channel layer on the first barrier layer and the second barrier layer; as well as forming a second isolation structure on the channel layer, The channel layer covers the second barrier layer and is in contact with the first barrier layer.

7. The method for manufacturing a buried word line structure according to claim 6, characterized in that: The method for forming the second barrier layer comprises: After forming the buried word line, forming a dielectric layer on the surface of the substrate, on the sidewalls of the trench, on the first barrier layer, and on the buried word line, wherein the thickness of the dielectric layer does not exceed the thickness of the first barrier layer; removing a portion of the dielectric layer to form a dielectric structure on the first barrier layer and expose a top surface of the buried word line; forming a barrier material layer on the surface of the substrate, on the sidewalls of the trench, on the dielectric structure, and on the top surface of the buried word line; forming a protection layer on the barrier material layer, wherein the protection layer exposes the barrier material layer at an upper portion of the trench; Using the protective layer as a mask, an anisotropic etching process is performed to remove a portion of the barrier material layer; and The protection layer and the dielectric structure are removed.

8. The method for manufacturing a buried word line structure according to claim 6, wherein: Before forming the first barrier layer, the method further includes forming an insulating layer on the sidewall and bottom surface of the trench.

Citation Information

Patent Citations

  • Semiconductor structure and forming method thereof

    CN114582867A