Semiconductor memory cell and method of forming the same

Abstract

A semiconductor memory cell and a method of forming the same are disclosed. The semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation between the transistor and the capacitor insulating layer, and in the doped region.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor memory cell including a doped region resistor and a method for manufacturing the same. Background Technology

[0002] Semiconductor memory elements, such as non-volatile memory (NVM), are widely used in a variety of electronic components, such as mobile phones, digital cameras, personal digital assistants, mobile computing devices, and other applications.

[0003] Typically, NVMs can be divided into multiple-time programmable (MTP) memories and single-time programmable (OTP) memories. MTP memories can be read and written multiple times. For example, electrically erasable programmable read-only memories (EEPROMs) and flash memory are designed with corresponding circuitry to support different operations such as programming, erasing, and reading. OTP memories have programming and reading capabilities but do not require circuitry for erasing operations.

[0004] An antifuse is a component that short-circuits at both ends after the fuse has melted. Typically, the two ends of an antifuse are separated by an insulating layer such as silicon oxide. In the open state, the two ends of the antifuse have a very high resistance. By applying a high voltage to break through the insulating layer, a short circuit is formed between the two ends of the antifuse, resulting in a low resistance of approximately 5–25 kΩ. Therefore, antifuses are well-suited for use in programmable memories. Programmable memories using antifuses offer better security protection due to their one-time programming (OTP) capability. Summary of the Invention

[0005] The present invention provides a semiconductor memory cell comprising a substrate having a first conductivity type, a doped region located in the substrate having a second conductivity type, the first conductivity type being complementary to the second conductivity type, a capacitor insulating layer and an upper electrode located on the doped region, a transistor located on the substrate, and a shallow trench isolation located between the transistor and the capacitor insulating layer and within the doped region.

[0006] The present invention further provides a method for forming a semiconductor memory cell, comprising providing a substrate having a first conductivity type, forming a doped region in the substrate, wherein the doped region has a second conductivity type and the first conductivity type is complementary to the second conductivity type, forming a capacitor insulating layer and an upper electrode on the doped region, forming a transistor on the substrate, and forming a shallow trench isolation between the transistor and the capacitor insulating layer and within the doped region.

[0007] This invention proposes an improved semiconductor memory element, characterized in that, in addition to a transistor and a capacitor, the semiconductor memory element also includes a resistor composed of doped regions disposed between the capacitor and the transistor. The resistor effectively reduces the voltage difference between the capacitor and the transistor, preventing excessive current from flowing into the transistor and causing damage. Furthermore, the size of the capacitor can be adjusted more flexibly. This invention offers the advantages of improved manufacturing process flexibility and enhanced semiconductor memory element quality. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a semiconductor memory cell;

[0009] Figure 2 Corresponding to the present invention Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor memory cell;

[0010] Figure 3 This is a circuit diagram of a semiconductor memory cell according to a preferred embodiment of the present invention;

[0011] Figure 4 Corresponding to the present invention Figure 3 A cross-sectional schematic diagram of a semiconductor memory cell.

[0012] Explanation of main component symbols

[0013] 1: Semiconductor memory cell

[0014] 2: Semiconductor memory unit

[0015] 10: Base

[0016] 12: Shallow trench isolation

[0017] 12A: Shallow trench isolation

[0018] 14: Doped region

[0019] 14A: Doped region

[0020] 20: Capacitor insulation layer

[0021] 22: Upper electrode

[0022] 24: High-concentration doped region

[0023] 30: Transistor insulating layer

[0024] 32: Gate

[0025] 40: Doped region

[0026] 50: Contact Structure

[0027] C: Capacitor

[0028] R: Resistance

[0029] T: Transistor

[0030] BL: Bitline

[0031] SL: Select Line

[0032] WL: Character line

[0033] P1: Current path

[0034] P2: Current path Detailed Implementation

[0035] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0036] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art as referring to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0037] Please refer to this first. Figure 1 and Figure 2 , Figure 1 Draw a circuit diagram of a semiconductor memory cell. Figure 2 Illustration of the corresponding invention Figure 1 A cross-sectional view of a semiconductor memory cell. (See diagram below.) Figure 1As shown, a semiconductor memory cell 1 is provided. The gate of transistor T is connected to a character line WL. One end of the source / drain of transistor T (taking the source as an example) is connected to capacitor C, and the other end of the source / drain of transistor T (taking the drain as an example) is connected to a bit line BL. The other end of capacitor C is connected to a select line SL. In other words, semiconductor memory cell 1 is mainly composed of a transistor T and a capacitor C, and therefore can also be called a transistor-capacitor (1T1C) memory cell. Furthermore, semiconductor memory cell 1 is controlled by the character line WL, the bit line BL, and the select line SL.

[0038] Please refer to Figure 2 The semiconductor memory cell 1 includes a substrate 10, such as a P-type silicon substrate (P-Sub). The substrate 10 contains multiple shallow trench isolation (STI) layers 12 and a portion of a doped region 14. The shallow trench isolation layers 12 contain an insulating material, and the doped regions 14 are doped with ions and therefore conductive. A portion of the doped region 14 (or doped region 14A) can be used as the source / drain of a transistor T. In this embodiment, the doped region 14 is, for example, a high-concentration N-type doped region. That is, the doped region 14 and the substrate 10 contain different conductivity types. The semiconductor memory cell 1 also includes a capacitor C, which includes a capacitor insulating layer 20 located on the substrate, an upper electrode 22, and a high-concentration doped region 24 within the substrate 10. The capacitor insulating layer 20 contains an insulating material, such as silicon oxide; the upper electrode 22 contains a conductive material, such as metal or polysilicon; and the high-concentration doped region 24, located within the substrate 10 and having conductive characteristics, can be used as the lower electrode of the capacitor C, for example, a high-concentration N-type doped region.

[0039] The semiconductor memory cell 1 also includes a transistor T, wherein the transistor T includes a transistor insulating layer 30 and a gate 32 formed on the substrate 10, and the gate 32, the transistor insulating layer 30 and the doped region 14 (as source / drain) located in part of the substrate 10 together constitute the transistor T.

[0040] In addition, transistor T and capacitor C can be connected to the character line WL and select line SL respectively, and one of the source / drain terminals (doped region 14) of the transistor is connected to bit line BL.

[0041] Additionally, the semiconductor memory cell 1 may selectively include multiple contact structures 50 to connect various components. For example, these may connect the aforementioned transistor T, capacitor C, doped region 14, character line WL, bit line BL, select line SL, etc. The contact structures 50 may contain conductive materials, such as metals, but are not limited to these.

[0042] When operating a semiconductor memory cell, an insulating layer is initially present between the upper and lower electrodes of capacitor C, thus setting the semiconductor memory cell to a high-resistance state (H). During programming, the character line WL controls and turns on the gate of transistor T, introducing an external voltage (e.g., via the select line SL). When the voltage is sufficiently high and passes through capacitor C, capacitor C breaks down, allowing current to flow and reducing the resistance from high to low (L). For example, based on the applicant's experimental results, under a fixed voltage, a current greater than 10 μA (microamperes) is considered low resistance in a semiconductor memory cell, while a current less than 10 nA (nanoamperes) is considered high resistance. It is also worth noting that a complete memory can contain an array of multiple semiconductor memory cells 1 described above. Data is stored by programming selected semiconductor memory cells.

[0043] The applicant discovered Figure 2 The semiconductor memory cell 1 has a drawback: when a high voltage is applied to the capacitor C from the outside, the current path will sequentially pass through the capacitor C and the transistor T (e.g., ...). Figure 2 As shown in the current path P1, when the current passes through the transistor T, a large voltage difference and a large current are easily generated between the source / drain of the transistor T (doped region 14A) and the transistor insulating layer 30, which may damage the transistor T (for example, cause the transistor T to break down), affecting the accuracy of the semiconductor memory cell.

[0044] Therefore, to avoid the above problems, this invention proposes an improved semiconductor memory cell, please refer to [reference needed]. Figure 3 and Figure 4 , Figure 3 A circuit diagram illustrating a semiconductor memory cell according to a preferred embodiment of the present invention is shown. Figure 4 Illustration of the corresponding invention Figure 3 A cross-sectional structural diagram of a semiconductor memory cell is shown below. To clearly illustrate the differences between the various embodiments, the following paragraphs will describe the differences between the embodiments. Other identical components will be indicated by the same reference numerals, and these identical components have the same characteristics, such as having the same material or the same manufacturing process, and therefore will not be described in detail.

[0045] like Figure 3 As shown, the semiconductor memory cell 2 proposed in this embodiment, in addition to the transistor T and capacitor C mentioned above, also includes a resistor R. Therefore, as can be seen from the circuit diagram, the semiconductor memory cell 2 is mainly composed of a transistor T, a capacitor C and a resistor R, and can therefore also be called a one-transistor-one-capacitor-one-resistor (1T1C1R) memory cell.

[0046] like Figure 4 As shown, this embodiment is similar to the one described above. Figure 2 The illustrated embodiment differs in that the lower electrode (i.e., the highly doped region 24) contained in resistor C is replaced by a larger and deeper doped region 40, wherein the doped region 40 also has a conductivity type opposite to that of the substrate 10 (e.g., N-type). Additionally, at least one shallow trench isolation (e.g., Figure 4 The shallow trench isolation 12A is located within the doped region 40 and between the transistor T and the capacitor C. The depth of the doped region 40 is greater than the depth of the shallow trench isolation 12A. It is also worth noting that the doping concentration of the doped region 40 may exhibit a gradient decrease, for example, gradually decreasing from top to bottom. Furthermore, in this embodiment, the width of the upper electrode 22 of the capacitor C may be greater than the width of the capacitor insulating layer 20, and a portion of the upper electrode 22 may cover the shallow trench isolation 12 or the shallow trench isolation 12A.

[0047] The feature of this embodiment is that, since the lower electrode of capacitor C is replaced by a doped region 40, the depth of the doped region 40 is greater than the depth of the shallow trench isolation 12A, and the doping concentration of the doped region 40 gradually decreases from top to bottom, the doped region 40 can act as a resistor R, connecting capacitor C and transistor T. See reference... Figure 4 The indicated current path P2, when current is introduced from the selection line SL, will sequentially pass through capacitor C, bypass the bottom of shallow trench isolation 12A (i.e., through resistor R), and transistor T, and then flow out from the bit line at the drain terminal of transistor T. The doping concentration of the doped region 40 decreases from top to bottom, therefore the resistance value within the doped region 40 increases from top to bottom. When current passes through the doped region 40, the current value can be effectively reduced. This embodiment has the following advantages: First, the presence of resistor R can reduce the current between capacitor C and transistor T, preventing excessive current from affecting transistor T and improving the quality of the semiconductor memory cell. Second, the resistance value of resistor R can be adjusted according to the doping concentration of the doped region 40 and the depth of the shallow trench isolation 12A, making the manufacturing process more flexible. Furthermore, since the area of ​​the doped region 40, which serves as the lower electrode of capacitor C, is increased, the size of the upper electrode 22 of capacitor C can also be enlarged as needed, without being limited by the size of the lower electrode.

[0048] Based on the above figures and description paragraphs, the present invention provides a semiconductor memory cell 2, comprising a substrate 10, wherein the substrate 10 contains a first conductivity type (e.g., P-type), a doped region 40 located in the substrate 10, wherein the doped region 10 has a second conductivity type (e.g., N-type), and the first conductivity type (P-type) and the second conductivity type (N-type) are complementary, a capacitor insulating layer 20 and an upper electrode 22 are located on the doped region 40, a transistor T is located on the substrate 10, and a shallow trench isolation 12A is located between the transistor T and the capacitor insulating layer 20, and is located within the doped region 40.

[0049] According to another aspect of the present invention, a method for forming a semiconductor memory cell 2 is provided, comprising providing a substrate 10, the substrate 10 including a first conductivity type (e.g., P-type), forming a doped region 40 located in the substrate 10, wherein the doped region 10 has a second conductivity type (e.g., N-type), and the first conductivity type (P-type) and the second conductivity type (N-type) are complementary, forming a capacitor insulating layer 20 and an upper electrode 22 located on the doped region 40, forming a transistor T located on the substrate 10, and forming a shallow trench isolation 12A located between the transistor T and the capacitor insulating layer 20, and located within the doped region 40.

[0050] In some embodiments of the present invention, the depth of the doped region 40 is greater than the depth of the shallow trench isolation 12A.

[0051] In some embodiments of the present invention, the capacitor insulating layer 20, the upper electrode 22, and a portion of the doped region 40 together form a capacitor C.

[0052] In some embodiments of the present invention, a selection line SL is also included, which is electrically connected to a capacitor.

[0053] In some embodiments of the present invention, the doped region 40 has ions of a second conductivity type (e.g., N-type), and the doping concentration of the ions gradually decreases from top to bottom.

[0054] In some embodiments of the present invention, a character line WL is further included, electrically connected to a gate of transistor T, wherein the gate of transistor is not located directly above doped region 40.

[0055] In some embodiments of the invention, one source of the transistor ( Figure 4 The doped region 14A to the right of the transistor T is located in the substrate 10, and the source has a second conductivity type (N-type).

[0056] In some embodiments of the present invention, the source ( Figure 4A portion of the doped region 14A to the right of the transistor T is located within the doped region 40, and another portion of the source is located in the substrate 10 having the first conductivity type (P-type).

[0057] In some embodiments of the present invention, transistor T includes a drain ( Figure 4 The doped region 14 to the left of the transistor T is located in the substrate 10 and also contains a bit line BL electrically connected to the drain.

[0058] In some embodiments of the invention, a portion of the upper electrode 22 covers directly above the shallow trench isolation 12A, and a width of the capacitor insulating layer 20 is smaller than a width of the upper electrode 22.

[0059] In summary, this invention proposes an improved semiconductor memory element, characterized in that, in addition to a transistor and a capacitor, the semiconductor memory element also includes a resistor composed of doped regions disposed between the capacitor and the transistor. The resistor can effectively reduce the voltage difference between the capacitor and the transistor, preventing excessive current from flowing into the transistor and causing damage. Furthermore, the size of the capacitor can be adjusted more flexibly. This invention has the advantages of improving manufacturing process flexibility and enhancing the quality of the semiconductor memory element.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory cell, characterized in that, Include: A substrate containing a first conductivity type; A doped region is located in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, wherein the doped region has ions of the second conductivity type, and the doping concentration of the ions gradually decreases from top to bottom; The capacitor insulating layer and the upper electrode are located on this doped region; A transistor is located on the substrate, wherein the gate of the transistor is not located directly above the doped region; as well as Shallow trench isolation is located between the transistor and the capacitor insulating layer, and within the doped region.

2. The semiconductor memory cell of claim 1, wherein the depth of the doped region is greater than the depth of the shallow trench isolation.

3. The semiconductor memory cell of claim 1, wherein the capacitor insulating layer, the upper electrode, and a portion of the doped region together form a capacitor.

4. The semiconductor memory cell of claim 3, further comprising a select line (SL) electrically connected to the capacitor.

5. The semiconductor memory cell of claim 1, further comprising a character line electrically connected to the gate of the transistor.

6. The semiconductor memory cell of claim 1, wherein the source of the transistor is located in the substrate and the source has the second conductivity type.

7. The semiconductor memory cell of claim 6, wherein a portion of the source is located within the doped region and another portion of the source is located in the substrate having the first conductivity type.

8. The semiconductor memory cell of claim 6, wherein the transistor includes a drain located in the substrate and further includes a bit line (BL) electrically connected to the drain.

9. The semiconductor memory cell of claim 1, wherein a portion of the upper electrode covers directly above the shallow trench isolation, and the width of the capacitor insulating layer is smaller than the width of the upper electrode.

10. A method for forming a semiconductor memory cell, comprising: A substrate is provided, which contains a first conductivity type; A doped region is formed in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, wherein the doped region has ions of the second conductivity type, and the doping concentration of the ions gradually decreases from top to bottom; A capacitor insulating layer and an upper electrode are formed on the doped region; A transistor is formed on the substrate, wherein the gate of the transistor is not located directly above the doped region; and A shallow trench is formed between the transistor and the capacitor insulating layer, and is located within the doped region.

11. The formation method of claim 10, wherein the depth of the doped region is greater than the depth of the shallow trench isolation.

12. The forming method of claim 10, wherein the capacitor insulating layer, the upper electrode, and a portion of the doped region together form the capacitor.

13. The forming method of claim 12, further comprising a select line (SL) electrically connected to the capacitor.

14. The forming method of claim 10, further comprising forming a character line electrically connected to the gate of the transistor.

15. The method of forming as claimed in claim 10, wherein the source of the transistor is located in the substrate and the source has the second conductivity type.

16. The formation method of claim 15, wherein a portion of the source electrode is located within the doped region, and another portion of the source electrode is located in the substrate having the first conductivity type.

17. The method of forming as claimed in claim 15, wherein the transistor includes a drain located in the substrate and further includes a bit line (BL) electrically connected to the drain.

18. The forming method of claim 10, wherein a portion of the upper electrode covers directly above the shallow trench isolation, and the width of the capacitor insulating layer is smaller than the width of the upper electrode.

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