Semiconductor devices

Abstract

The embodiments provide a semiconductor device capable of implementing multiple gate drives. The semiconductor device of the embodiments includes: a first trench and a second trench extending in a first direction; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate wiring connected to the first gate electrode, including a first portion extending in a second direction perpendicular to the first direction, a second portion extending in the first direction, and a third portion extending in the second direction; a second gate wiring connected to the second gate electrode, including a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; a first gate electrode pad; and a second gate electrode pad; a first portion of the second gate wiring located between the first portion and the third portion of the first gate wiring, and a third portion of the first gate wiring located between the first portion and the third portion of the second gate wiring.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-47617 (filed on March 22, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] An example of a power semiconductor device is the Insulated Gate Bipolar Transistor (IGBT). An IGBT, for example, has a p-type collector region, an n-type drift region, and a p-type base region on its collector electrode. Furthermore, a gate electrode is provided in a trench that extends through the p-type base region and reaches the n-type drift region, separated by a gate insulating film. Moreover, an n-type emitter region, connected to the emitter electrode, is provided in a region adjacent to the trench on the surface of the p-type base region.

[0005] In an IGBT, a channel is formed in the base region of the p-type electrode by applying a positive voltage above a threshold voltage to the gate electrode. Simultaneously, electrons are injected from the emitter region of the n-type electrode into the drift region of the n-type electrode, while holes are injected from the collector region into the drift region of the n-type electrode. As a result, a current carrying electrons and holes flows between the collector and emitter electrodes.

[0006] In IGBTs, it is desirable to simultaneously reduce on-resistance and switching losses. To achieve this, an IGBT with multiple gates driven independently has been proposed. This technique shortens the switching time of the IGBT and reduces switching losses by changing the driving timing of the multiple gates. Summary of the Invention

[0007] Embodiments of the present invention provide a semiconductor device capable of driving multiple gates.

[0008] A semiconductor device according to an embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including a plurality of first trenches and a plurality of second trenches, the plurality of first trenches being disposed on the first surface side and extending in the first direction parallel to the first surface, the plurality of second trenches being disposed on the first surface side and extending in the first direction, and at least one second trench being disposed between the first trenches; a first electrode being disposed on the first surface side of the semiconductor layer; a second electrode being disposed on the second surface side of the semiconductor layer; a first gate electrode being disposed in the first trench; a second gate electrode being disposed in the second trench; and a first gate wiring being disposed on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction. The first gate wiring includes a second portion extending in the first direction and a third portion extending in the second direction; a second gate wiring disposed on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, comprising a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; a first gate electrode pad disposed on the first surface side of the semiconductor layer and electrically connected to the first gate wiring; and a second gate electrode pad disposed on the first surface side of the semiconductor layer and electrically connected to the second gate wiring; a first portion of the second gate wiring is provided between the first portion and the third portion of the first gate wiring; and a third portion of the first gate wiring is provided between the first portion and the third portion of the second gate wiring. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a schematic top view of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0014] Figure 6 This is a schematic diagram of the semiconductor device according to the second embodiment.

[0015] Figure 7This is a schematic diagram of a modified example of the semiconductor device according to the second embodiment.

[0016] Figure 8 This is a schematic diagram of the semiconductor device according to the third embodiment.

[0017] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0018] Figure 10 This is a schematic diagram of the semiconductor device according to the fourth embodiment.

[0019] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0020] Figure 12 This is a schematic diagram of the semiconductor device according to the fifth embodiment.

[0021] Figure 13 This is a schematic diagram of a first modification of the semiconductor device according to the fifth embodiment.

[0022] Figure 14 This is a schematic diagram of a second modification of the semiconductor device according to the fifth embodiment.

[0023] Figure 15 This is a schematic diagram of the semiconductor device according to the sixth embodiment.

[0024] Figure 16 This is a schematic diagram of the semiconductor device according to the seventh embodiment. Detailed Implementation

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be given the same reference numerals, and descriptions of components that have been described once will be appropriately omitted.

[0026] In this specification, when there is n + Type, n-type, n － In the case of type marking, it means that the concentration of n-type impurities is determined by n. + Type, n-type, n － The order of the type decreases. Furthermore, in the presence of p... + Type, p type, p － In the case of p-type marking, it means that the concentration of p-type impurities is according to p + Type, p type, p － The order of the types decreases.

[0027] (First Embodiment)

[0028] The semiconductor device according to the first embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface, including a plurality of first trenches and a plurality of second trenches, the plurality of first trenches being disposed on the first surface side and extending in the first direction parallel to the first surface, the plurality of second trenches being disposed on the first surface side and extending in the first direction, and at least one second trench being disposed between the first trenches; a first electrode being disposed on the first surface side of the semiconductor layer; a second electrode being disposed on the second surface side of the semiconductor layer; a first gate electrode being disposed in a first trench; a second gate electrode being disposed in a second trench; and a first gate wiring being disposed on the first surface side of the semiconductor layer and... The first gate electrode electrical connection includes a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, a second portion extending in the first direction, and a third portion extending in the second direction; the second gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, including a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; the first gate electrode pad is disposed on the first surface side of the semiconductor layer and electrically connected to the first gate wiring; and the second gate electrode pad is disposed on the first surface side of the semiconductor layer and electrically connected to the second gate wiring. Furthermore, the first portion of the second gate wiring is provided between the first portion and the third portion of the first gate wiring; and the third portion of the first gate wiring is provided between the first portion and the third portion of the second gate wiring.

[0029] The semiconductor device of the first embodiment is a trench-gate IGBT 100 with a gate electrode formed in a trench of a semiconductor layer. The IGBT 100 is an IGBT with two gates that can be controlled independently and capable of dual-gate driving.

[0030] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment. Figure 1 This indicates the configuration and connection relationship of the first trench, the second trench, the first gate wiring, the second gate wiring, the first contact, the second contact, the emitter electrode, the first gate electrode pad, and the second gate electrode pad.

[0031] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 It is the cross-section including the emitter electrode.

[0032] Figure 3 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 3 This is the top view in page 1 (P1). Figure 2 yes Figure 3 AA' section.

[0033] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 It is a cross-section including the first gate wiring and the first contact portion.

[0034] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 5 It is a cross-section including the second gate wiring and the second contact portion.

[0035] The IGBT 100 of the first embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a first contact portion 16, a second contact portion 17, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, an interlayer insulating layer 36, a first gate electrode pad 101, and a second gate electrode pad 102.

[0036] The semiconductor layer 10 includes a first gate trench 41 (first trench), a second gate trench 42 (second trench), a collector region 51, a drift region 52, a base region 53, an emitter region 54, and a contact region 55.

[0037] Emitter electrode 21 is an example of the first electrode. Collector electrode 22 is an example of the second electrode. First gate trench 41 is an example of the first trench. Second gate trench 42 is an example of the second trench.

[0038] Semiconductor layer 10 has a first surface P1 and a second surface P2 opposite to the first surface P1. Semiconductor layer 10 is, for example, monocrystalline silicon.

[0039] In this specification, the direction parallel to the first surface P1 is referred to as the first direction. Furthermore, the direction parallel to the first surface P1 and orthogonal to the first direction is referred to as the second direction. Additionally, the direction of the normal to the first surface P1 is referred to as the third direction.

[0040] An emitter electrode 21 is disposed on the first surface P1 side of the semiconductor layer 10. At least a portion of the emitter electrode 21 is in contact with the first surface P1 of the semiconductor layer 10. The emitter electrode 21 is, for example, a metal.

[0041] Emitter electrode 21 is electrically connected to emitter region 54 and contact region 55. An emitter voltage is applied to emitter electrode 21. The emitter voltage is, for example, 0V.

[0042] The collector electrode 22 is disposed on the second surface P2 side of the semiconductor layer 10. At least a portion of the collector electrode 22 is in contact with the second surface P2 of the semiconductor layer 10. The collector electrode 22 is, for example, a metal.

[0043] Collector electrode 22 is electrically connected to the p-type collector region 51. A collector voltage is applied to collector electrode 22. The collector voltage is, for example, 200V or more and 6500V or less.

[0044] Collector region 51 is a p-type semiconductor region. Collector region 51 is electrically connected to collector electrode 22. When IGBT 100 is in the on state, collector region 51 becomes a hole supply source.

[0045] Drift region 52 is n － The IGBT 100 is a semiconductor region of a certain type. A drift region 52 is disposed between the collector region 51 and the first surface P1. The drift region 52 serves as a path for the conducting current when the IGBT 100 is in the on-state. The drift region 52 also has the function of depleting itself when the IGBT 100 is in the off-state, thereby maintaining the IGBT 100's withstand voltage.

[0046] The base region 53 is a p-type semiconductor region. The base region 53 is located between the drift region 52 and the first surface P1. The base region 53 functions as the channel region of the transistor.

[0047] Emitter region 54 is n + The transistor is a semiconductor region. The emitter region 54 is disposed between the base region 53 and the first surface P1. The emitter region 54 is electrically connected to the emitter electrode 21. The emitter region 54 is connected to the emitter electrode 21. When the transistor is in the on state, the emitter region 54 becomes a source of electrons.

[0048] Contact area 55 is p + A semiconductor region of type 21. A contact region 55 is disposed between the base region 53 and the first surface P1. The contact region 55 is disposed adjacent to or spaced apart from the emitter region 54. The contact region 55 is electrically connected to the emitter electrode 21.

[0049] Multiple first gate trenches 41 are disposed on the first surface P1 side of the semiconductor layer 10. For example... Figure 3 As shown, the first gate trench 41 extends along a first direction parallel to the first surface P1. The first gate trench 41 has a stripe shape. A plurality of first gate trenches 41 are repeatedly arranged in a second direction orthogonal to the first direction. The first gate trench 41 penetrates the base region 53 and reaches the drift region 52.

[0050] Multiple second gate trenches 42 are disposed on the first surface P1 side of the semiconductor layer 10. For example... Figure 3As shown, the second gate trench 42 extends along a first direction parallel to the first surface P1. The second gate trench 42 has a stripe shape. The second gate trench 42 is repeatedly arranged in a second direction orthogonal to the first direction. The second gate trench 42 is disposed between the first gate trench 41 and the first gate trench 42. The second gate trench 42 penetrates the base region 53 and reaches the drift region 52.

[0051] The first gate electrode 31 is disposed in the first gate trench 41. The first gate electrode 31 is, for example, a semiconductor or a metal. The first gate electrode 31 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The first gate electrode 31 is electrically connected to the first gate wiring 11 and the first gate electrode pad 101.

[0052] The second gate electrode 32 is disposed in the second gate trench 42. The second gate electrode 32 is, for example, a semiconductor or a metal. The second gate electrode 32 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 32 is electrically connected to the second gate wiring 12 and the second gate electrode pad 102.

[0053] A gate insulating film 23 is disposed between the first gate electrode 31 and the semiconductor layer 10. A gate insulating film 23 is disposed between the second gate electrode 32 and the semiconductor layer 10. The gate insulating film 23 is, for example, silicon oxide.

[0054] An interlayer insulating layer 36 is disposed between the first gate electrode 31 and the emitter electrode 21. The interlayer insulating layer 36 electrically separates the first gate electrode 31 and the emitter electrode 21. An interlayer insulating layer 36 is disposed between the second gate electrode 32 and the emitter electrode 21. The interlayer insulating layer 36 electrically separates the second gate electrode 32 and the emitter electrode 21. The interlayer insulating layer 36 is, for example, silicon oxide.

[0055] The first gate wiring 11 is disposed on the first surface P1 side of the semiconductor layer 10. The first gate wiring 11 is electrically connected to the first gate electrode 31. The first gate wiring 11 is electrically connected to the first gate electrode pad 101. The first gate wiring 11 electrically connects the first gate electrode 31 and the first gate electrode pad 101.

[0056] The first gate wiring 11 includes a first portion 11a, a second portion 11b, and a third portion 11c. The first portion 11a extends in a second direction. The second portion 11b extends in a first direction. The third portion 11c extends in a second direction.

[0057] The first portion 11a of the first gate wiring 11 is connected to the first gate electrode 31 at the first contact portion 16 where the first portion 11a of the first gate wiring 11 intersects with the first gate trench 41. The first portion 11a is connected to the first gate electrode 31 via an opening formed in the interlayer insulating layer 36.

[0058] Similar to the first part 11a, the third part 11c of the first gate wiring 11 is connected to the first gate electrode 31 at the first contact portion 16 where the third part 11c of the first gate wiring 11 intersects with the first gate trench 41. The third part 11c is connected to the first gate electrode 31 via an opening formed in the interlayer insulating layer 36.

[0059] The first gate wiring 11 is, for example, a metal. For example, the material of the first gate wiring 11 is the same as the material of the emitter electrode 21. The first gate wiring 11 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0060] The second gate wiring 12 is disposed on the first surface P1 side of the semiconductor layer 10. The second gate wiring 12 is electrically connected to the second gate electrode 32. The second gate wiring 12 is electrically connected to the second gate electrode pad 102. The second gate wiring 12 electrically connects the second gate electrode 32 and the second gate electrode pad 102.

[0061] The second gate wiring 12 includes a first portion 12a, a second portion 12b, and a third portion 12c. The first portion 12a extends in a second direction. The second portion 12b extends in a first direction. The third portion 12c extends in a second direction.

[0062] The first portion 12a of the second gate wiring 12 is connected to the second gate electrode 32 at the second contact portion 17 where the first portion 12a of the second gate wiring 12 intersects with the second gate trench 42. The first portion 12a is connected to the second gate electrode 32 via an opening formed in the interlayer insulating layer 36.

[0063] Similar to the first part 12a, the third part 12c of the second gate wiring 12 is connected to the second gate electrode 32 at the second contact portion 17 where the third part 12c of the second gate wiring 12 intersects with the second gate trench 42. The third part 12c is connected to the second gate electrode 32 via an opening formed in the interlayer insulating layer 36.

[0064] The second gate wiring 12 is, for example, a metal. For example, the material of the second gate wiring 12 is the same as the material of the emitter electrode 21. The second gate wiring 12 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0065] A first portion 12a of a second gate wiring 12 is provided between a first portion 11a of a first gate wiring 11 and a third portion 11c of a first gate wiring 11. Furthermore, a third portion 11c of a first gate wiring 11 is provided between a first portion 12a of a second gate wiring 12 and a third portion 12c of a second gate wiring 12.

[0066] An emitter electrode 21 is provided between the first portion 12a of the second gate wiring 12 and the third portion 11c of the first gate wiring 11. Furthermore, an emitter electrode 21 is provided between the second portion 11b of the first gate wiring 11 and the second portion 12b of the second gate wiring 12.

[0067] The first gate electrode pad 101 is disposed on the first surface P1 side of the semiconductor layer 10. The first gate electrode pad 101 is connected to the first gate wiring 11. The first gate electrode pad 101 is electrically connected to the first gate electrode 31 via the first gate wiring 11.

[0068] A first gate voltage (Vg1) is applied to the first gate electrode pad 101. A first gate voltage (Vg1) is applied to the first gate wiring 11 and the first gate electrode 31.

[0069] The first gate electrode pad 101 is, for example, metal. For example, the material of the first gate electrode pad 101 is the same as the material of the emitter electrode 21. The first gate electrode pad 101 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0070] The second gate electrode pad 102 is disposed on the first surface P1 side of the semiconductor layer 10. The second gate electrode pad 102 is connected to the second gate wiring 12. The second gate electrode pad 102 is electrically connected to the second gate electrode 32 via the second gate wiring 12.

[0071] A second gate voltage (Vg2) is applied to the second gate electrode pad 102. A second gate voltage (Vg2) is applied to the second gate wiring 12 and the second gate electrode 32.

[0072] The second gate electrode pad 102 is, for example, metal. For example, the material of the second gate electrode pad 102 is the same as the material of the emitter electrode 21. The second gate electrode pad 102 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0073] Next, the function and effects of the IGBT100 in the first embodiment will be explained.

[0074] The IGBT 100 of the first embodiment includes a first gate electrode 31 to which a first gate voltage (Vg1) is applied and a second gate electrode 32 to which a second gate voltage (Vg2) is applied. The IGBT 100 of the first embodiment includes a first transistor controlled by the first gate electrode 31 and a second transistor controlled by the second gate electrode 32. For example, Figure 2 The region enclosed by the dashed line T1 corresponds to the first transistor. Furthermore, for example, Figure 2 The area enclosed by the dashed line T2 corresponds to the second transistor. Dual-gate drive can be achieved by providing independent gate signals to the first and second transistors. The IGBT100 achieves both reduced on-resistance and reduced switching losses through dual-gate drive.

[0075] To enable dual-gate driving, two gate electrode pads are required to apply two different gate voltages. Furthermore, two gate wirings are needed to connect from each gate electrode pad to the gate electrode. For example, if a layout with the two gate wirings crossing each other is used, new insulating layers are needed to insulate the two gate wirings vertically, as well as wiring layers for forming the additional gate wirings. Adding new insulating and wiring layers increases the manufacturing cost of the IGBT.

[0076] The IGBT 100 of the first embodiment adopts a layout in which the first gate wiring 11 and the second gate wiring 12 do not intersect. The first gate wiring 11 is connected to the first gate electrode 31 and the first gate electrode pad 101 without intersecting the second gate wiring 12. In addition, the second gate wiring 12 is connected to the second gate electrode pad 102 without intersecting the first gate wiring 11.

[0077] Furthermore, the first gate wiring 11 and the emitter electrode 21 are separated in the same plane. Additionally, the second gate wiring 12 and the emitter electrode 21 are separated in the same plane. Therefore, the first gate wiring 11, the second gate wiring 12, the first gate electrode pad 101, the second gate electrode pad 102, and the emitter electrode 21 can be formed by patterning the same metal layer. Thus, dual-gate driving can be achieved without increasing the manufacturing cost of the IGBT 100.

[0078] Furthermore, in the IGBT 100 of the first embodiment, a second gate wiring 12 is provided between the first gate wiring 11 sandwiched between the emitter electrode 21. By adopting this arrangement, the difference between the distance between the two first contact portions 16 sandwiched between the emitter electrode 21 and the distance between the two second contact portions 17 sandwiched between the emitter electrode 21 can be reduced. For example, it is also possible to make the distance between the two first contact portions 16 sandwiched between the emitter electrode 21 and the distance between the two second contact portions 17 sandwiched between the emitter electrode 21 the same.

[0079] Therefore, the delay time of the gate signal generated by the resistance of the gate electrode can be made to be the same between the first transistor driven by the first gate electrode 31 and the second transistor driven by the second gate electrode 32. For example, the difference between the delay time of the gate signal of the first transistor from the first contact 16 to the farthest position and the delay time of the gate signal of the second transistor from the second contact 17 to the farthest position can be minimized. Therefore, the deviation of the operation of the first transistor and the operation of the second transistor from the desired operation timing can be minimized. In addition, the difference between the distance from the first contact 16 to the farthest position of the first transistor and the distance from the second contact 17 to the farthest position of the second transistor is reduced, thereby eliminating, for example, uneven operation caused by current concentration. Therefore, according to the IGBT 100, stable dual-gate drive can be realized.

[0080] According to the first embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0081] (Second Implementation)

[0082] In the semiconductor device of the second embodiment, the first gate wiring further includes a fourth portion extending in the first direction and a fifth portion extending in the second direction, and the second gate wiring further includes a fourth portion extending in the first direction and a fifth portion extending in the second direction. A third portion of the second gate wiring is provided between the third portion and the fifth portion of the first gate wiring, and a fifth portion of the first gate wiring is provided between the third portion and the fifth portion of the second gate wiring. These aspects differ from the semiconductor device of the first embodiment. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0083] The semiconductor device of the second embodiment is a trench-gate IGBT 200 with a gate electrode formed in a trench of a semiconductor layer. The IGBT 200 is an IGBT that can be driven in a dual-gate configuration by having two independently controllable gates.

[0084] Figure 6 This is a schematic diagram of the semiconductor device according to the second embodiment. Figure 6 This indicates the configuration and connection relationship of the first trench, the second trench, the first gate wiring, the second gate wiring, the first contact, the second contact, the emitter electrode, the first gate electrode pad, and the second gate electrode pad.

[0085] The emitter electrode 21 has a first region 21a and a second region 21b. The first region 21a and the second region 21b are spaced apart in a first direction. The IGBT 200 has two transistor blocks: a transistor block including the first region 21a and a transistor block including the second region 21b.

[0086] The first gate wiring 11 includes a first portion 11a, a second portion 11b, a third portion 11c, a fourth portion 11d, and a fifth portion 11e. The first portion 11a extends in a second direction. The second portion 11b extends in a first direction. The third portion 11c extends in a second direction. The fourth portion 11d extends in a first direction. The fifth portion 11e extends in a second direction.

[0087] The fifth portion 11e of the first gate wiring 11 is connected to the first gate electrode 31 at the first contact portion 16 where the fifth portion 11e of the first gate wiring 11 intersects with the first gate trench 41. The fifth portion 11e is connected to the first gate electrode 31 through an opening formed in the interlayer insulating layer 36.

[0088] The second gate wiring 12 includes a first portion 12a, a second portion 12b, a third portion 12c, a fourth portion 12d, and a fifth portion 12e. The first portion 12a extends in a second direction. The second portion 12b extends in a first direction. The third portion 12c extends in a second direction. The fourth portion 12d extends in a first direction. The fifth portion 12e extends in a second direction.

[0089] The fifth portion 12e of the second gate wiring 12 is connected to the second gate electrode 32 at the second contact portion 17 where the fifth portion 12e of the second gate wiring 12 intersects with the second gate trench 42. The fifth portion 12e is connected to the second gate electrode 32 through an opening formed in the interlayer insulating layer 36.

[0090] A third portion 12c of a second gate wiring 12 is provided between a third portion 11c of a first gate wiring 11 and a fifth portion 11e of a first gate wiring 11. Furthermore, a fifth portion 11e of a first gate wiring 11 is provided between a third portion 12c of a second gate wiring 12 and a fifth portion 12e of a second gate wiring 12.

[0091] A first region 21a of the emitter electrode 21 is provided between the first portion 12a of the second gate wiring 12 and the third portion 11c of the first gate wiring 11. Furthermore, a first region 21a of the emitter electrode 21 is provided between the second portion 11b of the first gate wiring 11 and the second portion 12b of the second gate wiring 12.

[0092] A second region 21b of the emitter electrode 21 is provided between the third portion 12c of the second gate wiring 12 and the fifth portion 11e of the first gate wiring 11. Furthermore, a second region 21b of the emitter electrode 21 is provided between the fourth portion 11d of the first gate wiring 11 and the fourth portion 12d of the second gate wiring 12.

[0093] The IGBT 200 of the second embodiment includes two transistor blocks, and a contact portion connecting the gate wiring to the gate electrode is also provided between the two transistor blocks. Since the IGBT 200 has a contact connection portion between the two transistor blocks, no additional insulating layer or wiring layer is required.

[0094] Like the IGBT 100 in the first embodiment, the IGBT 200 in the second embodiment can form the first gate wiring 11, the second gate wiring 12, the first gate electrode pad 101, the second gate electrode pad 102, and the emitter electrode 21 by patterning the same metal layer. Therefore, dual-gate driving can be achieved without increasing the manufacturing cost of the IGBT 200.

[0095] Furthermore, like the IGBT 100 of the first embodiment, the IGBT 200 of the second embodiment can minimize the deviation of the operation of the first transistor and the operation of the second transistor from the desired operating timing. Also, similar to the IGBT 100 of the first embodiment, the difference between the distance from the first contact 16 to the farthest first transistor and the distance from the second contact 17 to the farthest second transistor is reduced, thereby eliminating, for example, uneven operation caused by current concentration. Therefore, stable dual-gate drive can be achieved.

[0096] Figure 7 This is a schematic diagram of a modified example of the semiconductor device according to the second embodiment. The modified IGBT 201 differs from the IGBT 200 of the second embodiment in that the third portion 12c of the first gate wiring 11 is located between the third portion 12c of the second gate wiring 12 and the fifth portion 11e of the first gate wiring 11. In the modified IGBT 201, the vertical relationship between the third portion 11c of the first gate wiring 11 and the third portion 12c of the second gate wiring 12 is reversed compared to that of the IGBT 200.

[0097] Based on the second embodiment and its variations, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0098] (Third Implementation)

[0099] In the semiconductor device of the third embodiment, the semiconductor layer further includes a plurality of third trenches disposed on the first surface side and extending in the first direction; the semiconductor device further includes: a third gate electrode disposed in the third trench; a third gate wiring including a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction, and electrically connected to the third gate electrode; and a third gate electrode pad disposed on the first surface side of the semiconductor layer and electrically connected to the third gate wiring; a first portion of the first gate wiring is provided between the first portion of the third gate wiring and the first portion of the second gate wiring; a third portion of the third gate wiring is provided between the third portion of the first gate wiring and the third portion of the second gate wiring, which differs from the semiconductor device of the first embodiment. Hereinafter, some descriptions that are repeated in the first embodiment are omitted.

[0100] The semiconductor device of the third embodiment is a trench-gate IGBT 300 with gate electrodes formed in a trench in a semiconductor layer. The IGBT 300 is an IGBT that can be driven by three gates that can be controlled independently.

[0101] Figure 8 This is a schematic diagram of the semiconductor device according to the third embodiment. Figure 8 This indicates the configuration and connection relationship of the first trench, the second trench, the third trench, the first gate wiring, the second gate wiring, the third gate wiring, the first contact, the second contact, the third contact, the emitter electrode, the first gate electrode pad, the second gate electrode pad, and the third gate electrode pad.

[0102] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 9 It is the cross-section including the emitter electrode.

[0103] The IGBT 300 of the third embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first contact portion 16, a second contact portion 17, a third contact portion 18, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, an interlayer insulating layer 36, a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103.

[0104] The semiconductor layer 10 includes a first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a collector region 51, a drift region 52, a base region 53, an emitter region 54, and a contact region 55.

[0105] Emitter electrode 21 is an example of the first electrode. Collector electrode 22 is an example of the second electrode. First gate trench 41 is an example of the first trench. Second gate trench 42 is an example of the second trench. Third gate trench 43 is an example of the third trench.

[0106] Multiple third gate trenches 43 are disposed on the first surface P1 side of the semiconductor layer 10. The third gate trenches 43 extend along a first direction parallel to the first surface P1. The third gate trenches 43 have a stripe shape. The third gate trenches 43 are repeatedly arranged in a second direction orthogonal to the first direction. The third gate trenches 43 are disposed between the second gate trench 42 and the first gate trench 41. The third gate trenches 43 penetrate the base region 53 and reach the drift region 52.

[0107] The third gate electrode 33 is disposed in the third gate trench 43. The third gate electrode 33 is, for example, a semiconductor or a metal. The third gate electrode 33 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The third gate electrode 33 is electrically connected to the third gate wiring 13 and the third gate electrode pad 103.

[0108] The third gate wiring 13 is disposed on the first surface P1 side of the semiconductor layer 10. The third gate wiring 13 is electrically connected to the third gate electrode 33. The third gate wiring 13 is electrically connected to the third gate electrode pad 103. The third gate wiring 13 electrically connects the third gate electrode 33 and the third gate electrode pad 103.

[0109] The third gate wiring 13 includes a first portion 13a, a second portion 13b, and a third portion 13c. The first portion 13a extends in a second direction. The second portion 13b extends in a first direction. The third portion 13c extends in a second direction.

[0110] The first portion 13a of the third gate wiring 13 is connected to the third gate electrode 33 at the third contact portion 18 where the first portion 13a of the third gate wiring 13 intersects with the third gate trench 43. The first portion 13a is connected to the third gate electrode 33 through an opening formed in the interlayer insulating layer 36.

[0111] Similar to the first part 13a, the third part 13c of the third gate wiring 13 is connected to the third gate electrode 33 at the third contact portion 18 where the third part 13c of the third gate wiring 13 intersects with the third gate trench 43. The third part 13c is connected to the third gate electrode 33 via an opening formed in the interlayer insulating layer 36.

[0112] The third gate wiring 13 is, for example, a metal. For example, the material of the third gate wiring 13 is the same as the material of the emitter electrode 21. The third gate wiring 13 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0113] A first portion 11a of a first gate wiring 11 is provided between a first portion 13a of a third gate wiring 13 and a first portion 12a of a second gate wiring 12. A third portion 13c of a third gate wiring 13 is provided between a third portion 11c of a first gate wiring 11 and a third portion 12c of a second gate wiring 12.

[0114] An emitter electrode 21 is provided between the first portion 13a and the third portion 13c of the third gate wiring 13. Furthermore, an emitter electrode 21 is provided between the second portion 13b of the third gate wiring 13 and the second portion 12b of the second gate wiring 12.

[0115] The third gate electrode pad 103 is disposed on the first surface P1 side of the semiconductor layer 10. The third gate electrode pad 103 is connected to the third gate wiring 13. The third gate electrode pad 103 is electrically connected to the third gate electrode 33 via the third gate wiring 13.

[0116] A third gate voltage (Vg3) is applied to the third gate electrode pad 103. A third gate voltage (Vg3) is applied to the third gate wiring 13 and the third gate electrode 33.

[0117] The third gate electrode pad 103 is, for example, metal. For example, the material of the third gate electrode pad 103 is the same as the material of the emitter electrode 21. The third gate electrode pad 103 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0118] The IGBT 300 of the third embodiment includes a first gate electrode 31 to which a first gate voltage (Vg1) is applied, a second gate electrode 32 to which a second gate voltage (Vg2) is applied, and a third gate electrode 33 to which a third gate voltage (Vg3) is applied. The IGBT 300 of the third embodiment includes a first transistor controlled by the first gate electrode 31, a second transistor controlled by the second gate electrode 32, and a third transistor controlled by the third gate electrode 33. For example, Figure 9 The region enclosed by the dashed line T1 corresponds to the first transistor. Furthermore, for example, Figure 9 The region enclosed by the dashed line T2 corresponds to the second transistor. Furthermore, for example, Figure 9The area enclosed by the dashed line T3 corresponds to the third transistor. By providing independent gate signals to the first, second, and third transistors, a three-gate drive can be achieved. Through this three-gate drive, the IGBT300 can simultaneously reduce on-resistance and switching losses.

[0119] To perform a tri-gate drive, three gate electrode pads are required to apply three different gate voltages. Additionally, three gate wirings are needed to connect the respective gate electrode pads to the gate electrode.

[0120] The IGBT 300 of the third embodiment employs a layout in which the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 do not intersect. Furthermore, the first gate wiring 11, the second gate wiring 12, and the third gate wiring are separated from the emitter electrode 21 in the same plane. Therefore, the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, the first gate electrode pad 101, the second gate electrode pad 102, the third gate electrode pad 103, and the emitter electrode 21 can be formed by patterning the same metal layer. Therefore, a three-gate drive can be achieved without increasing the manufacturing cost of the IGBT 300.

[0121] Furthermore, for the same reasons as with the IGBT 100 in the first embodiment, deviations from the desired timing of the operation of the first transistor, the second transistor, and the third transistor can be minimized. Moreover, by reducing the differences in the distances from the first contact 16 to the farthest first transistor, from the second contact 17 to the farthest second transistor, and from the third contact 18 to the farthest third transistor, uneven operation caused by factors such as current concentration can be eliminated. Therefore, stable tri-gate drive can be achieved.

[0122] According to the third embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0123] (Fourth implementation)

[0124] In the semiconductor device of the fourth embodiment, the semiconductor layer further includes a plurality of fourth trenches disposed on the first surface side and extending in the first direction; the semiconductor device further includes: a fourth gate electrode disposed in the fourth trench; a fourth gate wiring including a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction, electrically connected to the fourth gate electrode; and a fourth gate electrode pad disposed on the first surface side of the semiconductor layer and electrically connected to the fourth gate wiring; a first portion of the fourth gate wiring is provided between a first portion of the first gate wiring and a first portion of the second gate wiring; a third portion of the second gate wiring is provided between a third portion of the third gate wiring and a third portion of the fourth gate wiring, which differs from the semiconductor device of the third embodiment in these aspects. Hereinafter, some descriptions that are repeated in the first or third embodiments are omitted.

[0125] The semiconductor device of the fourth embodiment is a trench-gate IGBT 400 with gate electrodes formed in the trenches of the semiconductor layer. The IGBT 400 is an IGBT that can be driven by four gates that can be controlled independently.

[0126] Figure 10 This is a schematic diagram of the semiconductor device according to the fourth embodiment. Figure 10 This indicates the configuration and connection relationship of the first trench, the second trench, the third trench, the fourth trench, the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the first contact, the second contact, the third contact, the fourth contact, the emitter electrode, the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0127] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 11 It is the cross-section containing the emitter electrode.

[0128] The IGBT 400 of the fourth embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a fourth gate wiring 14, a first contact portion 16, a second contact portion 17, a third contact portion 18, a fourth contact portion 19, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a fourth gate electrode 34, an interlayer insulating layer 36, a first gate electrode pad 101, a second gate electrode pad 102, a third gate electrode pad 103, and a fourth gate electrode pad 104.

[0129] The semiconductor layer 10 includes a first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a fourth gate trench 44 (fourth trench), a collector region 51, a drift region 52, a base region 53, an emitter region 54, and a contact region 55.

[0130] Emitter electrode 21 is an example of the first electrode. Collector electrode 22 is an example of the second electrode. First gate trench 41 is an example of the first trench. Second gate trench 42 is an example of the second trench. Third gate trench 43 is an example of the third trench. Fourth gate trench 44 is an example of the fourth trench.

[0131] Multiple fourth gate trenches 44 are disposed on the first surface P1 side of the semiconductor layer 10. The fourth gate trenches 44 extend along a first direction parallel to the first surface P1. The fourth gate trenches 44 have a stripe shape. The fourth gate trenches 44 are repeatedly arranged in a second direction orthogonal to the first direction. The fourth gate trenches 44 are disposed between the third gate trench 43 and the first gate trench 41. The fourth gate trenches 44 penetrate the base region 53 and reach the drift region 52.

[0132] The fourth gate electrode 34 is disposed in the fourth gate trench 44. The fourth gate electrode 34 is, for example, a semiconductor or a metal. The fourth gate electrode 34 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The fourth gate electrode 34 is electrically connected to the fourth gate wiring 14 and the fourth gate electrode pad 104.

[0133] The fourth gate wiring 14 is disposed on the first surface P1 side of the semiconductor layer 10. The fourth gate wiring 14 is electrically connected to the fourth gate electrode 34. The fourth gate wiring 14 is electrically connected to the fourth gate electrode pad 104. The fourth gate wiring 14 electrically connects the fourth gate electrode 34 and the fourth gate electrode pad 104.

[0134] The fourth gate wiring 14 includes a first portion 14a, a second portion 14b, and a third portion 14c. The first portion 14a extends in a second direction. The second portion 14b extends in a first direction. The third portion 14c extends in a second direction.

[0135] The first portion 14a of the fourth gate wiring 14 is connected to the fourth gate electrode 34 at the fourth contact portion 19 where the first portion 14a of the fourth gate wiring 14 intersects with the fourth gate trench 44. The first portion 14a is connected to the fourth gate electrode 34 via an opening formed in the interlayer insulating layer 36.

[0136] Similar to part 14a, part 14c of the fourth gate wiring 14 is connected to the fourth gate electrode 34 at the fourth contact portion 19 where it intersects with the fourth gate trench 44. Part 14c is connected to the fourth gate electrode 34 via an opening formed in the interlayer insulating layer 36.

[0137] The fourth gate wiring 14 is, for example, a metal. For example, the material of the fourth gate wiring 14 is the same as the material of the emitter electrode 21. The fourth gate wiring 14 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0138] A first portion 14a of a fourth gate wiring 14 is provided between a first portion 11a of a first gate wiring 11 and a first portion 12a of a second gate wiring 12. A third portion 12c of a second gate wiring 12 is provided between a third portion 13c of a third gate wiring 13 and a third portion 14c of a fourth gate wiring 14.

[0139] An emitter electrode 21 is provided between the first portion 14a and the third portion 14c of the fourth gate wiring 14. Furthermore, an emitter electrode 21 is provided between the second portion 14b of the fourth gate wiring 14 and the second portion 11b of the first gate wiring 11.

[0140] The fourth gate electrode pad 104 is disposed on the first surface P1 side of the semiconductor layer 10. The fourth gate electrode pad 104 is connected to the fourth gate wiring 14. The fourth gate electrode pad 104 is electrically connected to the fourth gate electrode 34 via the fourth gate wiring 14.

[0141] A fourth gate voltage (Vg4) is applied to the fourth gate electrode pad 104. A fourth gate voltage (Vg4) is applied to the fourth gate wiring 14 and the fourth gate electrode 34.

[0142] The fourth gate electrode pad 104 is, for example, metal. For example, the material of the fourth gate electrode pad 104 is the same as the material of the emitter electrode 21. The fourth gate electrode pad 104 is formed, for example, by patterning the same metal layer as the emitter electrode 21.

[0143] The IGBT 400 of the fourth embodiment includes a first gate electrode 31 to which a first gate voltage (Vg1) is applied, a second gate electrode 32 to which a second gate voltage (Vg2) is applied, a third gate electrode 33 to which a third gate voltage (Vg3) is applied, and a fourth gate electrode 34 to which a fourth gate voltage (Vg4) is applied. The IGBT 400 of the fourth embodiment includes a first transistor controlled by the first gate electrode 31, a second transistor controlled by the second gate electrode 32, a third transistor controlled by the third gate electrode 33, and a fourth transistor controlled by the fourth gate electrode 34. For example, Figure 11 The region enclosed by the dashed line T1 corresponds to the first transistor. Furthermore, for example, Figure 11 The region enclosed by the dashed line T2 corresponds to the second transistor. Furthermore, for example, Figure 11 The region enclosed by the dashed line T3 corresponds to the third transistor. Furthermore, for example, Figure 11 The area enclosed by the dashed line T4 corresponds to the third transistor. By providing independent gate signals to the first, second, third, and fourth transistors, a four-gate drive can be achieved. Through this four-gate drive, the IGBT400 can simultaneously reduce on-resistance and switching losses.

[0144] To perform a quad-gate drive, four gate electrode pads are required to apply four different gate voltages. Additionally, four gate traces are needed to connect the individual gate electrode pads to the gate electrodes.

[0145] The IGBT 400 of the fourth embodiment employs a layout in which the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, and the fourth gate wiring 14 do not intersect. Furthermore, the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, and the fourth gate wiring 14 are separated from the emitter electrode 21 in the same plane. Therefore, the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, the fourth gate wiring 14, the first gate electrode pad 101, the second gate electrode pad 102, the third gate electrode pad 103, the fourth gate electrode pad 104, and the emitter electrode 21 can be formed by patterning the same metal layer. Therefore, four-gate driving can be achieved without increasing the manufacturing cost of the IGBT 400.

[0146] Furthermore, for the same reasons as with the IGBT 100 in the first embodiment, deviations from the desired timing of the operation of the first transistor, the second transistor, the third transistor, and the fourth transistor can be minimized. Moreover, by reducing the differences in the distances from the first contact 16 to the farthest first transistor, from the second contact 17 to the farthest second transistor, from the third contact 18 to the farthest third transistor, and from the fourth contact 19 to the farthest fourth transistor, uneven operation caused by factors such as current concentration can be eliminated. Therefore, stable four-gate drive can be achieved.

[0147] According to the fourth embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0148] (Fifth Embodiment)

[0149] The semiconductor device of the fifth embodiment differs from the semiconductor device of the fourth embodiment in that the first electrode includes a first region and a second region, and that it has a transistor block including the first region and a transistor block including the second region. Furthermore, the semiconductor device of the fifth embodiment differs from the semiconductor device of the second embodiment in that it has a third gate wiring and a fourth gate wiring. Hereinafter, some descriptions that are repeated in the fifth or second embodiment will be omitted.

[0150] The semiconductor device of the fifth embodiment is a trench-gate IGBT 500 with gate electrodes formed in a trench in a semiconductor layer. The IGBT 500 is an IGBT that can be driven by four gates that can be controlled independently.

[0151] Figure 12 This is a schematic diagram of the semiconductor device according to the fifth embodiment. Figure 12 This indicates the configuration and connection relationship of the first trench, the second trench, the third trench, the fourth trench, the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the first contact, the second contact, the third contact, the fourth contact, the emitter electrode, the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0152] The emitter electrode 21 has a first region 21a and a second region 21b. The first region 21a and the second region 21b are spaced apart in a first direction. The IGBT500 has two transistor blocks: a transistor block including the first region 21a and a transistor block including the second region 21b.

[0153] The first gate wiring 11 includes a first portion 11a, a second portion 11b, a third portion 11c, a fourth portion 11d, and a fifth portion 11e. The first portion 11a extends in a second direction. The second portion 11b extends in a first direction. The third portion 11c is a folded-back shape in which two portions extending in the second direction are connected on one side by portions extending in the first direction. The fourth portion 11d extends in the first direction. The fifth portion 11e extends in the second direction.

[0154] The fifth portion 11e of the first gate wiring 11 is connected to the first gate electrode 31 at the first contact portion 16 where the fifth portion 11e of the first gate wiring 11 intersects with the first gate trench 41. The fifth portion 11e is connected to the first gate electrode 31 through an opening formed in the interlayer insulating layer 36.

[0155] The second gate wiring 12 includes a first portion 12a, a second portion 12b, a third portion 12c, a fourth portion 12d, and a fifth portion 12e. The first portion 12a extends in a second direction. The second portion 12b extends in a first direction. The third portion 12c is a folded-back shape in which two portions extending in the second direction are connected on one side by portions extending in the first direction. The fourth portion 12d extends in the first direction. The fifth portion 12e extends in the second direction.

[0156] The fifth portion 12e of the second gate wiring 12 is connected to the second gate electrode 32 at the second contact portion 17 where the fifth portion 12e of the second gate wiring 12 intersects with the second gate trench 42. The fifth portion 12e is connected to the second gate electrode 32 through an opening formed in the interlayer insulating layer 36.

[0157] The third gate wiring 13 includes a first portion 13a, a second portion 13b, a third portion 13c, a fourth portion 13d, and a fifth portion 13e. The first portion 13a extends in a second direction. The second portion 13b extends in a first direction. The third portion 13c is a folded-back shape in which two portions extending in the second direction are connected on one side by portions extending in the first direction. The fourth portion 13d extends in the first direction. The fifth portion 13e extends in the second direction.

[0158] The fifth portion 13e of the third gate wiring 13 is connected to the third gate electrode 33 at the third contact portion 18 where the fifth portion 13e of the third gate wiring 13 intersects with the third gate trench 43. The fifth portion 13e is connected to the third gate electrode 33 through an opening formed in the interlayer insulating layer 36.

[0159] The fourth gate wiring 14 includes a first portion 14a, a second portion 14b, a third portion 14c, a fourth portion 14d, and a fifth portion 14e. The first portion 14a extends in a second direction. The second portion 14b extends in a first direction. The third portion 14c is a folded-back shape in which two portions extending in the second direction are connected on one side by portions extending in the first direction. The fourth portion 14d extends in the first direction. The fifth portion 14e extends in the second direction.

[0160] The fifth portion 14e of the fourth gate wiring 14 is connected to the fourth gate electrode 34 at the fourth contact portion 19 where the fifth portion 14e of the fourth gate wiring 14 intersects with the fourth gate trench 44. The fifth portion 14e is connected to the fourth gate electrode 34 via an opening formed in the interlayer insulating layer 36.

[0161] A third portion 14c of a fourth gate wiring 14 is provided between a third portion 13c of a third gate wiring 13 and a fifth portion 13e of a third gate wiring 13. Furthermore, a fifth portion 13e of a third gate wiring 13 is provided between a third portion 14c of a fourth gate wiring 14 and a fifth portion 14e of a fourth gate wiring 14.

[0162] A first region 21a of the emitter electrode 21 is provided between the first portion 14a of the fourth gate wiring 14 and the third portion 13c of the third gate wiring 13. Furthermore, a first region 21a of the emitter electrode 21 is provided between the second portion 13b of the third gate wiring 13 and the second portion 14b of the fourth gate wiring 14.

[0163] A second region 21b of the emitter electrode 21 is provided between the third portion 14c of the fourth gate wiring 14 and the fifth portion 13e of the third gate wiring 13. Furthermore, a second region 21b of the emitter electrode 21 is provided between the fourth portion 13d of the third gate wiring 13 and the fourth portion 14d of the fourth gate wiring 14.

[0164] The IGBT 500 of the fifth embodiment includes two transistor blocks, and a contact portion connecting the gate wiring to the gate electrode is also provided between the two transistor blocks. Since the IGBT 500 has a contact connection portion between the two transistor blocks, no additional insulating layer or wiring layer is required.

[0165] Like the IGBT 400 in the fourth embodiment, the IGBT 500 in the fifth embodiment can form the first gate wiring 11, the second gate wiring 12, the first gate electrode pad 101, the second gate electrode pad 102, and the emitter electrode 21 by patterning the same metal layer. Therefore, dual-gate driving can be achieved without increasing the manufacturing cost of the IGBT 500.

[0166] Furthermore, similar to the IGBT 400 in the fourth embodiment, deviations from the desired operating timing of the first transistor, the second transistor, the third transistor, and the fourth transistor can be minimized. Moreover, by reducing the differences in the distances from the first contact 16 to the farthest first transistor, from the second contact 17 to the farthest second transistor, from the third contact 18 to the farthest third transistor, and from the fourth contact 19 to the farthest fourth transistor, uneven operation caused by factors such as current concentration can be eliminated. Therefore, stable four-gate drive can be achieved.

[0167] Figure 13 This is a schematic diagram of a first modification of the semiconductor device according to the fifth embodiment. The semiconductor device of the first modification is an IGBT 501. The difference between IGBT 501 and IGBT 500 of the fifth embodiment lies in the arrangement of the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0168] Figure 14 This is a schematic diagram of a second modification of the semiconductor device according to the fifth embodiment. The semiconductor device in the second modification is an IGBT 502. The IGBT 502 differs from the IGBT 500 of the fifth embodiment in the arrangement of the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0169] As in the IGBT501 of the first modification or the IGBT502 of the second modification, the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad can be configured at any location required from the viewpoint of wire bonding.

[0170] According to the fifth embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0171] (Sixth Embodiment)

[0172] The semiconductor device of the sixth embodiment differs from that of the semiconductor device of the fifth embodiment in that the shapes of the third gate wiring and the fourth gate wiring disposed between the first region and the second region of the first electrode are different. Hereinafter, some descriptions that are repeated in the fifth embodiment will be omitted.

[0173] The semiconductor device of the sixth embodiment is a trench-gate IGBT 600 with gate electrodes formed in a trench in a semiconductor layer. The IGBT 600 is an IGBT that can be driven by four gates that can be controlled independently.

[0174] Figure 15 This is a schematic diagram of the semiconductor device according to the sixth embodiment. Figure 15 This indicates the configuration and connection relationship of the first trench, the second trench, the third trench, the fourth trench, the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the first contact, the second contact, the third contact, the fourth contact, the emitter electrode, the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0175] In IGBT 600, a third portion 13c of a third gate wiring 13 and a third portion 14c of a fourth gate wiring 14 are provided between the first region 21a and the second region 21b of the emitter electrode 21. The shape of the third portion 13c of the third gate wiring 13 is not a folded-back shape as in IGBT 500 of the fifth embodiment, but a single line. Furthermore, the shape of the third portion 14c of the fourth gate wiring 14 is also a single line.

[0176] In other words, in the IGBT600, the shape of the third portion 13c of the third gate wiring 13 between the two transistor blocks and the shape of the third portion 14c of the fourth gate wiring 14 become a single line.

[0177] In IGBT600, by making the shape of the third portion 13c of the third gate wiring 13 and the shape of the third portion 14c of the fourth gate wiring 14 a single line, the distance between the two transistor blocks can be shortened. In IGBT600, the distance between the first region 21a and the second region 21b of the emitter electrode 21 can be shortened.

[0178] Therefore, for example, compared to the IGBT500 in the fifth embodiment, the chip size can be reduced.

[0179] According to the sixth embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0180] (Seventh Embodiment)

[0181] The semiconductor device of the seventh embodiment differs from the semiconductor device of the sixth embodiment in that the first electrode has a third region and the length of the first region of the first electrode in the first direction is shorter. Hereinafter, some descriptions that are repeated in the sixth embodiment will be omitted.

[0182] The semiconductor device of the seventh embodiment is a trench-gate IGBT 700 with gate electrodes formed in the trenches of the semiconductor layer. The IGBT 700 is an IGBT that can be driven by four gates that can be controlled independently.

[0183] Figure 16 This is a schematic diagram of the semiconductor device according to the seventh embodiment. Figure 16 This indicates the configuration and connection relationship of the first trench, the second trench, the third trench, the fourth trench, the first gate wiring, the second gate wiring, the third gate wiring, the fourth gate wiring, the first contact, the second contact, the third contact, the fourth contact, the emitter electrode, the first gate electrode pad, the second gate electrode pad, the third gate electrode pad, and the fourth gate electrode pad.

[0184] The emitter electrode 21 has a first region 21a, a second region 21b, and a third region 21c. The first region 21a and the second region 21b are spaced apart in a first direction. The second region 21b and the third region 21c are also spaced apart in the first direction. The IGBT 700 has three transistor blocks: a transistor block including the first region 21a, a transistor block including the second region 21b, and a transistor block including the third region 21c.

[0185] The first gate wiring 11 includes a first portion 11a, a second portion 11b, a third portion 11c, a fourth portion 11d, a fifth portion 11e, a sixth portion 11f, and a seventh portion 11g. The first portion 11a extends in a second direction. The second portion 11b extends in a first direction. The third portion 11c extends in a second direction. The fourth portion 11d extends in a first direction. The fifth portion 11e extends in a second direction. The sixth portion 11f extends in a first direction. The seventh portion 11g extends in a second direction.

[0186] The second gate wiring 12 includes a first portion 12a, a second portion 12b, a third portion 12c, a fourth portion 12d, a fifth portion 12e, a sixth portion 12f, and a seventh portion 12g. The first portion 12a extends in a second direction. The second portion 12b extends in a first direction. The third portion 12c extends in a second direction. The fourth portion 12d extends in a first direction. The fifth portion 12e extends in a second direction. The sixth portion 12f extends in a first direction. The seventh portion 12g extends in a second direction.

[0187] The third gate wiring 13 includes a first portion 13a, a second portion 13b, a third portion 13c, a fourth portion 13d, a fifth portion 13e, a sixth portion 13f, and a seventh portion 13g. The first portion 13a extends in a second direction. The second portion 13b extends in a first direction. The third portion 13c extends in a second direction. The fourth portion 13d extends in a first direction. The fifth portion 13e extends in a second direction. The sixth portion 13f extends in a first direction. The seventh portion 13g extends in a second direction.

[0188] The fourth gate wiring 14 includes a first portion 14a, a second portion 14b, a third portion 14c, a fourth portion 14d, a fifth portion 14e, a sixth portion 14f, and a seventh portion 14g. The first portion 14a extends in a second direction. The second portion 14b extends in a first direction. The third portion 14c extends in a second direction. The fourth portion 14d extends in a first direction. The fifth portion 14e extends in a second direction. The sixth portion 14f extends in a first direction. The seventh portion 14g extends in a second direction.

[0189] According to the IGBT 700 of the seventh embodiment, for example compared to the IGBT 600 of the sixth embodiment, by increasing the number of transistor blocks, an IGBT with a larger chip size can be realized. Furthermore, according to the IGBT 700 of the seventh embodiment, for example compared to the IGBT 600 of the sixth embodiment, by shortening the length of the transistor blocks in the first direction, the delay of the gate signal in the transistor blocks can be suppressed, thereby realizing an IGBT with further reduced switching losses.

[0190] In the seventh embodiment, the case with three transistor blocks was described as an example, but the number of transistor blocks can also be four or more. Even if the number of transistor blocks is four or more, the gate wiring can be laid out without providing additional insulating layers and additional wiring layers.

[0191] According to the seventh embodiment, an IGBT capable of achieving stable multiple gate drive at low cost can be provided.

[0192] In embodiments 1 to 7, the case where the semiconductor device is an IGBT was described as an example, but the present invention can also be applied when the semiconductor device is a metal oxide field effect transistor (MOSFET).

[0193] In embodiments 1 to 7, the case in which the number of grooves 1 to 4 is two to four was described as an example, but the number of grooves 1 to 4 may also be five or more.

[0194] Furthermore, the arrangement order of the first, second, third, and fourth grooves and the ratio of the number of each groove are arbitrary and are not necessarily limited to the arrangement order and ratio of the number of grooves in the first to seventh embodiments.

[0195] Furthermore, in semiconductor devices, trenches may also be provided in which the conductive layer within the trench is not electrically connected to the gate wiring. For example, trenches may also be provided in which the conductive layer within the trench is electrically connected to the emitter electrode.

[0196] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: A semiconductor layer has a first surface and a second surface facing the first surface. The semiconductor layer includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are disposed on the first surface side and extend in the first direction parallel to the first surface. The plurality of second trenches are disposed on the first surface side and extend in the first direction. At least one of the plurality of second trenches is disposed between the first trenches. The first electrode is disposed on the first surface side of the semiconductor layer; The second electrode is disposed on the second surface side of the semiconductor layer; The first gate electrode is disposed in the first trench; The second gate electrode is disposed in the second trench; The first gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, a second portion extending in the first direction, and a third portion extending in the second direction; The second gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, and includes a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; The first gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the first gate wiring. as well as The second gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the second gate wiring. Between the first portion of the first gate wiring and the third portion of the first gate wiring, there is a first portion of the second gate wiring. Between the first portion and the third portion of the second gate wiring, there is a third portion of the first gate wiring. A first portion of the first gate wiring is connected to one end of a second portion of the first gate wiring, and a third portion of the first gate wiring is connected to the other end of the second portion of the first gate wiring. The first portion and the third portion of the first gate wiring are opposite to each other in the first direction. The first portion of the second gate wiring is connected to one end of the second portion of the second gate wiring, and the third portion of the second gate wiring is connected to the other end of the second portion of the second gate wiring. The first portion and the third portion of the second gate wiring are opposite to each other in the first direction. The first electrode is not disposed between the first portion of the first gate wiring and the first portion of the second gate wiring. The first electrode is not disposed between the third portion of the first gate wiring and the third portion of the second gate wiring. The first gate wiring does not intersect with the second gate wiring, and the first gate wiring and the second gate wiring are disposed on the same layer.

2. The semiconductor device of claim 1, wherein, The first portion of the first gate wiring is connected to the first gate electrode at the portion where the first portion of the first gate wiring intersects with the first trench. The third portion of the first gate wiring is connected to the first gate electrode at the portion where the third portion of the first gate wiring intersects with the first trench. The first portion of the second gate wiring is connected to the second gate electrode at the portion where the first portion of the second gate wiring intersects with the second trench. The third portion of the second gate wiring is connected to the second gate electrode at the portion where the third portion of the second gate wiring intersects with the second trench.

3. The semiconductor device as claimed in claim 1 or 2, wherein, The first electrode is provided between the first portion of the second gate wiring and the third portion of the first gate wiring. The first electrode is provided between the second portion of the first gate wiring and the second portion of the second gate wiring.

4. The semiconductor device as claimed in claim 1 or 2, wherein, The first gate wiring further includes a fourth portion extending in the first direction and a fifth portion extending in the second direction. The second gate wiring further includes a fourth portion extending in the first direction and a fifth portion extending in the second direction. Between the third portion and the fifth portion of the first gate wiring, there is a third portion of the second gate wiring. Between the third portion of the second gate wiring and the fifth portion of the second gate wiring, there is a fifth portion of the first gate wiring.

5. The semiconductor device of claim 4, wherein, The fifth portion of the first gate wiring is connected to the first gate electrode at the portion where the fifth portion of the first gate wiring intersects with the first trench. The fifth portion of the second gate wiring is connected to the second gate electrode at the portion where the fifth portion of the second gate wiring intersects with the second trench.

6. The semiconductor device of claim 4, wherein, The first electrode includes a first region and a second region. The first region is provided between the first portion of the second gate wiring and the third portion of the first gate wiring. The first region is provided between the second portion of the first gate wiring and the second portion of the second gate wiring. The second region is provided between the third portion of the second gate wiring and the fifth portion of the first gate wiring. The second region is provided between the fourth portion of the first gate wiring and the fourth portion of the second gate wiring.

7. A semiconductor device, wherein, have: A semiconductor layer has a first surface and a second surface facing the first surface. The semiconductor layer includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are disposed on the first surface side and extend in the first direction parallel to the first surface. The plurality of second trenches are disposed on the first surface side and extend in the first direction. At least one of the plurality of second trenches is disposed between the first trenches. The first electrode is disposed on the first surface side of the semiconductor layer; The second electrode is disposed on the second surface side of the semiconductor layer; The first gate electrode is disposed in the first trench; The second gate electrode is disposed in the second trench; The first gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, a second portion extending in the first direction, and a third portion extending in the second direction; The second gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, and includes a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; The first gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the first gate wiring. as well as The second gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the second gate wiring. Between the first portion of the first gate wiring and the third portion of the first gate wiring, there is a first portion of the second gate wiring. Between the first portion and the third portion of the second gate wiring, there is a third portion of the first gate wiring. The first gate wiring does not intersect with the second gate wiring, and the first gate wiring and the second gate wiring are disposed on the same layer. The semiconductor layer further includes a plurality of third trenches disposed on the first surface side and extending in the first direction. The semiconductor device also includes: The third gate electrode is disposed in the third trench; The third gate wiring, electrically connected to the third gate electrode, includes a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; as well as The third gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the third gate wiring. Between the first portion of the third gate wiring and the first portion of the second gate wiring, there is a first portion of the first gate wiring. Between the third portion of the first gate wiring and the third portion of the second gate wiring, there is a third portion of the third gate wiring.

8. The semiconductor device of claim 7, wherein, The semiconductor layer further includes a plurality of fourth trenches disposed on the first surface side and extending in the first direction. The semiconductor device also includes: The fourth gate electrode is disposed in the fourth trench; The fourth gate wiring, electrically connected to the fourth gate electrode, includes a first portion extending in the second direction, a second portion extending in the first direction, and a third portion extending in the second direction; as well as The fourth gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the fourth gate wiring. Between the first portion of the first gate wiring and the first portion of the second gate wiring, there is a first portion of the fourth gate wiring. Between the third portion of the third gate wiring and the third portion of the fourth gate wiring, there is a third portion of the second gate wiring.

9. A semiconductor device, wherein, have: A semiconductor layer has a first surface and a second surface facing the first surface. The semiconductor layer includes a plurality of first trenches and a plurality of second trenches. The plurality of first trenches are disposed on the first surface side and extend in the first direction parallel to the first surface. The plurality of second trenches are disposed on the first surface side and extend in the first direction. At least one of the plurality of second trenches is disposed between the first trenches. The first electrode is disposed on the first surface side of the semiconductor layer; The second electrode is disposed on the second surface side of the semiconductor layer; The first gate electrode is disposed in the first trench; The second gate electrode is disposed in the second trench; The first gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, a second portion extending in the first direction, a third portion extending in the second direction, a fourth portion extending in the first direction, and a fifth portion extending in the second direction; The second gate wiring is disposed on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, and includes a first portion extending in the second direction, a second portion extending in the first direction, a third portion extending in the second direction, a fourth portion extending in the first direction, and a fifth portion extending in the second direction; The first gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the first gate wiring. as well as The second gate electrode pad is disposed on the first surface side of the semiconductor layer and is electrically connected to the second gate wiring. Between the first portion of the first gate wiring and the third portion of the first gate wiring, there is a first portion of the second gate wiring; Between the third portion of the second gate wiring and the fifth portion of the first gate wiring, the third portion of the first gate wiring is provided; Between the third portion and the fifth portion of the second gate wiring, the fifth portion of the first gate wiring is provided. The first gate wiring does not intersect with the second gate wiring, and the first gate wiring and the second gate wiring are disposed on the same layer.

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