Semiconductor device and semiconductor memory device

Abstract

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes an oxide semiconductor layer; a gate electrode; a gate insulating layer; a first electrode and a second electrode electrically connected to the oxide semiconductor layer; a first conductive layer provided at at least one of a position between the oxide semiconductor layer and the first electrode and a position between the oxide semiconductor layer and the second electrode, containing at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and including a first portion and a second portion, the first portion having a higher atomic concentration of the metal element than an atomic concentration of aluminum in the first portion, and the second portion having a higher atomic concentration of aluminum than an atomic concentration of the metal element in the second portion; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer.

Description

[0001] Related applications

[0002] This application asserts the priority interest based on the priority of a prior Japanese patent application No. 2021-047615 filed on March 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology

[0004] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer exhibit excellent characteristics, such as extremely low channel leakage current during disconnection. Therefore, this paper discusses switching transistors, for example, that can be applied to memory cells of Dynamic Random Access Memory (DRAM).

[0005] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, they undergo thermal processing accompanying the formation of the memory cells or wiring. Therefore, it is desirable to develop an oxide semiconductor transistor with less characteristic change and higher heat resistance, even after thermal processing. Summary of the Invention

[0006] The problem to be solved by the present invention is to provide a semiconductor device with high heat resistance.

[0007] The semiconductor device of the embodiment includes: an oxide semiconductor layer comprising a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer disposed between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a first conductive layer disposed at at least one location between the first region and the first electrode, and between the second region and the second electrode, comprising at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen. (N), and comprising a first part and a second part, wherein the first part is located between the second part and the oxide semiconductor layer, or the second part is located between the first part and the oxide semiconductor layer, wherein the atomic concentration of the at least one metal element in the first part is higher than the aluminum atomic concentration in the first part, and the aluminum atomic concentration in the second part is higher than the atomic concentration of the at least one metal element in the second part; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd), and oxygen (O).

[0008] Based on the aforementioned configuration, a semiconductor device with high heat resistance can be provided. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0014] Figure 6 This is a block diagram of the semiconductor memory device according to the third embodiment.

[0015] Figure 7 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment.

[0016] Figure 8This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment.

[0017] Figure 9 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the third embodiment.

[0018] Figure 10 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the third embodiment.

[0019] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0020] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.

[0021] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will be appropriately omitted.

[0023] Furthermore, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" are merely terms indicating the relative positional relationship within the accompanying drawings, and do not specify the positional relationship relative to gravity.

[0024] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor devices and semiconductor memory devices described in this specification can be performed using methods such as: Secondary Ion Mass Spectrometry (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), Rutherford Back-Scattering Spectroscopy (RBS), and Electron Energy-Loss Spectroscopy (EELS). Furthermore, the thickness of the components constituting the semiconductor device, the distance between components, and the crystal grain size can be determined using, for example, a transmission electron microscope (TEM).

[0025] (First Embodiment) The semiconductor device of the first embodiment includes: an oxide semiconductor layer comprising a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer disposed between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a first conductive layer disposed at at least one location between the first region and the first electrode, and between the second region and the second electrode, comprising at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr). The first conductive layer comprises aluminum (Al) and nitrogen (N), and includes a first portion and a second portion, wherein the first portion is located between the second portion and the oxide semiconductor layer, or the second portion is located between the first portion and the oxide semiconductor layer, wherein the atomic concentration of at least one metal element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of at least one metal element in the second portion; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd), and oxygen (O).

[0026] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0027] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 100 is a so-called bottom-gate type transistor, having a gate electrode on the lower side of the oxide semiconductor layer forming the channel and a source electrode and a drain electrode on the upper side. The transistor 100 is an n-channel type transistor that uses electrons as carriers.

[0028] The transistor 100 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, a first insulating layer 24, and a second insulating layer 26.

[0029] Source electrode 16 is an example of the first electrode. Drain electrode 18 is an example of the second electrode. Barrier layer 20 is an example of the first conductive layer. Contact layer 22 is an example of the second conductive layer.

[0030] In the oxide semiconductor layer 10, when the transistor 100 is turned on, a channel is formed that serves as a current path. The direction of electron flow in the channel is called the channel length direction. Figure 1 The two arrows in the middle indicate the direction of the channel length.

[0031] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0032] The oxide semiconductor layer 10 includes, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of the metal elements contained in the oxide semiconductor layer 10 is 90% or more. Furthermore, the ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of elements other than oxygen contained in the oxide semiconductor layer 10 is 90% or more. For example, in the oxide semiconductor layer 10, there are no elements other than oxygen that have an atomic concentration greater than any one of indium, gallium, aluminum, and zinc.

[0033] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is the region between the first region 10a and the second region 10b.

[0034] The oxide semiconductor layer 10 contains, for example, oxygen defects. The oxygen defects in the oxide semiconductor layer 10 function as donors.

[0035] The thickness of the oxide semiconductor layer 10 is, for example, 10 nm or more and 100 nm or less.

[0036] The oxide semiconductor layer 10 is formed, for example, by atomic layer deposition (ALD).

[0037] Gate electrode 12 is disposed on the underside of oxide semiconductor layer 10. Gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. Gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of gate electrode 12 is, for example, 20 nm to 100 nm. The gate length of gate electrode 12 is the length of gate electrode 12 in the channel length direction.

[0038] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 is disposed between the third region 10c and the gate electrode 12.

[0039] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more but less than 10 nm.

[0040] Alternatively, an oxide layer (not shown) made of a different material than the gate insulating layer 14 may be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.

[0041] The source electrode 16 is disposed on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the source electrode 16.

[0042] The source electrode 16 is disposed on the upper side of the first region 10a. The source electrode 16 is electrically connected to the first region 10a.

[0043] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition than the barrier layer 20.

[0044] The source electrode 16 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0045] The drain electrode 18 is disposed on the upper side of the oxide semiconductor layer 10. The oxide semiconductor layer 10 is sandwiched between the gate electrode 12 and the drain electrode 18.

[0046] The drain electrode 18 is disposed on the upper side of the second region 10b. The drain electrode 18 is electrically connected to the second region 10b.

[0047] The drain electrode 18 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0048] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is disposed between the first region 10a and the source electrode 16. The barrier layer 20 is, for example, connected to the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusion from the oxide semiconductor layer 10 to the source electrode 16.

[0049] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is disposed between the second region 10b and the drain electrode 18. The barrier layer 20 is, for example, connected to the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusion from the oxide semiconductor layer 10 to the drain electrode 18.

[0050] The barrier layer 20 comprises at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N). Among the elements other than aluminum (Al) and nitrogen (N) contained in the barrier layer 20, the atomic concentration of the at least one metallic element is the highest. Hereinafter, the at least one metallic element will also be simply referred to as the metallic element.

[0051] The barrier layer 20 is a nitride of the at least one metallic element containing aluminum (Al).

[0052] The ratio of the aluminum atom concentration in barrier layer 20 to the sum of the atomic concentrations of the metal elements and the aluminum atom concentration is, for example, more than 10% and less than 50%.

[0053] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0054] The thickness of the barrier layer 20 is, for example, less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 1 nm and less than 10 nm.

[0055] The following explanation will be based on the case where the metal element contained in the barrier layer 20 is titanium (Ti). The explanation will also be based on the case where the barrier layer 20 is titanium nitride containing aluminum (Al).

[0056] Figure 2 This is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. Figure 2 It is a cross-sectional view including barrier layer 20.

[0057] The barrier layer 20 includes a first high titanium concentration portion 20a, a first high aluminum concentration portion 20b, a second high titanium concentration portion 20c, a second high aluminum concentration portion 20d, and a third high titanium concentration portion 20e.

[0058] Section 1, high titanium concentration 20a, is an example of Section 1. Section 1, high aluminum concentration 20b, is an example of Section 2. Section 2, high titanium concentration 20c, is an example of Section 3. Section 2, high aluminum concentration 20d, is an example of Section 4.

[0059] In the first high-titanium concentration region 20a, the titanium atom concentration is higher than the aluminum atom concentration. In the second high-titanium concentration region 20c, the titanium atom concentration is higher than the aluminum atom concentration. In the third high-titanium concentration region 20e, the titanium atom concentration is higher than the aluminum atom concentration.

[0060] The first high titanium concentration portion 20a, the second high titanium concentration portion 20c, and the third high titanium concentration portion 20e may or may not contain aluminum.

[0061] In the first high-aluminum-concentration portion 20b, the aluminum atom concentration is higher than the titanium atom concentration. In the second high-aluminum-concentration portion 20d, the aluminum atom concentration is higher than the titanium atom concentration.

[0062] The first high aluminum concentration portion 20b and the second high aluminum concentration portion 20d may or may not contain titanium.

[0063] The first high titanium concentration portion 20a is located between the first high aluminum concentration portion 20b and the oxide semiconductor layer 10. The first high titanium concentration portion 20a is located between the first high aluminum concentration portion 20b and the contact layer 22.

[0064] The first high-aluminum concentration portion 20b is located between the first high-titanium concentration portion 20a and the second high-titanium concentration portion 20c. The second high-titanium concentration portion 20c is located between the first high-aluminum concentration portion 20b and the second high-aluminum concentration portion 20d. The second high-aluminum concentration portion 20d is located between the second high-titanium concentration portion 20c and the third high-titanium concentration portion 20e.

[0065] The first high titanium concentration portion 20a is, for example, connected to the contact layer 22. The third high titanium concentration portion 20e is, for example, connected to the source electrode 16.

[0066] The thicknesses of the first high titanium concentration portion 20a, the first high aluminum concentration portion 20b, the second high titanium concentration portion 20c, the second high aluminum concentration portion 20d, and the third high titanium concentration portion 20e are, for example, 0.2 nm or more and 0.5 nm or less. The thicknesses of the first high titanium concentration portion 20a, the first high aluminum concentration portion 20b, the second high titanium concentration portion 20c, the second high aluminum concentration portion 20d, and the third high titanium concentration portion 20e are the thicknesses in the direction from the contact layer 22 toward the source electrode 16.

[0067] like Figure 2 As shown, the barrier layer 20 has a structure in which high titanium concentration portions and high aluminum concentration portions alternately repeat. Furthermore, Figure 2 The example provided is a case where there are 3 high-titanium concentration portions and 2 high-aluminum concentration portions. However, there are no special restrictions as long as there is at least one high-titanium concentration portion and at least one high-aluminum concentration portion.

[0068] The barrier layer 20 is formed, for example, by the ALD method. The barrier layer 20 is formed by, for example, by the ALD method, alternately repeating a first process of supplying titanium (Ti) material gas and ammonia (NH3) and a second process of supplying aluminum (Al) material gas and ammonia (NH3). By repeating the first and second processes, a high titanium concentration portion and a high aluminum concentration portion are alternately formed.

[0069] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is disposed between the first region 10a and the source electrode 16. Furthermore, the contact layer 22 is disposed between the second region 10b and the drain electrode 18.

[0070] Contact layer 22 is, for example, connected to barrier layer 20. Contact layer 22 is, for example, connected to oxide semiconductor layer 10. Contact layer 22 is, for example, connected to first region 10a. Contact layer 22 is, for example, connected to second region 10b.

[0071] The contact layer 22 has the function of reducing the resistance between the first region 10a and the source electrode 16. The contact layer 22 also has the function of reducing the resistance between the second region 10b and the drain electrode 18.

[0072] Contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Contact layer 22 is an oxide. Contact layer 22 is a metal oxide.

[0073] Contact layer 22 comprises, for example, indium (In) and tin (Sn). Contact layer 22 is, for example, an oxide comprising indium (In) and tin (Sn).

[0074] The thickness of the contact layer 22 is, for example, greater than the thickness of the barrier layer 20. The thicknesses of the contact layer 22 and the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0075] The thickness of the contact layer 22 is, for example, more than twice the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, more than 5 nm and less than 30 nm.

[0076] The contact layer 22 is formed by, for example, sputtering or ALD.

[0077] The first insulating layer 24 is disposed on the underside of the oxide semiconductor layer 10. The first insulating layer 24 is, for example, an oxide, a nitride, or an oxide oxynitride. The first insulating layer 24 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0078] The second insulating layer 26 is disposed on the upper side of the oxide semiconductor layer 10. The second insulating layer 26 is disposed between the source electrode 16 and the drain electrode 18.

[0079] The second insulating layer 26 electrically separates the source electrode 16 from the drain electrode 18. The second insulating layer 26 is, for example, an oxide, a nitride, or an oxynitride. The second insulating layer 26 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0080] The function and effects of the semiconductor device according to the first embodiment will be explained below.

[0081] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, the oxide semiconductor transistors undergo thermal processing accompanying the formation of the memory cells or wiring. There are cases where the threshold voltage of the oxide semiconductor transistor changes due to this thermal processing.

[0082] Threshold voltage variations in oxide semiconductor transistors are caused by oxygen escaping from the oxide semiconductor layer forming the channel to the source or drain electrode. This oxygen escape creates oxygen defects within the oxide semiconductor layer.

[0083] Oxygen defects function as donors in oxide semiconductor layers. Therefore, in the case of an n-channel oxide semiconductor transistor, for example, the threshold voltage of the oxide semiconductor transistor decreases when oxygen defects are generated.

[0084] The transistor 100 of the first embodiment has a barrier layer 20 for suppressing oxygen diffusion between the oxide semiconductor layer 10 and the source electrode 16, and between the oxide semiconductor layer 10 and the drain electrode 18. By having the barrier layer 20, oxygen in the oxide semiconductor layer 10 is suppressed from escaping to the source electrode 16 or the drain electrode 18. Therefore, threshold voltage fluctuations of the transistor 100 are suppressed.

[0085] Figure 3 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 3 This represents the crystalline structure of aluminum-containing titanium nitride (hereinafter referred to as aluminum-containing titanium nitride) that forms the barrier layer.

[0086] Titanium nitride has a sodium chloride-type crystalline structure. Aluminum-containing titanium nitride also has a sodium chloride-type crystalline structure.

[0087] In the aluminum-containing titanium nitride that forms the barrier layer 20, for example, Figure 3 As shown, atomic layers composed of titanium and nitrogen atoms, and atomic layers composed of aluminum and nitrogen atoms are alternately deposited. The atomic layers composed of titanium and nitrogen atoms correspond, for example, to the first high titanium concentration portion 20a, the second high titanium concentration portion 20c, and the third high titanium concentration portion 20e. Furthermore, the atomic layers composed of aluminum and nitrogen atoms correspond, for example, to the first high aluminum concentration portion 20b and the second high aluminum concentration portion 20d.

[0088] In aluminum-containing titanium nitride, the oxygen atoms are stable in their inter-lattice positions. The centroid of a regular tetrahedron composed of 2 titanium atoms, 2 aluminum atoms, and 4 nitrogen atoms is the stable position of the oxygen atom.

[0089] In order for an oxygen atom to move to an adjacent stable position, there are three transition states that must be traversed. The three transition states are: the first transition state, which is surrounded by 2 titanium atoms and 2 nitrogen atoms; the second transition state, which is surrounded by 1 titanium atom, 1 aluminum atom and 2 nitrogen atoms; and the third transition state, which is surrounded by 2 aluminum atoms and 2 nitrogen atoms.

[0090] To move an oxygen atom to an adjacent stable position, there are three paths that pass through each of the three transition states. The three paths are: Figure 3 The paths A, B, and C are shown.

[0091] Path A passes through the first transition state. Path B passes through the second transition state. Path C passes through the third transition state.

[0092] Simulations conducted by the inventors revealed that the diffusion barrier for path A is 4.8 eV, for path B it is 1.5 eV, and for path C it is 1.4 eV. In the case of titanium nitride without aluminum, the diffusion barrier for the path where oxygen atoms move to adjacent stable positions is 0.9 eV.

[0093] By incorporating aluminum into titanium oxide, the diffusion barrier for oxygen atoms to move to adjacent stable positions is increased. Therefore, by incorporating aluminum into titanium oxide, oxygen diffusion can be suppressed. In particular, by possessing a first transition state surrounded by two titanium atoms and two nitrogen atoms, oxygen diffusion can be effectively suppressed.

[0094] The reason why the diffusion barrier of oxygen atoms is increased by adding aluminum to titanium oxide is that the presence of aluminum reduces the lattice constant of the crystal.

[0095] In the first embodiment, the barrier layer 20 of the transistor 100 alternately deposits high-titanium concentration portions and high-aluminum concentration portions from the contact layer 22 toward the source electrode 16 or drain electrode 18. By providing the high-titanium concentration portions with a first transition state that has a high diffusion barrier, oxygen diffusion from the contact layer 22 to the source electrode 16 or drain electrode 18 can be suppressed. Therefore, oxygen escape from the oxide semiconductor layer 10 to the source electrode 16 or drain electrode 18 is suppressed. As a result, threshold voltage fluctuations of the transistor 100 are suppressed.

[0096] in addition, Figure 3 The example illustrates a scenario where each of the high titanium concentration and high aluminum concentration portions consists of a single atomic layer; however, the high titanium concentration and high aluminum concentration portions are not limited to a single atomic layer. For example, each of the high titanium concentration and high aluminum concentration portions may also consist of multiple atomic layers. Furthermore, the high titanium concentration portion may also contain aluminum atoms. Similarly, the high aluminum concentration portion may also contain titanium atoms.

[0097] The ratio of aluminum atom concentration in barrier layer 20 to the sum of the atomic concentrations of metal elements and aluminum atom concentration is preferably 10% to 50%, more preferably 20% to 40%. By exceeding this lower limit, barrier layer 20 can possess a certain amount of first to third transition states, improving the oxygen diffusion suppression effect. Furthermore, by falling below the upper limit, barrier layer 20 can possess a certain amount of first transition states, further improving the oxygen diffusion suppression effect. Additionally, by falling below the upper limit, the resistance of barrier layer 20 can be reduced, thus reducing the resistance between source electrode 16 and oxide semiconductor layer 10. Furthermore, the resistance between drain electrode 18 and oxide semiconductor layer 10 can be reduced.

[0098] The thickness of the barrier layer 20 is preferably 1 nm to 10 nm, more preferably 2 nm to 8 nm, and even more preferably 5 nm or less. A thickness higher than the lower limit improves the oxygen diffusion suppression effect. A thickness lower than the upper limit reduces the resistance of the barrier layer 20, thereby reducing the resistance between the source electrode 16 and the oxide semiconductor layer 10. Furthermore, it reduces the resistance between the drain electrode 18 and the oxide semiconductor layer 10.

[0099] Preferably, the first high titanium concentration portion 20a is in contact with the contact layer 22. By setting a first transition state with a high diffusion barrier at the closest point to the contact layer 22, oxygen intrusion from the contact layer 22 into the barrier layer 20 is suppressed.

[0100] For example, when the first high aluminum concentration portion 20b is in contact with the contact layer 22, there is a concern that the first high aluminum concentration portion 20b may be oxidized, forming high-resistivity aluminum oxide. By contacting the first high titanium concentration portion 20a with the contact layer 22, the formation of aluminum oxide can be suppressed.

[0101] The transistor 100 of the first embodiment has a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. By having the contact layer 22, for example, compared to the case where the barrier layer 20 is directly connected to the oxide semiconductor layer 10 without the contact layer 22, the contact resistance is reduced.

[0102] The contact layer 22 of the transistor 100 is an oxide containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O). By making the contact layer 22 an oxide containing at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O), the formation of high-resistivity reaction products due to heat treatment between the oxide semiconductor layer 10 and the contact layer 22 can be suppressed. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact layer 22 can be reduced.

[0103] From the viewpoint of reducing the contact resistance between the oxide semiconductor layer 10 and the contact layer 22, the contact layer 22 is preferably an oxide containing indium (In) and tin (Sn).

[0104] The thickness of the barrier layer 20 is preferably thinner than the thickness of the contact layer 22. The thickness of the barrier layer 20 is preferably less than half the thickness of the contact layer 22, and more preferably less than one-third.

[0105] The thickness of the contact layer 22 is preferably thicker than the thickness of the barrier layer 20. The thickness of the contact layer 22 is preferably more than twice the thickness of the barrier layer 20, and more preferably more than three times the thickness.

[0106] The resistivity of the barrier layer 20 is, for example, higher than that of the contact layer 22. By making the thickness of the barrier layer 20 thinner than that of the contact layer 22, or in other words, making the thickness of the contact layer 22 thicker than that of the barrier layer 20, the resistance between the source electrode 16 and the oxide semiconductor layer 10 can be reduced, for example. Furthermore, the resistance between the drain electrode 18 and the oxide semiconductor layer 10 can be reduced.

[0107] Furthermore, while titanium (Ti) has been used as an example of a metallic element, the same effects can be achieved by replacing titanium (Ti) with vanadium (V), zirconium (Zr), niobium (Nb), or chromium (Cr). The nitrides of each of vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr) possess the same sodium chloride-type crystalline structure as titanium.

[0108] According to the first embodiment, an oxide semiconductor transistor that suppresses threshold voltage fluctuations after heat treatment and has high heat resistance is realized.

[0109] (Second Embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the gate electrode surrounds the oxide semiconductor layer. Hereinafter, some parts of the description that are repeated in the first embodiment will be omitted.

[0110] Figure 4 , Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 5 yes Figure 4 AA' sectional view. Figure 4 In this context, the horizontal direction is referred to as the first direction, the depth direction as the second direction, and the vertical direction as the third direction.

[0111] The semiconductor device in the second embodiment is a transistor 200. The transistor 200 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 200 is a so-called Surrounding Gate Transistor (SGT) in which the gate electrode surrounds the oxide semiconductor layer forming the channel. The transistor 200 is a so-called vertical transistor.

[0112] Transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, a contact layer 22, and an interlayer insulating layer 32. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer.

[0113] An oxide semiconductor layer 10 is disposed between the source electrode 16 and the drain electrode 18. In the oxide semiconductor layer 10, a channel is formed that serves as a current path when the transistor 200 is turned on. The oxide semiconductor layer 10 extends in a third direction. The oxide semiconductor layer 10 is columnar, extending in the third direction. For example, the oxide semiconductor layer 10 is cylindrical.

[0114] The direction of electron flow in the channel is called the channel length direction. The third direction is the channel length direction of transistor 200.

[0115] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0116] The oxide semiconductor layer 10 includes, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of the metal elements contained in the oxide semiconductor layer 10 is 90% or more. Furthermore, the ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of elements other than oxygen contained in the oxide semiconductor layer 10 is 90% or more. For example, in the oxide semiconductor layer 10, there are no elements other than oxygen that have an atomic concentration greater than any one of indium, gallium, aluminum, and zinc.

[0117] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is the region between the first region 10a and the second region 10b.

[0118] The oxide semiconductor layer 10 contains, for example, oxygen defects. The oxygen defects in the oxide semiconductor layer 10 function as donors.

[0119] The width of the oxide semiconductor layer 10 in the first direction is, for example, 20 nm or more and 100 nm or less. The length of the oxide semiconductor layer 10 in the third direction is, for example, 80 nm or more and 200 nm or less.

[0120] The gate electrode 12 is disposed surrounding the oxide semiconductor layer 10.

[0121] The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm to 100 nm. The gate length of the gate electrode 12 is the length of the gate electrode 12 in the third direction.

[0122] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 surrounds the oxide semiconductor layer 10. The gate insulating layer 14 is disposed between the third region 10c and the gate electrode 12.

[0123] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more but less than 10 nm.

[0124] Alternatively, an oxide layer (not shown) made of a different material than the gate insulating layer 14 may be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.

[0125] The source electrode 16 is disposed on the underside of the oxide semiconductor layer 10. The source electrode 16 is disposed on the underside of the first region 10a. The source electrode 16 is electrically connected to the first region 10a.

[0126] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition than the barrier layer 20.

[0127] The source electrode 16 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0128] Drain electrode 18 is disposed on the upper side of oxide semiconductor layer 10. Drain electrode 18 is disposed on the upper side of second region 10b. Drain electrode 18 is electrically connected to second region 10b.

[0129] The drain electrode 18 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0130] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 20 is disposed between the first region 10a and the source electrode 16. The barrier layer 20 is, for example, connected to the source electrode 16. The barrier layer 20 functions as a diffusion barrier for oxygen diffusion from the oxide semiconductor layer 10 to the source electrode 16.

[0131] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 20 is disposed between the second region 10b and the drain electrode 18. The barrier layer 20 is, for example, connected to the drain electrode 18. The barrier layer 20 functions as a diffusion barrier for oxygen diffusion from the oxide semiconductor layer 10 to the drain electrode 18.

[0132] The barrier layer 20 comprises at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N). Among the elements other than aluminum (Al) and nitrogen (N) contained in the barrier layer 20, the atomic concentration of the at least one metallic element is the highest. Hereinafter, the at least one metallic element will also be simply referred to as the metallic element.

[0133] The barrier layer 20 is a nitride of the at least one metallic element containing aluminum (Al).

[0134] The ratio of the aluminum atom concentration in barrier layer 20 to the sum of the atomic concentrations of the metal elements and the aluminum atom concentration is, for example, more than 10% and less than 50%.

[0135] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0136] The thickness of the barrier layer 20 is, for example, less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 1 nm and less than 10 nm.

[0137] The barrier layer 20 includes a first high titanium concentration portion 20a, a first high aluminum concentration portion 20b, a second high titanium concentration portion 20c, a second high aluminum concentration portion 20d, and a third high titanium concentration portion 20e.

[0138] Section 1, high titanium concentration 20a, is an example of Section 1. Section 1, high aluminum concentration 20b, is an example of Section 2. Section 2, high titanium concentration 20c, is an example of Section 3. Section 2, high aluminum concentration 20d, is an example of Section 4.

[0139] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is disposed between the first region 10a and the source electrode 16. Furthermore, the contact layer 22 is disposed between the second region 10b and the drain electrode 18.

[0140] Contact layer 22 is, for example, connected to barrier layer 20. Contact layer 22 is, for example, connected to oxide semiconductor layer 10. Contact layer 22 is, for example, connected to first region 10a. Contact layer 22 is, for example, connected to second region 10b.

[0141] The contact layer 22 has the function of reducing the resistance between the first region 10a and the source electrode 16. The contact layer 22 also has the function of reducing the resistance between the second region 10b and the drain electrode 18.

[0142] Contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Contact layer 22 is an oxide.

[0143] Contact layer 22 comprises, for example, indium (In) and tin (Sn). Contact layer 22 is, for example, an oxide comprising indium (In) and tin (Sn).

[0144] The thickness of the contact layer 22 is, for example, greater than the thickness of the barrier layer 20. The thicknesses of the contact layer 22 and the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0145] The thickness of the contact layer 22 is, for example, more than twice the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, more than 5 nm and less than 30 nm.

[0146] An interlayer insulating layer 32 is disposed around the gate electrode 12, the source electrode 16, and the drain electrode 18. The interlayer insulating layer 32 is, for example, an oxide, a nitride, or an oxide oxynitride. Alternatively, the interlayer insulating layer 32 may be silicon oxide, silicon nitride, or silicon oxynitride.

[0147] As described above, according to the second embodiment, similarly to the first embodiment, an oxide semiconductor transistor that suppresses threshold voltage fluctuations after heat treatment and possesses high heat resistance is achieved. Furthermore, according to the second embodiment, since it is an SGT (Semiconductor Ground Tunnel), transistors can be densely arranged per unit area.

[0148] (Third Embodiment) The semiconductor memory device of the third embodiment includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; and a memory cell; the memory cell includes: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, and the third region being surrounded by a portion of the second wiring; a gate insulating layer disposed between the third region and a portion of the second wiring; a capacitor electrically connected to the second region; and a first conductive layer disposed at at least one location between the first region and the first wiring, and between the second region and the capacitor, comprising titanium (Ti) or vanadium (V). The first conductive layer comprises at least one metallic element selected from the group consisting of zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and includes a first portion and a second portion. The first portion is located between the second portion and the oxide semiconductor layer, or the second portion is located between the first portion and the oxide semiconductor layer. The atomic concentration of at least one metallic element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of at least one metallic element in the second portion. A second conductive layer is disposed between the oxide semiconductor layer and the first conductive layer, and comprises at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Hereinafter, descriptions of content repeated in the first or second embodiment are omitted.

[0149] The semiconductor memory device of the third embodiment is a semiconductor memory 300. The semiconductor memory device of the third embodiment is a Dynamic Random Access Memory (DRAM). The semiconductor memory 300 uses the transistor 200 of the second embodiment as the switching transistor of the memory cell of the DRAM.

[0150] Figure 6 This is a block diagram of the semiconductor memory device according to the third embodiment.

[0151] like Figure 6 As shown, the semiconductor memory 300 includes a memory cell array 210, a word line driver circuit 212, a row decoder circuit 214, a sense amplifier circuit 215, a column decoder circuit 217, and a control circuit 221.

[0152] Figure 7 , Figure 8 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment. Figure 7 It is a cross-sectional view including the planes in the first and third directions. Figure 8This is a cross-sectional view of a plane including the second and third directions. The first and second directions intersect. The first and second directions are, for example, perpendicular. The third direction is perpendicular to both the first and second directions. The third direction is, for example, perpendicular to the substrate.

[0153] The storage cell array 210 of the third embodiment has a three-dimensional structure with storage cells arranged in a three-dimensional configuration. Figure 7 , Figure 8 The areas enclosed by dashed lines represent one storage unit each.

[0154] The memory cell array 210 has a silicon substrate 250.

[0155] The memory cell array 210 is located on a silicon substrate 250 and includes, for example, a plurality of bit lines BL and a plurality of word lines WL. The bit lines BL extend in a first direction. The word lines WL extend in a second direction.

[0156] Bit line BL and word line WL intersect perpendicularly, for example. A memory cell is configured in the region where bit line BL intersects word line WL. The memory cell includes a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 and the second memory cell MC2 are examples of a memory cell.

[0157] The bit line BL connected to the first memory cell MC1 and the second memory cell MC2 is called bit line BLx. Bit line BLx is an example of the first routing. The word line WL connected to the first memory cell MC1 is called word line WLx. Word line WLx is an example of the second routing.

[0158] The word line WL connected to the second memory cell MC2 is called word line WLy. Word line WLx is located on one side of bit line BLx. Word line WLy is located on the other side of bit line BLx.

[0159] The memory cell array 210 has multiple planar electrode lines PL. The planar electrode lines PL are connected to the planar electrodes 72 of each memory cell.

[0160] The memory cell array 210 has an interlayer insulating layer 260 for electrically separating each wiring and each electrode.

[0161] Multiple word lines WL are electrically connected to the row decoder circuit 214. Multiple bit lines BL are electrically connected to the sense amplifier circuit 215.

[0162] The row decoder circuit 214 has the function of selecting word lines WL according to the input row address signal. The word line driver circuit 212 has the function of applying a specific voltage to the word lines WL selected by the row decoder circuit 214.

[0163] The column decoder circuit 217 has the function of selecting bit line BL according to the input column address signal. The sense amplifier circuit 215 has the function of applying a specific voltage to the bit line BL selected by the column decoder circuit 217. In addition, it has the function of detecting and amplifying the potential of the bit line BL.

[0164] The control circuit 221 has the functions of controlling word line driver circuit 212, row decoder circuit 214, sense amplifier circuit 215, column decoder circuit 217 and other circuits not shown.

[0165] The word line driver circuit 212, row decoder circuit 214, sense amplifier circuit 215, column decoder circuit 217, and control circuit 221, etc., are constructed, for example, by transistors or wiring layers not shown. The transistors are formed using, for example, a silicon substrate 250.

[0166] Bit lines BL and word lines WL are, for example, metallic. Bit lines BL and word lines WL are, for example, titanium nitride, tungsten, or a composite structure of titanium nitride and tungsten.

[0167] Figure 9 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the third embodiment. Figure 10 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the third embodiment.

[0168] The first memory cell MC1 is disposed between the silicon substrate 250 and the bit line BLx. The bit line BLx is disposed between the silicon substrate 250 and the second memory cell MC2.

[0169] The first memory cell MC1 is located below the bit line BLx. The second memory cell MC2 is located above the bit line BLx.

[0170] The first memory cell MC1 is located on one side of bit line BLx. The second memory cell MC2 is located on the other side of bit line BLx.

[0171] The second storage cell MC2 has a structure that allows the first storage cell MC1 to be flipped upside down. The first storage cell MC1 and the second storage cell MC2 each have a transistor 200 and a capacitor 201.

[0172] Transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 20, and a contact layer 22. The gate electrode 12 is an example of a portion of a second wiring. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. Transistor 200 has the same configuration as the transistor 200 of the second embodiment.

[0173] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is the region between the first region 10a and the second region 10b. The third region 10c is surrounded by a gate electrode 12. The gate electrode 12 is considered to be part of the word line WL.

[0174] The barrier layer 20 includes a first high titanium concentration portion 20a, a first high aluminum concentration portion 20b, a second high titanium concentration portion 20c, a second high aluminum concentration portion 20d, and a third high titanium concentration portion 20e.

[0175] Section 1, high titanium concentration 20a, is an example of Section 1. Section 1, high aluminum concentration 20b, is an example of Section 2. Section 2, high titanium concentration 20c, is an example of Section 3. Section 2, high aluminum concentration 20d, is an example of Section 4.

[0176] The capacitor 201 includes a unit electrode 71, a planar electrode 72, and a capacitor insulating film 73. The unit electrode 71 and the planar electrode 72 are, for example, titanium nitride. In addition, the capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0177] Capacitor 201 is electrically connected to one end of the oxide semiconductor layer 10 of the first memory cell MC1 and the second memory cell MC2. The cell electrode 71 of capacitor 201 is connected to the drain electrode 18. The plate electrode 72 is connected to the plate electrode line PL.

[0178] Source electrode 16 is connected to bit line BL. Gate electrode 12 is connected to word line WL.

[0179] in addition, Figure 7 , Figure 8 , Figure 9 , Figure 10 The example shown illustrates the case where the bit line BL and the source electrode 16, and the word line WL and the gate electrode 12 are formed simultaneously from the same material. Alternatively, the bit line BL and the source electrode 16, and the word line WL and the gate electrode 12 can be formed separately from different materials.

[0180] In the oxide semiconductor layer 10 of the first memory cell MC1, the end opposite to the end of the capacitor 201 (the other end) is electrically connected to bit line BLx. In the oxide semiconductor layer 10 of the second memory cell MC2, the end opposite to the end of the capacitor 201 (the other end) is also electrically connected to bit line BLx.

[0181] The gate electrode 12 of the first memory cell MC1 is electrically connected to the word line WLx. Furthermore, the gate electrode 12 of the second memory cell MC2 is electrically connected to the word line WLy.

[0182] The transistor 200 has a barrier layer 20 between the oxide semiconductor layer 10 and the source electrode 16 and the drain electrode 18. In addition, a contact layer 22 is provided between the oxide semiconductor layer 10 and the barrier layer 20.

[0183] When using oxide semiconductor transistors (OSTs) as switching transistors in DRAM memory cells, a high-temperature and prolonged heat treatment is applied after transistor formation. This heat treatment is, for example, the heat treatment used to form a capacitor. Due to the high temperature and prolonged heat treatment, the threshold voltage of the OST is prone to fluctuation.

[0184] Transistor 200 has a barrier layer 20 between oxide semiconductor layer 10 and source electrode 16 and drain electrode 18. Therefore, even if high temperature and long-term heat treatment are applied after transistor formation, threshold voltage fluctuations are suppressed.

[0185] Furthermore, transistor 200 has a contact layer 22 between oxide semiconductor layer 10 and barrier layer 20. Therefore, the contact resistance is reduced. Consequently, the turn-on current of transistor 200 is increased.

[0186] According to the third embodiment, by using the transistor 200 of the second embodiment as the switching transistor of DRAM, a semiconductor memory with high heat resistance is achieved, which suppresses threshold voltage fluctuations after heat treatment.

[0187] (Fourth Embodiment) The semiconductor device of the fourth embodiment includes: an oxide semiconductor layer; an electrode; a first conductive layer disposed between the oxide semiconductor layer and the electrode, comprising at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb) and chromium (Cr), aluminum (Al) and nitrogen (N), and comprising a first portion and a second portion, wherein the first portion is located between the second portion and the oxide semiconductor layer, or the second portion is located between the first portion and the oxide semiconductor layer, wherein the atomic concentration of at least one metal element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of at least one metal element in the second portion; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd), and oxygen (O).

[0188] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0189] The semiconductor device of the fourth embodiment includes a contact structure 400. The contact structure 400 includes an oxide semiconductor layer 10, a barrier layer 20, a contact layer 22, a wiring layer 40, a contact plug 42, and an interlayer insulating layer 44. The barrier layer 20 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer. The contact plug 42 is an example of an electrode.

[0190] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0191] The oxide semiconductor layer 10 includes, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of the metal elements contained in the oxide semiconductor layer 10 is 90% or more. Furthermore, the ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of elements other than oxygen contained in the oxide semiconductor layer 10 is 90% or more. For example, in the oxide semiconductor layer 10, there are no elements other than oxygen that have an atomic concentration greater than any one of indium, gallium, aluminum, and zinc.

[0192] Wiring layer 40 is, for example, a metal or a metal compound.

[0193] Contact plug 42 is disposed between oxide semiconductor layer 10 and wiring layer 40.

[0194] The contact plug 42 is, for example, a metal or a metal compound. The contact plug 42 is, for example, a metal having a different chemical composition than the barrier layer 20.

[0195] The contact plug 42 is, for example, made of titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0196] A barrier layer 20 is disposed between the oxide semiconductor layer 10 and the contact plug 42. The barrier layer 20 is, for example, in contact with the contact plug 42. The barrier layer 20 functions as a diffusion barrier for oxygen to diffuse from the oxide semiconductor layer 10 to the contact plug 42 side.

[0197] The barrier layer 20 comprises at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N). Among the elements other than aluminum (Al) and nitrogen (N) contained in the barrier layer 20, the atomic concentration of the at least one metallic element is the highest. Hereinafter, the at least one metallic element will also be simply referred to as the metallic element.

[0198] The barrier layer 20 is a nitride of the at least one metallic element containing aluminum (Al).

[0199] The ratio of the aluminum atom concentration in barrier layer 20 to the sum of the atomic concentrations of the metal elements and the aluminum atom concentration is, for example, more than 10% and less than 50%.

[0200] The thickness of the barrier layer 20 is, for example, thinner than the thickness of the contact layer 22. The thicknesses of the barrier layer 20 and the contact layer 22 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0201] The thickness of the barrier layer 20 is, for example, less than half the thickness of the contact layer 22. The thickness of the barrier layer 20 is, for example, more than 1 nm and less than 10 nm.

[0202] The barrier layer 20 includes a first high titanium concentration portion 20a, a first high aluminum concentration portion 20b, a second high titanium concentration portion 20c, a second high aluminum concentration portion 20d, and a third high titanium concentration portion 20e.

[0203] Section 1, high titanium concentration 20a, is an example of Section 1. Section 1, high aluminum concentration 20b, is an example of Section 2. Section 2, high titanium concentration 20c, is an example of Section 3. Section 2, high aluminum concentration 20d, is an example of Section 4.

[0204] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 20. The contact layer 22 is, for example, in contact with the barrier layer 20. The contact layer 22 is, for example, in contact with the oxide semiconductor layer 10.

[0205] The contact layer 22 has the function of reducing the resistance between the oxide semiconductor layer 10 and the contact plug 42.

[0206] Contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Contact layer 22 is an oxide.

[0207] Contact layer 22 comprises, for example, indium (In) and tin (Sn). Contact layer 22 is, for example, an oxide comprising indium (In) and tin (Sn).

[0208] The thickness of the contact layer 22 is, for example, greater than the thickness of the barrier layer 20. The thickness of the contact layer 22 and the thickness of the barrier layer 20 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the contact plug 42.

[0209] The thickness of the contact layer 22 is, for example, more than twice the thickness of the barrier layer 20. The thickness of the contact layer 22 is, for example, more than 5 nm and less than 30 nm.

[0210] An interlayer insulating layer 44 is disposed between the oxide semiconductor layer 10 and the wiring layer 40. The interlayer insulating layer 44 is, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0211] In the absence of a barrier layer 20 in the contact structure 400, the contact plug 42 is oxidized by heat treatment applied after the contact structure 400 is formed. That is, the oxygen contained in the oxide semiconductor layer 10 diffuses into the contact plug 42, oxidizing the metal constituting the contact plug 42 to form a metal oxide layer.

[0212] A metal oxide layer is formed between the oxide semiconductor layer 10 and the contact plug 42, thereby increasing the contact resistance between the oxide semiconductor layer 10 and the contact plug 42.

[0213] The contact structure 400 has a barrier layer 20 between the oxide semiconductor layer 10 and the contact plug 42. By having the barrier layer 20, oxidation of the contact plug 42 is suppressed. Therefore, the increase in contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is suppressed.

[0214] Furthermore, the contact structure 400 has a contact layer 22 between the oxide semiconductor layer 10 and the barrier layer 20. Therefore, the contact resistance between the oxide semiconductor layer 10 and the contact plug 42 is reduced.

[0215] According to the fourth embodiment, a semiconductor device that suppresses the increase in contact resistance after heat treatment and has high heat resistance is achieved.

[0216] (Fifth Embodiment) The semiconductor device of the fifth embodiment includes: an oxide semiconductor layer comprising a first region, a second region, and a third region between the first and second regions; a gate electrode; a gate insulating layer disposed between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer disposed at at least one location between the first region and the first electrode, and between the second region and the second electrode, comprising at least one metal element selected from rhodium (Rh) and iridium (Ir) and oxygen (O); and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Furthermore, the gate electrode surrounds the oxide semiconductor layer. The semiconductor device of the fifth embodiment differs from the semiconductor device of the second embodiment in that the material of the first conductive layer is different. Hereinafter, descriptions that are repeated in the second embodiment are omitted.

[0217] Figure 12 , Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Figure 13 yes Figure 12 BB' sectional view. Figure 12 In this context, the horizontal direction is referred to as the first direction, the depth direction as the second direction, and the vertical direction as the third direction.

[0218] The semiconductor device in the fifth embodiment is a transistor 500. The transistor 500 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 500 is a so-called Surrounding Gate Transistor (SGT) in which a gate electrode surrounds the oxide semiconductor layer forming the channel. The transistor 500 is a so-called vertical transistor.

[0219] Transistor 500 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a source electrode 16, a drain electrode 18, a barrier layer 21, a contact layer 22, and an interlayer insulating layer 32. The source electrode 16 is an example of a first electrode. The drain electrode 18 is an example of a second electrode. The barrier layer 21 is an example of a first conductive layer. The contact layer 22 is an example of a second conductive layer.

[0220] An oxide semiconductor layer 10 is disposed between the source electrode 16 and the drain electrode 18. In the oxide semiconductor layer 10, a channel is formed that serves as a current path when the transistor 500 is turned on. The oxide semiconductor layer 10 extends in a third direction. The oxide semiconductor layer 10 is columnar, extending in the third direction. For example, the oxide semiconductor layer 10 is cylindrical.

[0221] The direction of electron flow in the channel is called the channel length direction. The third direction is the channel length direction of transistor 500.

[0222] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0223] The oxide semiconductor layer 10 includes, for example, at least one of gallium (Ga) and aluminum (Al), indium (In), and zinc (Zn). The ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of the metal elements contained in the oxide semiconductor layer 10 is 90% or more. Furthermore, the ratio of the total atomic concentration of indium, gallium, aluminum, and zinc to the total atomic concentration of elements other than oxygen contained in the oxide semiconductor layer 10 is 90% or more. For example, in the oxide semiconductor layer 10, there are no elements other than oxygen that have an atomic concentration greater than any one of indium, gallium, aluminum, and zinc.

[0224] The oxide semiconductor layer 10 has a first region 10a, a second region 10b, and a third region 10c. The third region 10c is the region between the first region 10a and the second region 10b.

[0225] The oxide semiconductor layer 10 contains, for example, oxygen defects. The oxygen defects in the oxide semiconductor layer 10 function as donors.

[0226] The width of the oxide semiconductor layer 10 in the first direction is, for example, 20 nm or more and 100 nm or less. The length of the oxide semiconductor layer 10 in the third direction is, for example, 80 nm or more and 200 nm or less.

[0227] The gate electrode 12 is disposed surrounding the oxide semiconductor layer 10.

[0228] The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm to 100 nm. The gate length of the gate electrode 12 is the length of the gate electrode 12 in the third direction.

[0229] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 surrounds the oxide semiconductor layer 10. The gate insulating layer 14 is disposed between the third region 10c and the gate electrode 12.

[0230] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, 2 nm or more but less than 10 nm.

[0231] Alternatively, an oxide layer (not shown) made of a different material than the gate insulating layer 14 may be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.

[0232] The source electrode 16 is disposed on the underside of the oxide semiconductor layer 10. The source electrode 16 is disposed on the underside of the first region 10a. The source electrode 16 is electrically connected to the first region 10a.

[0233] The source electrode 16 is, for example, a metal or a metal compound. The source electrode 16 is, for example, a metal having a different chemical composition than the barrier layer 21.

[0234] The source electrode 16 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0235] Drain electrode 18 is disposed on the upper side of oxide semiconductor layer 10. Drain electrode 18 is disposed on the upper side of second region 10b. Drain electrode 18 is electrically connected to second region 10b.

[0236] The drain electrode 18 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, copper, aluminum, tantalum, tantalum nitride, or molybdenum.

[0237] A barrier layer 21 is disposed between the oxide semiconductor layer 10 and the source electrode 16. The barrier layer 21 is disposed between the first region 10a and the source electrode 16. The barrier layer 21 is, for example, connected to the source electrode 16. The barrier layer 21 functions as a diffusion barrier for oxygen to diffuse from the oxide semiconductor layer 10 to the source electrode 16.

[0238] A barrier layer 21 is disposed between the oxide semiconductor layer 10 and the drain electrode 18. The barrier layer 21 is disposed between the second region 10b and the drain electrode 18. The barrier layer 21 is, for example, connected to the drain electrode 18. The barrier layer 21 functions as a diffusion barrier for oxygen diffusion from the oxide semiconductor layer 10 to the drain electrode 18.

[0239] The barrier layer 21 contains at least one metallic element, either rhodium (Rh) or iridium (Ir), and oxygen (O). Among the elements other than oxygen (O) contained in the barrier layer 21, rhodium (Rh) or iridium (Ir) has the highest atomic concentration.

[0240] The barrier layer 21 is an oxide. The barrier layer 21 contains, for example, rhodium oxide or iridium oxide. The barrier layer 21 is, for example, rhodium oxide or iridium oxide.

[0241] The thickness of the barrier layer 21 is, for example, less than half the thickness of the contact layer 22. The thickness of the barrier layer 21 is, for example, more than 1 nm and less than 10 nm.

[0242] A contact layer 22 is disposed between the oxide semiconductor layer 10 and the barrier layer 21. The contact layer 22 is disposed between the first region 10a and the source electrode 16. Furthermore, the contact layer 22 is disposed between the second region 10b and the drain electrode 18.

[0243] Contact layer 22 is, for example, connected to barrier layer 21. Contact layer 22 is, for example, connected to oxide semiconductor layer 10. Contact layer 22 is, for example, connected to first region 10a. Contact layer 22 is, for example, connected to second region 10b.

[0244] The contact layer 22 has the function of reducing the resistance between the first region 10a and the source electrode 16. The contact layer 22 also has the function of reducing the resistance between the second region 10b and the drain electrode 18.

[0245] Contact layer 22 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Contact layer 22 is an oxide.

[0246] Contact layer 22 comprises, for example, indium (In) and tin (Sn). Contact layer 22 is, for example, an oxide comprising indium (In) and tin (Sn).

[0247] The thickness of the contact layer 22 is, for example, greater than the thickness of the barrier layer 21. The thicknesses of the contact layer 22 and the barrier layer 21 are the thicknesses in the direction from the oxide semiconductor layer 10 toward the source electrode 16.

[0248] The thickness of the contact layer 22 is, for example, more than twice the thickness of the barrier layer 21. The thickness of the contact layer 22 is, for example, more than 5 nm and less than 30 nm.

[0249] An interlayer insulating layer 32 is disposed around the gate electrode 12, the source electrode 16, and the drain electrode 18. The interlayer insulating layer 32 is, for example, an oxide, a nitride, or an oxide oxynitride. Alternatively, the interlayer insulating layer 32 may be silicon oxide, silicon nitride, or silicon oxynitride.

[0250] The transistor 500 of the fifth embodiment has a barrier layer 21 for suppressing oxygen diffusion between the oxide semiconductor layer 10 and the source electrode 16, and between the oxide semiconductor layer 10 and the drain electrode 18. By having the barrier layer 21, oxygen escape from the oxide semiconductor layer 10 to the source electrode 16 or the drain electrode 18 is suppressed. Therefore, threshold voltage fluctuations of the transistor 500 are suppressed.

[0251] According to the fifth embodiment, an oxide semiconductor transistor (OST) with high heat resistance is achieved, which suppresses threshold voltage fluctuations after heat treatment. Furthermore, according to the fifth embodiment, since it is an SGT, transistors can be arranged at a high density per unit area.

[0252] Alternatively, the barrier layer 21 of the fifth embodiment can be used to replace the barrier layer 20 of the first embodiment to realize a bottom-gate transistor. Furthermore, the barrier layer 21 of the fifth embodiment can be used to replace the barrier layer 20 of the third embodiment to realize a semiconductor memory. Additionally, the barrier layer 21 of the fifth embodiment can be used to replace the barrier layer 20 of the fourth embodiment to realize a contact structure.

[0253] In the first to fourth embodiments, a transistor in which the barrier layer 20 and the contact layer 22 are disposed at two locations: between the first region 10a and the source electrode 16, and between the second region 10b and the drain electrode 18, has been described as an example. However, a transistor in which the barrier layer 20 and the contact layer 22 are disposed at only one location: between the first region 10a and the source electrode 16, and between the second region 10b and the drain electrode 18.

[0254] In the first to fifth embodiments, the case in which the oxide semiconductor layer 10 is a metal oxide containing at least one of gallium (Ga) and aluminum (Al), indium (In) and zinc (Zn) has been described as an example, but other metal oxides may also be applied to the oxide semiconductor layer 10.

[0255] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified to the constituent elements of other embodiments. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer disposed between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a first conductive layer disposed at at least one location between the first region and the first electrode, and between the second region and the second electrode, comprising at least one element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr). The material comprises a metal element, aluminum (Al), and nitrogen (N), and includes a first portion and a second portion, wherein the first portion is located between the second portion and the oxide semiconductor layer, wherein the atomic concentration of the at least one metal element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of the at least one metal element in the second portion; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O).

2. The semiconductor device of claim 1, wherein the first conductive layer further comprises a third portion, wherein the atomic concentration of the at least one metal element in the third portion is higher than the atomic concentration of aluminum, and the second portion is located between the first portion and the third portion.

3. The semiconductor device of claim 2, wherein the first conductive layer further comprises a fourth portion having an aluminum atom concentration higher than the atomic concentration of the at least one metal element, and the third portion being located between the second portion and the fourth portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the ratio of the aluminum atom concentration in the first conductive layer to the sum of the atomic concentrations of the at least one metal element and the aluminum atom concentration is 50% or less.

5. The semiconductor device of claim 1, wherein the thickness of the first conductive layer is thinner than the thickness of the second conductive layer.

6. The semiconductor device according to claim 1, wherein the thickness of the first conductive layer is 10 nm or less.

7. The semiconductor device according to claim 1, wherein the thickness of the first portion is 0.5 nm or less, and the thickness of the second portion is 0.5 nm or less.

8. The semiconductor device of claim 1, wherein the first portion is connected to the second conductive layer.

9. The semiconductor device of claim 1, wherein the oxide semiconductor layer comprises at least one of gallium (Ga) and aluminum (Al), indium (In) and zinc (Zn).

10. The semiconductor device of claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

11. A semiconductor memory device comprising: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; and a memory cell; the memory cell comprising: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region, the first region being electrically connected to the first wiring, and the third region being surrounded by a portion of the second wiring; a gate insulating layer disposed between the third region and a portion of the second wiring; a capacitor electrically connected to the second region; and a first conductive layer disposed at at least one location between the first region and the first wiring, and between the second region and the capacitor, comprising a selection of... The first conductive layer comprises at least one metallic element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and includes a first portion and a second portion, wherein the first portion is located between the second portion and the oxide semiconductor layer, the atomic concentration of the at least one metallic element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of the at least one metallic element in the second portion; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O).

12. The semiconductor memory device of claim 11, wherein the first conductive layer further comprises: a third portion, wherein the atomic concentration of the at least one metal element is higher than the atomic concentration of aluminum; and the second portion is located between the first portion and the third portion.

13. The semiconductor memory device of claim 12, wherein the first conductive layer further comprises: a fourth portion having an aluminum atom concentration higher than the atomic concentration of the at least one metal element; and the third portion being located between the second portion and the fourth portion.

14. The semiconductor memory device according to any one of claims 11 to 13, wherein the ratio of the aluminum atom concentration in the first conductive layer to the sum of the atomic concentrations of the at least one metal element and the aluminum atom concentration is 50% or less.

15. A semiconductor device comprising: an oxide semiconductor layer; an electrode; a first conductive layer disposed between the oxide semiconductor layer and the electrode, comprising at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb) and chromium (Cr), aluminum (Al) and nitrogen (N), and comprising a first portion and a second portion, the first portion being located between the second portion and the oxide semiconductor layer, wherein the atomic concentration of at least one metal element in the first portion is higher than the atomic concentration of aluminum in the first portion, and the atomic concentration of aluminum in the second portion is higher than the atomic concentration of at least one metal element in the second portion; and a second conductive layer disposed between the oxide semiconductor layer and the first conductive layer, comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn) and cadmium (Cd), and oxygen (O).

16. The semiconductor device of claim 15, wherein the first conductive layer further comprises a third portion, wherein the atomic concentration of the at least one metal element in the third portion is higher than the atomic concentration of aluminum, and the second portion is located between the first portion and the third portion.

17. The semiconductor device of claim 16, wherein the first conductive layer further comprises a fourth portion having an aluminum atom concentration higher than the atomic concentration of the at least one metal element, and the third portion being located between the second portion and the fourth portion.

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