Semiconductor device and semiconductor memory device

Abstract

Embodiments provide a semiconductor device and a semiconductor memory device with high heat resistance. A semiconductor device of an embodiment includes an oxide semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion; a gate electrode; a gate insulating layer between the third portion and the gate electrode; a first electrode electrically connected to the first portion, including a first region, a second region, a third region, and a fourth region, the first region being between the first portion and the second region, the first region being between the third region and the fourth region, the first region including at least one element selected from the group consisting of In, Zn, Sn, and Cd and oxygen, the second region including at least one metal element selected from the group consisting of Ti, Ta, W, and Ru, the third region and the fourth region including at least one metal element and O, the oxygen atom concentration of the third region and the fourth region being higher than that of the second region; and a second electrode electrically connected to the second portion.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-44169 (filed on March 17, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device. Background Technology

[0004] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer exhibit excellent characteristics, such as extremely low channel leakage current during shutdown. Therefore, OSTs are studied, for example, as switching transistors for use in memory cells of Dynamic Random Access Memory (DRAM).

[0005] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, the oxide semiconductor transistors undergo heat treatment, which is performed during the formation of the memory cells or wiring. Therefore, it is desirable to achieve oxide semiconductor transistors with high heat resistance, whose characteristics change little even after heat treatment. Summary of the Invention

[0006] The present invention provides a semiconductor device and a semiconductor memory device with high heat resistance.

[0007] A semiconductor device according to an embodiment includes: an oxide semiconductor layer comprising a first portion, a second portion, and a third portion between the first portion and the second portion; a gate electrode extending in a direction intersecting the oxide semiconductor layer; a gate insulating layer disposed between the third portion and the gate electrode; and a first electrode electrically connected to the first portion, the first electrode comprising a first region, a second region, a third region, and a fourth region, the first region being located between the first portion and the second region, the third region being located between the third region and the fourth region, the third region being located on the oxide semiconductor layer side of the second region, the fourth region being located on the oxide semiconductor layer side of the second region, and the first region comprising a selective... The second region comprises at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); the third region comprises the at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru); the fourth region comprises the at least one metal element and oxygen (O); the atomic concentration of oxygen (O) in the third region is higher than that in the second region; the atomic concentration of oxygen (O) in the fourth region is higher than that in the second region; and a second electrode electrically connected to the second portion, wherein the oxide semiconductor layer is disposed between the second electrode and the first electrode. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figures 3 to 13 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 14 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0012] Figure 15 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0013] Figure 16 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0014] Figure 17 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0015] Figure 18This is a block diagram of the semiconductor memory device according to the third embodiment.

[0016] Figure 19 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment.

[0017] Figure 20 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment.

[0018] Figure 21 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the third embodiment.

[0019] Figure 22 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the third embodiment. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will be omitted as appropriate.

[0021] Additionally, for convenience, terms such as "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" are merely terms indicating relative positional relationships within the accompanying drawings, and do not specify positional relationships relative to gravity.

[0022] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device and semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), Rutherford back-scattering spectroscopy (RBS), or electron energy-loss spectroscopy (EELS). Furthermore, measurements of the thickness of the components constituting the semiconductor device, the distance between components, and the grain diameter can be performed, for example, by transmission electron microscopy (TEM). Additionally, measurements of the resistance of the components constituting the semiconductor device and semiconductor memory device can be performed, for example, by scanning diffusion resistance microscopy (SSRM).

[0023] (First Embodiment)

[0024] The semiconductor device of the first embodiment includes: an oxide semiconductor layer comprising a first portion, a second portion, and a third portion between the first portion and the second portion; a gate electrode extending in a direction intersecting the oxide semiconductor layer; a gate insulating layer disposed between the third portion and the gate electrode; a first electrode electrically connected to the first portion, the first electrode comprising a first region, a second region, a third region, and a fourth region, the first region being located between the first portion and the second region, the third region being located between the third region and the fourth region, the third region being located on the oxide semiconductor layer side of the second region, the fourth region being located on the oxide semiconductor layer side of the second region, and the first region comprising indium (In) The first region contains at least one element selected from the group consisting of zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); the second region contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru); the third region contains at least one metallic element and oxygen (O); the fourth region contains at least one metallic element and oxygen (O); the atomic concentration of oxygen (O) in the third region is higher than that in the second region; the atomic concentration of oxygen (O) in the fourth region is higher than that in the second region; and the second electrode is electrically connected to the second part, and an oxide semiconductor layer is provided between the second electrode and the first electrode.

[0025] Figure 1 , Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' section view. In Figure 1 In this context, the horizontal direction is referred to as the first direction, the depth direction as the second direction, and the vertical direction as the third direction.

[0026] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which channels are formed in an oxide semiconductor layer. The transistor 100 is a so-called gate-around transistor (SGT), in which a gate electrode surrounds the oxide semiconductor layer in which channels are formed. The transistor 100 is a so-called vertical transistor. The transistor 100 is an n-channel transistor that uses electrons as charge carriers.

[0027] The transistor 100 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a lower electrode 16, an upper electrode 18, and an interlayer insulating layer 20. The lower electrode 16 is an example of a first electrode. The upper electrode 18 is an example of a second electrode.

[0028] An oxide semiconductor layer 10 is disposed between the lower electrode 16 and the upper electrode 18. A channel is formed in the oxide semiconductor layer 10 that serves as a current path when the transistor 100 is turned on. The oxide semiconductor layer 10 extends in a third direction. The oxide semiconductor layer 10 is columnar, extending in the third direction. For example, the oxide semiconductor layer 10 is cylindrical.

[0029] The direction in which electrons flow in the channel is called the channel length direction. The third direction is the channel length direction of transistor 100.

[0030] The oxide semiconductor layer 10 is an oxide semiconductor. The oxide semiconductor layer 10 is a metal oxide. The oxide semiconductor layer 10 is, for example, amorphous.

[0031] The oxide semiconductor layer 10 includes, for example, indium (In), gallium (Ga), and zinc (Zn). The ratio of the total atomic concentration of indium, gallium, and zinc to the total atomic concentration of the metal elements contained in the oxide semiconductor layer 10 is, for example, 90% or more. Furthermore, the ratio of the total atomic concentration of indium, gallium, and zinc to the total atomic concentration of elements other than oxygen contained in the oxide semiconductor layer 10 is, for example, 90% or more. For example, the oxide semiconductor layer 10 does not contain an element other than oxygen that has a higher atomic concentration than indium, gallium, and zinc.

[0032] The oxide semiconductor layer 10 has a first portion 10a, a second portion 10b, and a third portion 10c. The third portion 10c is the portion between the first portion 10a and the second portion 10b.

[0033] The oxide semiconductor layer 10 contains, for example, oxygen defects. The oxygen defects in the oxide semiconductor layer 10 function as donors.

[0034] The width of the oxide semiconductor layer 10 in the first direction is, for example, 20 nm or more and 100 nm or less. The length of the oxide semiconductor layer 10 in the third direction is, for example, 80 nm or more and 200 nm or less.

[0035] A gate electrode 12 is disposed surrounding the oxide semiconductor layer 10. The gate electrode 12 is disposed around the oxide semiconductor layer 10. The gate electrode 12 extends in a direction intersecting the oxide semiconductor layer 10. The gate electrode 12 extends, for example, in a first direction or a second direction.

[0036] The gate electrode 12 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 12 is, for example, titanium nitride (TiN) or tungsten (W). The gate length of the gate electrode 12 is, for example, 20 nm to 100 nm. The gate length of the gate electrode 12 is the length in the third direction of the gate electrode 12.

[0037] A gate insulating layer 14 is disposed between the oxide semiconductor layer 10 and the gate electrode 12. The gate insulating layer 14 surrounds the oxide semiconductor layer 10. The gate insulating layer 14 is disposed between the third portion 10c and the gate electrode 12.

[0038] The gate insulating layer 14 is, for example, an oxide or an oxide nitride. The gate insulating layer 14 is, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 14 is, for example, more than 2 nm and less than 10 nm.

[0039] Alternatively, an oxide layer (not shown) with a different material from the gate insulating layer 14 may be provided between the oxide semiconductor layer 10 and the gate insulating layer 14.

[0040] The lower electrode 16 is disposed on the lower side of the oxide semiconductor layer 10. The lower electrode 16 is disposed on the lower side of the first portion 10a. The lower electrode 16 is electrically connected to the first portion 10a of the oxide semiconductor layer 10.

[0041] The lower electrode 16 includes a first region 16a, a second region 16b, a third region 16c, and a fourth region 16d.

[0042] Region 16a is located between the first portion 10a of the oxide semiconductor layer 10 and region 16b. Region 16a is located in the third direction of region 16b.

[0043] Region 16a is located between Region 3 16c and Region 4 16d. Region 16a is located in the first direction between Region 3 16c and Region 4 16d.

[0044] Region 16a is located between a portion 16b1 of region 16b and another portion 16b2 of region 16b. Region 16a is located in the first direction between a portion 16b1 of region 16b and another portion 16b2 of region 16b.

[0045] The third region 16c is located on the oxide semiconductor layer 10 side of the second region 16b. The third region 16c is located in the third direction of the second region 16b. The third region 16c is located on the oxide semiconductor layer 10 side of a portion 16b1 of the second region 16b. The third region 16c is located in the third direction of a portion 16b1 of the second region 16b.

[0046] Region 4 16d is located on the oxide semiconductor layer 10 side of region 2 16b. Region 4 16d is located on the oxide semiconductor layer 10 side of region 2 16b. Region 4 16d is located on the oxide semiconductor layer 10 side of another portion 16b2 of region 2 16b. Region 4 16d is located in the third direction of the other portion 16b2 of region 2 16b.

[0047] Region 16a contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd), and oxygen (O). Among the elements included in Region 16a other than oxygen (O), the atomic concentration of the at least one element is the highest. Region 16a is a conductive metal oxide.

[0048] Region 16a may contain, for example, indium (In) and tin (Sn). Region 16a may be, for example, an oxide containing indium (In) and tin (Sn).

[0049] The thickness of region 16a is, for example, 10 nm to 30 nm. The thickness of region 16a is the thickness in the third direction.

[0050] Region 2, 16b contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru). Among the metallic elements contained in Region 2, 16b, the atomic concentration of said at least one metallic element is the highest. Among the elements contained in Region 2, 16b other than nitrogen (N), the atomic concentration of said at least one metallic element is the highest.

[0051] Region 2 16b may contain nitrogen (N). Region 2 16b may or may not contain oxygen (O). The atomic concentration of oxygen in Region 2 16b is lower than that in Region 1 16a.

[0052] Region 16b is a conductor. Region 16b is, for example, a metal or a metal nitride.

[0053] Region 2, 16b, is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.

[0054] The thickness of region 16b is thinner than that of region 16a. The thickness of region 16b is, for example, 2 nm to 10 nm. The thickness of region 16b is the thickness in the third direction.

[0055] Region 3, 16c, contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru), and oxygen (O). Region 3, 16c contains the same metallic elements as Region 2, 16b. Among the metallic elements contained in Region 3, 16c, the atomic concentration of the at least one metallic element is the highest. Among the elements contained in Region 3, 16c other than oxygen (O) and nitrogen (N), the atomic concentration of the at least one metallic element is the highest.

[0056] Region 3, 16c, for example, contains nitrogen (N).

[0057] Region 3, 16c, is, for example, an insulator. Region 3, 16c, is, for example, a metal oxide or a metal nitride.

[0058] Region 3, 16c, is, for example, titanium oxide, titanium oxynitride, tantalum oxide, tantalum oxynitride, or tungsten oxynitride.

[0059] The atomic concentration of oxygen (O) in region 3, 16c is higher than that in region 2, 16b. For example, the atomic concentration of oxygen (O) in region 3, 16c is more than two orders of magnitude higher than that in region 2, 16b. For example, the atomic concentration of oxygen (O) in region 3, 16c is 1 × 10⁻⁶. 20 atoms / cm 3 above.

[0060] The resistance of region 3, 16c, is higher than that of region 2, 16b.

[0061] Region 4, 16d, contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru), and oxygen (O). Region 4, 16d contains the same metallic elements as Region 2, 16b. Among the metallic elements contained in Region 4, 16d, the atomic concentration of the at least one metallic element is the highest. Among the elements contained in Region 4, 16d other than oxygen (O) and nitrogen (N), the atomic concentration of the at least one metallic element is the highest.

[0062] Region 4, 16d, for example, contains nitrogen (N).

[0063] Region 4, 16d, is, for example, an insulator. Region 4, 16d, is, for example, a metal oxide or a metal nitride.

[0064] Region 4, 16d, is for example titanium oxide, titanium oxynitride, tantalum oxide, tantalum oxynitride, or tungsten oxynitride.

[0065] The atomic concentration of oxygen (O) in region 4, 16d is higher than that in region 2, 16b. For example, the atomic concentration of oxygen (O) in region 4, 16d is more than two orders of magnitude higher than that in region 2, 16b. For example, the atomic concentration of oxygen (O) in region 4, 16d is 1 × 10⁻⁶. 20 atoms / cm 3 above.

[0066] The resistance of region 4, 16d, is higher than that of region 2, 16b.

[0067] The upper electrode 18 is disposed on the upper side of the oxide semiconductor layer 10. The upper electrode 18 is disposed on the upper side of the second part 10b. The upper electrode 18 is electrically connected to the second part 10b.

[0068] The upper electrode 18 includes a fifth region 18a and a sixth region 18b. The fifth region 18a is located between the second part 10b and the sixth region 18b. The fifth region 18a is located in the third direction of the sixth region 18b.

[0069] Region 5 18a contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O). Region 5 18a is a conductive metal oxide.

[0070] Region 5 18a may contain, for example, indium (In) and tin (Sn). Region 5 18a may be, for example, an oxide containing indium (In) and tin (Sn).

[0071] The thickness of region 5, 18a, is, for example, 10 nm to 30 nm. The thickness of region 5, 18a, is the thickness in the third direction.

[0072] Region 6, 18b, for example, contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru). Among the metallic elements contained in Region 6, 18b, the at least one metallic element has the highest atomic concentration. Region 6, 18b, for example, contains the same metallic elements as Region 2, 16b, Region 3, 16c, and Region 4, 16d.

[0073] Region 6, 18b, may contain nitrogen (N), for example. Region 6, 18b may or may not contain oxygen (O).

[0074] Region 6, 18b, is a conductor. Region 6, 18b, for example, is a metal or a metal nitride.

[0075] Region 2, 16b, is, for example, titanium, titanium nitride, tantalum, tantalum nitride, or tungsten nitride.

[0076] The thickness of region 6 18b is thinner than the thickness of region 5 18a. The thickness of region 6 18b is, for example, more than 2 nm and less than 10 nm. The thickness of region 6 18b is the thickness in the third direction.

[0077] The atomic concentration of oxygen (O) in region 6, 18b, is, for example, lower than that in region 3, 16c. Furthermore, the atomic concentration of oxygen (O) in region 6, 18b, is, for example, lower than that in region 4, 16d.

[0078] An interlayer insulating layer 20 is disposed around the gate electrode 12, the gate insulating layer 14, the lower electrode 16, and the upper electrode 18. The interlayer insulating layer 20 is, for example, an oxide, a nitride, or an oxide oxynitride. Alternatively, the interlayer insulating layer 20 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0079] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described. Figures 3 to 13 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment.

[0080] First, a groove 31 is formed in the insulating layer 30. Figure 3 The trench 31 is formed, for example, using photolithography and reactive ion etching (RIE). The insulating layer 30 is, for example, a silicon oxide layer. The insulating layer 30 ultimately becomes part of the interlayer insulating layer 20.

[0081] Next, the first conductive film 32 and the first metal oxide film 33 are used to fill the trench 31. Figure 4 The first conductive film 32 is, for example, a titanium nitride film formed by sputtering. The first metal oxide film 33 is, for example, an indium tin oxide film formed by sputtering.

[0082] The first conductive film 32 eventually becomes the second region 16b, the third region 16c, and the fourth region 16d. The first metal oxide film 33 eventually becomes the first region 16a.

[0083] Next, the first conductive film 32 and the first metal oxide film 33 on the insulating layer 30 are removed. Figure 5 The removal of the first conductive film 32 and the first metal oxide film 33 was performed using chemical mechanical polishing (CMP).

[0084] Next, the upper part of the first conductive film 32 exposed on the surface of the insulating layer 30 will be oxidized. Figure 6 An oxide film 34 is formed by oxidizing the upper part of the first conductive film 32. The oxide film 34 is, for example, a titanium oxide film. The oxide film 34 ultimately forms the third region 16c and the fourth region 16d.

[0085] There are no particular limitations on the oxidation method of the upper part of the first conductive film 32. However, it must be a method that can fully oxidize the upper part of the first conductive film 32, such as heat treatment in an oxygen environment or oxygen plasma treatment.

[0086] Next, a first insulating film 35, a conductive layer 36, and a second insulating film 37 are formed on the insulating layer 30 and the first metal oxide film 33. Figure 7The first insulating film 35 is, for example, a silicon oxide film formed by chemical vapor deposition (CVD). The conductive layer 36 is, for example, a tungsten layer formed by CVD. The second insulating film 37 is, for example, a silicon oxide film formed by CVD.

[0087] The first insulating film 35 and the second insulating film 37 ultimately become part of the interlayer insulating layer 20. The conductive layer 36 ultimately becomes the gate electrode 12.

[0088] Next, an opening 38 is formed in the second insulating film 37, the conductive layer 36, and the first insulating film 35. Figure 8 The opening 38 is formed, for example, using photolithography and RIE.

[0089] Next, a third insulating film 39 is formed in the opening 38. Figure 9 The third insulating film 39 is, for example, a silicon oxide film formed by CVD. The third insulating film 39 ultimately becomes the gate insulating layer 14.

[0090] Next, the bottom of the opening 38 and the third insulating film 39 on the surface of the second insulating film 37 are removed. Figure 10 The removal of the third insulating film 39 is carried out, for example, using the RIE method.

[0091] Next, an oxide semiconductor film 40 is formed in the opening 38. Figure 11 The oxide semiconductor film 40, for example, contains indium (In), gallium (Ga), and zinc (Zn). The oxide semiconductor film 40 is formed, for example, using a CVD method. The oxide semiconductor film 40 ultimately becomes the oxide semiconductor layer 10.

[0092] Next, the oxide semiconductor film 40 on the surface of the second insulating film 37 is removed. Figure 12 The removal of the oxide semiconductor film 40 is performed, for example, using the CMP method.

[0093] Next, a second metal oxide film 41 and a second conductive film 42 are formed on the surfaces of the second insulating film 37 and the oxide semiconductor film 40. The second metal oxide film 41 is, for example, an indium tin oxide film formed by sputtering. The second conductive film 42 is, for example, a titanium nitride film formed by sputtering.

[0094] The second metal oxide film 41 eventually becomes the fifth region 18a. Additionally, the second conductive film 42 eventually becomes the sixth region 18b.

[0095] Next, the second metal oxide film 41 and the second conductive film 42 are patterned. Figure 13 The patterning of the second metal oxide film 41 and the second conductive film 42 is performed, for example, by photolithography and RIE.

[0096] Then, an insulating film is formed on the second metal oxide film 41 and the second conductive film 42.

[0097] Using the manufacturing method described above, the transistor 100 of the first embodiment is formed.

[0098] The function and effects of the semiconductor device according to the first embodiment will be explained below.

[0099] When forming the lower electrode 16 of the transistor 100, after embedding the first metal oxide film 33 in the trench 31 formed in the insulating layer 30, the first metal oxide film 33 is planarized using a CMP method. The first metal oxide film 33 becomes the first region 16a of the lower electrode 16. When the first metal oxide film 33 is embedded in the trench 31, the adhesion to the insulating layer 30 is low, and there is a concern that film peeling may occur when the first metal oxide film 33 is removed using a CMP method.

[0100] In the lower electrode 16 of transistor 100, a second region 16b is provided between the first region 16a and the interlayer insulating layer 20. During the manufacture of transistor 100, as follows... Figure 4 As shown, a first conductive film 32, which will become the second region 16b, is formed before the first metal oxide film 33 is formed. The first conductive film 32 has high adhesion to the insulating layer 30. Therefore, film peeling during the removal of the first metal oxide film 33 using the CMP method is suppressed. As a result, the manufacturing yield of the transistor 100 is improved.

[0101] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, the oxide semiconductor transistors undergo heat treatment, which is performed during the formation of the memory cells or wiring. Sometimes, due to the heat treatment, the threshold voltage of the oxide semiconductor transistor will fluctuate.

[0102] The threshold voltage variation in oxide semiconductor transistors is caused by oxygen escaping from the oxide semiconductor layer containing channels during heat treatment, either towards the lower or upper electrode. This oxygen escape leads to oxygen defects within the oxide semiconductor layer.

[0103] Oxygen defects function as donors in oxide semiconductor layers. Therefore, for example, in the case of an n-channel oxide semiconductor transistor, the threshold voltage of the oxide semiconductor transistor decreases when oxygen defects are generated.

[0104] Figure 14 This is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is a transistor 900.

[0105] The transistor 900 of the comparative example differs from the transistor 100 of the first embodiment in that the lower electrode 16 does not include the third region 16c and the fourth region 16d.

[0106] Figure 15 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0107] Figure 15 This illustrates a situation where alignment misalignment occurs during the manufacturing of the comparative example transistor 900. Specifically, it describes a situation where alignment misalignment occurs during the manufacturing process of transistor 100. Figure 8 In the same process as the opening 38 shown, the opening 38 and the lower layer pattern are misaligned.

[0108] By offsetting the oxide semiconductor layer 10 relative to the lower electrode 16 in the first direction, the oxide semiconductor layer 10 is directly connected to the second region 16b of the lower electrode 16.

[0109] The second region 16b is, for example, a metal or a metal nitride. During the heat treatment when manufacturing the transistor 900, oxygen in the oxide semiconductor layer 10 is absorbed by the second region 16b, causing oxygen to escape from the oxide semiconductor layer 10. Therefore, oxygen defects are generated in the oxide semiconductor layer 10. Consequently, the threshold voltage of the transistor 900 decreases.

[0110] Figure 16 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0111] Figure 16 This describes a situation where alignment misalignment occurs during the manufacturing of the transistor 100 of the first embodiment. Specifically, it describes a situation where alignment misalignment occurs during the manufacturing process of the transistor 100. Figure 8 In the process of the opening 38 shown, the opening 38 and the lower layer pattern are misaligned.

[0112] By offsetting the oxide semiconductor layer 10 relative to the lower electrode 16 in the first direction, the oxide semiconductor layer 10 is directly connected to the third region 16c of the lower electrode 16.

[0113] Region 16c is an oxide layer. Therefore, during the heat treatment process in manufacturing transistor 100, the absorption of oxygen in the oxide semiconductor layer 10 by region 16c is suppressed. This suppresses the reduction of the threshold voltage of transistor 100. Consequently, the heat resistance of transistor 100 is improved.

[0114] Furthermore, the same effect can be obtained when the oxide semiconductor layer 10 is offset relative to the lower electrode 16 in the first direction, so that the oxide semiconductor layer 10 is directly connected to the fourth region 16d of the lower electrode 16.

[0115] Furthermore, the third region 16c and the fourth region 16d of the lower electrode 16 of the transistor 100 are high-resistance due to being made of oxide. For example, the third region 16c and the fourth region 16d are insulators. Therefore, the upper corner of the lower electrode 16 (made by...) Figure 1 The electric field concentration at the portion (X) enclosed by the dashed circle in the diagram is mitigated. As a result, for example, leakage current between the lower electrode 16 and the gate electrode 12 is suppressed, and malfunction of the transistor 100 is suppressed.

[0116] From the viewpoint of suppressing oxygen absorption in the third region 16c and the fourth region 16d, the atomic concentration of oxygen (O) in the third region 16c and the fourth region 16d is preferably two orders of magnitude higher than the atomic concentration of oxygen (O) in the second region 16b, and more preferably three orders of magnitude higher.

[0117] From the viewpoint of suppressing oxygen absorption in region 3 16c and region 4 16d, the atomic concentration of oxygen (O) in region 3 16c and region 4 16d is preferably 1 × 10⁻⁶. 20 atoms / cm 3 The above is preferred to be 1×10 21 atoms / cm 3 above.

[0118] From the viewpoint of reducing the resistance of the lower electrode 16, the thickness of the second region 16b is preferably thinner than the thickness of the first region 16a. Furthermore, as described above, the thicknesses of the first region 16a and the second region 16b are the thicknesses in the third direction.

[0119] Furthermore, in the transistor 100, the case in which the gate electrode 12 surrounds the oxide semiconductor layer 10 has been described as an example, but the gate electrode 12 may not completely surround the oxide semiconductor layer 10. For example, it is also possible to form a configuration in which the gate electrode 12 is disposed opposite to a portion of the oxide semiconductor layer 10.

[0120] According to the first embodiment, the change in threshold voltage after heat treatment can be suppressed, thereby realizing an oxide semiconductor transistor with high heat resistance.

[0121] (Second Implementation)

[0122] The semiconductor device differs from that of the first embodiment in that it further includes a first conductive layer and a second conductive layer. The first conductive layer is electrically connected to a first electrode, and the first electrode is disposed between the first conductive layer and the oxide semiconductor layer. The second conductive layer is electrically connected to a second electrode, and the second electrode is disposed between the second conductive layer and the oxide semiconductor layer. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0123] Figure 17 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0124] The semiconductor device in the second embodiment is a transistor 200. The transistor 200 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 200 is a so-called SGT (Structured Ground Tunneling) transistor, in which a gate electrode surrounds the oxide semiconductor layer in which the channel is formed. The transistor 200 is a so-called vertical transistor.

[0125] Transistor 200 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a lower electrode 16, an upper electrode 18, an interlayer insulating layer 20, a lower conductive layer 22, and an upper conductive layer 24. The lower electrode 16 is an example of a first electrode. The upper electrode 18 is an example of a second electrode. The lower conductive layer 22 is an example of a first conductive layer. The upper conductive layer 24 is an example of a second conductive layer.

[0126] The lower electrode 16 includes a first region 16a, a second region 16b, a third region 16c, and a fourth region 16d. The upper electrode 18 includes a fifth region 18a and a sixth region 18b.

[0127] A lower conductive layer 22 is disposed below the lower electrode 16. The lower conductive layer 22 is located in the third direction of the lower electrode 16. The lower electrode 16 is disposed between the lower conductive layer 22 and the oxide semiconductor layer 10. The lower conductive layer 22 is electrically connected to the lower electrode 16.

[0128] The lower conductive layer 22 is a conductor. The lower conductive layer 22 may be, for example, a metal or a semiconductor. The lower conductive layer 22 may be, for example, tungsten or polycrystalline silicon.

[0129] An upper conductive layer 24 is disposed above the upper electrode 18. The upper conductive layer 24 is located in the third direction of the upper electrode 18. The upper electrode 18 is disposed between the upper conductive layer 24 and the oxide semiconductor layer 10. The upper conductive layer 24 is electrically connected to the upper electrode 18.

[0130] The upper conductive layer 24 is a conductor. The upper conductive layer 24 can be, for example, a metal or a semiconductor. The upper conductive layer 24 can be, for example, tungsten or polycrystalline silicon.

[0131] The lower electrode 16 has a second region 16b between the lower conductive layer 22 and the first region 16a. When manufacturing the transistor 200, similar to the transistor 100, the first conductive film 32, which will become the second region 16b, is formed before the first metal oxide film 33, which will become the first region 16a of the lower electrode 16, is formed. Therefore, oxidation of the lower conductive layer 22 is suppressed. Because oxidation of the lower conductive layer 22 is suppressed, the formation of a high-resistivity oxide film between the lower conductive layer 22 and the lower electrode 16 is also suppressed.

[0132] According to the second embodiment, similar to the first embodiment, the change in threshold voltage after heat treatment can be suppressed, thereby realizing an oxide semiconductor transistor with high heat resistance.

[0133] (Third Implementation)

[0134] The semiconductor memory device of the third embodiment includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, and a memory cell; the memory cell includes an oxide semiconductor layer, a gate electrode, a gate insulating layer, a first electrode, a second electrode, and a capacitor. The oxide semiconductor layer includes a first portion, a second portion, and a third portion between the first portion and the second portion. The gate electrode extends in a direction intersecting the oxide semiconductor layer and is electrically connected to the second wiring. The gate insulating layer is disposed between the third portion and the gate electrode. The first electrode is electrically connected to the first portion, and the first electrode includes a first region, a second region, a third region, and a fourth region. The first region is located between the first portion and the second region, the third region is located between the third region and the fourth region, the third region is located on the oxide semiconductor layer side of the second region, and the fourth region is located on the second region. On the oxide semiconductor layer side of region 2, region 1 contains at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O); region 2 contains at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru); region 3 contains at least one metal element and oxygen (O); and region 4 contains at least one metal element and oxygen (O). The atomic concentration of oxygen (O) in region 3 is higher than that in region 2, and the atomic concentration of oxygen (O) in region 4 is higher than that in region 2. The second electrode is electrically connected to the second portion, and an oxide semiconductor layer is provided between the second electrode and the first electrode. The capacitor is electrically connected to one of the first electrode or the second electrode; and the first wiring is electrically connected to the other of the first electrode or the second electrode. Hereinafter, descriptions that are repeated in the first or second embodiment will sometimes be omitted.

[0135] The semiconductor memory device of the third embodiment is a semiconductor memory 300. The semiconductor memory device of the third embodiment is a dynamic random access memory (DRAM). The semiconductor memory 300 uses the transistor 100 of the first embodiment as a switching transistor for a memory cell of the DRAM.

[0136] Figure 18 This is a block diagram of the semiconductor memory device according to the third embodiment.

[0137] like Figure 18 As shown, the semiconductor memory 300 includes a memory cell array 210, a word line driver circuit 212, a row decoder circuit 214, a sense amplifier circuit 215, a column decoder circuit 217, and a control circuit 221.

[0138] Figure 19 , Figure 20 This is a schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the third embodiment. Figure 19 It is a cross-sectional view including the planes in the first and third directions. Figure 20 This is a cross-sectional view of a plane including the second and third directions. The first and second directions intersect. The first and second directions are, for example, perpendicular. The third direction is perpendicular to both the first and second directions. The third direction is, for example, perpendicular to the substrate.

[0139] The memory cell array 210 of the third embodiment has a three-dimensional structure formed by the three-dimensional arrangement of memory cells. Figure 19 , Figure 20 The areas enclosed by dashed lines represent one storage unit each.

[0140] The memory cell array 210 has a silicon substrate 250.

[0141] The memory cell array 210 is on a silicon substrate 250, and includes, for example, multiple bit lines BL and multiple word lines WL. The bit lines BL extend in a first direction. The word lines WL extend in a second direction.

[0142] Bit line BL and word line WL intersect, for example, perpendicularly. Memory cells are arranged in the area where bit line BL and word line WL intersect. Each memory cell includes a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 and the second memory cell MC2 are examples of memory cells.

[0143] The bit line BL connected to the first memory cell MC1 and the second memory cell MC2 is called bit line BLx. Bit line BLx is an example of the first wiring.

[0144] The word line WL connected to the first memory cell MC1 is called word line WLx. Word line WLx is an example of the second wiring. The word line WL connected to the second memory cell MC2 is called word line WLy. Word line WLx is located on one side of bit line BLx. Word line WLy is located on the other side of bit line BLx.

[0145] The memory cell array 210 has multiple plate-shaped electrode lines PL. The plate-shaped electrode lines PL are connected to the plate-shaped electrodes 72 of each memory cell.

[0146] The memory cell array 210 has an interlayer insulating layer 260 for electrically isolating each wiring and each electrode.

[0147] Multiple word lines WL are electrically connected to the line decoder circuit 214. Multiple bit lines BL are electrically connected to the sense amplifier circuit 215.

[0148] The line decoder circuit 214 is capable of selecting word lines WL based on the input line address signal. The word line driver circuit 212 is capable of applying a specific voltage to the word lines WL selected by the line decoder circuit 214.

[0149] The column decoder circuit 217 has the function of selecting bit line BL according to the input column address signal. The sense amplifier circuit 215 has the function of applying a specific voltage to the bit line BL selected by the column decoder circuit 217. In addition, it has the function of detecting the potential of the bit line BL and amplifying it.

[0150] The control circuit 221 has the function of controlling the word line driver circuit 212, the row decoder circuit 214, the sense amplifier circuit 215, the column decoder circuit 217, and other circuits not shown.

[0151] The word line driver circuit 212, the row decoder circuit 214, the sense amplifier circuit 215, the column decoder circuit 217, and the control circuit 221, etc., are constructed, for example, by transistors or wiring layers not shown. The transistors are formed, for example, using a silicon substrate 250.

[0152] Bit lines BL and word lines WL are conductive. Bit lines BL and word lines WL can also be metal, for example.

[0153] Figure 21 This is a schematic cross-sectional view of the first memory cell of the semiconductor memory device according to the third embodiment. Figure 22 This is a schematic cross-sectional view of the second memory cell of the semiconductor memory device according to the third embodiment.

[0154] The first memory cell MC1 is disposed between the silicon substrate 250 and the bit line BLx. The bit line BLx is disposed between the silicon substrate 250 and the second memory cell MC2.

[0155] The first memory cell MC1 is located below the bit line BLx. The second memory cell MC2 is located above the bit line BLx.

[0156] The first memory cell MC1 is located on one side of bit line BLx. The second memory cell MC2 is located on the other side of bit line BLx.

[0157] The first storage unit MC1 and the second storage unit MC2 each have a transistor 100 and a capacitor 201.

[0158] The transistor 100 includes an oxide semiconductor layer 10, a gate electrode 12, a gate insulating layer 14, a lower electrode 16, an upper electrode 18, and an interlayer insulating layer 20. The lower electrode 16 is an example of a first electrode. The upper electrode 18 is an example of a second electrode.

[0159] The oxide semiconductor layer 10 has a first portion 10a, a second portion 10b, and a third portion 10c. The third portion 10c is the region between the first portion 10a and the second portion 10b.

[0160] The lower electrode 16 includes a first region 16a, a second region 16b, a third region 16c, and a fourth region 16d. The upper electrode 18 includes a fifth region 18a and a sixth region 18b.

[0161] The gate electrode 12 of the first memory cell MC1 is electrically connected to the word line WLx. Additionally, the gate electrode 12 of the second memory cell MC2 is electrically connected to the word line WLy.

[0162] The capacitor 201 includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 and the plate electrode 72 are, for example, titanium nitride. In addition, the capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0163] In the first memory cell MC1, capacitor 201 is electrically connected to the lower electrode 16. Cell electrode 71 of capacitor 201 is connected to the lower electrode 16. Plate electrode 72 is connected to plate electrode line PL. In the first memory cell MC1, bit line BLx is electrically connected to the upper electrode 18.

[0164] In the second memory cell MC2, capacitor 201 is electrically connected to the upper electrode 18. Cell electrode 71 of capacitor 201 is connected to the upper electrode 18. Plate electrode 72 is connected to plate electrode line PL. In the second memory cell MC2, bit line BLx is electrically connected to the lower electrode 16.

[0165] In addition, Figure 19 , Figure 20 , Figure 21 ,and Figure 22In this example, the word line WL and the gate electrode 12 are formed simultaneously from the same material. However, the word line WL and the gate electrode 12 can also be formed separately from different materials.

[0166] In addition, Figure 19 , Figure 20 , Figure 21 ,and Figure 22 In this example, the bit line BL and the lower electrode 16, and the bit line BL and the upper electrode 18 are formed separately from different materials. Alternatively, the bit line BL and the lower electrode 16, and the bit line BL and the upper electrode 18 can be formed simultaneously from the same material.

[0167] According to the third embodiment, by using the transistor 100 of the first embodiment as a switching transistor for DRAM, the fluctuation of the threshold voltage after heat treatment can be suppressed, thereby realizing a semiconductor memory with high heat resistance.

[0168] In the first to third embodiments, the case where the oxide semiconductor layer 10 is a metal oxide containing indium (In), gallium (Ga), and zinc (Zn) was described as an example, but other metal oxides can also be used for the oxide semiconductor layer 10.

[0169] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, an element of one embodiment may be replaced or modified with an element of another embodiment. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

[0170] [Symbol Explanation]

[0171] 10: Oxide semiconductor layer

[0172] 10a: Part 1

[0173] 10b: Part 2

[0174] 10c: Part 3

[0175] 12: Gate electrode

[0176] 14: Gate insulating layer

[0177] 16: Lower electrode (Electrode 1)

[0178] 16a: Region 1

[0179] 16b: Region 2

[0180] 16b1: Part of Region 2

[0181] 16b2: Another part of region 2

[0182] 16c: Region 3

[0183] 16d: Region 4

[0184] 18: Upper electrode (second electrode)

[0185] 18a: Area 5

[0186] 18b: Region 6

[0187] 22: Lower conductive layer (first conductive layer)

[0188] 24: Upper conductive layer (second conductive layer)

[0189] 100: Transistor (semiconductor device)

[0190] 200: Transistor (semiconductor device)

[0191] 201: Capacitor

[0192] 300: Semiconductor memory (semiconductor storage device)

[0193] BLx: Bit line (first wiring)

[0194] MC1: First storage unit (storage unit)

[0195] WLx: Word line (second wiring).

Claims

1. A semiconductor device comprising: An oxide semiconductor layer comprising a first portion, a second portion, and a third portion between the first portion and the second portion; The gate electrode extends in a direction intersecting the oxide semiconductor layer; A gate insulating layer is disposed between the third portion and the gate electrode; A first electrode is electrically connected to the first portion. The first electrode includes a first region, a second region, a third region, and a fourth region. The first region is located between the first portion and the second region. The third region is located between the third region and the fourth region. The third region is located on the oxide semiconductor layer side of the second region. The fourth region is located on the oxide semiconductor layer side of the second region. The first region comprises an alloy selected from indium (In), zinc (Zn), tin (Sn), and cadmium (Cd). The second region comprises at least one element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru); the third region comprises the at least one metal element and oxygen (O); the fourth region comprises the at least one metal element and oxygen (O); the atomic concentration of oxygen (O) in the third region is higher than the atomic concentration of oxygen (O) in the second region; and the atomic concentration of oxygen (O) in the fourth region is higher than the atomic concentration of oxygen (O) in the second region. The second electrode is electrically connected to the second part, and the oxide semiconductor layer is provided between the second electrode and the first electrode.

2. The semiconductor device of claim 1, wherein the first region is located between a portion of the second region and another portion of the second region.

3. The semiconductor device of claim 1, wherein the thickness of the second region is thinner than the thickness of the first region.

4. The semiconductor device of claim 1, wherein the resistance of the third region is higher than the resistance of the second region, and the resistance of the fourth region is higher than the resistance of the second region.

5. The semiconductor device according to claim 1, wherein the atomic concentration of oxygen (O) in the third region is more than two orders of magnitude higher than the atomic concentration of oxygen (O) in the second region, and the atomic concentration of oxygen (O) in the fourth region is more than two orders of magnitude higher than the atomic concentration of oxygen (O) in the second region.

6. The semiconductor device according to claim 1, wherein the atomic concentration of oxygen (O) in the third region is 1 × 10⁻⁶. 20 atoms / cm 3 The atomic concentration of oxygen (O) in the fourth region is 1 × 10⁴. 20 atoms / cm 3 above.

7. The semiconductor device of claim 1, wherein the second region, the third region, and the fourth region further comprise nitrogen (N).

8. The semiconductor device according to claim 1, further comprising a first conductive layer electrically connected to the first electrode, wherein the first electrode is disposed between the first conductive layer and the oxide semiconductor layer.

9. The semiconductor device of claim 1, wherein the second electrode comprises a fifth region and a sixth region, the fifth region being located between the second portion and the sixth region, the fifth region comprising at least one element selected from the group consisting of indium (In), zinc (Zn), tin (Sn), and cadmium (Cd) and oxygen (O), the sixth region comprising the at least one metal element, the atomic concentration of oxygen (O) in the sixth region being lower than the atomic concentration of oxygen (O) in the third region, and the atomic concentration of oxygen (O) in the sixth region being lower than the atomic concentration of oxygen (O) in the fourth region.

10. The semiconductor device according to claim 1, further comprising a second conductive layer electrically connected to the second electrode, wherein the second electrode is disposed between the second conductive layer and the oxide semiconductor layer.

11. The semiconductor device of claim 1, wherein the oxide semiconductor layer is in contact with the third region or the fourth region.

12. The semiconductor device of claim 1, wherein the oxide semiconductor layer comprises indium (In), gallium (Ga), and zinc (Zn).

13. The semiconductor device of claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

14. A semiconductor memory device comprising: The first wiring extends in the first direction; The second wiring extends in a second direction that intersects the first direction; and Storage unit; The storage unit includes: An oxide semiconductor layer comprising a first portion, a second portion, and a third portion between the first portion and the second portion; A gate electrode extends in a direction intersecting the oxide semiconductor layer and is electrically connected to the second wiring; A gate insulating layer is disposed between the third portion and the gate electrode; A first electrode is electrically connected to the first portion. The first electrode includes a first region, a second region, a third region, and a fourth region. The first region is located between the first portion and the second region. The third region is located between the third region and the fourth region. The third region is located on the oxide semiconductor layer side of the second region. The fourth region is located on the oxide semiconductor layer side of the second region. The first region comprises an element selected from indium (In), zinc (Zn), tin (Sn), and cadmium (Cd). The second region contains at least one element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and ruthenium (Ru), the third region contains the at least one metal element and oxygen (O), the fourth region contains the at least one metal element and oxygen (O), the atomic concentration of oxygen (O) in the third region is higher than the atomic concentration of oxygen (O) in the second region, and the atomic concentration of oxygen (O) in the fourth region is higher than the atomic concentration of oxygen (O) in the second region; A second electrode, electrically connected to the second portion, wherein the oxide semiconductor layer is disposed between the second electrode and the first electrode; and A capacitor is electrically connected to either the first electrode or the second electrode; and The first wiring is electrically connected to either the first electrode or the second electrode.

15. The semiconductor memory device of claim 14, wherein the first region is located between a portion of the second region and another portion of the second region.

16. The semiconductor memory device of claim 14, wherein the thickness of the second region is thinner than the thickness of the first region.

17. The semiconductor memory device of claim 14, wherein the resistance of the third region is higher than the resistance of the second region, and the resistance of the fourth region is higher than the resistance of the second region.

18. The semiconductor memory device according to claim 14, wherein the atomic concentration of oxygen (O) in the third region is more than two orders of magnitude higher than the atomic concentration of oxygen (O) in the second region, and the atomic concentration of oxygen (O) in the fourth region is more than two orders of magnitude higher than the atomic concentration of oxygen (O) in the second region.

19. The semiconductor memory device of claim 14, wherein the atomic concentration of oxygen (O) in the third region is 1 × 10⁻⁶. 20 atoms / cm 3 The atomic concentration of oxygen (O) in the fourth region is 1 × 10⁴. 20 atoms / cm 3 above.

20. The semiconductor memory device of claim 14, wherein the second region, the third region, and the fourth region further comprise nitrogen (N).

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