A low-power acquisition method and system for Beidou navigation chips

Abstract

This invention discloses a low-power acquisition system applied to a BeiDou navigation chip, including an acquisition engine module, a tracking engine module, and a system clock circuit module. The low-power acquisition system also includes an N-divider. The acquisition engine module includes a first sampling buffer unit, an acquisition calculation unit, and a preprocessing unit. The first sampling buffer unit and the acquisition calculation unit are connected to the N-divider and use the system clock of the system clock circuit module after N-division. The preprocessing unit is connected to the system clock circuit module and uses the system clock of the system clock circuit module. The tracking engine module includes a tracking calculation unit and a second sampling buffer unit, which are connected to the system clock circuit module's system clock. Through clock architecture optimization and frequency adaptation, the power consumption and area of ​​the acquisition engine are significantly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and particularly relates to a low-power acquisition method and system applied to a Beidou navigation chip. BACKGROUND

[0002] Under the background of rapid development and increasingly fierce competition in the field of satellite navigation, satellite navigation system performance gradually attracts widespread attention, and the performance of the satellite navigation system directly affects its operation and service level. The navigation chip is an important part of the navigation system, and the improvement of its performance is crucial to the improvement of the performance of the entire navigation system. Power consumption is a very important performance indicator of the navigation chip. In the Beidou navigation chip, the acquisition engine and the tracking engine are usually included, and the power consumption of these units accounts for a large proportion of the entire navigation chip power consumption, which limits the low-power application scenarios of the navigation chip.

[0003] The existing acquisition engine implementation has certain limitations for navigation chip applications, such as Figure 1 As shown in the figure, in the clock architecture of the existing Beidou navigation chip, the acquisition engine and the tracking engine use the same system clock. The working frequency of the acquisition engine is the same as that of the tracking engine; for the scene where the tracking performance is high and the tracking engine works at high frequency, the acquisition engine is passively working at high frequency and cannot be independently reduced in frequency, resulting in an increase in power consumption; in addition, the sampling buffer of the acquisition engine is relatively large, which further increases the chip power consumption. If the power consumption is simply reduced by reducing the system frequency, it cannot meet the high-performance application scenario.

[0004] Therefore, it is necessary to provide a new low-power acquisition method and system applied to a Beidou navigation chip. SUMMARY

[0005] The main purpose of the present application is to provide a new low-power acquisition method and system applied to a Beidou navigation chip to solve the above technical problems, to realize the self-adaptive working clock of the acquisition engine to solve the contradiction between the high-performance application scenario and the low-power application scenario, to realize the flexible switching of the two application scenarios, and to reduce the area through shared buffer and further reduce the power consumption.

[0006] To achieve the above object, the application provides a low-power acquisition system applied to a Beidou navigation chip, comprising an acquisition engine module, a tracking engine module and a system clock circuit module, the low-power acquisition system further comprises an N frequency divider arranged between the acquisition engine module and the system clock circuit module; the acquisition engine module comprises a first sampling buffer unit, an acquisition calculation unit and a preprocessing unit, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of a system clock of the system clock circuit module is used, the preprocessing unit is connected with the system clock circuit module, and a system clock of the system clock circuit module is used; the tracking engine module comprises a tracking calculation unit and a second sampling buffer unit, and the tracking calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module.

[0007] Further, the maximum bit width of the first sampling buffer unit is the bit number of a single sampling data multiplied by the N value of the N frequency divider.

[0008] Further, the second sampling buffer unit is used for buffering the cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; and all or part of the cache space of the second sampling buffer unit is used for buffering the cache data of the acquisition engine module when the Beidou navigation chip is in an acquisition state.

[0009] The application further provides a low-power acquisition method applied to the low-power acquisition system applied to the Beidou navigation chip, comprising the following steps:

[0010] When the Beidou navigation chip is in a tracking state, the acquisition engine module and the tracking engine module are simultaneously controlled to use the system clock of the system clock circuit module;

[0011] When the Beidou navigation chip is in an acquisition state, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, and a frequency-divided clock obtained by N frequency division of a system clock of the system clock circuit module is used.

[0012] Further, the method further comprises the following step: when the acquisition state is switched to the tracking state, the bit width of the first sampling buffer unit is set to be equal to the bit number of a single sampling data multiplied by the N value of the N frequency divider according to the current N frequency division value of the N frequency divider, so as to perform delay reading on the data generated by the acquisition calculation unit.

[0013] The application of the low-power consumption acquisition system for the Beidou navigation chip in the technical solution of the application comprises an acquisition engine module, a tracking engine module and a system clock circuit module, the low-power consumption acquisition system further comprises an N frequency divider arranged between the acquisition engine module and the system clock circuit module; the acquisition engine module comprises a first sampling buffer unit, an acquisition calculation unit and a preprocessing unit, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of a system clock of the system clock circuit module is used, the preprocessing unit is connected with the system clock circuit module, a system clock of the system clock circuit module is used; the tracking engine module comprises a tracking calculation unit and a second sampling buffer unit, the tracking calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module. When the Beidou navigation chip is in a tracking state, the acquisition engine module and the tracking engine module are controlled to use the system clock of the system clock circuit module simultaneously; when the Beidou navigation chip is in an acquisition state, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of the system clock of the system clock circuit module is used. The application solves the contradiction between the high-performance application scenario and the low-power consumption application scenario by realizing the self-adaptive working clock of the acquisition engine, realizes the flexible switching of the two application scenarios, reduces the area through the shared buffer and further reduces the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is a clock architecture diagram of the acquisition system for the Beidou navigation chip in the prior art;

[0015] Figure 2 It is a clock architecture diagram of the low-power consumption acquisition system for the Beidou navigation chip in an embodiment of the application;

[0016] The object implementation, functional features and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0017] It should be understood that the specific embodiments described herein are merely intended to explain the application, and are not intended to limit the application.

[0018] In the following description, the suffixes such as "module", "part" or "unit" used for an element are merely used to facilitate explanation of the application, and have no specific meaning by themselves. Therefore, "module", "part" or "unit" can be mixedly used.

[0019] Please refer to Figure 2To achieve the above object, the application provides a low-power acquisition system applied to a Beidou navigation chip, which comprises an acquisition engine module, a tracking engine module and a system clock circuit module, further comprises an N frequency divider arranged between the acquisition engine module and the system clock circuit module; the acquisition engine module comprises a first sampling buffer unit, an acquisition calculation unit and a preprocessing unit, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of a system clock of the system clock circuit module is used, the preprocessing unit is connected with the system clock circuit module, and a system clock of the system clock circuit module is used; the tracking engine module comprises a tracking calculation unit and a second sampling buffer unit, and the tracking calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module.

[0020] Specifically, the preprocessing unit of the acquisition engine module uses the same clock as the tracking engine module, that is, the system clock, and the first sampling buffer unit and all the acquisition calculation units of the acquisition engine module use the clock obtained by N frequency division of the system clock. Selecting different N can make the acquisition engine work at different low-frequency clocks, so that flexible configuration can be realized according to the power consumption application scene.

[0021] Further, the maximum bit width of the first sampling buffer unit is the number of bits of a single sampling data multiplied by the N value of the N frequency divider.

[0022] Specifically, first, for adaptive frequency division ratio, the same address caches multiple sampling data; however, the bit width of each address is not the number of single sampling data multiplied by N, because the supportable NSHI 1-15 is variable, so the number of sampling stored in each address is fixed, which can meet the processing under 15 frequency division.

[0023] Specifically, the acquisition engine module supports the range of N frequency division in the clock architecture diagram is 1-15, and the acquisition engine module does not perceive the frequency division ratio, and can realize the acquisition function by adaptive 1-15 frequency division. First, the clock of sampling is a high-frequency clock, and the internal processing clock of the acquisition engine is N frequency division of the input sampling clock, N=1-15; second, a plurality of samplings are spliced together (such as 64 samplings) by the input sampling clock and are latched, and then written into the cache working at the N frequency division clock after the bit width of the cache is reached, so as to realize adaptive frequency division; in addition, there is a clock domain conversion processing of control signal.

[0024] The capture and tracking require that the sampling point data used by the two engines be aligned, so the clock used by the preprocessing unit in the capture engine module is the same as the clock of the tracking engine module, so that the two can align the sampling point data when capturing and tracking, and correctly complete the function of tracking. Specifically, first, the preprocessing unit is an internal function of the capture engine, and also works when capturing alone; second, in a stable tracking state, the capture engine can be turned off, and turned on again when capturing is needed again; third, after the capture engine completes the capture, the code phase and frequency information are transmitted to the tracking engine to start tracking calculation; fourth, the capture engine and the tracking engine use the same sampling, so the capture engine transmits the sampling count information to the tracking engine, which is implemented in the preprocessing unit, so in order to align the sampling positions of the capture and tracking engines, the preprocessing unit needs to use the same clock as the tracking engine.

[0025] The other parts of the capture engine module, including the sampling buffer and capture calculation, use the divided clock. Thus, the problem of adaptive storage of the preprocessing unit and the sampling buffer unit in the clock division ratio of 1-15 needs to be solved. The present application realizes the clock conversion before the preprocessing unit and the first sampling buffer unit by setting the appropriate bit width of the sampling buffer, which can store multiple sampling data at the same address, and by accumulating multiple sampling data before writing into the sampling buffer, and can adapt to different clock division ratios.

[0026] Further, the second sampling buffer unit is used to buffer the cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; and the second sampling buffer unit is used to buffer the cache data of the capture engine module in all or part of the cache space when the Beidou navigation chip is in a capture state.

[0027] The capture engine module and the tracking engine module both need to cache a large amount of sampling data to realize respective functions. Considering that the cache of the tracking engine module is not used in real time, especially not completely used before tracking, a part of the cache of the tracking engine module can be shared for the capture engine module, so that the sampling cache size of the capture engine can be reduced, and power consumption is reduced. Since the capture engine module and the tracking engine module work at different clock frequencies, clock conversion processing is needed. When the shared cache is enabled, the capture engine module writes sampling points into the shared cache through a preprocessing unit, and the working frequencies of the two are the same, so special processing is not needed. The calculation processing unit of the capture engine module works at an N-divided clock of the tracking engine module, so clock conversion is needed when the capture engine module reads sampling data from the shared cache. The method adopted by the application is to use the low-frequency clock of the capture engine to generate a reading control signal, and register the read data in the low-frequency clock domain to match the delay required by the capture engine, so as to realize clock domain conversion. Specifically, first, capture is performed before tracking. During capture, the tracking engine is not started, so the capture can use part of the cache of the tracking engine to store more samples when needed, that is, cache sharing; second, the code phase and frequency information of the capture result are transmitted to the tracking engine after capture is completed; third, the tracking engine performs tracking calculation according to the information provided by the capture engine; fourth, when the tracking engine changes from a stable tracking state to a lock loss state, the capture engine needs to be started to recapture, and tracking is performed again after capture is successful.

[0028] The application further provides a low-power consumption capture method applied to the low-power consumption capture system applied to the Beidou navigation chip, and the method comprises the following steps:

[0029] When the Beidou navigation chip is in a tracking state, the capture engine module and the tracking engine module are controlled to use the system clock of the system clock circuit module at the same time.

[0030] When the Beidou navigation chip is in a capture state, the first sampling cache unit and the capture calculation unit are connected with the N divider, and the system clock of the system clock circuit module is used after N division to obtain a divided clock.

[0031] Further, the method further comprises the following step: when the capture state is switched to the tracking state, the bit width of the first sampling cache unit is set to be equal to the bit number of a single sampling data multiplied by the N value of the N divider according to the current N division value of the N divider, so as to perform delay reading on the data generated by the capture calculation unit.

[0032] The application of the low-power consumption acquisition system applied to the Beidou navigation chip in the technical scheme of the application comprises an acquisition engine module, a tracking engine module and a system clock circuit module, the low-power consumption acquisition system further comprises an N frequency divider arranged between the acquisition engine module and the system clock circuit module; the acquisition engine module comprises a first sampling buffer unit, an acquisition calculation unit and a preprocessing unit, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of a system clock of the system clock circuit module is used, the preprocessing unit is connected with the system clock circuit module, a system clock of the system clock circuit module is used; the tracking engine module comprises a tracking calculation unit and a second sampling buffer unit, the tracking calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module. When the Beidou navigation chip is in a tracking state, the acquisition engine module and the tracking engine module are controlled to use the system clock of the system clock circuit module simultaneously; when the Beidou navigation chip is in an acquisition state, the first sampling buffer unit and the acquisition calculation unit are connected with the N frequency divider, a frequency-divided clock obtained by N frequency division of the system clock of the system clock circuit module is used. The application solves the contradiction between the high-performance application scenario and the low-power consumption application scenario by realizing the self-adaptive working clock of the acquisition engine, realizes the flexible switching of the two application scenarios, reduces the area by sharing the buffer and further reduces the power consumption.

[0033] In the description of the present specification, the description of the terms "one embodiment", "another embodiment", "other embodiments", or "first embodiment to Xth embodiment" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, method steps or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0034] The above embodiment numbers of the present application are only for description, not representing the advantages or disadvantages of the embodiments.

[0035] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A low power consumption acquisition system applied to a Beidou navigation chip, comprising an acquisition engine module, a tracking engine module and a system clock circuit module, characterized in that, The low-power consumption capture system further comprises an N frequency divider arranged between the capture engine module and the system clock circuit module; the capture engine module comprises a first sampling buffer unit, a capture calculation unit and a preprocessing unit, the first sampling buffer unit and the capture calculation unit are connected with the N frequency divider and use a divided frequency clock obtained by N dividing a system clock of the system clock circuit module, and the preprocessing unit is connected with the system clock circuit module and uses the system clock of the system clock circuit module; The tracking engine module comprises a tracking calculation unit and a second sampling buffer unit, and the tracking calculation unit and the second sampling buffer unit are connected with the system clock of the system clock circuit module; The maximum bit width of the first sampling buffer unit is the number of bits of a single sampling data multiplied by the N value of the N frequency divider; The second sampling buffer unit is used for buffering the cache data of the tracking engine module when the Beidou navigation chip is in a tracking state; When the Beidou navigation chip is in a capture state, all or part of the cache space of the second sampling buffer unit is used for buffering the cache data of the capture engine module.

2. A low-power consumption capturing method for the low-power consumption capturing system applied to the Beidou navigation chip according to claim 1, characterized in that, The method comprises the steps of: When the Beidou navigation chip is in a tracking state, the capture engine module and the tracking engine module are controlled to simultaneously use the system clock of the system clock circuit module; When the Beidou navigation chip is in a capture state, the first sampling buffer unit and the capture calculation unit are connected with the N frequency divider and use a divided frequency clock obtained by N dividing a system clock of the system clock circuit module.

3. The low-power acquisition method of claim 2, wherein, The method further comprises the step of: when the capture state is switched to the tracking state, the bit width of the first sampling buffer unit is set to be equal to the number of bits of a single sampling data multiplied by the N value of the N frequency divider according to the current N dividing value of the N frequency divider, so as to perform delay reading on the data generated by the capture calculation unit.

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