Data processing method, related apparatus and computer readable storage medium

Abstract

The application provides a data processing method, related devices and a computer readable storage medium. The method is applied to a data processing device, which comprises a system on chip and a network port. A DMA and a target cache unit are arranged in the system on chip. A receiving FIFO is arranged in the network port. The method comprises: when a preset overflow risk condition is triggered, adjusting the state of a register contained in the system on chip to execute a processing strategy matched with the state of the register; wherein after the state of a first register is adjusted to a first state, the network port is controlled to enable its own flow control strategy; after the state of a second register is adjusted to a second state, the DMA is instructed to write data output by the receiving FIFO into the target cache unit; and after the state of a third register is adjusted to a third state, the scheduling priority of a DMA bus of the DMA is adjusted to the highest priority. The application can reduce the risk of overflow of the receiving FIFO and reduce the packet loss probability.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and more specifically, to a data processing method, related apparatus, and computer-readable storage medium. Background Technology

[0002] like Figure 1 As shown, in actual traffic forwarding, data enters the receive FIFO (First Input First Output) inside the network interface (e.g., GMAC (Gigabit Media Access Control) port) for storage. Data in the receive FIFO, according to the FIFO principle, is directly sent to the CPU (Central Processing Unit) via DMA (Direct Memory Access); the CPU then processes the data. After processing, the CPU forwards the data to the transmit FIFO of the GMAC port for storage. The transmit FIFO then sends the data out sequentially according to the FIFO principle.

[0003] During this process, if there is excessive or sudden data flow, the receiving FIFO may overflow, leading to packet loss. Summary of the Invention

[0004] The purpose of this application is to provide a data processing method, related apparatus, and computer-readable storage medium to reduce the risk of receiving FIFO overflow and reduce the probability of packet loss.

[0005] This application provides a data processing method applied in a data processing device, the data processing device including a system-on-a-chip (SoC) and a network interface; a DMA and a target cache unit are provided in the SoC; a receive FIFO is provided in the network interface; the method includes:

[0006] When a preset overflow risk condition is triggered, the state of the registers included in the on-chip system is adjusted to execute a processing strategy that matches the state of the registers. Specifically, after the state of the first register is adjusted to the first state, the network port is controlled to enable its own flow control strategy to limit the amount of data arriving at the receive FIFO. After the state of the second register is adjusted to the second state, the DMA is instructed to write the data output from the receive FIFO into the target buffer unit. After the state of the third register is adjusted to the third state, the scheduling priority of the DMA bus is adjusted to the highest priority.

[0007] In the above implementation process, by adjusting the state of the registers included in the on-chip system when a preset overflow risk condition is triggered, the on-chip system can execute different processing strategies through adjustments to the states of different registers. This allows for flexible selection and free combination of different processing strategies, thereby achieving more flexible flow management. Whether it's controlling the network port to enable its own flow control strategy to limit the amount of data reaching the receive FIFO, instructing the DMA to write the data output from the receive FIFO into the target buffer unit, or adjusting the scheduling priority of the DMA bus to the highest priority, all these measures can reduce the risk of receive FIFO overflow, thereby reducing the probability of packet loss. Specifically, by enabling its own flow control strategy on the control network port to limit the amount of data reaching the receive FIFO, the amount of data received by the receive FIFO per unit time will decrease, thereby reducing the risk of receive FIFO overflow and the probability of packet loss. When instructing the DMA to write the data output from the receive FIFO into the target cache unit, since the target cache unit is located on-chip, the processor core will retrieve data from the target cache unit faster than it can retrieve data from memory, thus improving the data output efficiency of the receive FIFO. In this way, the risk of receive FIFO overflow can be reduced, and the probability of packet loss can be reduced. When the scheduling priority of the DMA bus is adjusted to the highest priority, since data transmission in the on-chip system is implemented through the bus, the data output from the receive FIFO transmitted via the DMA bus can be transmitted preferentially, thereby improving the data output efficiency of the receive FIFO. In this way, the risk of receive FIFO overflow can be reduced, and the probability of packet loss can be reduced. Furthermore, when the preset overflow risk condition is triggered, adjusting the state of any one or more of the first, second, and third registers in the on-chip system can reduce the risk of receiving FIFO overflow and decrease the probability of packet loss. Moreover, the more processing strategies executed, the better the effect of reducing the risk of receiving FIFO overflow and decreasing the probability of packet loss.

[0008] Furthermore, the target cache unit is a level 3 cache within the on-chip system.

[0009] It should be understood that in practical applications, on-chip systems typically have a Level 1 cache (L1 cache), a Level 2 cache (L2 cache), and a Level 3 cache (L3 cache). The processor core retrieves data from the L1, L2, and L3 caches faster than from main memory, with L1 cache being the fastest, followed by L2 and L3 caches at speeds between L1 and main memory. Therefore, whether it's L1, L2, or L3 cache, as a target cache unit, it can improve the processor core's efficiency in retrieving data from the receive FIFO, thereby improving the receive FIFO's output efficiency, reducing the risk of receive FIFO overflow, and lowering the probability of packet loss. However, considering that L1 cache typically needs to store important instructions and is structurally limited, its capacity cannot be too large, usually only 32KB to 256KB; while L2 cache can be larger than L1 cache, it is still typically only 256KB to 1MB; and L3 cache, compared to L1 and L2 cache, can be much larger and usually does not need to store instructions. Therefore, in the above implementation, by using the on-chip system's three-level cache as the target cache unit, a larger data storage capacity can be provided to accommodate the data received from the FIFO while minimizing the impact on the on-chip system's functionality, thereby avoiding the problem of data not being able to be written normally due to capacity limitations.

[0010] Furthermore, the control of the network port to enable its own traffic control strategy includes: determining the communication mode between the network port and the data source; when the communication mode is half-duplex, controlling the network port to send a suppression signal to the data source to reduce the data transmission speed of the data source; when the communication mode is full-duplex, controlling the network port to send a pause signal to the data source to pause data transmission of the data source.

[0011] In the above implementation process, by sending a suppression signal to the data source in half-duplex mode to make the data source reduce the data transmission speed, and by sending a pause signal to the data source in full-duplex mode to make the data source pause data transmission, the amount of data that the receiving FIFO needs to receive per unit time can be easily controlled, thereby reducing the risk of receiving FIFO overflow and reducing the probability of packet loss.

[0012] Furthermore, the overflow risk conditions include at least one of the following: the amount of data received by the receiving FIFO per unit time is greater than a preset data amount threshold; the receiving FIFO has overflowed; the on-chip system receives a notification indicating that packet loss has occurred.

[0013] In the above implementation process, when the amount of data received by the receiving FIFO per unit time is greater than the preset data amount threshold, or the receiving FIFO has overflowed, or the on-chip system receives a notification message indicating that there is packet loss, it indicates that there is or has occurred a risk. Therefore, the following contents are used as overflow risk conditions, and the processing strategy can be activated in time to deal with them in order to reduce the risk of receiving FIFO overflow and reduce the probability of packet loss as soon as possible.

[0014] Furthermore, the storage space size of the receiving FIFO is less than the target threshold.

[0015] It should be understood that when the storage space of the receive FIFO is large, it can usually meet the traffic forwarding needs of most application scenarios, and the receive FIFO overflow will generally not occur. The technical solution described in this application can be applied to scenarios where the storage space of the receive FIFO is small (i.e., when the storage space of the receive FIFO is less than the target threshold) to avoid potential overflow risks.

[0016] This application embodiment also provides a data processing apparatus, including a system-on-a-chip (SoC) and a network port; the SoC includes a processor core, a DMA, and a target cache unit with communication connections; the network port includes a receive FIFO; wherein, the processor core is used to adjust the state of registers included in the SoC when a preset overflow risk condition is triggered, so as to execute a processing strategy matching the state of the registers; wherein:

[0017] After the state of the first register is adjusted to the first state, the processor core controls the network port to enable its own flow control policy to limit the amount of data arriving at the receive FIFO; after the state of the second register is adjusted to the second state, the processor core instructs the DMA to write the data output from the receive FIFO into the target buffer unit; after the state of the third register is adjusted to the third state, the processor core adjusts the scheduling priority of the DMA bus of the DMA to the highest priority.

[0018] The data processing apparatus provided in this application embodiment, when a preset overflow risk condition is triggered, can reduce the probability of overflow risk in the receive FIFO and reduce the packet loss probability regardless of which register(s) among the first, second, and third registers included in the on-chip system are adjusted. Furthermore, the more processing strategies executed, the better the effect of reducing the risk of receive FIFO overflow and the packet loss probability. Moreover, the data processing apparatus provided in this application embodiment can flexibly select and freely combine different processing strategies, thereby achieving more flexible traffic management.

[0019] Furthermore, the target cache unit is a level 3 cache within the on-chip system.

[0020] Furthermore, the overflow risk conditions include at least one of the following: the amount of data received by the receiving FIFO per unit time is greater than a preset data amount threshold; the receiving FIFO has overflowed; the on-chip system receives a notification indicating that packet loss has occurred.

[0021] This application also provides a system-on-a-chip (SoC) having a processor core, a DMA controller, and a target cache unit that are communicatively connected within the SoC; the SoC can communicate with a network port equipped with a receiving FIFO; the processor core is used to execute one or more pre-stored programs to perform data processing methods as described above.

[0022] This application also provides a computer-readable storage medium storing one or more programs, which are executed by a processor core to perform any of the above-described data processing methods. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a data processing device in the prior art;

[0025] Figure 2 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a data processing system provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of a DMA structure provided in an embodiment of this application;

[0028] Figure 5 A result diagram of a test example provided in an embodiment of this application;

[0029] Figure 6 This is a flowchart illustrating a data processing method provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0031] To reduce the risk of FIFO overflow and decrease the probability of packet loss, this application provides a data processing device. See also... Figure 2 As shown, Figure 2 This is a schematic diagram of the basic structure of the data processing device provided in the embodiments of this application, including a system-on-a-chip (SoC) and a network port. The SoC includes a processor core, a DMA, and a target cache unit for communication; the network port includes a receive FIFO; wherein:

[0032] The processor core is used to adjust the state of the registers included in the on-chip system when a preset overflow risk condition is triggered, in order to execute a processing strategy that matches the state of the registers. Specifically:

[0033] After the state of the first register is adjusted to the first state, the processor core control network port enables its own flow control strategy to limit the amount of data arriving at the receive FIFO;

[0034] After the state of the second register is adjusted to the second state, the processor core instructs the DMA to write the data output by the receive FIFO into the target cache unit;

[0035] After the state of the third register is adjusted to the third state, the processor core adjusts the scheduling priority of the DMA bus to the highest priority.

[0036] It should be understood that in the embodiments of this application, the system-on-a-chip can be a processor, such as a CPU, MPU (Microprocessor Unit), MCU (Microcontroller Unit), etc., which has one or more processor cores and caches such as DMA, registers, L1 cache, L2 cache, L3 cache, etc. (It should be understood that L1 cache, L2 cache, L3 cache, etc. can be located within the processor core, but in some practical applications, L2 cache and L3 cache can also be located outside the processor core, and this embodiment of the application does not limit this). It can also have memory.

[0037] It should also be understood that processor cores typically contain a large number of registers. Registers are high-speed storage components with limited storage capacity, used to temporarily store instructions, data, and addresses. Because different instructions are stored in registers, different registers can be used to implement different functions. Thus, by adjusting the state (i.e., data or instructions) within a register, the processor core can be triggered to execute the function corresponding to that register, such as enabling network interface flow control policies.

[0038] In this embodiment, the first register is a register related to the network port's flow control policy. When the state of the first register is adjusted to the first state, the processor core can control the network port to enable its own flow control policy to limit the amount of data arriving at the receive FIFO. Conversely, when the state of the first register is the default state, the processor core will not control the network port to enable its own flow control policy.

[0039] Similarly, the second register is related to the storage control of the target cache unit. When the state of the second register is adjusted to the second state, the processor core can instruct the DMA to write the data output from the receive FIFO into the target cache unit. Conversely, when the state of the second register is in the default state, the DMA will normally write the data output from the receive FIFO into memory.

[0040] Similarly, the third register is related to the scheduling priority of the DMA bus. When the state of the third register is adjusted to the third state, the processor core adjusts the scheduling priority of the DMA bus to the highest priority.

[0041] Based on the aforementioned data processing device, when a preset overflow risk condition is triggered, the state of the registers contained in the on-chip system can be adjusted. By adjusting the state of different registers, the on-chip system can execute different processing strategies, thereby enabling flexible selection and free combination of different processing strategies, thus achieving more flexible flow management.

[0042] Whether by adjusting the state of the first register to control the network interface to enable its own flow control strategy and limit the amount of data reaching the receive FIFO, or by adjusting the state of the second register to instruct the DMA to write the data output from the receive FIFO into the target buffer unit, or by adjusting the state of the third register to adjust the scheduling priority of the DMA bus to the highest priority, the risk of receive FIFO overflow can be reduced, thereby reducing the probability of packet loss.

[0043] Specifically, after the processor core controls the network port to enable its own flow control strategy to limit the amount of data reaching the receive FIFO, the amount of data received by the receive FIFO per unit time will decrease, thereby reducing the risk of receive FIFO overflow and reducing the probability of packet loss.

[0044] When the processor core instructs the DMA to write the data output from the receive FIFO into the target cache unit, since the target cache unit is located on-chip, the processor core can retrieve data from the target cache unit at a higher speed than it can retrieve data from memory. This can improve the data output efficiency of the receive FIFO, reduce the risk of receive FIFO overflow, and lower the probability of packet loss.

[0045] When the processor core adjusts the scheduling priority of the DMA bus to the highest priority, since data transmission in the on-chip system is all implemented through the bus, the data output from the receive FIFO transmitted through the DMA bus can be transmitted first, thereby improving the data output efficiency of the receive FIFO and reducing the risk of receive FIFO overflow and the probability of packet loss.

[0046] Based on this, when the preset overflow risk condition is triggered, the above-mentioned data processing device can reduce the risk of receiving FIFO overflow and reduce the probability of packet loss by adjusting the state of any one or more of the first, second and third registers included in the on-chip system, and the more processing strategies are executed, the better the effect of reducing the risk of receiving FIFO overflow and reducing the probability of packet loss.

[0047] In one optional embodiment of this application, the spillover risk condition includes at least one of the following:

[0048] The amount of data received by the receiving FIFO per unit time exceeds the preset data threshold; the receiving FIFO has overflowed; the on-chip system receives a notification indicating packet loss.

[0049] It should be understood that, in this embodiment, the data processing device can add a counter at the entrance of the receiving FIFO to count the amount of data received by the receiving FIFO per unit time, and transmit the count to the processor core for judgment, determining that the amount of data received by the receiving FIFO per unit time is greater than a preset data amount threshold. The preset data amount threshold can be set by the engineer based on the capacity of the receiving FIFO.

[0050] It should be understood that, in this embodiment, the data processing device may also add a flow monitoring device at the inlet of the receiving FIFO to detect whether the receiving FIFO has overflowed or whether packet loss has occurred. If so, the processor core can be notified or an alarm can be triggered according to a preset method. The preset method includes, but is not limited to, sending alarm information to a preset contact address, emitting an alarm sound through a sound-emitting device, or emitting a preset warning light through a light-emitting component.

[0051] In one feasible implementation of this application, when a preset overflow risk condition is triggered, an engineer can manually adjust the state of at least one of the first register, the second register, and the third register so that the processor core executes the corresponding processing strategy.

[0052] In another feasible embodiment of this application, when a preset overflow risk condition is triggered, the processor core or other control components of the on-chip system can load a pre-stored register state into the register corresponding to the selected processing strategy according to a preset processing strategy selection method, thereby triggering the processor core to execute a processing strategy that matches the state of the register. The processing strategies include the following three types:

[0053] The first processing strategy: The processor core controls the network port to enable its own flow control strategy to limit the amount of data arriving at the receive FIFO. When selecting the first processing strategy, the state of the first register needs to be adjusted to the first state.

[0054] The second processing strategy: The processor core instructs the DMA to write the data output from the receive FIFO into the target cache unit. When selecting the second processing strategy, the state of the second register needs to be adjusted to the second state.

[0055] The third processing strategy: The processor core adjusts the scheduling priority of the DMA bus to the highest priority. When selecting the third processing strategy, the state of the third register needs to be adjusted to the third state.

[0056] For example, in the above feasible implementations, the processing strategy can be selected in the following ways:

[0057] Method 1: When a preset overflow risk condition is triggered, the processor core or other control components of the on-chip system adjust the state of the first register to the first state, the state of the second register to the second state, and the state of the third register to the third state, thereby simultaneously employing three different processing strategies. That is, the preset processing strategy selection method can be: always employing the three different processing strategies described above in the embodiments of this application simultaneously.

[0058] Method 2: When a preset overflow risk condition is triggered, the processor core or other control components of the on-chip system determine the overflow risk level of the receive FIFO based on the status of the receive FIFO recorded in the FIFO status register, or based on the amount of data received by the receive FIFO per unit time. Then, at different overflow risk levels, the following operations are performed:

[0059] When the overflow risk level of the received FIFO is low, select one of the three processing strategies and modify the state of the register corresponding to the selected processing strategy.

[0060] When the overflow risk level of the received FIFO is medium, two processing strategies are selected from the three processing strategies, and the state of the registers corresponding to the two selected processing strategies is modified.

[0061] When the overflow risk level of the receive FIFO is high, three processing strategies are selected and processed simultaneously. At this time, the state of the first register is adjusted to the first state, the state of the second register is adjusted to the second state, and the state of the third register is adjusted to the third state.

[0062] In this way, by configuring different levels of processing capabilities for different overflow risk levels of the receive FIFO, the problem of packet loss caused by receive FIFO overflow can be solved as much as possible while reducing the modification of the original logic of the on-chip system.

[0063] It should be noted that in practical applications, the on-chip system typically includes a FIFO status register for recording the state of the receive FIFO. To determine the overflow risk level of the receive FIFO based on its state recorded in the FIFO status register, this embodiment pre-sets a correspondence between different receive FIFO state values ​​and their overflow risk levels. Based on this correspondence and the received FIFO state read from the FIFO status register, the overflow risk level of the receive FIFO can be determined.

[0064] Similarly, in order to determine the overflow risk level of the receiving FIFO based on the detected amount of data received by the receiving FIFO per unit time, in this embodiment of the application, a correspondence between different data volumes and the overflow risk level of the receiving FIFO can be pre-set. Based on this correspondence and the detected amount of data received by the receiving FIFO per unit time, the overflow risk level of the receiving FIFO can be determined. It should be understood that in the pre-set correspondence between different data volumes and the overflow risk level of the receiving FIFO, the higher the overflow risk level, the larger the corresponding data volume.

[0065] It should also be noted that, based on the above method two, the processing strategy selection method can be further configured, including: when the received FIFO overflow risk level is low or medium, first determine whether the data source is a preset data source that cannot request data delay.

[0066] When the FIFO overflow risk level is low, if the data source is a preset data source for which data delay cannot be requested, the state can be adjusted by selecting either the second or third register. If the data source is not a preset data source for which data delay cannot be requested, the state can be adjusted randomly by selecting either the first, second, or third register, or the state of the first register can be directly adjusted to the first state.

[0067] Correspondingly, when the FIFO overflow risk level is medium, if the data source is a preset data source for which data delay cannot be requested, the state of the second register is adjusted to the second state, and the state of the third register is adjusted to the third state. If the data source is not a preset data source for which data delay cannot be requested, two processing strategies are selected from the three processing strategies, and the states of the registers corresponding to the two selected processing strategies are modified.

[0068] In this way, for data sources that cannot be required to delay data transmission, their data transmission will no longer be controlled, thus avoiding any negative impact on business operations.

[0069] It should be understood that in the above method, a whitelist is pre-set in the processing device. The whitelist contains data sources that cannot be required to delay data transmission, thereby ensuring that the above method can be implemented normally.

[0070] It should also be understood that the processing strategy selection methods described above are only a few optional implementation methods provided in the embodiments of this application, and are not intended to limit the embodiments of this application.

[0071] In one feasible embodiment of this application, after the state of the first register is adjusted to the first state, the way in which the processor core controls the network interface to enable its own flow control strategy may include:

[0072] The processor core determines the communication method between the network port and the data source;

[0073] When the communication mode is half-duplex, the processor core controls the network port to send a suppression signal (such as a jamming signal) to the data source to reduce the data transmission speed of the data source.

[0074] When the communication mode is full-duplex, the processor core control network port sends a pause signal (e.g., a "pause" frame) to the data source to cause the data source to pause data transmission.

[0075] This allows for easy control over the amount of data that the receiving FIFO needs to receive per unit of time, thereby reducing the risk of receiving FIFO overflow and lowering the probability of packet loss.

[0076] Optionally, the network port in this embodiment may be, but is not limited to, a GMAC network port.

[0077] In one feasible embodiment of this application, after the state of the second register is adjusted to the second state, the processor core can instruct the DMA to write the data output from the received FIFO into the on-chip system's L3 cache. That is, the on-chip system's L3 cache can be used as the target cache unit.

[0078] It should be understood that while all three levels of cache—Level 1, Level 2, and Level 3—can improve the efficiency of the processor core in acquiring data from the receive FIFO when used as the target cache unit, thereby improving the data output efficiency of the receive FIFO, reducing the risk of receive FIFO overflow, and lowering the probability of packet loss, Level 1 cache is typically used to store important instructions and its capacity is limited by its structure, usually ranging from 32KB to 256KB. While Level 2 cache can be larger than Level 1, it is still typically only 256KB to 1MB. Level 3 cache, compared to Level 1 and Level 2 cache, can be much larger and usually does not need to store instructions. Therefore, using the on-chip system's Level 3 cache as the target cache unit allows for a larger data storage capacity to accommodate data from the receive FIFO while minimizing the impact on on-chip system functionality, thus avoiding data write failures due to capacity limitations.

[0079] It should also be understood that as caching technology continues to develop, if the size of the first-level cache and the second-level cache can be made larger in the future, then the first-level cache or the second-level cache can also be used as the target cache unit.

[0080] Furthermore, with the continuous development of computer technology, if other levels of cache are designed in addition to the L1, L2, and L3 caches, then as long as the processor core retrieves data from these other levels of cache faster than the processor core retrieves data from memory, these other levels of cache can also be used as target cache units. This application does not limit this.

[0081] In one feasible embodiment of this application, after the state of the third register is adjusted to the third state, the processor core may adjust the scheduling priority of the DMA bus of the DMA to the highest priority by coordinating with the bus matrix to adjust the scheduling priority of the DMA bus to the highest priority, so as to ensure that the DMA bus request is scheduled first.

[0082] It should be noted that, in an optional embodiment of this application, the storage space of the receiving FIFO should be smaller than the target threshold. This is because a larger receiving FIFO storage space is usually sufficient to meet the traffic forwarding requirements of the application scenario, without causing the receiving FIFO to overflow. Therefore, in this optional embodiment, the solution of this application is only adopted for data processing devices with a smaller receiving FIFO storage space (i.e., the receiving FIFO storage space is smaller than the target threshold). This eliminates the need to configure the solution of this application for every data processing device equipped with a receiving FIFO, thereby reducing the production cost of the data processing device.

[0083] It should be understood that the target threshold can be set by engineers based on statistics of the capacity of the receiving FIFO in various products in the industry, as well as whether there is a situation of receiving FIFO overflow.

[0084] To facilitate a further understanding of the solutions in the embodiments of this application, the following describes the data processing apparatus based on the foregoing description, using... Figure 3 The structure of the data system shown is used as an example to further illustrate this application.

[0085] like Figure 3 As shown, the data processing device mainly includes a system-on-a-chip (SoC) and a GMAC network port. The SoC includes a processor core (containing registers, cache, etc.), memory, and DMA. The GMAC network port has a receive FIFO and a transmit FIFO.

[0086] When the amount of data received by the receiving FIFO per unit time exceeds a preset data threshold, perform the following operations:

[0087] The state of the first register is adjusted to the first state by writing to the register via software code. At this point, the processor core senses this state change and implements backpressure through the following two methods:

[0088] In half-duplex mode, a jamming signal is sent to the data source via the GMAC network port to cause the data source to reduce the data transmission speed.

[0089] In full-duplex mode, a "pause" frame is sent to the data source via the GMAC network port to cause the data source to pause data transmission.

[0090] The state of the second register is adjusted to the second state by writing to the register using software code.

[0091] At this time, when the data output from the receive FIFO is sent to the processor core via DMA, the DMA writes the data into the L3 Cache to speed up the data copying speed of the processor core, thereby reducing the risk of receive FIFO overflow.

[0092] The state of the third register is adjusted to the third state by writing to the register using software code.

[0093] At this point, the processor core senses the change in state and coordinates with the bus matrix to adjust the scheduling priority of the DMA bus to the highest priority.

[0094] At this time, see Figure 4As shown, when the data from the receive FIFO is sent up, the DMA peripheral sends a DMA request to the DMA controller. Upon receiving the request, the DMA controller triggers DMA operation. The DMA controller obtains data from the AHB (Advanced High performance Bus, system bus) peripheral (connected to the receive FIFO to obtain the data output by the receive FIFO) and stores it in the DMA channel. The AHB is used to write the data collected by the peripheral into the L3 Cache via the DMA channel and the DMA bus (when the state of the second register is not adjusted to the second state, the AHB is used to write the data collected by the peripheral into the SRAM (Static Random-Access Memory) via the DMA channel and the DMA bus; the SRAM is the memory described in the embodiments of this application).

[0095] Based on the above implementation scheme, after adjusting the states of the first, second, and third registers, the actual hang-up test results can be obtained through actual testing, as follows: Figure 5 As shown, during the test, the data transmission from port 4 to port 5 was as follows: Port 4 sent packet 7153346546, and port 5 received packet 7153346546. The data transmission from port 5 to port 4 was as follows: Port 5 sent packet 7152575800, and port 4 received packet 7152575800. Clearly, no data loss was observed during the entire test. However, without adjusting the states of the first, second, and third registers, a certain degree of packet loss occurred in both transmissions from port 4 to port 5 and from port 5 to port 4, thus proving that the solution in this embodiment can successfully solve the packet loss problem caused by FIFO overflow.

[0096] Based on the same inventive concept, this application also provides a data processing method that can be applied to the processor core of the aforementioned data processing device, see below. Figure 6 As shown, it includes:

[0097] S601: When a preset overflow risk condition is triggered, adjust the state of the registers contained in the on-chip system to execute a processing strategy that matches the state of the register.

[0098] in:

[0099] After the state of the first register is adjusted to the first state, the network port is controlled to enable its own flow control policy to limit the amount of data arriving at the receive FIFO;

[0100] After the state of the second register is adjusted to the second state, the DMA is instructed to write the data output by the receive FIFO into the target buffer unit;

[0101] After the state of the third register is adjusted to the third state, the scheduling priority of the DMA bus of the DMA is adjusted to the highest priority.

[0102] It should be understood that in the above data processing method, the target cache unit can be implemented using an on-chip system-level three cache, but this is not a limitation.

[0103] It should be understood that, in the above data processing method, the process of controlling the network interface to enable its own traffic control policy may include:

[0104] Determine the communication method between the network port and the data source;

[0105] When the communication mode is half-duplex, the control network port sends a suppression signal to the data source to make the data source reduce the data transmission speed.

[0106] When the communication mode is full-duplex, the control network port sends a pause signal to the data source to cause the data source to pause data transmission.

[0107] It should be understood that, in the above data processing methods, the spillover risk conditions include at least one of the following:

[0108] The amount of data received by the FIFO per unit time is greater than a preset data volume threshold.

[0109] The receive FIFO has overflowed;

[0110] The on-chip system received a notification indicating that packet loss had occurred.

[0111] It should be understood that in the above data processing method, the storage space size of the receiving FIFO can be smaller than the target threshold.

[0112] It should be understood that, for the sake of brevity, some of the content described in the data processing device section will not be repeated in the method section, but the relevant content is still applicable in the method section.

[0113] Based on the same inventive concept, embodiments of this application also provide a system-on-a-chip (SoC), which includes a processor core, a DMA, and a target cache unit with communication connections. Wherein:

[0114] The on-chip system can communicate with a network port equipped with a receive FIFO. Specifically, the DMA can communicate with the network port via a bus. Furthermore, in addition to the receive FIFO, the network port can also be configured with a transmit FIFO. Moreover, the network port can be a GMAC port.

[0115] The processor core is used to execute one or more pre-stored programs to perform the aforementioned data processing methods.

[0116] It is understandable that the relevant program can be stored in the system-on-chip cache (such as L1 or L2 cache), or in the system-on-chip memory, or in other storage devices that can be accessed by the processor core.

[0117] It is understandable that the target cache unit, as mentioned above, can be, but is not limited to, a level 3 cache.

[0118] It is also understood that the system-on-a-chip may include more components, and this application embodiment does not impose any restrictions on this.

[0119] In the embodiments of this application, the system-on-chip may be a processor, such as a CPU, MPU (Microprocessor Unit), MCU (Microcontroller Unit), etc., but this is not a limitation.

[0120] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more programs are stored. These one or more programs can be executed by one or more processor cores to perform the above-described data processing method. Further details will not be elaborated here.

[0121] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. Furthermore, the communication connections discussed can be implemented through some communication interface, and can be electrical, mechanical, or other forms.

[0122] Furthermore, in the embodiments of this application, relational terms such as first and second are used only to distinguish one entity from another, and do not necessarily require or imply any such actual relationship or order between these entities.

[0123] In the embodiments of this application, "multiple" refers to two or more.

[0124] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A data processing method, characterized in that, The invention is applied in a data processing device, which includes a system-on-a-chip (SoC) and a network port; the SoC is equipped with a direct memory access controller (DMA) and a target cache unit. A receiving FIFO is set up in the network port; the method includes: When a preset overflow risk condition is triggered, the state of the registers included in the on-chip system is adjusted to execute a processing strategy that matches the state of the registers; wherein, After the state of the first register is adjusted to the first state, the network port is controlled to enable its own flow control policy to limit the amount of data arriving at the receive FIFO; After the state of the second register is adjusted to the second state, the DMA is instructed to write the data output by the receive FIFO into the target buffer unit; After the state of the third register is adjusted to the third state, the scheduling priority of the DMA bus of the DMA is adjusted to the highest priority.

2. The method as described in claim 1, characterized in that, The target cache unit is a level 3 cache within the on-chip system.

3. The method as described in claim 1, characterized in that, The control of the network interface to enable its own traffic control policy includes: Determine the communication method between the network port and the data source; When the communication mode is half-duplex, the network port is controlled to send a suppression signal to the data source so that the data source reduces the data transmission speed. When the communication mode is full-duplex, the network port is controlled to send a pause signal to the data source so that the data source pauses data transmission.

4. The method according to any one of claims 1-3, characterized in that, The spillover risk conditions include at least one of the following: The amount of data received by the receiving FIFO per unit time is greater than a preset data amount threshold. The receive FIFO has overflowed; The system-on-chip receives a notification indicating that packet loss has occurred.

5. The method as described in claim 4, characterized in that, The storage space size of the receiving FIFO is less than the target threshold.

6. A data processing apparatus, characterized in that, It includes a system-on-a-chip (SoC) and a network port; the SoC includes a processor core, a direct memory access controller (DMA), and a target cache unit for communication; the network port includes a receive FIFO; wherein, The processor core is used to adjust the state of the registers included in the on-chip system when a preset overflow risk condition is triggered, so as to execute a processing strategy that matches the state of the registers; wherein: After the state of the first register is adjusted to the first state, the processor core controls the network port to enable its own flow control policy to limit the amount of data arriving at the receive FIFO; After the state of the second register is adjusted to the second state, the processor core instructs the DMA to write the data output by the receive FIFO into the target cache unit; After the state of the third register is adjusted to the third state, the processor core adjusts the scheduling priority of the DMA bus of the DMA to the highest priority.

7. The data processing apparatus as described in claim 6, characterized in that, The target cache unit is a level 3 cache within the on-chip system.

8. The data processing apparatus as described in claim 6 or 7, characterized in that, The spillover risk conditions include at least one of the following: The amount of data received by the receiving FIFO per unit time is greater than a preset data amount threshold. The receive FIFO has overflowed; The system-on-chip receives a notification indicating that packet loss has occurred.

9. A system-on-a-chip, characterized in that, The system-on-a-chip is equipped with a processor core, DMA, and target cache unit that are connected for communication; the system-on-a-chip can communicate with a network port equipped with a receiving FIFO; The processor core is used to execute one or more pre-stored programs to perform the data processing method as described in any one of claims 1-5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which, when executed by a processor core, perform the data processing method as described in any one of claims 1-5.

Images