Method, device and equipment for determining switch downstream port of SR-IOV device and medium

Abstract

The application discloses a switch downstream port determination method and device for accessing an SR-IOV device, a device and a medium, and relates to the technical field of computers.The method comprises the following steps: determining a switch to which a plurality of downstream ports are assigned, and accessing an SR-IOV device for each downstream port; starting a server and enumerating the SR-IOV device through a basic input / output system, then recording the current number of downstream ports; determining the current number of bus numbers corresponding to the assignment based on the current number of downstream ports, and judging whether the current number of bus numbers exceeds the range that can be provided by a PCI-E slot; if not, changing the number of downstream ports and re-executing the steps of starting the server and enumerating the SR-IOV device through the basic input / output system until the current number of bus numbers reaches the threshold of the range that can be provided by the PCI-E slot, so as to obtain the target number of downstream ports.Through the technical scheme of the application, it can be ensured that the determined number of downstream ports can still be successfully enumerated and normally started by the server when all the SR-IOV devices are accessed.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for determining the downstream port of a switch connected to an SR-IOV device. Background Technology

[0002] PCI Express, or PCI-E for short, is an important branch of the computer bus. Numerous devices connect to computers using PCI-E. A single PCI-E card functions as a single device, such as a network card or graphics card. With technological advancements, the functionality of a single PCI-E physical card has become increasingly rich. Using ASIC (Application Specific Integrated Circuit) / FPGA (Field-Programmable Gate Array) or a combination of hardware and software, multiple levels of devices can be simulated on the PCI-E card. These simulated devices can be added and removed as needed during operation, resulting in a relatively complex device type and overall bus topology. For example... Figure 1 The diagram shows the PCI-E topology. The PCI-E bus architecture can be visualized as multiple sets of point-to-point interconnected components. It roughly consists of: a Root Complex (RC), multiple Endpoints (PCI-E devices), a Switch, and a PCI-E to PCI / PCI-X Bridge. The bus between these members is called PCIExpress. Figure 2 The diagram shows the internal structure of a PCI-E switch. The computer's PCI-E devices are organized into a tree structure through the switch. As can be seen, the switch expands the PCI-E ports. The port closest to the control panel (RC) is called the upstream port, and the other ports are called downstream ports. A switch has only one upstream port but can expand to several downstream ports. Downstream ports can directly connect to the endpoint or connect to the switch to expand even more PCI-E ports. In other words, what appears to be a single physical network card (NIC) can be configured by the server to allow the server to perceive multiple NICs in the PCI-E slot, as if a switch were connected to the slot, or even expanded to a higher level. Each device has multiple functions.

[0003] After the PCI-E card simulates a multi-level switch and multiple complex endpoints, if the host (server) is restarted, the bios (Basic Input Output System) will enumerate all the created endpoints during the restart process and assign a bus to each endpoint. When a normal device accesses the downstream, it only needs one bus number, but for SR-IOV devices, multiple bus numbers may be needed. Since the bios implementation is related to the specific manufacturer, in actual implementation, even if an SR-IOV device itself only needs one bus number, the bios may force to assign multiple bus numbers to the downstream. Therefore, it may not be able to start after accessing the device. For example, a slot only supports 34 bus numbers, when a 32-downstream switch is accessed on the slot, the bios enumeration stage needs 34 bus numbers, and the slot can meet the demand, and the system starts normally; when the switch accesses a non-SR-IOV device, it can also start normally; when the switch accesses an SR-IOV device, the bios reserves two bus numbers for the downstream of the accessed SR-IOV device, resulting in a total of 34+1 bus numbers, which exceeds the slot capacity, and the system cannot start normally. Currently, when there is an SR-IOV device accessing the downstream port, it is usually to check the bios source code to analyze the maximum number of switch downstreams that can be supported, but often the server bios source code is difficult to obtain, and it is also difficult to contact the bios developer to obtain information.

[0004] Therefore, how to provide a switch without causing system restart and crash after accessing an SR-IOV device, and support the PCI-E card to automatically detect the maximum switch downstream capability that can be supported after the system is equipped with an SR-IOV device and make further adaptive adjustment is a problem to be solved at present. SUMMARY

[0005] Therefore, how to provide a switch without causing system restart and crash after accessing an SR-IOV device, and support the PCI-E card to automatically detect the maximum switch downstream capability that can be supported after the system is equipped with an SR-IOV device and make further adaptive adjustment is a problem to be solved at present.

[0006] In a first aspect, the application discloses a method for determining a switch downstream port of an SR-IOV device, comprising:

[0007] determine a switch assigned with a plurality of downstream ports, and access an SR-IOV device for each of the downstream ports;

[0008] start a server and enumerate the SR-IOV device through a basic input output system, and then record a current downstream port quantity;

[0009] determine a current bus number quantity corresponding to the assignment based on the current downstream port quantity, and determine whether the current bus number quantity exceeds a range of a PCI-E slot available;

[0010] if the current bus number quantity does not exceed the range of the PCI-E slot available, change the downstream port quantity, and re-perform the step of starting the server and enumerating the SR-IOV device through the basic input output system by a preset restart mode until the current bus number quantity reaches a threshold of the range of the PCI-E slot available, to obtain a target downstream port quantity.

[0011] Optionally, the step of starting the server and enumerating the SR-IOV device through the basic input output system, and then recording the current downstream port quantity, comprises:

[0012] start the server and enumerate the SR-IOV device through a basic input output system, and then determine whether a current state is a downstream port quantity detection state through an Option Rom;

[0013] if the current state is the downstream port quantity detection state and the downstream port quantity is valid, record the current downstream port quantity;

[0014] correspondingly, the step of if the current bus number quantity does not exceed the range of the PCI-E slot available, changing the downstream port quantity, and re-performing the step of starting the server and enumerating the SR-IOV device through the basic input output system, comprises:

[0015] if the current bus number quantity does not exceed the range of the PCI-E slot available, change the downstream port quantity, and restart the server through the Option Rom, and then re-perform the step of enumerating the SR-IOV device through the basic input output system.

[0016] Optionally, the step of if the current state is the downstream port quantity detection state and the downstream port quantity is valid, comprises:

[0017] If the current number of downstream ports is in a probing state, and the current number of downstream ports corresponding to the current number of bus numbers allocated does not exceed the range of the PCI-E slot available, it is determined that the number of downstream ports is valid.

[0018] Optionally, if the current number of bus numbers does not exceed the range of the PCI-E slot available, the number of downstream ports is changed, including:

[0019] If the current number of bus numbers does not exceed the range of the PCI-E slot available, the number of downstream ports is changed using a preset convergence value determination method, and a preset threshold value to which the number of downstream ports converges is determined as the target number of downstream ports.

[0020] Optionally, before determining the switch allocated with a plurality of downstream ports and accessing the SR-IOV device for each of the downstream ports, further comprising:

[0021] Determine the current number of bus numbers allocated from the server in the current simulation state of the PCI-E card;

[0022] Correspondingly, the current number of bus numbers corresponding to the current number of downstream ports is determined based on the current number of downstream ports, and whether the current number of bus numbers exceeds the range of the PCI-E slot available is determined, including:

[0023] The current number of bus numbers corresponding to the current number of downstream ports is determined based on the current number of downstream ports, and whether the current number of bus numbers exceeds the number of bus numbers allocated is determined.

[0024] Optionally, the determination of whether the current number of bus numbers exceeds the range of the PCI-E slot available includes:

[0025] If the current number of bus numbers causes the server to start abnormally in the process of starting the server, it is determined that the current number of bus numbers exceeds the range of the PCI-E slot available;

[0026] If the current number of bus numbers does not cause the server to start abnormally in the process of starting the server, it is determined that the current number of bus numbers does not exceed the range of the PCI-E slot available.

[0027] In a second aspect, the application discloses a switch downstream port determination device for accessing an SR-IOV device, including:

[0028] The SR-IOV device access module is configured to determine a switch allocated with a plurality of downstream ports, and access an SR-IOV device for each of the downstream ports.

[0029] A current downstream port quantity recording module is configured to start a server and enumerate the SR-IOV device through a basic input / output system, and then record a current downstream port quantity;

[0030] A current bus number quantity judgment module is configured to determine a current bus number quantity corresponding to an allocation based on the current downstream port quantity, and judge whether the current bus number quantity exceeds a range that can be provided by a PCI-E slot;

[0031] A target downstream port quantity determination module is configured to, if the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, change the downstream port quantity, and re-execute the step of starting the server and enumerating the SR-IOV device through the basic input / output system by a preset restart mode until the current bus number quantity reaches a threshold of the range that can be provided by the PCI-E slot, so as to obtain a target downstream port quantity.

[0032] Optionally, the target downstream port quantity determination module is further configured to, if the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, change the downstream port quantity by using a preset convergence value determination method, and determine a preset threshold to which the downstream port quantity converges as the target downstream port quantity.

[0033] In a third aspect, the present application discloses an electronic device, which comprises a processor and a memory; wherein the memory is configured to store a computer program, and the computer program is loaded and executed by the processor to implement the switch downstream port determination method for accessing an SR-IOV device as described above.

[0034] In a fourth aspect, the present application discloses a computer readable storage medium configured to store a computer program; wherein the computer program is executed by a processor to implement the switch downstream port determination method for accessing an SR-IOV device as described above.

[0035] In the application, a switch assigned with a plurality of downstream ports is determined, and an SR-IOV device is accessed for each of the downstream ports; a server is started, and the SR-IOV device is enumerated through a basic input / output system, and then a current downstream port quantity is recorded; a current bus number quantity corresponding to the assignment is determined based on the current downstream port quantity, and it is judged whether the current bus number quantity exceeds a range that can be provided by a PCI-E slot; if the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, the downstream port quantity is changed, and the step of starting the server and enumerating the SR-IOV device through the basic input / output system is re-executed through a preset restart mode until the current bus number quantity reaches a threshold of the range that can be provided by the PCI-E slot, so as to obtain a target downstream port quantity. It can be seen that, when a virtual machine is provided by a PCI-E card, since the downstream port accessing the SR-IOV device can be assigned to a plurality of bus numbers, the SR-IOV device is accessed for each of the downstream ports, and the downstream port quantity is continuously detected, when the SR-IOV device is enumerated, the current bus number quantity reaches the threshold of the range that can be provided by the PCI-E slot, which indicates that the specification capability supported by the system is reached at this time. In this way, the maximum downstream port quantity that can be supported by the switch when the SR-IOV device is accessed is analyzed, and it can be ensured that whether a normal device only needing to be assigned with one bus number or the SR-IOV device that can be assigned with a plurality of bus numbers is accessed, the basic input / output system will not fail to restart, which is convenient for adaptation according to actual conditions, and on this basis, adaptive and other functions can be further developed. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0037] Figure 1 A PCI-E topology architecture diagram disclosed by the present application;

[0038] Figure 2 A PCI-E switch internal structure diagram disclosed by the present application;

[0039] Figure 3 A switch downstream port determination method flow chart of accessing an SR-IOV device disclosed by the present application;

[0040] Figure 4A specific switch downstream port determination method flow chart for accessing SR-IOV devices is disclosed in the present application;

[0041] Figure 5 A switch downstream port determination device structure schematic diagram for accessing SR-IOV devices is disclosed in the present application;

[0042] Figure 6 An electronic device structure diagram is disclosed in the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0044] Currently, only one bus number is needed when a common device accesses downstream, but for SR-IOV devices, multiple bus numbers may be needed. Since the bios implementation is related to specific manufacturers, in actual implementation, even if only one bus number is needed for a certain SR-IOV device itself, the bios may force to assign multiple bus numbers for this downstream. Therefore, the situation that the device cannot be started after being accessed may occur.

[0045] Therefore, the present application provides a switch downstream port determination scheme for accessing SR-IOV devices, which can consider that the system will not be restarted or stuck after the SR-IOV devices are accessed when providing a switch, and support the automatic detection of the maximum switch downstream capability that can be supported by the system after the SR-IOV devices are accessed to make further adaptive adjustment.

[0046] The embodiments of the present application disclose a switch downstream port determination method for accessing SR-IOV devices, referring to Figure 3 The method comprises the following steps:

[0047] Step S11: determining a switch to which a plurality of downstream ports are assigned, and accessing SR-IOV devices to each downstream port.

[0048] In the embodiments of the present application, when providing a switch, whether the bus number assignment will exceed the capability range of the slot after the SR-IOV devices are accessed is considered, so the analog state of the PCI-E card is changed multiple times, different numbers of bus numbers are tried to be assigned from the server, and the SR-IOV devices are carried thereon. That is, a switch with a plurality of downstream port numbers is simulated, and the SR-IOV devices are carried on each downstream port.

[0049] Step S12: Start the server and enumerate the SR-IOV device through the basic input / output system, and then record the current number of downstream ports.

[0050] In the embodiment of the present application, the basic input / output system will enumerate all the created devices during the server startup process and assign bus numbers to them. It should be noted that the server will read the Option Rom from the PCI-E card during operation. The Option Rom contains a command that can determine whether the current state is in the downstream port number range detection state. The Option Rom determines whether the current state is in the downstream port number detection state. If the current state is in the downstream port number detection state and the downstream port number is valid, the PCI-E card is notified, and the current number of downstream ports is recorded.

[0051] In addition, since the Option Rom notifies the PCI-E card of the current valid number of downstream ports in the embodiment of the present application, other ways can also be used to notify the PCI-E card of the current valid number of downstream ports, such as manually sending a command or other ways of notification, and the PCI-E card can also automatically determine by detecting the enumeration of the PCI-E packet transmission, which is not limited here.

[0052] In the embodiment of the present application, if the current number of downstream ports corresponding to the current number of bus numbers assigned does not exceed the range that the PCI-E slot can provide, it is determined that the number of downstream ports is valid. It can be understood that for a specific server, due to hardware implementation limitations, the number of available bus numbers for a certain slot is limited. When the number of bus numbers cannot meet the needs of the access card, it can cause the basic input / output system to fail to start. Therefore, when the current number of downstream ports corresponding to the current number of bus numbers assigned does not exceed the range that the PCI-E slot can provide, the detected number of downstream ports is valid at this time.

[0053] Step S13: Determine the current number of bus numbers corresponding to the current number of downstream ports, and determine whether the current number of bus numbers exceeds the range that the PCI-E slot can provide.

[0054] In the embodiment of the present application, if the bus number exceeds the range that can be provided by the PCI-E slot, the server will be stuck or abnormally restarted. Therefore, after the current bus number corresponding to the assigned current number of downstream ports is determined, whether the current bus number exceeds the range that can be provided by the PCI-E slot is determined by: if the current bus number causes abnormal server startup during the server startup process, it is determined that the current bus number exceeds the range that can be provided by the PCI-E slot; if the current bus number does not cause abnormal server startup during the server startup process, it is determined that the current bus number does not exceed the range that can be provided by the PCI-E slot.

[0055] Step S14: If the current bus number does not exceed the range that can be provided by the PCI-E slot, the number of downstream ports is changed, and the steps of restarting the server and enumerating the SR-IOV device through the basic input / output system are re-executed by a preset restart mode until the current bus number reaches the threshold of the range that can be provided by the PCI-E slot, so as to obtain a target number of downstream ports.

[0056] In the embodiment of the present application, if the bus number does not exceed the range that can be provided by the PCI-E slot, it is proved that the current number of downstream ports is valid, then the number of downstream ports is changed, and whether the system can support this bus number specification is identified according to whether the enumeration stage can be completed. If the bus number exceeds the range that can be supported by the system, the server will be stuck or abnormally restarted. At this time, the last successful enumeration of the number of downstream ports is read from the PCI-E card, which is the maximum number of downstream ports that can be provided by the switch to ensure that the server is restarted normally.

[0057] In the embodiment of the present application, the server is automatically restarted by the Option Rom when the number of downstream ports is changed, and then the step of enumerating the SR-IOV device through the basic input / output system is re-executed. Therefore, automatic restart during the detection process and automatic change of the simulation state are realized. It can be understood that if the Option Rom is not used for restart, other ways can also be used for restart, such as manual control, and the restart is completed after the server is normally started.

[0058] It should be noted that since the downstream port accesses the SR-IOV device, which can be assigned to multiple bus numbers, the SR-IOV device is assigned to each downstream port during simulation. The embodiment of the present application only takes the SR-IOV device as an example to illustrate the simulation of assigning downstream ports, and other resources with the same characteristics as the SR-IOV device can be simulated according to the embodiment of the present application, such as assigning memory. The method can also be used when assigning memory, and will not be described here.

[0059] In the present application, a switch with several downstream ports is determined, and an SR-IOV device is accessed for each downstream port; a server is started, and the SR-IOV device is enumerated through a basic input / output system, and then the current number of downstream ports is recorded; the current number of bus numbers corresponding to the allocation is determined based on the current number of downstream ports, and it is judged whether the current number of bus numbers exceeds the range that can be provided by a PCI-E slot; if the current number of bus numbers does not exceed the range that can be provided by the PCI-E slot, the number of downstream ports is changed, and the step of starting the server and enumerating the SR-IOV device through the basic input / output system is re-executed through a preset restart mode until the current number of bus numbers reaches the threshold of the range that can be provided by the PCI-E slot, so as to obtain a target number of downstream ports. It can be seen that, when providing a virtual machine, since the downstream port accessing the SR-IOV device can be allocated to multiple bus numbers, the SR-IOV device is accessed for each downstream port, and the number of downstream ports is continuously detected; when the SR-IOV device is enumerated, the current number of bus numbers reaches the threshold of the range that can be provided by the PCI-E slot, which indicates that the specification capability supported by the system is reached at this time. In this way, the maximum number of downstream ports that can be supported by the switch when accessing the SR-IOV device is analyzed, and it can be ensured that whether an ordinary device that only needs to be allocated one bus number or an SR-IOV device that can be allocated multiple bus numbers is accessed, the basic input / output system will not fail to restart, which is convenient for adaptation according to actual conditions, and on this basis, adaptive and other functions can be further developed.

[0060] The embodiment of the present application discloses a specific method for determining downstream ports of a switch accessing an SR-IOV device, as shown in Figure 4 The method comprises the following steps:

[0061] Step S21: determining the current number of allocated bus numbers allocated from the server in the current simulation state of the PCI-E card.

[0062] In the embodiment of the present application, by changing the simulation state of the PCI-E card multiple times, different numbers of bus numbers are attempted to be allocated from the server, and the SR-IOV device is carried thereon, and whether the enumeration stage can be completed is used to identify whether the system can support this bus specification.

[0063] Step S22: determining a switch with several downstream ports, and accessing an SR-IOV device for each downstream port.

[0064] Step S23: starting a server and enumerating the SR-IOV device through a basic input / output system, and then recording the current number of downstream ports.

[0065] The more specific process of the step S22 and the step S23 will be described in the following embodiments.

[0066] Step S24: Determine the current bus number quantity corresponding to the current downstream port quantity, and determine whether the current bus number quantity exceeds the allocated bus number quantity.

[0067] In the embodiments, the PCI-E card detects the bus number allocation on the current downstream port, records the bus number quantity and the current downstream port quantity, and the current bus number quantity should not exceed the allocated bus number quantity. It can be understood that the bus number quantity cannot be directly calculated from the downstream port quantity, so after starting the server, the SR-IOV device is enumerated by the basic input / output system, and it is determined whether the current bus number quantity exceeds the allocated bus number quantity in the current simulation state.

[0068] Step S25: If the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, the downstream port quantity is changed by using a preset convergence value determination method, and the preset threshold value to which the downstream port quantity converges is determined as the target downstream port quantity.

[0069] In the embodiments, the downstream port quantity is changed by using a preset convergence value determination method, such as increasing the downstream port quantity from small to large, simulating a switch with n downstream ports, and if the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, it proves that the current downstream port quantity is effective, and the quantity to be simulated next time is increased to (n=n+1), and then the step of starting the server and enumerating the SR-IOV device by the basic input / output system is re-executed by using a preset restart method, until the current bus number quantity reaches the threshold value of the range that can be provided by the PCI-E slot, so as to obtain the target downstream port quantity.

[0070] It can be understood that when the downstream port quantity is changed by using the preset convergence value determination method, if the downstream port quantity is changed from large to small, or other order, as long as it converges to a value finally, the purpose can also be achieved. The change of the downstream port quantity is not limited here.

[0071] In the application, the number of currently allocated bus numbers allocated by the server in the current analog state of the PCI-E card is determined; a switch allocated with a plurality of downstream ports is determined, and an SR-IOV device is accessed for each downstream port; the server is started and the SR-IOV device is enumerated through a basic input / output system, and then the current number of downstream ports is recorded; the number of currently allocated bus numbers corresponding to the current number of downstream ports is determined, and whether the number of currently allocated bus numbers exceeds the range of the PCI-E slot that can be provided is judged; if the number of currently allocated bus numbers does not exceed the range of the PCI-E slot that can be provided, the number of downstream ports is changed by using a preset convergence value determination method, and a preset threshold value to which the number of downstream ports converges is determined as the target number of downstream ports. It can be seen that when the PCI-E card provides a virtual machine, since the SR-IOV device accessed by the downstream port may be allocated with a plurality of bus numbers, the SR-IOV device is accessed for each downstream port and the number of downstream ports is continuously detected, when the SR-IOV device is enumerated, the number of currently allocated bus numbers reaches the threshold value of the range of the PCI-E slot that can be provided, which indicates that the specification capability supported by the system is reached at this time. In this way, the maximum number of downstream ports that can be supported by the switch when the SR-IOV device is accessed is analyzed, and it can be ensured that whether the ordinary device that only needs to be allocated with one bus number or the SR-IOV device that can be allocated with a plurality of bus numbers is accessed, the basic input / output system will not fail to restart, which is convenient for adaptation according to the actual situation, and on this basis, adaptive and other functions can be further developed.

[0072] Correspondingly, the application also discloses a switch downstream port determination device for accessing an SR-IOV device, as shown in Figure 5 The device comprises:

[0073] An SR-IOV device access module 11 is configured to determine a switch allocated with a plurality of downstream ports, and access an SR-IOV device for each downstream port.

[0074] A current number of downstream ports recording module 12 is configured to start a server and enumerate the SR-IOV device through a basic input / output system, and then record the current number of downstream ports.

[0075] A current number of bus numbers determination module 13 is configured to determine the number of currently allocated bus numbers corresponding to the current number of downstream ports, and judge whether the number of currently allocated bus numbers exceeds the range of a PCI-E slot that can be provided.

[0076] The target downstream port quantity determination module 14 is configured to change the downstream port quantity if the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, and re-perform the steps of starting the server and enumerating the SR-IOV device through the basic input / output system in a preset restart mode until the current bus number quantity reaches a threshold of the range that can be provided by the PCI-E slot, so as to obtain a target downstream port quantity.

[0077] The specific working processes of the above modules are described in the foregoing embodiments, and thus will not be repeated here.

[0078] According to the above scheme, the switch to which a plurality of downstream ports are assigned is determined, and the SR-IOV device is connected to each of the downstream ports. The server is started, and the SR-IOV device is enumerated through the basic input / output system. Then, the current downstream port quantity is recorded. The current bus number quantity corresponding to the current downstream port quantity is determined, and it is determined whether the current bus number quantity exceeds the range that can be provided by the PCI-E slot. If the current bus number quantity does not exceed the range that can be provided by the PCI-E slot, the downstream port quantity is changed, and the steps of starting the server and enumerating the SR-IOV device through the basic input / output system are re-performed in a preset restart mode until the current bus number quantity reaches a threshold of the range that can be provided by the PCI-E slot, so as to obtain a target downstream port quantity. As can be seen, when the PCI-E card provides a virtual machine, the SR-IOV device connected to the downstream port can be assigned a plurality of bus numbers. Therefore, the SR-IOV device is connected to each of the downstream ports, and the downstream port quantity is constantly detected. When the SR-IOV device is enumerated, the current bus number quantity reaches the threshold of the range that can be provided by the PCI-E slot, which indicates that the system reaches the supported specification capability at this time. In this way, the maximum downstream port quantity that can be supported by the switch when the SR-IOV device is connected is analyzed, and it can be ensured that whether the normal device to which only one bus number is assigned or the SR-IOV device to which a plurality of bus numbers can be assigned will not cause the basic input / output system to fail to restart. Therefore, the system can be adapted according to the actual situation, and further self-adaptive functions can be developed on this basis.

[0079] Further, the embodiment of the application further discloses an electronic device, Figure 6 FIG. 1 is a structural diagram of an electronic device 20 according to an example embodiment, and the content in the figure should not be considered as any limitation on the use range of the application.

[0080] Figure 6A structural schematic diagram of an electronic device 20 is provided in the embodiments of the present application. The electronic device 20 can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is configured to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the related steps in the method for determining a downstream port of a switch accessing an SR-IOV device disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the embodiments of the present application can be specifically a computer.

[0081] In the embodiments of the present application, the power supply 23 is configured to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 is capable of creating a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solutions of the present application, which is not specifically limited herein; the input / output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not specifically limited herein.

[0082] In addition, the memory 22 as a carrier for resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222 and data 223, etc., and the data 223 can include various data. The storage mode can be temporary storage or permanent storage.

[0083] The operating system 221 is configured to manage and control each hardware device on the electronic device 20 and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. The computer program 222 can further include computer programs capable of completing other specific work in addition to the computer program capable of completing the method for determining a downstream port of a switch accessing an SR-IOV device executed by the electronic device 20 disclosed in any of the foregoing embodiments.

[0084] Further, the embodiments of the present application further disclose a computer readable storage medium, which includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk or an optical disk or any other form of storage medium known in the technical field. The computer program is executed by the processor to implement the foregoing method for determining a downstream port of a switch accessing an SR-IOV device. The specific steps of the method can refer to the corresponding contents disclosed in the foregoing embodiments, which will not be described herein again.

[0085] The various embodiments described in this specification are presented by way of example, and each embodiment describes a specific implementation of the application. The embodiments are not intended to limit the scope of the application, which is defined by the appended claims. Each embodiment can be combined with one or more other embodiments, and the description of each embodiment is not intended to exclude the combination of the described embodiment with one or more other embodiments.

[0086] The steps of the switch downstream port determination or algorithm for accessing SR-IOV devices described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, hard disk can be used as a storage medium.

[0087] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and do not imply singular or plural. Moreover, the terms "include", "have", or any other variant thereof are intended to encompass non-exclusive inclusions, such that processes, methods, articles, or apparatuses that include a series of elements are not required to include only those elements that are explicitly listed, or that also include other elements that are not expressly listed, or that also include inherent elements of such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0088] The above describes in detail the access SR-IOV device switch downstream port determination method, device, equipment and medium provided by the application, and the principle and implementation mode of the application are described by applying specific examples in this specification. The above description of the embodiments is only to help understand the method of the application and its core idea; at the same time, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed, and the above description of the specification should not be understood as limiting the application.

Claims

1. A method for determining the downstream port of a switch connected to an SR-IOV device, characterized in that, The method comprises the following steps: determining the number of currently allocated bus numbers assigned by the server in the current analog state of the PCI-E card; determining a switch assigned with a plurality of downstream ports, and accessing an SR-IOV device for each of the downstream ports; starting the server and enumerating the SR-IOV device through a basic input / output system, and then recording the current number of downstream ports; determining the number of currently allocated bus numbers corresponding to the current number of downstream ports, and judging whether the number of currently allocated bus numbers exceeds the range of the PCI-E slot; if the number of currently allocated bus numbers does not exceed the range of the PCI-E slot, changing the number of downstream ports, and re-executing the steps of starting the server and enumerating the SR-IOV device through the basic input / output system by a preset restart mode until the number of currently allocated bus numbers reaches the threshold of the range of the PCI-E slot, so as to obtain a target number of downstream ports; wherein the step of determining the number of currently allocated bus numbers corresponding to the current number of downstream ports, and judging whether the number of currently allocated bus numbers exceeds the range of the PCI-E slot comprises: determining the number of currently allocated bus numbers corresponding to the current number of downstream ports, and judging whether the number of currently allocated bus numbers exceeds the number of allocated bus numbers.

2. The method of claim 1, wherein the method further comprises: The step of starting the server and enumerating the SR-IOV device through the basic input / output system, and then recording the current number of downstream ports comprises: starting the server and enumerating the SR-IOV device through the basic input / output system, and then judging whether the current is in the state of detecting the number of downstream ports through an OptionRom; if the current is in the state of detecting the number of downstream ports, and the number of downstream ports is valid, recording the current number of downstream ports; correspondingly, the step of changing the number of downstream ports if the number of currently allocated bus numbers does not exceed the range of the PCI-E slot, and re-executing the step of starting the server and enumerating the SR-IOV device through the basic input / output system comprises: if the number of currently allocated bus numbers does not exceed the range of the PCI-E slot, changing the number of downstream ports, and restarting the server through the OptionRom, and then re-executing the step of enumerating the SR-IOV device through the basic input / output system.

3. The method of claim 2, wherein the method further comprises: the step of judging whether the current is in the state of detecting the number of downstream ports, and the number of downstream ports is valid comprises: if the current is in the state of detecting the number of downstream ports, and the number of currently allocated bus numbers corresponding to the current number of downstream ports does not exceed the range of the PCI-E slot, determining that the number of downstream ports is valid.

4. The method of claim 1, wherein the method further comprises: the step of changing the number of downstream ports if the number of currently allocated bus numbers does not exceed the range of the PCI-E slot comprises: If the current bus number quantity does not exceed the range that the PCI-E slot can provide, the quantity of downstream ports is changed by using a preset convergence value determination method, and a preset threshold value to which the quantity of downstream ports converges is determined as the target quantity of downstream ports.

5. The method of claim 1 to 4, wherein, The method further includes: If the current bus number quantity causes the server to abnormally start during the process of starting the server, it is determined that the current bus number quantity exceeds the range that the PCI-E slot can provide. If the current bus number quantity does not cause the server to abnormally start during the process of starting the server, it is determined that the current bus number quantity does not exceed the range that the PCI-E slot can provide.

6. A device for determining the downstream port of a switch connected to an SR-IOV device, characterized in that, The method further includes: An SR-IOV device access module is configured to determine a switch to which a plurality of downstream ports are assigned, and access an SR-IOV device for each of the downstream ports. A current quantity of downstream ports recording module is configured to start a server and enumerate the SR-IOV device through a basic input output system, and then record a current quantity of downstream ports. A current bus number quantity judging module is configured to determine a current bus number quantity corresponding to the current quantity of downstream ports based on the current quantity of downstream ports, and judge whether the current bus number quantity exceeds the range that the PCI-E slot can provide. A target quantity of downstream ports determining module is configured to, if the current bus number quantity does not exceed the range that the PCI-E slot can provide, change the quantity of downstream ports, and re-perform the steps of starting the server and enumerating the SR-IOV device through the basic input output system by using a preset restart mode until the current bus number quantity reaches a threshold value of the range that the PCI-E slot can provide, so as to obtain a target quantity of downstream ports.

7. The apparatus of claim 6, wherein the downstream port determination means of a switch accessing an SR-IOV device is characterized by, The target quantity of downstream ports determining module is further configured to, if the current bus number quantity does not exceed the range that the PCI-E slot can provide, change the quantity of downstream ports by using a preset convergence value determination method, and determine a preset threshold value to which the quantity of downstream ports converges as the target quantity of downstream ports.

8. An electronic device, comprising: The electronic device includes a processor and a memory; wherein the memory is configured to store a computer program, the computer program is loaded and executed by the processor to implement the method for determining the quantity of downstream ports of the switch accessing the SR-IOV device according to any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that, The computer program is stored in the memory and is executed by the processor to implement the method for determining the quantity of downstream ports of the switch accessing the SR-IOV device according to any one of claims 1 to 5.

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