Method, device and equipment for improving transmission bandwidth between bmc and cmc and storage medium

Abstract

The application discloses a bandwidth transmission improving method and device between a BMC and a CMC, equipment and a storage medium, relates to the technical field of computers, and comprises the following steps: constructing preset codes for converting an I2C bus mode into a serial peripheral interface SPI bus mode in the BMC and the CMC respectively, so as to determine a first SPI bus corresponding to the BMC and a second SPI bus corresponding to the CMC; obtaining an in-situ signal of a complex programmable logic device of a server node through the first SPI bus and monitoring the state change thereof; based on the state change process of the in-situ signal, communicating with the complex programmable logic device on the server backboard by using a low-voltage differential signal, so that the complex programmable logic device on the server backboard transmits with the CMC through the second SPI bus. Through the technical scheme of the application, the design difficulty is reduced and the cost is saved without additional chip support for hot plug, and meanwhile, the transmission speed between the CMC and the BMC is improved without affecting the safety.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for increasing the transmission bandwidth between BMC and CMC. Background Technology

[0002] With the development and widespread application of storage services, increasingly larger storage systems are emerging. These massive systems consist of numerous nodes. In multi-node systems, each node has its own Basic Management Controller (BMC) and Chassis Management Controller (CMC). Communication between the BMC and CMC must be based on Intelligent Platform Management Interface (IPMI), using I2C (Inter-Integrated Circuit). Multi-node systems also need to support hot-plugging of nodes to improve maintainability. However, hot-plugging can disrupt the I2C channel, necessitating the use of I2C hot-plug IC chips to mitigate these issues. However, the relatively slow speed of I2C limits many of the CMC's functions in managing the individual node BMCs.

[0003] Currently, in multi-node systems, the primary communication between the node BMCs and the chassis management CMC is still via the I2C bus to transmit management information, and the BMC network and CMC network use I2C commands to facilitate the transfer of larger files. However, the fixed information that the CMC needs to obtain must still be transmitted via I2C, which limits the CMC's management functions, such as... Figure 1As shown. Due to the slow speed of I2C (100kHz / 400kHz or 1MHz), the transmission rate between the BMC and CMC of its nodes remains slow. Furthermore, currently available I2C hot-plug re-drivers only support up to 400kHz, with no faster I2C hot-plug re-driver ICs. This results in longer communication times between the CMC and each BMC, preventing the CMC from promptly confirming the status of each node's BMC. Additionally, the slow bandwidth of the CMC makes it unsuitable for transferring large files, such as firmware (large images like the BIOS BMC), leading to longer update times and occupying already slow channels, thus limiting CMC management functions. Moreover, supporting high-speed I2C (400kHz or 1MHz) requires additional drivers to avoid parasitic capacitance on the channels preventing the speed from reaching the planned level. Furthermore, multi-node systems must support hot-swapping to avoid requiring multiple nodes to shut down when a single node needs replacement. However, the I2C channel itself does not support hot-plugging. To support it, a hot-plug IC is required to enable the channel and avoid data disturbance during the hot-plugging process.

[0004] In summary, how to support hot-swapping for the aforementioned storage system cluster without the need for additional chips, thereby reducing design complexity and saving costs, while simultaneously improving the transmission speed between the CMC and BMC without compromising security, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method, apparatus, device, and storage medium for increasing the transmission bandwidth between the BMC and CMC, which can support hot-swapping without the need for external chips, reducing design complexity and saving costs, while improving the transmission speed between the CMC and BMC without compromising security. The specific solution is as follows:

[0006] In a first aspect, this application discloses a method for increasing transmission bandwidth between BMC and CMC, including:

[0007] Each of the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) contains preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode, thereby determining the first SPI bus corresponding to the Baseboard Management Controller (BMC) and the second SPI bus corresponding to the Chassis Management Controller (CMC); wherein, each server node is provided with one Baseboard Management Controller (BMC), and the Chassis Management Controller (CMC) is connected to the server backplane;

[0008] The presence signal of the complex programmable logic device of the server node is obtained through the first SPI bus, and the state change of the presence signal is monitored; wherein, the presence signal is used to characterize whether the current server node has undergone hot-plugging.

[0009] Based on the state change process of the in-situ signal, a low-voltage differential signal is used to communicate with the complex programmable logic device on the server backplane, so that the complex programmable logic device on the server backplane can transmit with the chassis management controller (CMC) through the second SPI bus.

[0010] Optionally, pre-defined code for converting I2C bus mode to Serial Peripheral Interface (SPI) bus mode can be built within the Baseboard Management Controller (BMC), including:

[0011] Preset code is built within the Baseboard Management Controller (BMC) to convert 400kHz or 1MHz I2C bus mode to Serial Peripheral Interface (SPI) bus mode.

[0012] Optionally, the communication with the complex programmable logic devices on the server backplane using low-voltage differential signals includes:

[0013] Multiple server nodes communicate with complex programmable logic devices on the server backplane using a multiplexer and low-voltage differential signals.

[0014] Optionally, both the baseboard management controller (BMC) and the chassis management controller (CMC) use AST2600 series chips and / or AST2500 series chips.

[0015] Optionally, the method for increasing the transmission bandwidth between the BMC and CMC further includes:

[0016] In the Baseboard Management Controller (BMC) and Chassis Management Controller (CMC), the bandwidth of the Baseboard Management Controller (BMC) is read through the first SPI interface, the flash memory of the Basic Input / Output System is updated through the second SPI interface, and the I2C bus mode is converted to the Serial Peripheral Interface (SPI) bus mode using the preset code through the third SPI interface.

[0017] Optionally, the process of communicating with complex programmable logic devices on the server backplane using low-voltage differential signals based on the state change of the in-situ signal includes:

[0018] If the state of the in-situ signal changes from in-situ to out-of-situ during the first process, then the time range corresponding to the first process is determined, and the low-voltage differential signal is removed by the complex programmable logic device on the server backplane within the time range.

[0019] If the state of the in-situ signal changes from an out-of-situ state to an in-situ state during the second process, then when the in-situ signal appears, the low-voltage differential signal is read through the complex programmable logic device on the server backplane.

[0020] Optionally, when the in-situ signal occurs, reading the low-voltage differential signal via a complex programmable logic device on the server backplane includes:

[0021] When the in-place signal appears, the low-voltage differential signal is read after a preset time interval using complex programmable logic devices on the server backplane.

[0022] Secondly, this application discloses a transmission bandwidth enhancement device between BMC and CMC, comprising:

[0023] A bus mode conversion module is used to construct preset codes in the baseboard management controller (BMC) and chassis management controller (CMC) respectively for converting the I2C bus mode to the serial peripheral interface (SPI) bus mode, so as to determine the first SPI bus corresponding to the baseboard management controller (BMC) and the second SPI bus corresponding to the chassis management controller (CMC); wherein, each server node is provided with one baseboard management controller (BMC), and the chassis management controller (CMC) is connected to the server backplane;

[0024] The in-situ signal monitoring module is used to acquire the in-situ signal of the complex programmable logic device of the server node through the first SPI bus and monitor the state changes of the in-situ signal; wherein, the in-situ signal is used to characterize whether the current server node has undergone hot-plugging.

[0025] The communication module is used to communicate with the complex programmable logic device on the server backplane using a low-voltage differential signal based on the state change process of the in-situ signal, so that the complex programmable logic device on the server backplane can transmit data with the chassis management controller (CMC) via the second SPI bus.

[0026] Thirdly, this application discloses an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the aforementioned method for increasing the transmission bandwidth between the BMC and CMC.

[0027] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned method for increasing the transmission bandwidth between the BMC and CMC.

[0028] In this application, firstly, preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode is constructed in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to determine the first SPI bus corresponding to the BMC and the second SPI bus corresponding to the CMC. Each server node has one BMC, and the CMC is connected to the server backplane. Then, the presence signal of the complex programmable logic device (CPL) on the server node is acquired via the first SPI bus, and the state changes of the presence signal are monitored. The presence signal is used to characterize whether a hot-plug has occurred on the current server node. Finally, based on the state changes of the presence signal, a low-voltage differential signal is used to communicate with the CPL on the server backplane, so that the CPL on the server backplane can transmit data with the CMC via the second SPI bus. As can be seen, by placing the pre-defined code that converts I2C to SPI in the BMC / CMC, the IPMI protocol can be applied to the existing SPI hardware channel of the BMC / CMC, replacing the I2C channel. This simplifies and reduces the system component requirements, reduces design complexity and saves costs, and eliminates the need for a high-speed I2C driver IC. In addition, the node design with in-situ signals allows the low-voltage differential signal bus to support multi-node hot-plug applications, eliminating the need for an I2C hot-plug IC. Besides optimizing costs, this also reduces the space required for component area. Since SPI can achieve a bandwidth of 200MHz for short-distance transmission, which is much higher than I2C, and can then utilize low-voltage differential signal transmission through existing complex programmable logic devices on the node and backplane, the speed of which can reach more than 500MHz, the functionality can be integrated into the existing complex programmable logic devices on the motherboard and backplane. This reduces the number of chips required by the system, thereby increasing system density, reducing product costs, and enhancing product competitiveness. Without compromising security, it can also improve the transmission speed between the CMC and BMC, as well as the bandwidth performance of communication management between the CMC and the node BMC, and further provide more CMC management capabilities. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 A schematic diagram of the communication architecture between the four-way multi-node CMC and each node BMC provided in this application;

[0031] Figure 2 This is a flowchart of a method for improving transmission bandwidth between BMC and CMC disclosed in this application;

[0032] Figure 3 This is a schematic diagram of the LVDS architecture that replaces I2C with SPI and CPLD through BMC and CMC as disclosed in this application;

[0033] Figure 4 This application discloses a flowchart of a specific method for improving transmission bandwidth between BMC and CMC.

[0034] Figure 5 This is a schematic diagram of the LVDS bus hot-plugging operation of a CPLD disclosed in this application;

[0035] Figure 6 This is a schematic diagram of a transmission bandwidth enhancement device between BMC and CMC disclosed in this application;

[0036] Figure 7 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Currently, in multi-node systems, the main communication between the BMCs of each node and the CMC of the chassis management is still through the I2C bus to transmit management information, which limits the management functions of the CMC. In addition, the I2C channel itself does not support hot-plugging, and hot-plug ICs are required to enable the channel to support it.

[0039] To this end, this application provides a solution to improve the transmission bandwidth between BMC and CMC, which can support hot-swapping without the need for external chips, reduce design difficulty and save costs, and improve the transmission speed between CMC and BMC without affecting security.

[0040] This invention discloses a method for increasing transmission bandwidth between BMC and CMC. See [link to relevant documentation]. Figure 2 As shown, the method includes:

[0041] Step S11: Build preset code in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to convert the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode, thereby determining the first SPI bus corresponding to the Baseboard Management Controller (BMC) and the second SPI bus corresponding to the Chassis Management Controller (CMC); wherein, each server node is provided with one Baseboard Management Controller (BMC), and the Chassis Management Controller (CMC) is connected to the server backplane.

[0042] In this embodiment, both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) use AST2600 series chips and / or AST2500 series chips. It is understood that these IC chips all have three SPI (Serial Peripheral Interface) channels: one for reading the BMC's bandwidth (FW), another for updating the BIOS Flash (Basic Input Output System flash memory), and a missing SPI channel in the current architecture. Since the IPMI protocol currently does not support SPI channels, a set of I2C to SPI conversion interface code is developed within the BMC code to meet the current IPMI architecture. Correspondingly, I2C to SPI conversion code is also added to the CMC code. In this way, by replacing I2C with SPI, the bandwidth limitation of I2C is overcome, the bandwidth of CMC and node BMC is increased, the design difficulty is reduced and the cost is saved, and an extra hardware SPI bus of BMC / CMC can be effectively utilized; moreover, SPI can achieve a bandwidth of 200MHz for short-distance transmission, which is much higher than I2C, and can improve the bandwidth performance of communication management between CMC and node BMC.

[0043] Specifically, in the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC), the bandwidth of the Baseboard Management Controller (BMC) is read through the first SPI interface, the flash memory of the Basic Input / Output System is updated through the second SPI interface, and the I2C bus mode is converted to the Serial Peripheral Interface (SPI) bus mode using the preset code through the third SPI interface.

[0044] Step S12: Obtain the presence signal of the complex programmable logic device of the server node through the first SPI bus, and monitor the state change of the presence signal; wherein, the presence signal is used to characterize whether the current server node has undergone hot-plugging.

[0045] In this embodiment, since I2C in high-speed mode, i.e. 400KHz or 1MHz, node hot-plug applications need to be handled by an external IC. When the presence signal of the complex programmable logic device of the server node is obtained through the first SPI bus and the state change of the presence signal is monitored, the need for node hot-plugging can be overcome according to the change of the presence signal. In this way, the need for an external chip can be omitted, reducing design difficulty and saving costs.

[0046] Step S13: Based on the state change process of the in-situ signal, use a low-voltage differential signal to communicate with the complex programmable logic device on the server backplane, so that the complex programmable logic device on the server backplane can transmit with the chassis management controller (CMC) through the second SPI bus.

[0047] In this embodiment, the changes in the in-situ signal of the node are provided to the Complex Programmable Logic Device (CPLD) on the backplane. The CPLD transmits the signal through hardware SPI. The CPLD of the node then uses Low-Voltage Differential Signaling (LVDS) to meet the long-distance transmission between the node and the CPLD of the server backplane. In this way, the CPLD transmits the signal through LVDS, and its LVDS speed can reach more than 500MHz.

[0048] It should be noted that the CPLD on the server backplane communicates with the complex programmable logic devices of each node through a multiplexer, such as... Figure 3 As shown, each server node's BMC uses preset code to convert I2C to SPI, then links to the node's CPLD via SPI, and then connects to LVDS. The server backplane CPLD's internal code creates a 1:4 MUX (multiplexer, data selector) to communicate with each node's CPLD. Finally, the CMC uses preset code to convert I2C to SPI to communicate with each server node. This embodiment of the application allows the server node and CMC to communicate without going through an external network. This architecture provides greater bandwidth to meet the needs of high-bandwidth applications, such as FW updates, CMC display of the BMC front screen, and control applications.

[0049] It is understood that the embodiments of this application are examples of a 4-channel system, but they can also be applied to 8-channel or more-channel systems, and no specific limitation is made here.

[0050] In this application, firstly, preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode is constructed in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to determine the first SPI bus corresponding to the BMC and the second SPI bus corresponding to the CMC. Each server node has one BMC, and the CMC is connected to the server backplane. Then, the presence signal of the complex programmable logic device (CPL) on the server node is acquired via the first SPI bus, and the state changes of the presence signal are monitored. The presence signal is used to characterize whether a hot-plug has occurred on the current server node. Finally, based on the state changes of the presence signal, a low-voltage differential signal is used to communicate with the CPL on the server backplane, so that the CPL on the server backplane can transmit data with the CMC via the second SPI bus. As can be seen, by placing the pre-defined code that converts I2C to SPI in the BMC / CMC, the IPMI protocol can be applied to the existing SPI hardware channel of the BMC / CMC, replacing the I2C channel. This simplifies and reduces the system component requirements, reduces design complexity and saves costs, and eliminates the need for a high-speed I2C driver IC. In addition, the node design with in-situ signals allows the low-voltage differential signal bus to support multi-node hot-plug applications, eliminating the need for an I2C hot-plug IC. Besides optimizing costs, this also reduces the space required for component area. Since SPI can achieve a bandwidth of 200MHz for short-distance transmission, which is much higher than I2C, and can then utilize low-voltage differential signal transmission through existing complex programmable logic devices on the node and backplane, the speed of which can reach more than 500MHz, the functionality can be integrated into the existing complex programmable logic devices on the motherboard and backplane. This reduces the number of chips required by the system, thereby increasing system density, reducing product costs, and enhancing product competitiveness. Without compromising security, it can also improve the transmission speed between the CMC and BMC, as well as the bandwidth performance of communication management between the CMC and the node BMC, and further provide more CMC management capabilities.

[0051] This application discloses a specific method for increasing transmission bandwidth between BMC and CMC. See [link to relevant documentation]. Figure 4 As shown, the method includes:

[0052] Step S21: Construct preset code in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to convert the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode, thereby determining the first SPI bus corresponding to the Baseboard Management Controller (BMC) and the second SPI bus corresponding to the Chassis Management Controller (CMC); wherein, each server node is provided with one Baseboard Management Controller (BMC), and the Chassis Management Controller (CMC) is connected to the server backplane.

[0053] Step S22: Obtain the presence signal of the complex programmable logic device of the server node through the first SPI bus, and monitor the state change of the presence signal; wherein, the presence signal is used to characterize whether the current server node is hot-plugged.

[0054] For more detailed processing procedures regarding steps S21 and S22, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0055] Step S23: If the state of the in-situ signal changes from in-situ to out-of-situ during the first process, then determine the time range corresponding to the first process, and remove the low-voltage differential signal within the time range using the complex programmable logic device on the server backplane.

[0056] In this embodiment, the node is designed with an in-situ signal to enable the LVDS bus to support multi-node hot-swappable applications. By judging the status of the in-situ signal, the hot-swappable function of the node is satisfied, and interference with LVDS reading is avoided.

[0057] Understandably, since the presence signal is used to characterize whether the current server node has been hot-plugged, when the presence signal changes from present to absent in the first process, it indicates that the server node is in the hot removal process. At this time, the server backplane CPLD directly removes the LVDS signal for this period to prevent the disturbance to the LVDS bus caused by the node hot removal process from causing the backplane CPLD to obtain incorrect signals.

[0058] Step S24: If the state of the present signal changes from absent to present in the second process, then when the present signal appears, the low voltage differential signal is read through the complex programmable logic device on the server backplane.

[0059] In this embodiment of the application, if the state of the presence signal changes from the absence state to the presence state in the second process, it indicates that the server node is in the hot insertion process. At this time, when the node is not in place, the server backplane CPLD will not read the LVDS bus channel until the node presence signal appears.

[0060] In this embodiment of the application, when the node is present, the server backplane will delay for a period of time, such as 100ms (this time can be adjusted), before acquiring the LVDS bus channel signal. That is, the low voltage differential signal is read after a preset time interval to prevent the backplane CPLD from obtaining incorrect signals due to the disturbance of the LVDS bus caused by the node hot insertion process.

[0061] For example, such as Figure 5 The diagram illustrates how changes in the PRESENT_N presence signal of a node are used to provide information to the backplane CPLD, enabling hot-swapping of the node and preventing interference with LVDS reads. Specifically, when the node's presence signal changes, if it changes from a present state to an absent state, the LVDS signal for that period is removed (LVDS bus off); if it changes from an absent state to a present state, the LVDS bus channel signal is acquired after a 100ms delay (LVDS bus on).

[0062] Step S25: The complex programmable logic devices on the server backplane transmit data to the chassis management controller (CMC) via the second SPI bus.

[0063] For a more detailed description of the process of step S25, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0064] In this application, firstly, preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode is constructed in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to determine the first SPI bus corresponding to the BMC and the second SPI bus corresponding to the CMC. Each server node has one BMC, and the CMC is connected to the server backplane. Then, the presence signal of the complex programmable logic device (CLP) of the server node is obtained through the first SPI bus, and the state changes of the presence signal are monitored. The signal is used to characterize whether the current server node has been hot-plugged. If the state of the in-place signal changes from in-place to out-of-place in the first process, the time range corresponding to the first process is determined, and the low-voltage differential signal is removed by the complex programmable logic device on the server backplane within the time range. If the state of the in-place signal changes from out-of-place to in-place in the second process, the low-voltage differential signal is read by the complex programmable logic device on the server backplane when the in-place signal appears. Finally, the complex programmable logic device on the server backplane transmits data with the chassis management controller (CMC) via the second SPI bus. It is evident that by placing the pre-defined code for converting I2C to SPI on the BMC / CMC, the IPMI protocol can be applied to the existing SPI hardware channel of the BMC / CMC, replacing the I2C channel, simplifying and reducing system component requirements, reducing design difficulty and saving costs, and eliminating the need for an I2C high-speed driver IC. Furthermore, the node design uses an in-place signal, allowing the low-voltage differential signal bus to support multi-node hot-plug applications, eliminating the need for an I2C hot-plug IC, thus optimizing costs and reducing the space required for component area. Since SPI can achieve a bandwidth of 200MHz for short-distance transmission, which is much higher than I2C, and can then utilize low-voltage differential signal transmission through existing complex programmable logic devices on the node and backplane, the speed of which can reach more than 500MHz, the functionality can be integrated into the existing complex programmable logic devices on the motherboard and backplane. This reduces the number of chips required by the system, thereby increasing system density, reducing product costs, and enhancing product competitiveness. Without compromising security, it can also improve the transmission speed between the CMC and BMC, as well as the bandwidth performance of communication management between the CMC and the node BMC, and further provide more CMC management capabilities.

[0065] Accordingly, embodiments of this application also disclose a transmission bandwidth enhancement device between BMC and CMC, see [link to relevant documentation]. Figure 6 As shown, the device includes:

[0066] The bus mode conversion module 11 is used to construct preset codes in the baseboard management controller (BMC) and chassis management controller (CMC) respectively for converting the I2C bus mode to the serial peripheral interface (SPI) bus mode, so as to determine the first SPI bus corresponding to the baseboard management controller (BMC) and the second SPI bus corresponding to the chassis management controller (CMC); wherein, each server node is provided with one baseboard management controller (BMC), and the chassis management controller (CMC) is connected to the server backplane;

[0067] The in-situ signal monitoring module 12 is used to acquire the in-situ signal of the complex programmable logic device of the server node through the first SPI bus and monitor the state change of the in-situ signal; wherein, the in-situ signal is used to characterize whether the current server node has undergone hot-plugging.

[0068] The communication module 13 is used to communicate with the complex programmable logic device on the server backplane using a low-voltage differential signal based on the state change process of the in-situ signal, so that the complex programmable logic device on the server backplane can transmit data with the chassis management controller (CMC) through the second SPI bus.

[0069] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0070] Therefore, through the above-described scheme of this embodiment, firstly, preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode is constructed in both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) to determine the first SPI bus corresponding to the Baseboard Management Controller (BMC) and the second SPI bus corresponding to the Chassis Management Controller (CMC). Each server node is equipped with one Baseboard Management Controller (BMC), and the Chassis Management Controller (CMC) is connected to the server backplane. Then, the presence signal of the complex programmable logic device (CPL) of the server node is obtained through the first SPI bus, and the state change of the presence signal is monitored. The presence signal is used to characterize whether a hot-plugging has occurred on the current server node. Finally, based on the state change process of the presence signal, a low-voltage differential signal is used to communicate with the CPL on the server backplane, so that the CPL on the server backplane can transmit data with the Chassis Management Controller (CMC) through the second SPI bus. As can be seen, by placing the pre-defined code that converts I2C to SPI in the BMC / CMC, the IPMI protocol can be applied to the existing SPI hardware channel of the BMC / CMC, replacing the I2C channel. This simplifies and reduces the system component requirements, reduces design complexity and saves costs, and eliminates the need for a high-speed I2C driver IC. In addition, the node design with in-situ signals allows the low-voltage differential signal bus to support multi-node hot-plug applications, eliminating the need for an I2C hot-plug IC. Besides optimizing costs, this also reduces the space required for component area. Since SPI can achieve a bandwidth of 200MHz for short-distance transmission, which is much higher than I2C, and can then utilize low-voltage differential signal transmission through existing complex programmable logic devices on the node and backplane, the speed of which can reach more than 500MHz, the functionality can be integrated into the existing complex programmable logic devices on the motherboard and backplane. This reduces the number of chips required by the system, thereby increasing system density, reducing product costs, and enhancing product competitiveness. Without compromising security, it can also improve the transmission speed between the CMC and BMC, as well as the bandwidth performance of communication management between the CMC and the node BMC, and further provide more CMC management capabilities.

[0071] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0072] Figure 7This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the method for improving the transmission bandwidth between the BMC and CMC disclosed in any of the foregoing embodiments. Alternatively, the electronic device 20 in this embodiment may specifically be a computer.

[0073] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0074] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 221, computer programs 222, and data 223, etc. The data 223 can include various types of data. The storage method can be temporary storage or permanent storage.

[0075] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the BMC and CMC transmission bandwidth enhancement method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.

[0076] Furthermore, this application also discloses a computer-readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. When the computer program is executed by a processor, it implements the aforementioned method for increasing the transmission bandwidth between the BMC and CMC. The specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0077] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0078] The steps of the transmission bandwidth enhancement or algorithm between the BMC and CMC described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0079] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The foregoing has provided a detailed description of the method, apparatus, device, and storage medium for enhancing the transmission bandwidth between BMC and CMC provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for increasing transmission bandwidth between BMC and CMC, characterized in that, include: Each of the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) contains preset code for converting the I2C bus mode to the Serial Peripheral Interface (SPI) bus mode, thereby determining the first SPI bus corresponding to the Baseboard Management Controller (BMC) and the second SPI bus corresponding to the Chassis Management Controller (CMC); wherein, each server node is provided with one Baseboard Management Controller (BMC), and the Chassis Management Controller (CMC) is connected to the server backplane; The presence signal of the complex programmable logic device of the server node is obtained through the first SPI bus, and the state change of the presence signal is monitored; wherein, the presence signal is used to characterize whether the current server node has undergone hot-plugging. Based on the state change process of the in-situ signal, a low-voltage differential signal is used to communicate with the complex programmable logic device on the server backplane, so that the complex programmable logic device on the server backplane can transmit with the chassis management controller (CMC) through the second SPI bus.

2. The method for increasing transmission bandwidth between BMC and CMC according to claim 1, characterized in that, Pre-defined code for converting I2C bus mode to Serial Peripheral Interface (SPI) bus mode is built within the Baseboard Management Controller (BMC), including: Preset code is built within the Baseboard Management Controller (BMC) to convert a 400kHz I2C bus mode or a 1MHz I2C bus mode to a Serial Peripheral Interface (SPI) bus mode.

3. The method for increasing transmission bandwidth between BMC and CMC according to claim 1, characterized in that, The method of communicating with complex programmable logic devices on the server backplane using low-voltage differential signals includes: Multiple server nodes communicate with complex programmable logic devices on the server backplane using a multiplexer and low-voltage differential signals.

4. The method for increasing transmission bandwidth between BMC and CMC according to claim 1, characterized in that, Both the Baseboard Management Controller (BMC) and the Chassis Management Controller (CMC) use AST2600 series chips and / or AST2500 series chips.

5. The method for increasing transmission bandwidth between BMC and CMC according to claim 4, characterized in that, Also includes: In the Baseboard Management Controller (BMC) and Chassis Management Controller (CMC), the bandwidth of the Baseboard Management Controller (BMC) is read through the first SPI interface, the flash memory of the Basic Input / Output System is updated through the second SPI interface, and the I2C bus mode is converted to the Serial Peripheral Interface (SPI) bus mode using the preset code through the third SPI interface.

6. The method for increasing transmission bandwidth between BMC and CMC according to any one of claims 1 to 5, characterized in that, The process of state change based on the in-situ signal, utilizing low-voltage differential signals to communicate with complex programmable logic devices on the server backplane, includes: If the state of the in-situ signal changes from in-situ to out-of-situ during the first process, then the time range corresponding to the first process is determined, and the low-voltage differential signal is removed by the complex programmable logic device on the server backplane within the time range. If the state of the in-situ signal changes from an out-of-situ state to an in-situ state during the second process, then when the in-situ signal appears, the low-voltage differential signal is read through the complex programmable logic device on the server backplane.

7. The method for increasing transmission bandwidth between BMC and CMC according to claim 6, characterized in that, When the in-situ signal occurs, reading the low-voltage differential signal via a complex programmable logic device on the server backplane includes: When the in-place signal appears, the low-voltage differential signal is read after a preset time interval using complex programmable logic devices on the server backplane.

8. A transmission bandwidth enhancement device between BMC and CMC, characterized in that, include: A bus mode conversion module is used to construct preset codes in the baseboard management controller (BMC) and chassis management controller (CMC) respectively for converting the I2C bus mode to the serial peripheral interface (SPI) bus mode, so as to determine the first SPI bus corresponding to the baseboard management controller (BMC) and the second SPI bus corresponding to the chassis management controller (CMC); wherein, each server node is provided with one baseboard management controller (BMC), and the chassis management controller (CMC) is connected to the server backplane; The in-situ signal monitoring module is used to acquire the in-situ signal of the complex programmable logic device of the server node through the first SPI bus and monitor the state changes of the in-situ signal; wherein, the in-situ signal is used to characterize whether the current server node has undergone hot-plugging. The communication module is used to communicate with the complex programmable logic device on the server backplane using a low-voltage differential signal based on the state change process of the in-situ signal, so that the complex programmable logic device on the server backplane can transmit data with the chassis management controller (CMC) via the second SPI bus.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the method for increasing transmission bandwidth between the BMC and CMC as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein the computer program, when executed by a processor, implements the method for increasing transmission bandwidth between the BMC and CMC as described in any one of claims 1 to 7.

Images