Method and apparatus for generating chip register rtl code

Abstract

The application provides a chip register RTL code generation method and device, the method comprises the following steps: obtaining a port signal list of a chip; the port signal list comprises signal attributes of a plurality of signals, the signal attributes at least comprise a register mark, the register mark is used to indicate whether the corresponding signal is associated with a register by specifying an offset address or automatically offsetting the address; according to the register mark, determining a target signal associated with the register in the port signal list; based on the specified offset address or the automatic offset address in the register mark corresponding to the target signal, generating an offset address dictionary; the offset address dictionary comprises related information of the target signal, and the related information at least comprises an offset address; according to the offset address in the offset address dictionary, performing domain-by-domain processing on the offset address dictionary to generate a register document; and according to the code logic of each line in the register document, generating a register RTL code. The scheme can improve the generation efficiency and accuracy of the register RTL code.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of integrated circuits, and in particular, to a chip register RTL code generation method and device. BACKGROUND

[0002] In chip design, a modular design approach is usually adopted, and each module is configured with multiple registers to realize the function of the corresponding module. However, as the chip function increases, the number of functional modules in the chip also increases, and the number of registers that need to be maintained also increases.

[0003] In the prior art, after obtaining a port signal list corresponding to each module in the chip, a register transfer level (RTL) code is manually written by a human to realize the chip function using the RTL code, but the manual writing approach is inefficient and prone to errors. SUMMARY

[0004] Embodiments of the present application provide a chip register RTL code generation method and device, which can improve the efficiency and accuracy of register RTL code generation.

[0005] In a first aspect, embodiments of the present application provide a chip register RTL code generation method, including:

[0006] Obtaining a port signal list of a chip; the port signal list includes signal attributes of a plurality of signals, and the signal attributes at least include a register mark, which is used to indicate whether a corresponding signal is associated with a register by specifying an offset address or automatically offsetting an address;

[0007] According to the register mark, determining a target signal in the port signal list that is associated with a register;

[0008] Based on the specified offset address or the automatically offset address in the register mark corresponding to the target signal, generating an offset address dictionary; the offset address dictionary includes related information of the target signal, and the related information at least includes an offset address;

[0009] According to the offset address in the offset address dictionary, performing domain-by-domain processing on the offset address dictionary to generate a register document;

[0010] According to the code logic of each line in the register document, generating a register RTL code.

[0011] In a possible design, the generating of the offset address dictionary based on the specified offset address or the automatically offset address in the register mark corresponding to the target signal includes:

[0012] determining a first target signal corresponding to the specified offset address, and storing information about the first target signal into a first dictionary;

[0013] determining a second target signal corresponding to the automatic offset address, and determining an offset address of each of the second target signals according to the offset addresses stored in the first dictionary, and storing information about the second target signals into a second dictionary;

[0014] merging the first dictionary and the second dictionary to obtain an offset address dictionary.

[0015] In a possible design, each offset address in the first dictionary includes a key-value pair list with a maximum bit width.

[0016] The storing of the information about the first target signal into the first dictionary includes:

[0017] traversing each of the first target signals, and performing the following operations for each of the first target signals traversed:

[0018] determining an offset address of the first target signal;

[0019] determining whether the offset address exists in the first dictionary; if the offset address exists, determining remaining bit positions of the offset address, and allocating a bit field for the first target signal according to the remaining bit positions of the offset address; or if the offset address does not exist, adding the offset address in the first dictionary, and allocating a bit field for the first target signal according to the maximum bit width of the offset address;

[0020] storing the information about the first target signal into a key-value pair list in a corresponding bit field of the first dictionary according to the offset address and the allocated bit field.

[0021] In a possible design, each offset address in the second dictionary includes a key-value pair list with a maximum bit width.

[0022] The determining of the offset address of each of the second target signals according to the offset addresses stored in the first dictionary, and the storing of the information about the second target signals into the second dictionary include:

[0023] traversing each of the second target signals, and performing the following operations for each of the second target signals traversed:

[0024] determining whether there is a remaining bit in the offset address currently stored in the second dictionary to satisfy the offset address of the second target signal; if yes, assigning the offset address to the second target signal and assigning a bit field to the second target signal according to the remaining bit of the offset address; if no, adding a new offset address in the second dictionary, assigning the new offset address to the second target signal, and assigning a bit field to the second target signal according to the maximum bit width of the new offset address; wherein the new offset address is different from other offset addresses in the second dictionary and offset addresses in the first dictionary;

[0025] storing the related information of the second target signal into the key-value pair list of the corresponding bit field of the second dictionary according to the offset address and the assigned bit field.

[0026] In a possible design, the difference between the address code of the new offset address and the address code of the maximum offset address in the second dictionary is minimum.

[0027] In a possible design, the domain-by-domain processing of the offset address dictionary according to the offset addresses in the offset address dictionary to generate the register document includes:

[0028] traversing the offset addresses in the offset address dictionary in ascending order;

[0029] for each offset address traversed, performing:

[0030] obtaining the key-value pair list stored in the offset address dictionary for the offset address;

[0031] traversing the key-value pair list in descending order of bit field, and writing the information stored in each bit field traversed to an Excel document to generate the register document.

[0032] In a possible design, the content of each row of the register document includes: offset address, register direction, register bit width, bit field occupied by the register, register type, register default value, and register description.

[0033] Before the register RTL code is generated, the method further includes:

[0034] for each row in the register document, performing:

[0035] generating port declaration code logic according to the register direction, register bit width, and register name of the row;

[0036] generating signal declaration code logic according to the offset address and register type of the row;

[0037] generating register RTL code according to the register type, the offset address, and the register default value of the line;

[0038] generating register RTL code according to the register type, the offset address, and the register default value of the line;

[0039] generating register RTL code according to the register type, the offset address, and the register default value of the line;

[0040] processing a special register type to generate code logic of a clear signal;

[0041] The generating register RTL code comprises:

[0042] The RTL code is generated one by one according to the port declaration code logic, the signal declaration code logic, the register packing and unpacking code logic, the register bus write operation code logic, the register bus read operation code logic, and the clear signal code logic corresponding to each line.

[0043] In a second aspect, an embodiment of the present application further provides a chip register RTL code generation device, comprising:

[0044] The obtaining module is configured to obtain a port signal list of a chip; the port signal list comprises signal attributes of a plurality of signals, and the signal attributes at least comprise a register mark, which is used to represent whether a corresponding signal is associated with a register by specifying an offset address or automatically offsetting an address;

[0045] The determining module is configured to determine target signals associated with a register in the port signal list according to the register mark;

[0046] The first generating module is configured to generate an offset address dictionary based on a specified offset address or an automatic offset address in the register mark corresponding to the target signal; the offset address dictionary comprises related information of the target signal, and the related information at least comprises an offset address;

[0047] The second generating module is configured to perform field-by-field processing on the offset address dictionary according to the offset address in the offset address dictionary to generate a register document;

[0048] The third generating module is configured to generate register RTL code according to code logic of each line in the register document.

[0049] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method in any of the embodiments of the present application.

[0050] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, having stored thereon a computer program, which, when executed in a computer, causes the computer to perform the method described in any of the embodiments of the present application.

[0051] The embodiment of the present application provides a chip register RTL code generation method and device. The method first acquires a port signal list of a chip containing a plurality of signals, then determines target signals associated with registers according to register marks of each signal, then generates an offset address dictionary according to a specified offset address or an automatic offset address in the register mark corresponding to the target signal, and generates a register document according to signal related information stored in the offset address dictionary, and finally generates register RTL code according to the code logic of each line in the register document. The method takes the port signal list as input, first automatically generates a register document, and then automatically generates register RTL code from the register document, thereby greatly improving the generation efficiency and accuracy of the register RTL code. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0053] Figure 1 is a chip register RTL code generation method flow chart provided by an embodiment of the present application;

[0054] Figure 2 is a hardware architecture diagram of an electronic device provided by an embodiment of the present application;

[0055] Figure 3 is a chip register RTL code generation device structure diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0057] As described above, the prior chip register RTL code generation method is inefficient and prone to errors, especially when the number of modules in the chip system is large and the number of registers required by each module is large, the prior method will consume a lot of manpower and time, and the error rate will also increase significantly.

[0058] To solve the above problems, the inventors propose a method for automatically generating chip register RTL code, which can improve the generation efficiency and accuracy of register RTL code.

[0059] The following describes a specific implementation of the above concept.

[0060] Please refer to Figure 1 The embodiment of the application provides a chip register RTL code generation method, which comprises the following steps:

[0061] In step 100, a port signal list of a chip is obtained; the port signal list comprises signal attributes of a plurality of signals, and the signal attributes at least comprise a register mark, which is used to indicate whether the corresponding signal is associated with a register by specifying an offset address or automatically offsetting the address;

[0062] In step 102, target signals associated with the register in the port signal list are determined according to the register mark;

[0063] In step 104, an offset address dictionary is generated based on the specified offset address or the automatic offset address in the register mark corresponding to the target signal; the offset address dictionary comprises related information of the target signal, and the related information at least comprises the offset address;

[0064] In step 106, the offset address dictionary is processed domain by domain according to the offset address in the offset address dictionary to generate a register document;

[0065] In step 108, register RTL code is generated according to the code logic of each line in the register document.

[0066] In the embodiment of the application, first, the port signal list of the chip comprising a plurality of signals is obtained, then the target signals associated with the register are determined according to the register mark of each signal, then the offset address dictionary is generated according to the specified offset address or the automatic offset address in the register mark corresponding to the target signal, and the register document is generated according to the signal related information stored in the offset address dictionary, and finally the register RTL code is generated according to the code logic of each line in the register document. This method takes the port signal list as input, first automatically generates a register document, and then automatically generates register RTL code from the register document, thereby greatly improving the generation efficiency and accuracy of register RTL code.

[0067] The following describes Figure 1The execution manner of each step shown.

[0068] First, for step 100, a port signal list of a chip is acquired; the port signal list includes signal attributes of a plurality of signals, and the signal attributes at least include a register mark, which is used to represent whether the corresponding signal is associated with a register by specifying an offset address or automatically offsetting an address;

[0069] In this step, the port signal list can be in any format, such as the port signal list shown in Table 1, and the signal attributes include a signal direction, a signal bit width, a signal name, a signal description, a default value, and a register mark.

[0070] Table 1: Port signal list

[0071]

[0072]

[0073] In Table 1, input represents that the signal direction is input, i.e., from a register, and the signal type is read / write (R / W), and output represents that the signal direction is output, i.e., to a register, and the signal type is read only (R / O); in addition, the register mark is empty, which represents that the signal is not associated with a register, if the register mark is True, it represents that the signal is associated with a register, and corresponds to an automatic offset address; if the register mark is a specific address (such as 0x01), it represents that the signal is associated with a register, and corresponds to a specified offset address with an address code of 0x01.

[0074] Then, for step 102, target signals associated with registers in the port signal list are determined according to the register marks.

[0075] In this step, if the register mark corresponding to the signal is a specified offset address or an automatic offset address, the signal is determined as a target signal.

[0076] Then, for step 104, an offset address dictionary is generated based on the specified offset address or the automatic offset address in the register mark corresponding to the target signal; the offset address dictionary includes related information of the target signal, and the related information at least includes an offset address.

[0077] In this step, the related information of the target signal includes, in addition to the offset address, a signal bit width, a signal type, a signal name, a signal description, and a default value, etc.

[0078] In some embodiments, step 104 includes:

[0079] Step A1, determine the first target signal corresponding to the specified offset address, and store the related information of the first target signal into the first dictionary;

[0080] Step A2, determine the second target signal corresponding to the automatic offset address, and determine the offset address of each second target signal according to the offset address in the first dictionary, and store the related information of the second target signal into the second dictionary;

[0081] Step A3, combine the first dictionary and the second dictionary to obtain the offset address dictionary.

[0082] For step A1, the register marked as the signal of the specified offset address is determined as the first target signal, for example, the r_cfg_02h signal and the r_tese_en signal in table 1 are the first target signal, and the related information of the two signals is stored into the first dictionary;

[0083] In this step, each offset address of the first dictionary includes a list of key-value pairs with the maximum bit width, and when the list of key-value pairs is just established, the value is an empty list, and in the process of storing the related information of the first target signal, the list of key-value pairs is continuously filled and updated. The maximum bit width of the key-value pair list can be 8 bits (7:0), or 16 bits (15:0) or 32 bits (31:0), which is not limited in the present application.

[0084] In some embodiments, step A1 includes:

[0085] Traverse each first target signal, and for each first target signal traversed, execute:

[0086] Determine the offset address of the first target signal;

[0087] Determine whether the offset address currently exists in the first dictionary; if it exists, determine the remaining bit of the offset address, and allocate a bit field for the first target signal according to the remaining bit of the offset address; if it does not exist, add the offset address in the first dictionary, and allocate a bit field for the first target signal according to the maximum bit width of the offset address;

[0088] According to the offset address and the allocated bit field, the related information of the first target signal is stored into the key-value pair list of the corresponding bit field of the first dictionary.

[0089] Specifically, taking Table 1 as an example, when the r_cfg_02h signal is traversed, it is determined that the offset address corresponding to the r_cfg_02h signal is 0x01, and since the address first appears in the current first dictionary, the offset address is added to the current first dictionary, and since the key-value pair list of the address is empty, the maximum bit width (7:0) of the offset address is used to allocate a bit field for the first target signal, for example, 0-3 bit field, that is, 3:0, that is, the related information of the signal is stored in the key-value pair list of the 3:0 bit field, and the first dictionary is updated. Of course, the related information of the signal can also be stored in the key-value pair list of the 7:4 bit field, which is not limited in the present application.

[0090] When the r_tese_en signal is traversed, it is determined that the offset address corresponding to the r_tese_en signal is 0x01, the address already exists in the first dictionary, and the remaining bit of the address is 7:4, and then the remaining bit of the offset address is used to allocate a bit field for the first target signal, that is, 4-6 bit field, that is, the related information of the signal is stored in the key-value pair list of the 6:4 bit field, and the first dictionary is updated.

[0091] By analogy, until the related information of all first target signals is stored in the first dictionary.

[0092] For step A2, the signals marked with the automatic offset address are determined as the second target signals, for example, the r_cfg_01h signal, the o_debug_signals signal and the r_cfg_03h signal in Table 1 are the second target signals, and then the related information of the two signals is stored in the second dictionary.

[0093] In this step, each offset address of the second dictionary includes a key-value pair list with a maximum bit width, and when the key-value pair list is just established, the value is an empty list, and in the process of gradually storing the related information of the second target signal, the key-value pair list is constantly filled and updated. The maximum bit width of the key-value pair list can be 8 bits (7:0), 16 bits (15:0) or 32 bits (31:0), which is not limited in the present application.

[0094] In some embodiments, step A2 includes:

[0095] Traverse each second target signal, and for each second target signal traversed, the following is performed:

[0096] determining whether there are remaining bits in the offset address currently stored in the second dictionary to satisfy the offset address of the second target signal; if yes, assigning the offset address to the second target signal and assigning a bit field to the second target signal according to the remaining bits of the offset address; if no, adding a new offset address in the second dictionary, assigning the new offset address to the second target signal, and assigning a bit field to the second target signal according to the maximum bit width of the new offset address; wherein the new offset address is different from other offset addresses in the second dictionary and offset addresses in the first dictionary;

[0097] storing the related information of the second target signal into the key-value pair list of the corresponding bit field of the second dictionary according to the offset address and the assigned bit field.

[0098] In this embodiment, the coding rule of the new offset address in the second dictionary is automatic coding. Generally, the default offset address is 0x00. When the remaining bits of the 0x00 address cannot satisfy the storage requirement of the signal, a new offset address is added. The new offset address cannot be the same as the offset addresses in the first dictionary and the offset addresses in the current second dictionary.

[0099] Specifically, taking Table 1 as an example, when the r_cfg_01h signal is traversed, it is determined that the corresponding offset address is True (i.e. automatic offset address). Since it is the first second target signal, a new automatic offset address needs to be added. Generally, the default offset address is 0x00, and the key-value pair list of the address is empty. Therefore, a bit field (6:0) is assigned to the first target signal according to the maximum bit width (7:0) of the offset address, i.e. the related information of the signal is stored into the key-value pair list of the 6:0 bit field, and the second dictionary is updated.

[0100] When the o_debug_signals signal is traversed, it is determined that the corresponding offset address is also an automatic offset address. Since the bit width of the signal is 3 bits, the remaining bit width (1 bit) of the 0x00 offset address in the second dictionary cannot satisfy the storage requirement of the signal. Therefore, a new offset address needs to be generated. The new offset address can be any address other than 0x00 and 0x01 addresses. Of course, it is preferred that the difference between the address code of the new offset address and the address code of the maximum offset address in the current second dictionary is the smallest, i.e. the new offset address is 0x02. The related information of the signal is stored into the key-value pair list of the 2:0 bit field of the 0x02 offset address, and the second dictionary is updated.

[0101] In some embodiments, if the remaining bit positions of multiple offset addresses in the second dictionary can satisfy the storage requirement of the second target signal, the related information of the target signal is stored in the offset address with the smallest address code. For example, the r_cfg_03h signal has a bit width of 1 bit, and the remaining bit widths of the 0x00 offset address and the 0x02 offset address in the second dictionary can satisfy the storage requirement of the signal, so the target signal is stored in the 0x00 offset address, thereby saving address space. By analogy, for each second target signal traversed, it is determined whether the remaining bit positions of the offset address with the smallest address code satisfy the storage requirement of the signal, and if so, the related information of the signal is stored in the key-value pair list corresponding to the offset address, and the traversal is stopped.

[0102] Finally, the first dictionary and the second dictionary are combined to obtain an offset address dictionary, as shown in Table 2:

[0103] Table 2 Offset address dictionary

[0104]

[0105] In Table 2, the 7-bit position in the offset address 0x01 is described as reserved, indicating that the bit position is temporarily not storing signal information and can be used to store signal information later.

[0106] Next, for step 106, the offset address dictionary is processed by domain according to the offset addresses in the offset address dictionary to generate a register document, including:

[0107] The offset addresses in the offset address dictionary are traversed in ascending order;

[0108] For each offset address traversed, the following is performed:

[0109] Obtain the key-value pair list stored by the offset address in the offset address dictionary;

[0110] The key-value pair list is traversed in descending order of bit domain, and the information stored by each bit domain traversed is written to an Excel document to generate a register document.

[0111] As shown in the offset address dictionary in Table 2, the offset address codes are not sorted in ascending order, and some bit domains do not store information, so the offset addresses in the offset address dictionary are traversed in ascending order, and then the key-value pair list is traversed in descending order of bit domain. The information stored by each bit domain traversed is written to an Excel document, and the information stored by each bit domain includes: the offset address, the bit domain, the domain name, the operation type, the default value and the description. The register document generated according to Table 2 is shown in Table 3:

[0112] Table 3 Register document

[0113]

[0114] As can be seen from Table 3, the register document generated according to the offset address dictionary has removed redundant bits, and the offset addresses are in ascending order, and the bit fields are in descending order.

[0115] In some embodiments, the content of each row of the register document includes: offset address, bit field occupied by the register, register name, register type, register bit width, register default value, and register description;

[0116] Before step 108 is performed, it further includes:

[0117] For each row in the register document, the following is performed:

[0118] According to the register type, register bit width, and register name of the row, generate port declaration code logic;

[0119] According to the offset address and register type of the row, generate signal declaration code logic;

[0120] According to the offset address, register name, bit field occupied by the register, and register type of the row, generate register packing and unpacking code logic;

[0121] According to the offset address, register default value, and register type of the row, generate code logic of register bus write operation;

[0122] According to the offset address and register type of the row, generate code logic of register bus read operation;

[0123] Handle special register types to generate code logic of clearing signals;

[0124] Finally, for step 108, according to the code logic of each row in the register document, generate register RTL code, including:

[0125] For each row, the corresponding port declaration code logic, signal declaration code logic, register packing and unpacking code logic, register bus write operation code logic, register bus read operation code logic, and clearing signal code logic are generated one by one to generate RTL code.

[0126] In some embodiments, the text in the port signal list format can also be determined based on the register RTL code by using a regular expression, and the port signal list can be generated based on the determined text. Specifically, the register RTL code is read in as a string, all text in the port signal format is matched by using a regular expression to obtain a list, and then the obtained list is written to an Excel document according to the format of the port signal list, that is, the port signal list is generated.

[0127] Through the above embodiments, automatic conversion between the port signal list, the register document and the register RTL code can be realized, thereby facilitating centralized management of the chip registers, and the management efficiency is high and errors are less likely to occur.

[0128] As shown in Figure 2 , Figure 3 , the embodiment of the present application provides a chip register RTL code generation device. The device embodiment can be realized by software, or by hardware or a combination of software and hardware. From the hardware layer, as shown in Figure 2 , a hardware architecture diagram of an electronic device where the chip register RTL code generation device of the embodiment of the present application is located, in addition to the processor, the memory, the network interface and the non-volatile memory shown in Figure 2 , the electronic device where the device is located in the embodiment can usually include other hardware, such as a forwarding chip responsible for processing packets, etc. Taking the software implementation as an example, as shown in Figure 3 , as a logically meaningful device, it is formed by the CPU of the electronic device where it is located reading the corresponding computer program in the non-volatile memory into the memory for running. The chip register RTL code generation device provided in the embodiment includes:

[0129] The obtaining module 300 is configured to obtain a port signal list of a chip. The port signal list includes signal attributes of a plurality of signals, and the signal attributes at least include register marks. The register marks are used to represent whether the corresponding signals are associated with registers by specifying offset addresses or automatic offset addresses.

[0130] The determining module 302 is configured to determine target signals associated with registers in the port signal list according to the register marks.

[0131] The first generating module 304 is configured to generate an offset address dictionary based on the specified offset addresses or the automatic offset addresses in the register marks corresponding to the target signals. The offset address dictionary includes related information of the target signals, and the related information at least includes offset addresses.

[0132] The second generating module 306 is configured to perform domain-by-domain processing on the offset address dictionary according to offset addresses in the offset address dictionary to generate a register document.

[0133] The third generating module 308 is configured to generate register RTL code according to code logic of each row in the register document.

[0134] In the embodiments of the present application, the obtaining module 300 can be configured to perform step 100 in the method embodiments described above, the determining module 302 can be configured to perform step 102 in the method embodiments described above, the first generating module 304 can be configured to perform step 104 in the method embodiments described above, the second generating module 306 can be configured to perform step 106 in the method embodiments described above, and the third generating module 308 can be configured to perform step 108 in the method embodiments described above.

[0135] In some embodiments, the first generating module 304 is configured to perform:

[0136] determine a first target signal corresponding to the specified offset address, and store related information of the first target signal into a first dictionary;

[0137] determine a second target signal corresponding to the automatic offset address, determine an offset address of each second target signal according to offset addresses in the first dictionary, and store related information of the second target signal into a second dictionary;

[0138] merge the first dictionary and the second dictionary to obtain an offset address dictionary.

[0139] In some embodiments, each offset address in the first dictionary includes a key-value pair list of a maximum bit width;

[0140] storing the related information of the first target signal into the first dictionary includes:

[0141] traversing each first target signal, and for each first target signal traversed, performing:

[0142] determining an offset address of the first target signal;

[0143] determining whether the offset address exists in the first dictionary; if the offset address exists, determining a remaining bit position of the offset address, and assigning a bit domain to the first target signal according to the remaining bit position of the offset address; if the offset address does not exist, adding the offset address in the first dictionary, and assigning a bit domain to the first target signal according to the maximum bit width of the offset address;

[0144] storing the related information of the first target signal into a key-value pair list of a corresponding bit domain in the first dictionary according to the offset address and the assigned bit domain.

[0145] In some embodiments, each offset address in the second dictionary includes a key-value pair list of the maximum bit width;

[0146] According to the offset address stored in the first dictionary, the offset address of each second target signal is determined, and the related information of the second target signal is stored in the second dictionary, including:

[0147] Each second target signal is traversed, and for each second target signal traversed, the following is performed:

[0148] It is determined whether there are remaining bits in the offset address currently stored in the second dictionary to satisfy the offset address of the second target signal; if so, the offset address is assigned to the second target signal, and the bit field is assigned to the second target signal according to the remaining bits of the offset address; if not, a new offset address is added in the second dictionary, the new offset address is assigned to the second target signal, and the bit field is assigned to the second target signal according to the maximum bit width of the new offset address; wherein the new offset address is different from other offset addresses in the second dictionary and offset addresses in the first dictionary;

[0149] According to the offset address and the assigned bit field, the related information of the second target signal is stored in the key-value pair list of the corresponding bit field in the second dictionary.

[0150] In some embodiments, the difference between the address code of the new offset address and the address code of the maximum offset address in the second dictionary is the smallest.

[0151] In some embodiments, the second generation module 306 is configured to perform:

[0152] The offset addresses in the offset address dictionary are traversed in ascending order;

[0153] For each offset address traversed, the following is performed:

[0154] The key-value pair list stored in the offset address dictionary is obtained;

[0155] The key-value pair list is traversed in descending order of bit field, and the information stored in each bit field is written to the Excel document to generate the register document.

[0156] In some embodiments, before executing the third generation module 308, the following is further included:

[0157] For each row in the register document, the following is performed:

[0158] According to the register direction, register bit width, and register name of the row, a port declaration code logic is generated;

[0159] According to the offset address and the register type of the line, signal declaration code logic is generated;

[0160] According to the offset address, the register name, the bit field occupied by the register and the register type of the line, register packing and unpacking code logic is generated;

[0161] According to the offset address, the register default value and the register type of the line, code logic of a register bus write operation is generated;

[0162] According to the offset address and the register type of the line, code logic of a register bus read operation is generated;

[0163] Special register types are processed, and code logic of clearing a signal is generated;

[0164] In some embodiments, the third generation module 308 is configured to perform the following operations:

[0165] The port declaration code logic, the signal declaration code logic, the register packing and unpacking code logic, the code logic of the register bus write operation, the code logic of the register bus read operation and the code logic of clearing the signal corresponding to each line are generated one by one to generate the RTL code.

[0166] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the chip register RTL code generation device. In other embodiments of the present application, the chip register RTL code generation device can include more or fewer components than the diagram, or combine certain components, or split certain components, or different component arrangements. The components shown can be implemented in hardware, software or a combination of software and hardware.

[0167] The information interaction and execution process between the modules in the device are based on the same concept as the method embodiments of the present application, and the specific content can be referred to the description in the method embodiments of the present application, which will not be described here.

[0168] The embodiments of the present application also provide an electronic device, which includes a memory and a processor, the memory stores a computer program, and the processor implements the chip register RTL code generation method in any of the embodiments of the present application when executing the computer program.

[0169] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program makes the processor execute the chip register RTL code generation method in any of the embodiments of the present application when the processor executes the computer program.

[0170] Specifically, a system or apparatus equipped with a storage medium on which a software program code for implementing the functions of any of the above-described embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus can be provided, which reads out and executes the program code stored in the storage medium.

[0171] In this case, the program code read out from the storage medium can implement the functions of any of the above-described embodiments, and the program code itself and the storage medium which stores the program code constitute the present application.

[0172] Embodiments of the storage medium for supplying the program code include a floppy disk, a hard disk, an optical disk such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW, a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0173] Further, it should be understood by those skilled in the art that not only the program code read out by the computer, but also the operating system or the like operating on the computer based on the instructions of the program code can perform part or all of the actual operations to realize the functions of any of the above-described embodiments.

[0174] Further, it should be understood by those skilled in the art that not only the program code read out by the computer, but also the operating system or the like operating on the computer based on the instructions of the program code can perform part or all of the actual operations to realize the functions of any of the above-described embodiments.

[0175] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying that there is any such relationship or order between these entities or actions. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0176] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the foregoing storage medium includes various storage media that can store program codes, such as ROM, RAM, magnetic disk or optical disk.

[0177] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for generating RTL code for a chip register, characterized in that, include: Obtain the port signal list of the chip; the port signal list includes signal attributes of several signals, and the signal attributes include at least a register flag, which is used to characterize whether the corresponding signal is associated with a register by specifying an offset address or an automatic offset address; Based on the register label, determine the target signal associated with the register in the port signal list; Determine the first target signal corresponding to the specified offset address, and store the relevant information of the first target signal in the first dictionary; The second target signal corresponding to the automatic offset address is determined, and the offset address of each second target signal is determined according to the offset address in the first dictionary. The relevant information of the second target signal is stored in the second dictionary. The first dictionary and the second dictionary are merged to obtain an offset address dictionary; the offset address dictionary includes relevant information of the target signal, and the relevant information includes at least the offset address; The offset address dictionary is processed field by field based on the offset addresses in the offset address dictionary to generate a register document; Generate register RTL code based on the code logic of each line in the register document; Each offset address of the first dictionary includes a list of key-value pairs with the maximum bit width; The step of storing the relevant information of the first target signal into the first dictionary includes: Iterate through each first target signal, and for each first target signal encountered, execute: Determine the offset address of the first target signal; Determine whether the offset address exists in the first dictionary; if it exists, determine the remaining bits of the offset address and allocate a bit field for the first target signal based on the remaining bits of the offset address; if it does not exist, add the offset address to the first dictionary and allocate a bit field for the first target signal based on the maximum bit width of the offset address. Based on the offset address and the allocated bit field, the relevant information of the first target signal is stored in the key-value pair list of the corresponding bit field of the first dictionary; Each offset address of the second dictionary includes a list of key-value pairs with the maximum bit width; The step of determining the offset address of each second target signal based on the offset addresses stored in the first dictionary, and storing the relevant information of the second target signal in the second dictionary, includes: Iterate through each second target signal, and for each second target signal encountered, execute: Determine whether there are any remaining bits in the offset addresses currently stored in the second dictionary that can satisfy the offset address of the second target signal; if so, assign the offset address to the second target signal and allocate a bit field for the second target signal according to the remaining bits of the offset address; if not, add an offset address to the second dictionary, assign the new offset address to the second target signal, and allocate a bit field for the second target signal according to the maximum bit width of the new offset address; wherein, the new offset address is different from other offset addresses in the second dictionary and offset addresses in the first dictionary; Based on the offset address and the allocated bit field, the relevant information of the second target signal is stored in the key-value pair list of the corresponding bit field of the second dictionary; If the second dictionary contains multiple offset addresses with remaining bits that can satisfy the storage requirements of the second target signal, then the relevant information of the second target signal is stored in the offset address with the smallest address code.

2. The method according to claim 1, characterized in that, The difference between the address code of the newly added offset address and the address code of the maximum offset address in the second dictionary is the smallest.

3. The method according to claim 1, characterized in that, The step of processing the offset address dictionary field by field based on the offset addresses in the offset address dictionary to generate a register document includes: Traverse the offset addresses in the offset address dictionary in ascending order; For each offset address encountered during the iteration, execute: Obtain the list of key-value pairs stored in the offset address dictionary for the offset address; Traverse the list of key-value pairs in descending order of bit fields, write the information stored in each bit field to an Excel document, and generate a register document.

4. The method according to claim 1, characterized in that, Before generating the register RTL code, the following is also included: For each line in the register document, execute: Based on the register direction, register bit width, and register name of this line, generate port declaration code logic; Generate signal declaration code logic based on the offset address and register type of the line; Based on the offset address, register name, bit field occupied by the register, and register type of the line, generate register encapsulation and decapsulation code logic; Based on the offset address, register default value, and register type of the line, generate the code logic for the register bus write operation; Based on the offset address and register type of the line, generate the code logic for the register bus read operation; Handle special register types and generate code logic to clear signals; The generated register RTL code includes: For each line of code, corresponding to the port declaration code logic, signal declaration code logic, register encapsulation and decapsulation code logic, register bus write operation code logic, register bus read operation code logic, and signal clearing code logic, RTL code is generated one by one.

5. A device for generating RTL code for a chip register, characterized in that, For implementing the method of claim 1, the apparatus comprises: An acquisition module is used to acquire a list of port signals of the chip; the list of port signals includes signal attributes of several signals, and the signal attributes include at least a register flag, which is used to characterize whether the corresponding signal is associated with a register by specifying an offset address or an automatic offset address; The determination module is used to determine the target signal associated with the register in the port signal list based on the register label; The first generation module is used to generate an offset address dictionary based on a specified offset address or an automatic offset address in the register tag corresponding to the target signal; the offset address dictionary includes relevant information of the target signal, and the relevant information includes at least the offset address; The second generation module is used to perform field-by-field processing on the offset address dictionary based on the offset addresses in the offset address dictionary to generate a register document; The third generation module is used to generate register RTL code based on the code logic of each line in the register document.

6. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-4.

7. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed in the computer, it causes the computer to perform the method of any one of claims 1-4.

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