A Timing Modeling Method for Near-Threshold Clock Trees
By performing process parameter fluctuation analysis and model optimization on the clock buffer and interconnection lines, the timing mean and fluctuation model of the clock path is constructed, which solves the problem of excessive clock deviation fluctuation under near-threshold conditions, and improves the comprehensive speed of the clock tree and the circuit robustness.
Patent Information
- Application Number
- CN202210609322.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-31
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2042-05-31
AI Technical Summary
The existing clock tree timing modeling method has excessive clock deviation fluctuations under near-threshold conditions, resulting in increased circuit design difficulty and increased timing violations, and the modeling process is complex and the accuracy is poor.
The clock buffer and interconnection lines were used to analyze the process parameters fluctuations, and the Hspice simulation and Levinberg-Marquard algorithm were initially fitted, and the timing model of the clock path was optimized by combining the simulated annealing algorithm to optimize the timing model.
Improves the comprehensive speed and accuracy of the clock tree, reduces clock deviation fluctuations, and enhances the robustness of the circuit.
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Figure CN115130425B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and particularly to a timing modeling method for a near-threshold clock tree. Background Art
[0002] With the improvement of the design density of integrated circuits, low-power technology has gradually become one of the most widely used technologies in mobile device chips. This technology greatly improves the energy efficiency ratio of the circuit by reducing the operating voltage. However, the low supply voltage also brings instability factors to the circuit, restricting the design and application of digital timing circuits.
[0003] The stability of the clock signal greatly affects the working state of the circuit, and the clock tree has thus become an important part of the timing circuit. The core of the clock tree is the clock path, which is composed of clock units and interconnects. The flipping of the clock units and the transmission of the interconnects of the clock signal are the main sources of the power consumption and propagation delay of the clock tree. Therefore, efficient and accurate clock tree timing modeling is very important for clock tree synthesis.
[0004] Traditional clock tree timing modeling consists of three parts: the lookup table model of the clock unit, the wire load model of the interconnect, and the timing arc model for calculating the path timing. The operation logic of the traditional timing model is simple, but its accuracy decreases as the supply voltage decreases.
[0005] Under near-threshold conditions, the influence of PVT fluctuations increases, the clock skew and the clock skew fluctuations increase, resulting in difficult convergence of the circuit timing, an increase in the number of timing violations, and an increase in the circuit design difficulty. At the same time, with the reduction of the process node, the circuit complexity increases, and the difficulty and data throughput of the timing calculation by the design tool also increase significantly. Therefore, an accurate and efficient timing model is very necessary for large-scale integrated circuit design. Currently, most of the timing modeling methods for clock trees mostly model the timing mean of the clock signal, and on this basis, consider some additional process deviation factors, and construct the model through mathematical derivation or statistical methods. However, most timing models do not accurately model the timing fluctuations of the clock signal, and rarely consider the correlation between different process deviation factors, resulting in poor model accuracy under near-threshold conditions, a complex modeling process, introducing additional errors and modeling time overhead, and there is a large room for improvement. Therefore, we are committed to proposing a new near-threshold clock tree timing model. Summary of the Invention
[0006] In view of this, the purpose of the present invention is to provide a timing modeling method for a near-threshold clock tree to solve the problem of excessive clock skew fluctuations existing in the existing near-threshold clock trees. Under the condition of having little influence on the timing accuracy, the present invention can not only reduce the clock skew fluctuations of the clock tree, but also improve the clock tree synthesis speed.
[0007] To achieve the above object, the present invention adopts the following technical solutions:
[0008] A timing modeling method for a near-threshold clock tree, the method comprising: performing timing modeling on a clock buffer, an interconnect line, and a clock path, wherein,
[0009] Performing timing modeling on the clock buffer and the interconnect line, which includes:
[0010] Step S101: Analyze the process parameter fluctuations of the clock buffer and the interconnect line during the manufacturing process, and obtain the influence of different process parameter fluctuations on their timings;
[0011] Step S102: Based on the process parameters obtained in step S101, determine the key process parameters affecting the timing, and give the fluctuation range of the key process parameters; then perform modeling for this fluctuation to obtain: the delay and output transition time functions of the clock buffer and the delay and output transition time functions of the interconnect line;
[0012] Step S103: Write the Hspice netlist of the interconnect line and the clock buffer, and then use Hspice to perform Monte Carlo simulation on the written netlist to obtain a data set;
[0013] Step S104: For the data set obtained in step S103, perform preliminary fitting using the Levenberg-Marquardt algorithm;
[0014] Step S105: For the timing model obtained by preliminary fitting, optimize the modeling accuracy by using the simulated annealing algorithm to obtain the final timing models of the clock buffer and the interconnect line;
[0015] Performing timing modeling on the clock path, which includes:
[0016] Step S201: Analyze the timing path structure to obtain the path components;
[0017] Step S202: Construct the path timing model function as a function of the path driving unit and the interconnect line length, including a timing mean model and a timing fluctuation model;
[0018] Step S203: Decompose and split the clock path, and the smallest unit after splitting is a single clock unit as the input driver and the interconnect line between it and the next-level clock unit;
[0019] Step S204: Based on the timing models of the clock buffer and the interconnect line obtained in step S104, calculate the path timing model.
[0020] Further, in the step S101, the different process parameters specifically include:
[0021] For a clock buffer, the process parameter fluctuations include: random doping fluctuations, gate line edge roughness, drain-induced barrier lowering effect, temperature and supply voltage fluctuations, and gate oxide thickness fluctuations;
[0022] For an interconnect, the process parameter fluctuations include: multiple patterning lithography and chemical mechanical polishing.
[0023] Further, in the step S101, the influence of the different process parameter fluctuations on the timing of the two specifically includes: for the clock buffer, obtaining the influence of the process parameter fluctuations on the device threshold voltage; for the interconnect, obtaining the influence of the process parameter fluctuations on the resistance and capacitance of the interconnect; where
[0024] The influence of the process parameter fluctuations on the device threshold voltage has the following specific function:
[0025]
[0026] In the formula, C ox is the gate oxide capacitance, N SUB is the substrate doping, W dm is the effective channel width of the transistor, L is the effective channel length of the transistor, W is the average transistor width, q is the charge quantity, V th is the transistor threshold voltage;
[0027] The influence of the process parameter fluctuations on the resistance and capacitance of the interconnect, the specific function of the interconnect resistance is:
[0028]
[0029] In the formula, w is the interconnect width, t is the interconnect thickness, ρ is the unit resistance, dt is the loss of the interconnect thickness due to etching, R dish is the concave radius of the interconnect, and length is the interconnect length;
[0030] The specific function of its interconnect capacitance is:
[0031] C = 2·C L2L (W, T, S, H, ε) + 2·C L2G (W, T, S, H, ε)
[0032] In the formula, C L2G represents the capacitance between the line and the ground, C L2L represents the capacitance between the lines, W is the interconnect width, T is the interconnect thickness, S is the interconnect spacing, H is the interconnect dielectric thickness, and ε is the process parameter fluctuation amount.
[0033] Further, in the step S102, the key process parameters include:
[0034] For the clock buffer, the key process parameters are gate oxide thickness and substrate doping;
[0035] For the interconnect line, the key process parameter is crosstalk capacitance;
[0036] The fluctuation of the gate oxide thickness of the clock buffer is ±7%, and the fluctuation of the substrate doping is ±5%;
[0037] The fluctuation of the crosstalk capacitance of the interconnect line is ±15%.
[0038] Further, in the step S102, the delay and output transition time function of the clock buffer, the specific expression is:
[0039] Delay(Slew input ,Cap load ) = Delay mean + Delay σ
[0040] Slew(Slew input ,Cap load ) = Slew mean + Slew σ
[0041] In the formula, Delay mean and Slew mean represent the mean value, Slew input represents the input transition time, Cap load represents the output load capacitance;
[0042] Delay σ and Slew σ represent the fluctuation, which is expressed as:
[0043] Delay σ = {P1 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q1 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2 , ΔT]} * Delay mean
[0044] Slew σ = {P2 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q2 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2, ΔT]} * Slew mean
[0045] Among them, ΔRd, ΔD, ΔV, ΔRo, and ΔT are the amounts of random doping fluctuation, DIBL effect, supply voltage, line edge roughness, and gate oxide thickness fluctuation respectively, and P1, P2, Q1, and Q2 are their weight coefficients respectively.
[0046] Furthermore, in the step S102, the delay and output transition time function of the interconnecting line;
[0047] Delay wire = Delay mean (Slew, Length) + Delay σ [ΔProcess]
[0048] Slew wire = Slew mean (Slew, Length) + Slew σ [ΔProcess]
[0049] In the formula, Delay mean and Slew mean represent the mean value, Slew represents the input transition time, Length represents the length of the interconnecting line, Delay σ and Slew σ represent the fluctuations of the output delay and output transition time, ΔProcess represents the fluctuations of the process parameters, and,
[0050] ΔProcess = {P * [ΔR, ΔC] + Q * [ΔR 2 , ΔC 2}
[0051] Among them, ΔR and ΔC are the changes in resistance and capacitance caused by multiple-pattern lithography and chemical mechanical polishing respectively, and P and Q are weight coefficients.
[0052] Furthermore, in the step S103, for the dataset obtained by simulation, the following operations need to be further performed:
[0053] Use Python for text processing to obtain the delay and output transition time data of the clock buffer and the interconnecting line, and this data includes the mean value and fluctuations; then use cscope to analyze its completeness.
[0054] Furthermore, in the step S104, the Levenberg-Marquardt algorithm is used for preliminary fitting to obtain:
[0055] The solution space of the mean and fluctuation values of the delay and output transition time functions of the clock buffer and the delay and output transition time functions of the interconnect line.
[0056] Further, in the step S104, the initial fitting using the Levenberg-Marquardt algorithm specifically includes:
[0057] Step S1041: Select a function in the function library as the function form for fitting;
[0058] Step S1042: Given an initial point, take the square of the difference between the value obtained by fitting the given input point p(Cap load , Slew in ) and the true value as the error function;
[0059] Step S1043: Taylor-expand the error function to obtain the Jacobian matrix and solve the increment normal equation;
[0060] Step S1044: Make a determination. Assume that the current iteration point is p k , and the obtained difference δ p,k is such that the difference between the current iteration point and the previous iteration point is minimized, then it is determined as the optimal solution; otherwise, perform the next round of iteration;
[0061] Step S1045: Output the optimal solution of the current function form when the iteration termination condition is satisfied;
[0062] Step S1046: Repeat the above steps for other function forms in the function library to obtain the initial fitting solution space.
[0063] Further, in the step S105, the modeling accuracy is optimized using the simulated annealing algorithm, which specifically includes:
[0064] Step S1051: Randomly generate an initial solution S0 within the function solution space, calculate the error function between the fitted timing model and the simulation value in the initial solution state, and take the error function as the objective function for the algorithm to solve;
[0065] Step S1052: Perturb near the initial solution to generate a new solution S', and calculate the difference between the new solution and the initial solution;
[0066] Step S1053: Make a determination on the difference. If the error of the new solution is less than that of the initial solution, take it as the initial solution for the next round of iteration; otherwise, make a determination according to the Metropolis criterion;
[0067] Step S1054: Output the function with the minimum error when the iteration termination condition is satisfied as the final timing model.
[0068] Further, in the step S204, the path timing model is calculated by the following method, including:
[0069] For the path timing mean:
[0070] μ path = ∑μ i + ∑μ j
[0071] In the formula, ∑μ i represents the sum of the timing means of all clock buffers on this path, and ∑μ j represents the sum of the timing means of the interconnect lines between every two timing units. μ path is the path timing mean;
[0072] For the path timing variation:
[0073]
[0074] In the formula, represents the sum of the timing deviations of all clock buffers on this path, represents the sum of the timing variations of the interconnect lines between every two timing units, is the path timing variation;
[0075] The path timing model includes a path delay and output transition time mean model and a path delay and output transition time variation model. The model form is:
[0076] Delay = Function(Driver, Length)
[0077] Slew = Function(Driver, Length)
[0078] Delayσ = Function(Driver, Length)
[0079] Slew σ = Function(Driver, Length)
[0080] In the formula, Delay mean and Slew mean represent the mean, and Delay σ and Slew σ represent the variation; Driver is the driving ability of the clock buffer on the timing path, and Length is the length of the interconnect line on the path.
[0081] The beneficial effects of the present invention are:
[0082] 1. The timing model provided by the present invention has a simple structure and is highly efficient in timing calculations for large-scale circuits.
[0083] 2. The present invention accurately models the mean values of the timing of clock buffers, interconnects, and paths, and provides additional modeling of timing fluctuations.
[0084] 3. When using the present invention for clock tree synthesis, the clock skew and clock skew fluctuations of the circuit are improved, and the circuit robustness is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS
[0085] Figure 1 It is a schematic flow chart of a timing modeling method for a near-threshold clock tree provided in Embodiment 1;
[0086] Figure 2 It is a schematic flow chart of timing modeling for clock buffers and interconnects provided in Embodiment 1;
[0087] Figure 3 It is a schematic flow chart of preliminary fitting of the timing model provided in Embodiment 1;
[0088] Figure 4 It is a schematic flow chart of optimizing the accuracy of the timing model provided in Embodiment 1;
[0089] Figure 5 It is a schematic flow chart of performing path timing modeling in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0090] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0091] Embodiment 1
[0092] This embodiment provides a timing modeling method for a near-threshold clock tree, including: a clock buffer timing model, an interconnect timing model, and a clock path timing model.
[0093] The clock buffer timing model is used to calculate the mean value and fluctuation of the output delay and output transition time of the clock buffer unit. Based on the input delay and input transition time at the input end of the clock buffer, the timing model calculates the output delay and output transition time at the output end.
[0094] The function of the interconnect timing model is to calculate the delay and signal time of the clock signal after passing through an interconnect of a certain length, taking the signal transition time at the input of the interconnect and the interconnect length as input variables, and obtaining the output delay and output transition time after calculation by the timing model.
[0095] The main function of the clock path timing model is to perform the minimum unit splitting according to the clock path structure and the components of the clock path, taking the unit driving ability and the interconnect length as inputs, calculating the clock path delay and the output transition time, calculating the fluctuation amounts of the two on this basis, and finally combining them to obtain the complete path timing model.
[0096] Specifically, the above-mentioned clock buffer timing modeling method and interconnect timing modeling method include three parts: simulation data acquisition, preliminary timing model fitting, and timing model accuracy optimization.
[0097] Among them, in the simulation data acquisition process, first analyze the clock buffer and interconnect structures and the process manufacturing process, select the key simulation parameters, and then perform Monte Carlo simulation using Hspice to traverse the input quantity combinations to obtain the fitting data set.
[0098] In the preliminary timing model fitting process, first propose the mathematical representation forms of the timing models of the clock buffer and the interconnect, and then perform preliminary fitting on the timing mean and the timing fluctuation on this basis to obtain the relevant function sets.
[0099] The timing model accuracy optimization process mainly screens and performs secondary accuracy optimization on the function sets obtained by the preliminary timing model fitting, and finally outputs the mathematical representations of the timing mean and the timing fluctuation with the smallest fitting error.
[0100] Specifically, the above-mentioned clock path timing modeling method includes three parts: timing path structure analysis, path minimum unit splitting, and path timing model combination.
[0101] The timing path structure analysis mainly proposes the timing path model representation form, taking the clock unit driving ability and the interconnect line length on a single path as the input variables of the timing model.
[0102] The path minimum unit splitting deconstructs and splits the complex clock path, and the smallest unit after splitting is a single clock unit as the input driver and the interconnect between it and the next-level clock unit.
[0103] The path timing model combination is based on the above-mentioned clock buffer timing model and interconnect timing model, performs calculation processing on the minimum units on the clock path, and obtains the path timing mean and the timing fluctuation model.
[0104] The above-mentioned preliminary fitting method uses the Levenberg-Marquardt algorithm to make assumptions about the relevant parameters and function forms of the model under the given input conditions of the relevant model, obtain the error function and the incremental normal equation, select the set of parameters with the smallest residual value under each function form, and use it as the solution space.
[0105] The above-mentioned precision optimization scheme uses the simulated annealing algorithm to traverse the function solution space obtained by the preliminary fitting to obtain the optimal solution of the weight coefficient, and uses it as the final timing model.
[0106] See Figures 1 - 5 , and a further detailed description is given to a timing modeling method for a near-threshold clock tree provided in this embodiment. The method includes: timing modeling of clock buffers, timing modeling of interconnects, and timing modeling of clock paths.
[0107] Specifically, in this embodiment, the modeling methods of clock buffers and interconnects are similar. As Figure 2 shown, the input quantities of the clock buffer timing modeling are the input transition time and the load capacitance, and the input quantities of the interconnect timing model are the input transition time and the wire length. The modeling method includes the following steps:
[0108] Step S101: Analyze the clock buffer and interconnect structures to obtain the macroscopic influence of process parameter fluctuations under near-threshold conditions, that is, resulting in timing violations and reduced device yield;
[0109] Step S102: Based on the macroscopic influence of process parameter fluctuations, specifically analyze the process parameter fluctuations caused by the manufacturing processes of clock buffers and interconnects to obtain the influence of different process parameters on their timings. Among them, for clock buffers, obtain the influence of process parameter fluctuations on the device threshold voltage; for interconnects, obtain the influence of process parameter fluctuations on the resistance and capacitance of interconnects;
[0110] Specifically, for the above-mentioned process parameter fluctuations, for clock buffers, the process parameter fluctuations include: random doping fluctuations, gate line edge roughness, drain-induced barrier lowering effect, temperature and supply voltage fluctuations, and gate oxide thickness fluctuations; for interconnects, the process parameter fluctuations include: multiple patterning lithography and chemical mechanical polishing.
[0111] More specifically, the influence of the above-mentioned process parameter fluctuations on the device threshold voltage has the following specific function:
[0112]
[0113] In the formula, C ox is the gate oxide capacitance, N SUB is the substrate doping, W dmis the effective channel width of the transistor, L is the effective channel length of the transistor, W is the average width of the transistor, q is the electric charge, V th is the threshold voltage of the transistor. All the above physical quantities have considered the process parameter fluctuations;
[0114] More specifically, the influence of the above process parameter fluctuations on the resistance and capacitance of the interconnecting wire. Among them, the specific function of the interconnecting wire resistance is:
[0115]
[0116] In the formula, w is the width of the interconnecting wire, t is the thickness of the interconnecting wire, ρ is the unit resistance, dt is the loss of the thickness of the interconnecting wire caused by etching, R dish is the concave radius of the interconnecting wire, and length is the length of the interconnecting wire.
[0117] The specific function of the interconnecting wire capacitance is:
[0118] C = 2·C L2L (W, T, S, H, ε) + 2·C L2G (W, T, S, H, ε)
[0119] In the formula, C L2G represents the capacitance between the wire and the ground, C L2L represents the capacitance between the wires, W is the width of the interconnecting wire, T is the thickness of the interconnecting wire, S is the spacing between the interconnecting wires, H is the dielectric thickness of the interconnecting wire, and ε is the process parameter fluctuation amount.
[0120] Step S103: Based on the analysis in step S102, the key process parameters affecting the timing are obtained. For the clock buffer, its key process parameters are the gate oxide thickness and the substrate doping; for the interconnecting wire, its key process parameter is the crosstalk capacitance. Then, for this key process parameter, the process parameter fluctuation range is given, and function modeling is performed on the interconnecting wire and the clock buffer to obtain: the delay and output transition time functions of the clock buffer and the delay and output transition time functions of the interconnecting wire.
[0121] Specifically, the gate oxide thickness fluctuation of the clock buffer is ±7%, and the substrate doping fluctuation is ±5%; the crosstalk capacitance fluctuation of the interconnecting wire is ±15%.
[0122] Specifically, the delay and output transition time functions of the clock buffer are:
[0123] Delay(Slew input , Cap load ) = Delay mean + Delay σ
[0124] Slew(Slew input , Capload ) = Slew mean + Slew σ
[0125] In the formula, Delay mean and Slew mean represent the mean value, Slew input represents the input transition time, Cap load represents the output load capacitance.
[0126] Delay σ and Slew σ represent the fluctuations, which are expressed as:
[0127] Delay σ = {P1 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q1 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2 , ΔT]} * Delay mean
[0128] Slew σ = {P2 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q2 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2 , ΔT]} * Slew mean
[0129] Among them, ΔRd, ΔD, ΔV, ΔRo, ΔT are the random doping fluctuation, DIBL effect, supply voltage, line edge roughness, and gate oxide thickness fluctuation amounts respectively, and P1, P2, Q1, Q2 are their weight coefficients respectively.
[0130] Specifically, the functions of the interconnect delay and output transition time are:
[0131] Delay wire = Delay mean (Slew, Length) + Delay σ [ΔProcess]
[0132] Slew wire = Slew mean (Slew, Length) + Slew σ [ΔProcess]
[0133] In the formula,, Delay mean and Slew meandenotes the mean value, Slew denotes the input transition time, Length denotes the interconnect line length, Delay σ and Slew σ denote the fluctuations of the output delay and the output transition time, ΔProcess denotes the fluctuations of the process parameters, and,
[0134] ΔProcess = {P * [ΔR, ΔC] + Q * [ΔR 2 , ΔC 2}
[0135] wherein, ΔR and ΔC are respectively the resistance and capacitance changes caused by multiple-pattern lithography and chemical mechanical polishing, and P, Q are weight coefficients..
[0136] Step S104: Based on the models of the interconnect line and the clock buffer obtained in Step S103, perform the writing of the Hspice netlist for the interconnect line and the clock buffer.
[0137] Step S105: Use Hspice to perform Monte Carlo simulation on the written netlist to obtain a timing simulation result file.
[0138] Step S106: Use Python to perform text processing on the timing simulation result file to obtain the delay and output transition time data of the clock buffer and the interconnect line, and this data includes the mean value and the fluctuation; then use cscope to analyze its completeness.
[0139] Step S107: Use Python to write the Levenberg-Marquardt algorithm to perform a preliminary fit on the delay and output transition time data of the clock buffer and the interconnect line, and obtain a solution space of the timing mean value and the timing fluctuation value in the function form that conforms to Step S103, including the solution space of the mean value and the fluctuation value of the output delay and the output transition time.
[0140] Specifically, as Figure 3 shown, the Levenberg-Marquardt algorithm used in the above-mentioned clock buffer and interconnect line timing modeling method in Step S107 includes the following steps:
[0141] Specifically including:
[0142] Step S1071: Select a function in the function library as the function form for fitting;
[0143] Step S1072: Given an initial point, take the square of the difference between the value obtained by fitting the given input point p(Cap load , Slew in ) and the true value as the error function;
[0144] Step S1073: Taylor-expand the error function to obtain the Jacobian matrix, and solve the incremental normal equation;
[0145] Step S1074: Make a determination. Assume the currently iterated point is p k , and the obtained difference δ p,k is such that the difference between the current iterated point and the previous iterated point is minimized, then it is determined as the optimal solution; otherwise, proceed to the next round of iteration;
[0146] Step S1075: Output the optimal solution in the current function form when the iteration termination condition is satisfied;
[0147] Step S1076: Repeat the above steps for other function forms in the function library to obtain the preliminary fitting solution space.
[0148] Step S108: Use Python to write a simulated annealing algorithm to optimize the modeling accuracy of the timing model fitted in Step S107, and seek the optimal solution within the solution space, that is, the function form with the minimum error.
[0149] Specifically, as Figure 4 shown, the simulated annealing algorithm used in the timing modeling method of the clock buffer and the interconnect line includes the following steps:
[0150] Step S1081: Randomly generate an initial solution S0 within the function solution space, calculate the error function between the fitted timing model and the simulation value in the initial solution state, and use the error function as the objective function for the algorithm to solve;
[0151] Step S1082: Perturb near the initial solution to generate a new solution S', and calculate the difference between the new solution and the initial solution;
[0152] Step S1083: Make a determination on the difference. If the error of the new solution is less than the initial solution, use it as the initial solution for the next round of iteration; otherwise, make a determination according to the Metropolis criterion;
[0153] Step S1084: Output the function with the minimum error when the iteration termination condition is satisfied as the final timing model.
[0154] Specifically, in this embodiment, for the timing modeling of the clock path, its specific process is as Figure 5 shown. The path timing model takes the driving ability of the clock units on the path and the length of the interconnect line driven as inputs, and the modeling method includes the following steps:
[0155] Step S201: Analyze the timing path structure to obtain the path components, that is, the combination of the clock buffer and the interconnect line.
[0156] Step S202: Construct the path timing model function as a function of the path driving unit and the interconnect line length, including the timing mean model and the timing fluctuation model, i.e., the mean model and the fluctuation model of the path delay and the output transition time.
[0157] Step S203: Split the path into the minimum path units composed of the clock unit and the interconnect line it drives. The minimum unit is a clock buffer serving as the driver and the interconnect line between it and the next-level clock buffer.
[0158] Step S204: Based on the mean and fluctuation models of the delay and the output transition time in step S108 of the clock buffer timing model and the interconnect line timing model process, calculate the path timing model. The calculation method is as follows:
[0159] For the path timing mean:
[0160] μ path = ∑μ i + ∑μ j
[0161] In the formula, ∑μ i represents the sum of the timing means of all the clock buffers on this path, and ∑μ j represents the sum of the timing means of the interconnect lines between every two timing units. μ path is the path timing mean.
[0162] For the path timing fluctuation:
[0163]
[0164] In the formula, represents the sum of the timing deviations of all the clock buffers on this path, represents the sum of the timing fluctuations of the interconnect lines between every two timing units, is the path timing fluctuation.
[0165] The path timing model includes the mean model of the path delay and the output transition time and the fluctuation model of the path delay and the output transition time. The model form is:
[0166] Delay = Function(Driver, Lenght)
[0167] Slew = Function(Driver, Lenght)
[0168] Delay σ = Function(Driver, Length)
[0169] Slew σ= Function(Driver, Lenght)
[0170] In the formula, Delay mean and Slew mean represent the mean value, and Delay σ and Slew σ represent the fluctuation. Driver is the driving ability of the clock buffer on the timing path, and Length is the length of the interconnecting wire on the path.
[0171] Details not described in the present invention are all well-known techniques to those skilled in the art.
[0172] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative work. Therefore, all technical solutions that can be obtained by those skilled in the art in the technical field based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art shall fall within the protection scope determined by the claims.
Claims
1. A timing modeling method for a near-threshold clock tree, characterized in that The method includes: performing timing modeling on a clock buffer, an interconnect line, and a clock path, where performing timing modeling on the clock buffer and the interconnect line, which includes: Step S101: Analyze the process parameter fluctuations of the clock buffer and the interconnect line during the manufacturing process to obtain the impact of different process parameter fluctuations on their timings; Step S102: Based on the process parameters obtained in Step S101, determine the key process parameters affecting the timing, and give the fluctuation range of the key process parameter; then perform modeling for this fluctuation to obtain: the delay and output transition time functions of the clock buffer and the delay and output transition time functions of the interconnect line; Step S103: Write the Hspice netlist of the interconnect line and the clock buffer, and then perform Monte Carlo simulation on the written netlist using Hspice to obtain a data set; Step S104: For the data set obtained in Step S103, perform preliminary fitting using the Levenberg-Marquardt algorithm; Step S105: For the timing model obtained by preliminary fitting, optimize the modeling accuracy by using the simulated annealing algorithm to obtain the final timing models of the clock buffer and the interconnect line; performing timing modeling on the clock path, which includes: Step S201: Analyze the timing path structure to obtain the path components; Step S202: Construct the path timing model function as a function of the path driving unit and the interconnect line length, including the timing mean model and the timing fluctuation model; Step S203: Decompose and split the clock path, and the smallest unit after splitting is a single clock unit as the input driver and the interconnect line between it and the next-level clock unit; Step S204: Based on the timing models of the clock buffer and the interconnect line obtained in Step S104, calculate the path timing model.
2. A timing modeling method for a near-threshold clock tree according to claim 1, characterized in that In Step S101, the different process parameters specifically include: For the clock buffer, its process parameter fluctuations include: random doping fluctuations, gate line edge roughness, drain-induced barrier lowering effect, temperature and supply voltage fluctuations, and gate oxide thickness fluctuations; For the interconnect line, its process parameter fluctuations include: multiple patterning lithography and chemical mechanical polishing.
3. A timing modeling method for a near-threshold clock tree according to claim 2, characterized in that In Step S101, the impact of the different process parameter fluctuations on their timings specifically includes: for the clock buffer, obtain the impact of the process parameter fluctuations on the device threshold voltage; for the interconnect line, obtain the impact of the process parameter fluctuations on the interconnect line resistance and capacitance; where the specific function of the impact of the process parameter fluctuations on the device threshold voltage is: In the formula, C ox is the gate oxide capacitance, N SUB is the substrate doping, W dm is the effective channel width of the transistor, L is the effective channel length of the transistor, W is the average value of the transistor width, q is the charge quantity, V th is the threshold voltage of the transistor; the specific function of the interconnect line resistance for the impact of the process parameter fluctuations on the interconnect line resistance and capacitance is: In the formula, w is the width of the interconnect line, t is the thickness of the interconnect line, ρ is the unit resistance, dt is the loss of the thickness of the interconnect line due to etching, R dish is the concave radius of the interconnect line, and length is the length of the interconnect line; the specific function of its interconnect line capacitance is: C = 2·C L2L (W, T, S, H, ε) + 2·C L2G (W, T, S, H, ε) In the formula, C L2G represents the line-to-ground capacitance, C L2L represents the line-to-line capacitance, W is the interconnect line width, T is the interconnect line thickness, S is the interconnect line spacing, H is the interconnect line dielectric thickness, and ε is the process parameter fluctuation amount.
4. A timing modeling method for a near-threshold clock tree according to claim 3, characterized in that In Step S102, the key process parameters include: For the clock buffer, its key process parameters are the gate oxide thickness and the substrate doping; For the interconnect line, its key process parameter is the crosstalk capacitance; The gate oxide thickness fluctuation of the clock buffer is ±7%, and the substrate doping fluctuation is ±5%; The crosstalk capacitance fluctuation of the interconnect line is ±15%.
5. A timing modeling method for a near-threshold clock tree according to claim 4, characterized in that In the step S102, the delay and output transition time function of the clock buffer has the following specific expression: Delay(Slew input , Cap load ) = Delay mean + Delay σ Slew(Slew input , Cap load ) = Slew mean + Slew σ In the formula, Delay mean and Slew mean represent the mean value, and Slew input represents the input transition time, and Cap load represents the output load capacitance; Delay σ and Slew σ represent fluctuations, which are expressed as: Delay σ = {P1 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q1 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2 , ΔT]} * Delay mean Slew σ = {P2 * [ΔRd, ΔD, ΔV, ΔRo, ΔT] + Q2 * [ΔR 2 , ΔD 2 , ΔV 2 , ΔRo 2 , ΔT]} * Slew mean where ΔRd, ΔD, ΔV, ΔRo, and ΔT are the amounts of random doping fluctuation, DIBL effect, supply voltage, line edge roughness, and gate oxide thickness fluctuation respectively, and P1, P2, Q1, and Q2 are their weight coefficients; the delay and output transition time function of the interconnecting wire; Delay wire = Delay mean (Slew, Length) + Delay σ [ΔProcess] Slew wire = Slew mean (Slew, Length) + Slew σ [ΔProcess] In the formula, Delay mean and Slew mean represent the mean value, Slew represents the input transition time, Length represents the interconnect line length, Delay σ and Slew σ represent the fluctuations of the output delay and the output transition time, ΔProcess represents the fluctuations of the process parameters, and ΔProcess=(P*[ΔR, ΔC]+Q*[ΔR 2 , ΔC 2} where ΔR and ΔC are the resistance and capacitance changes caused by multiple-pattern lithography and chemical mechanical polishing respectively, and P and Q are the weight coefficients.
6. A timing modeling method for a near-threshold clock tree according to claim 5, characterized in that In the step S103, the following operations need to be further performed on the simulated data set: Use Python for text processing to obtain the delay and output transition time data of the clock buffer and the interconnecting wire, which includes the mean and fluctuation; then use cscope to analyze its completeness.
7. A timing modeling method for a near-threshold clock tree according to claim 6, characterized in that In the step S104, the Levenberg-Marquardt algorithm is used for preliminary fitting to obtain: the delay and output transition time function of the clock buffer and the delay and output transition time function of the interconnecting wire, and the solution space of their mean and fluctuation values.
8. A timing modeling method for a near-threshold clock tree according to claim 7, characterized in that In the step S104, the use of the Levenberg-Marquardt algorithm for preliminary fitting specifically includes: Step S1041: Select a function in the function library as the function form for fitting; Step S1042: Given an initial point, take the square of the difference between the value obtained by fitting the input given point p(Cap load , Slew in ) and the true value as the error function; Step S1043: Taylor-expand the error function to obtain the Jacobian matrix, and solve the incremental normal equation; Step S1044, make a determination. Assume that the point in the current iteration is p k , and the obtained difference δ p，k such that the difference between the current iteration point and the previous iteration point is minimized, then it is determined as the optimal solution; otherwise, proceed to the next round of iteration; Step S1045: Output the optimal solution of the current function form when the iteration termination condition is satisfied; Step S1046: Repeat the above steps for other function forms in the function library to obtain the preliminary fitting solution space.
9. A timing modeling method for a near-threshold clock tree according to claim 8, characterized in that, In the step S105, the use of the simulated annealing algorithm for optimizing the modeling accuracy specifically includes: Step S1051: Randomly generate an initial solution S0 within the function solution space, calculate the error function between the fitted timing model and the simulation value in the state of the initial solution, and use the error function as the objective function for the algorithm to solve; Step S1052: Perturb near the initial solution to generate a new solution S′, and calculate the difference between the new solution and the initial solution; Step S1053: Judge the difference. If the error of the new solution is less than that of the initial solution, use it as the initial solution for the next round of iteration, otherwise judge according to the Metropolis criterion; Step S1054: Output the function with the minimum error when the iteration termination condition is satisfied as the final timing model.
10. A timing modeling method for a near-threshold clock tree according to claim 9, characterized in that In the step S204, the path timing model is calculated through the following method, including: For the path timing mean: μ path = ∑μ i + ∑μ j In the formula, ∑μ i represents the sum of the timing means of all clock buffers on the path, and ∑μ j represents the sum of the timing means of the interconnects between every two timing units. μ path is the path timing mean; For the path timing fluctuation: In the formula, represents the sum of the timing deviations of all clock buffers on this path, represents the sum of the timing fluctuations of the interconnecting wires between every two timing units, is the path timing fluctuation; The path timing model includes the path delay and output transition time mean model and the path delay and output transition time fluctuation model, and the model form is: Delay=Function(Driver, Length) Slew=Function(Driver, Length) Delay σ = Function(Driver, Length) Slew σ = Function(Driver, Length) In the formula, Delay mean and Slew mean represent the mean value, and Delay σ and Slew σ represent the fluctuation; Driver is the driving capability of the clock buffer on the timing path, and Length is the length of the interconnecting wire on the path.